1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr_unaligned) {
679 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 rx_tid->vaddr_unaligned,
681 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 rx_tid->vaddr_unaligned = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr_unaligned) {
693 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 rx_tid->vaddr_unaligned,
695 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 rx_tid->vaddr_unaligned = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr_unaligned) {
712 dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 rx_tid->vaddr_unaligned,
714 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 rx_tid->vaddr_unaligned = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {0};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 rx_tid->vaddr_unaligned,
754 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 rx_tid->vaddr_unaligned = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 rx_tid->vaddr_unaligned,
807 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 rx_tid->vaddr_unaligned = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {0};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 rx_tid->vaddr_unaligned,
836 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 rx_tid->vaddr_unaligned = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->paddr_unaligned = 0;
842 rx_tid->size = 0;
843 rx_tid->unaligned_size = 0;
844 }
845
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 u32 *link_desc,
848 enum hal_wbm_rel_bm_act action)
849 {
850 struct ath11k_dp *dp = &ab->dp;
851 struct hal_srng *srng;
852 u32 *desc;
853 int ret = 0;
854
855 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856
857 spin_lock_bh(&srng->lock);
858
859 ath11k_hal_srng_access_begin(ab, srng);
860
861 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 if (!desc) {
863 ret = -ENOBUFS;
864 goto exit;
865 }
866
867 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 action);
869
870 exit:
871 ath11k_hal_srng_access_end(ab, srng);
872
873 spin_unlock_bh(&srng->lock);
874
875 return ret;
876 }
877
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 struct ath11k_base *ab = rx_tid->ab;
881
882 lockdep_assert_held(&ab->base_lock);
883
884 if (rx_tid->dst_ring_desc) {
885 if (rel_link_desc)
886 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 kfree(rx_tid->dst_ring_desc);
889 rx_tid->dst_ring_desc = NULL;
890 }
891
892 rx_tid->cur_sn = 0;
893 rx_tid->last_frag_no = 0;
894 rx_tid->rx_frag_bitmap = 0;
895 __skb_queue_purge(&rx_tid->rx_frags);
896 }
897
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 struct dp_rx_tid *rx_tid;
901 int i;
902
903 lockdep_assert_held(&ar->ab->base_lock);
904
905 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 rx_tid = &peer->rx_tid[i];
907
908 spin_unlock_bh(&ar->ab->base_lock);
909 del_timer_sync(&rx_tid->frag_timer);
910 spin_lock_bh(&ar->ab->base_lock);
911
912 ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 }
914 }
915
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 struct dp_rx_tid *rx_tid;
919 int i;
920
921 lockdep_assert_held(&ar->ab->base_lock);
922
923 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 rx_tid = &peer->rx_tid[i];
925
926 ath11k_peer_rx_tid_delete(ar, peer, i);
927 ath11k_dp_rx_frags_cleanup(rx_tid, true);
928
929 spin_unlock_bh(&ar->ab->base_lock);
930 del_timer_sync(&rx_tid->frag_timer);
931 spin_lock_bh(&ar->ab->base_lock);
932 }
933 }
934
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 struct ath11k_peer *peer,
937 struct dp_rx_tid *rx_tid,
938 u32 ba_win_sz, u16 ssn,
939 bool update_ssn)
940 {
941 struct ath11k_hal_reo_cmd cmd = {0};
942 int ret;
943
944 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 cmd.ba_window_size = ba_win_sz;
949
950 if (update_ssn) {
951 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 }
954
955 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 NULL);
958 if (ret) {
959 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 rx_tid->tid, ret);
961 return ret;
962 }
963
964 rx_tid->ba_win_sz = ba_win_sz;
965
966 return 0;
967 }
968
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 struct ath11k_peer *peer;
973 struct dp_rx_tid *rx_tid;
974
975 spin_lock_bh(&ab->base_lock);
976
977 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 if (!peer) {
979 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 goto unlock_exit;
981 }
982
983 rx_tid = &peer->rx_tid[tid];
984 if (!rx_tid->active)
985 goto unlock_exit;
986
987 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 rx_tid->vaddr_unaligned = NULL;
990
991 rx_tid->active = false;
992
993 unlock_exit:
994 spin_unlock_bh(&ab->base_lock);
995 }
996
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 u8 tid, u32 ba_win_sz, u16 ssn,
999 enum hal_pn_type pn_type)
1000 {
1001 struct ath11k_base *ab = ar->ab;
1002 struct ath11k_peer *peer;
1003 struct dp_rx_tid *rx_tid;
1004 u32 hw_desc_sz, *vaddr;
1005 void *vaddr_unaligned;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 if (!vaddr_unaligned) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 rx_tid->paddr_unaligned = paddr;
1064 rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 (unsigned long)rx_tid->vaddr_unaligned);
1066 ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 rx_tid->size = hw_desc_sz;
1068 rx_tid->active = true;
1069
1070 /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 * Since these changes are not reflected in the device, driver now needs to
1072 * explicitly call dma_sync_single_for_device.
1073 */
1074 dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 rx_tid->size,
1076 DMA_TO_DEVICE);
1077 spin_unlock_bh(&ab->base_lock);
1078
1079 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 tid, 1, ba_win_sz);
1081 if (ret) {
1082 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 peer_mac, tid, ret);
1084 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 }
1086
1087 return ret;
1088 }
1089
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 struct ieee80211_ampdu_params *params)
1092 {
1093 struct ath11k_base *ab = ar->ab;
1094 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 int vdev_id = arsta->arvif->vdev_id;
1096 int ret;
1097
1098 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 params->tid, params->buf_size,
1100 params->ssn, arsta->pn_type);
1101 if (ret)
1102 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103
1104 return ret;
1105 }
1106
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 struct ieee80211_ampdu_params *params)
1109 {
1110 struct ath11k_base *ab = ar->ab;
1111 struct ath11k_peer *peer;
1112 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 int vdev_id = arsta->arvif->vdev_id;
1114 dma_addr_t paddr;
1115 bool active;
1116 int ret;
1117
1118 spin_lock_bh(&ab->base_lock);
1119
1120 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1121 if (!peer) {
1122 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1123 spin_unlock_bh(&ab->base_lock);
1124 return -ENOENT;
1125 }
1126
1127 paddr = peer->rx_tid[params->tid].paddr;
1128 active = peer->rx_tid[params->tid].active;
1129
1130 if (!active) {
1131 spin_unlock_bh(&ab->base_lock);
1132 return 0;
1133 }
1134
1135 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1136 spin_unlock_bh(&ab->base_lock);
1137 if (ret) {
1138 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1139 params->tid, ret);
1140 return ret;
1141 }
1142
1143 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1144 params->sta->addr, paddr,
1145 params->tid, 1, 1);
1146 if (ret)
1147 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1148 ret);
1149
1150 return ret;
1151 }
1152
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1153 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1154 const u8 *peer_addr,
1155 enum set_key_cmd key_cmd,
1156 struct ieee80211_key_conf *key)
1157 {
1158 struct ath11k *ar = arvif->ar;
1159 struct ath11k_base *ab = ar->ab;
1160 struct ath11k_hal_reo_cmd cmd = {0};
1161 struct ath11k_peer *peer;
1162 struct dp_rx_tid *rx_tid;
1163 u8 tid;
1164 int ret = 0;
1165
1166 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1167 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1168 * for now.
1169 */
1170 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1171 return 0;
1172
1173 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1174 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1175 HAL_REO_CMD_UPD0_PN_SIZE |
1176 HAL_REO_CMD_UPD0_PN_VALID |
1177 HAL_REO_CMD_UPD0_PN_CHECK |
1178 HAL_REO_CMD_UPD0_SVLD;
1179
1180 switch (key->cipher) {
1181 case WLAN_CIPHER_SUITE_TKIP:
1182 case WLAN_CIPHER_SUITE_CCMP:
1183 case WLAN_CIPHER_SUITE_CCMP_256:
1184 case WLAN_CIPHER_SUITE_GCMP:
1185 case WLAN_CIPHER_SUITE_GCMP_256:
1186 if (key_cmd == SET_KEY) {
1187 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1188 cmd.pn_size = 48;
1189 }
1190 break;
1191 default:
1192 break;
1193 }
1194
1195 spin_lock_bh(&ab->base_lock);
1196
1197 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1198 if (!peer) {
1199 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1200 spin_unlock_bh(&ab->base_lock);
1201 return -ENOENT;
1202 }
1203
1204 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1205 rx_tid = &peer->rx_tid[tid];
1206 if (!rx_tid->active)
1207 continue;
1208 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1209 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1210 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1211 HAL_REO_CMD_UPDATE_RX_QUEUE,
1212 &cmd, NULL);
1213 if (ret) {
1214 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1215 tid, ret);
1216 break;
1217 }
1218 }
1219
1220 spin_unlock_bh(&ab->base_lock);
1221
1222 return ret;
1223 }
1224
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1225 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1226 u16 peer_id)
1227 {
1228 int i;
1229
1230 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1231 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1232 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1233 return i;
1234 } else {
1235 return i;
1236 }
1237 }
1238
1239 return -EINVAL;
1240 }
1241
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1242 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1243 u16 tag, u16 len, const void *ptr,
1244 void *data)
1245 {
1246 struct htt_ppdu_stats_info *ppdu_info;
1247 struct htt_ppdu_user_stats *user_stats;
1248 int cur_user;
1249 u16 peer_id;
1250
1251 ppdu_info = data;
1252
1253 switch (tag) {
1254 case HTT_PPDU_STATS_TAG_COMMON:
1255 if (len < sizeof(struct htt_ppdu_stats_common)) {
1256 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1257 len, tag);
1258 return -EINVAL;
1259 }
1260 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1261 sizeof(struct htt_ppdu_stats_common));
1262 break;
1263 case HTT_PPDU_STATS_TAG_USR_RATE:
1264 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1265 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 len, tag);
1267 return -EINVAL;
1268 }
1269
1270 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1271 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1272 peer_id);
1273 if (cur_user < 0)
1274 return -EINVAL;
1275 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1276 user_stats->peer_id = peer_id;
1277 user_stats->is_valid_peer_id = true;
1278 memcpy((void *)&user_stats->rate, ptr,
1279 sizeof(struct htt_ppdu_stats_user_rate));
1280 user_stats->tlv_flags |= BIT(tag);
1281 break;
1282 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1283 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1284 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1285 len, tag);
1286 return -EINVAL;
1287 }
1288
1289 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1290 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1291 peer_id);
1292 if (cur_user < 0)
1293 return -EINVAL;
1294 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1295 user_stats->peer_id = peer_id;
1296 user_stats->is_valid_peer_id = true;
1297 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1298 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1299 user_stats->tlv_flags |= BIT(tag);
1300 break;
1301 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1302 if (len <
1303 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1304 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1305 len, tag);
1306 return -EINVAL;
1307 }
1308
1309 peer_id =
1310 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1311 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1312 peer_id);
1313 if (cur_user < 0)
1314 return -EINVAL;
1315 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1316 user_stats->peer_id = peer_id;
1317 user_stats->is_valid_peer_id = true;
1318 memcpy((void *)&user_stats->ack_ba, ptr,
1319 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1320 user_stats->tlv_flags |= BIT(tag);
1321 break;
1322 }
1323 return 0;
1324 }
1325
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1326 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1327 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1328 const void *ptr, void *data),
1329 void *data)
1330 {
1331 const struct htt_tlv *tlv;
1332 const void *begin = ptr;
1333 u16 tlv_tag, tlv_len;
1334 int ret = -EINVAL;
1335
1336 while (len > 0) {
1337 if (len < sizeof(*tlv)) {
1338 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1339 ptr - begin, len, sizeof(*tlv));
1340 return -EINVAL;
1341 }
1342 tlv = (struct htt_tlv *)ptr;
1343 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1344 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1345 ptr += sizeof(*tlv);
1346 len -= sizeof(*tlv);
1347
1348 if (tlv_len > len) {
1349 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1350 tlv_tag, ptr - begin, len, tlv_len);
1351 return -EINVAL;
1352 }
1353 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1354 if (ret == -ENOMEM)
1355 return ret;
1356
1357 ptr += tlv_len;
1358 len -= tlv_len;
1359 }
1360 return 0;
1361 }
1362
1363 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1364 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1365 struct htt_ppdu_stats *ppdu_stats, u8 user)
1366 {
1367 struct ath11k_base *ab = ar->ab;
1368 struct ath11k_peer *peer;
1369 struct ieee80211_sta *sta;
1370 struct ath11k_sta *arsta;
1371 struct htt_ppdu_stats_user_rate *user_rate;
1372 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1373 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1374 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1375 int ret;
1376 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1377 u32 succ_bytes = 0;
1378 u16 rate = 0, succ_pkts = 0;
1379 u32 tx_duration = 0;
1380 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1381 bool is_ampdu = false;
1382
1383 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1384 return;
1385
1386 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1387 is_ampdu =
1388 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1389
1390 if (usr_stats->tlv_flags &
1391 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1392 succ_bytes = usr_stats->ack_ba.success_bytes;
1393 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1394 usr_stats->ack_ba.info);
1395 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1396 usr_stats->ack_ba.info);
1397 }
1398
1399 if (common->fes_duration_us)
1400 tx_duration = common->fes_duration_us;
1401
1402 user_rate = &usr_stats->rate;
1403 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1404 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1405 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1406 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1407 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1408 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1409
1410 /* Note: If host configured fixed rates and in some other special
1411 * cases, the broadcast/management frames are sent in different rates.
1412 * Firmware rate's control to be skipped for this?
1413 */
1414
1415 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1416 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1417 return;
1418 }
1419
1420 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1421 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1422 return;
1423 }
1424
1425 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1426 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1427 mcs, nss);
1428 return;
1429 }
1430
1431 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1432 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1433 flags,
1434 &rate_idx,
1435 &rate);
1436 if (ret < 0)
1437 return;
1438 }
1439
1440 rcu_read_lock();
1441 spin_lock_bh(&ab->base_lock);
1442 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1443
1444 if (!peer || !peer->sta) {
1445 spin_unlock_bh(&ab->base_lock);
1446 rcu_read_unlock();
1447 return;
1448 }
1449
1450 sta = peer->sta;
1451 arsta = ath11k_sta_to_arsta(sta);
1452
1453 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1454
1455 switch (flags) {
1456 case WMI_RATE_PREAMBLE_OFDM:
1457 arsta->txrate.legacy = rate;
1458 break;
1459 case WMI_RATE_PREAMBLE_CCK:
1460 arsta->txrate.legacy = rate;
1461 break;
1462 case WMI_RATE_PREAMBLE_HT:
1463 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1464 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1465 if (sgi)
1466 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1467 break;
1468 case WMI_RATE_PREAMBLE_VHT:
1469 arsta->txrate.mcs = mcs;
1470 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1471 if (sgi)
1472 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1473 break;
1474 case WMI_RATE_PREAMBLE_HE:
1475 arsta->txrate.mcs = mcs;
1476 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1477 arsta->txrate.he_dcm = dcm;
1478 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1479 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1480 ((user_rate->ru_end -
1481 user_rate->ru_start) + 1);
1482 break;
1483 }
1484
1485 arsta->txrate.nss = nss;
1486
1487 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1488 arsta->tx_duration += tx_duration;
1489 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1490
1491 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1492 * So skip peer stats update for mgmt packets.
1493 */
1494 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1495 memset(peer_stats, 0, sizeof(*peer_stats));
1496 peer_stats->succ_pkts = succ_pkts;
1497 peer_stats->succ_bytes = succ_bytes;
1498 peer_stats->is_ampdu = is_ampdu;
1499 peer_stats->duration = tx_duration;
1500 peer_stats->ba_fails =
1501 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1502 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1503
1504 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1505 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1506 }
1507
1508 spin_unlock_bh(&ab->base_lock);
1509 rcu_read_unlock();
1510 }
1511
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1512 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1513 struct htt_ppdu_stats *ppdu_stats)
1514 {
1515 u8 user;
1516
1517 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1518 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1519 }
1520
1521 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1522 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1523 u32 ppdu_id)
1524 {
1525 struct htt_ppdu_stats_info *ppdu_info;
1526
1527 lockdep_assert_held(&ar->data_lock);
1528
1529 if (!list_empty(&ar->ppdu_stats_info)) {
1530 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1531 if (ppdu_info->ppdu_id == ppdu_id)
1532 return ppdu_info;
1533 }
1534
1535 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1536 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1537 typeof(*ppdu_info), list);
1538 list_del(&ppdu_info->list);
1539 ar->ppdu_stat_list_depth--;
1540 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1541 kfree(ppdu_info);
1542 }
1543 }
1544
1545 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1546 if (!ppdu_info)
1547 return NULL;
1548
1549 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1550 ar->ppdu_stat_list_depth++;
1551
1552 return ppdu_info;
1553 }
1554
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1555 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1556 struct sk_buff *skb)
1557 {
1558 struct ath11k_htt_ppdu_stats_msg *msg;
1559 struct htt_ppdu_stats_info *ppdu_info;
1560 struct ath11k *ar;
1561 int ret;
1562 u8 pdev_id;
1563 u32 ppdu_id, len;
1564
1565 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1566 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1567 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1568 ppdu_id = msg->ppdu_id;
1569
1570 rcu_read_lock();
1571 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1572 if (!ar) {
1573 ret = -EINVAL;
1574 goto out;
1575 }
1576
1577 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1578 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1579
1580 spin_lock_bh(&ar->data_lock);
1581 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1582 if (!ppdu_info) {
1583 ret = -EINVAL;
1584 goto out_unlock_data;
1585 }
1586
1587 ppdu_info->ppdu_id = ppdu_id;
1588 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1589 ath11k_htt_tlv_ppdu_stats_parse,
1590 (void *)ppdu_info);
1591 if (ret) {
1592 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1593 goto out_unlock_data;
1594 }
1595
1596 out_unlock_data:
1597 spin_unlock_bh(&ar->data_lock);
1598
1599 out:
1600 rcu_read_unlock();
1601
1602 return ret;
1603 }
1604
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1605 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1606 {
1607 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1608 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1609 struct ath11k *ar;
1610 u8 pdev_id;
1611
1612 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1613
1614 rcu_read_lock();
1615
1616 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1617 if (!ar) {
1618 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1619 goto out;
1620 }
1621
1622 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1623 ar->ab->pktlog_defs_checksum);
1624
1625 out:
1626 rcu_read_unlock();
1627 }
1628
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1629 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1630 struct sk_buff *skb)
1631 {
1632 u32 *data = (u32 *)skb->data;
1633 u8 pdev_id, ring_type, ring_id, pdev_idx;
1634 u16 hp, tp;
1635 u32 backpressure_time;
1636 struct ath11k_bp_stats *bp_stats;
1637
1638 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1639 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1640 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1641 ++data;
1642
1643 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1644 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1645 ++data;
1646
1647 backpressure_time = *data;
1648
1649 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1650 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1651
1652 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1653 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1654 return;
1655
1656 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1657 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1658 pdev_idx = DP_HW2SW_MACID(pdev_id);
1659
1660 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1661 return;
1662
1663 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1664 } else {
1665 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1666 ring_type);
1667 return;
1668 }
1669
1670 spin_lock_bh(&ab->base_lock);
1671 bp_stats->hp = hp;
1672 bp_stats->tp = tp;
1673 bp_stats->count++;
1674 bp_stats->jiffies = jiffies;
1675 spin_unlock_bh(&ab->base_lock);
1676 }
1677
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1678 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1679 struct sk_buff *skb)
1680 {
1681 struct ath11k_dp *dp = &ab->dp;
1682 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1683 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1684 u16 peer_id;
1685 u8 vdev_id;
1686 u8 mac_addr[ETH_ALEN];
1687 u16 peer_mac_h16;
1688 u16 ast_hash;
1689 u16 hw_peer_id;
1690
1691 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1692
1693 switch (type) {
1694 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1695 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1696 resp->version_msg.version);
1697 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1698 resp->version_msg.version);
1699 complete(&dp->htt_tgt_version_received);
1700 break;
1701 case HTT_T2H_MSG_TYPE_PEER_MAP:
1702 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1703 resp->peer_map_ev.info);
1704 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1705 resp->peer_map_ev.info);
1706 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1707 resp->peer_map_ev.info1);
1708 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1709 peer_mac_h16, mac_addr);
1710 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1711 break;
1712 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1713 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1714 resp->peer_map_ev.info);
1715 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1716 resp->peer_map_ev.info);
1717 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1718 resp->peer_map_ev.info1);
1719 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1720 peer_mac_h16, mac_addr);
1721 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1722 resp->peer_map_ev.info2);
1723 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1724 resp->peer_map_ev.info1);
1725 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1726 hw_peer_id);
1727 break;
1728 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1729 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1730 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1731 resp->peer_unmap_ev.info);
1732 ath11k_peer_unmap_event(ab, peer_id);
1733 break;
1734 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1735 ath11k_htt_pull_ppdu_stats(ab, skb);
1736 break;
1737 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1738 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1739 break;
1740 case HTT_T2H_MSG_TYPE_PKTLOG:
1741 ath11k_htt_pktlog(ab, skb);
1742 break;
1743 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1744 ath11k_htt_backpressure_event_handler(ab, skb);
1745 break;
1746 default:
1747 ath11k_warn(ab, "htt event %d not handled\n", type);
1748 break;
1749 }
1750
1751 dev_kfree_skb_any(skb);
1752 }
1753
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1754 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1755 struct sk_buff_head *msdu_list,
1756 struct sk_buff *first, struct sk_buff *last,
1757 u8 l3pad_bytes, int msdu_len)
1758 {
1759 struct ath11k_base *ab = ar->ab;
1760 struct sk_buff *skb;
1761 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1762 int buf_first_hdr_len, buf_first_len;
1763 struct hal_rx_desc *ldesc;
1764 int space_extra, rem_len, buf_len;
1765 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1766
1767 /* As the msdu is spread across multiple rx buffers,
1768 * find the offset to the start of msdu for computing
1769 * the length of the msdu in the first buffer.
1770 */
1771 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1772 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1773
1774 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1775 skb_put(first, buf_first_hdr_len + msdu_len);
1776 skb_pull(first, buf_first_hdr_len);
1777 return 0;
1778 }
1779
1780 ldesc = (struct hal_rx_desc *)last->data;
1781 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1782 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1783
1784 /* MSDU spans over multiple buffers because the length of the MSDU
1785 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1786 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1787 */
1788 skb_put(first, DP_RX_BUFFER_SIZE);
1789 skb_pull(first, buf_first_hdr_len);
1790
1791 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1792 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1793 */
1794 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1795
1796 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1797 if (space_extra > 0 &&
1798 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1799 /* Free up all buffers of the MSDU */
1800 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1801 rxcb = ATH11K_SKB_RXCB(skb);
1802 if (!rxcb->is_continuation) {
1803 dev_kfree_skb_any(skb);
1804 break;
1805 }
1806 dev_kfree_skb_any(skb);
1807 }
1808 return -ENOMEM;
1809 }
1810
1811 rem_len = msdu_len - buf_first_len;
1812 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1813 rxcb = ATH11K_SKB_RXCB(skb);
1814 if (rxcb->is_continuation)
1815 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1816 else
1817 buf_len = rem_len;
1818
1819 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1820 WARN_ON_ONCE(1);
1821 dev_kfree_skb_any(skb);
1822 return -EINVAL;
1823 }
1824
1825 skb_put(skb, buf_len + hal_rx_desc_sz);
1826 skb_pull(skb, hal_rx_desc_sz);
1827 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1828 buf_len);
1829 dev_kfree_skb_any(skb);
1830
1831 rem_len -= buf_len;
1832 if (!rxcb->is_continuation)
1833 break;
1834 }
1835
1836 return 0;
1837 }
1838
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1839 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1840 struct sk_buff *first)
1841 {
1842 struct sk_buff *skb;
1843 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1844
1845 if (!rxcb->is_continuation)
1846 return first;
1847
1848 skb_queue_walk(msdu_list, skb) {
1849 rxcb = ATH11K_SKB_RXCB(skb);
1850 if (!rxcb->is_continuation)
1851 return skb;
1852 }
1853
1854 return NULL;
1855 }
1856
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1857 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1858 {
1859 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1860 struct rx_attention *rx_attention;
1861 bool ip_csum_fail, l4_csum_fail;
1862
1863 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1864 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1865 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1866
1867 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1868 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1869 }
1870
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1871 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1872 {
1873 switch (enctype) {
1874 case HAL_ENCRYPT_TYPE_OPEN:
1875 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1876 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1877 return 0;
1878 case HAL_ENCRYPT_TYPE_CCMP_128:
1879 return IEEE80211_CCMP_MIC_LEN;
1880 case HAL_ENCRYPT_TYPE_CCMP_256:
1881 return IEEE80211_CCMP_256_MIC_LEN;
1882 case HAL_ENCRYPT_TYPE_GCMP_128:
1883 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1884 return IEEE80211_GCMP_MIC_LEN;
1885 case HAL_ENCRYPT_TYPE_WEP_40:
1886 case HAL_ENCRYPT_TYPE_WEP_104:
1887 case HAL_ENCRYPT_TYPE_WEP_128:
1888 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1889 case HAL_ENCRYPT_TYPE_WAPI:
1890 break;
1891 }
1892
1893 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1894 return 0;
1895 }
1896
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1897 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1898 enum hal_encrypt_type enctype)
1899 {
1900 switch (enctype) {
1901 case HAL_ENCRYPT_TYPE_OPEN:
1902 return 0;
1903 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1904 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1905 return IEEE80211_TKIP_IV_LEN;
1906 case HAL_ENCRYPT_TYPE_CCMP_128:
1907 return IEEE80211_CCMP_HDR_LEN;
1908 case HAL_ENCRYPT_TYPE_CCMP_256:
1909 return IEEE80211_CCMP_256_HDR_LEN;
1910 case HAL_ENCRYPT_TYPE_GCMP_128:
1911 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1912 return IEEE80211_GCMP_HDR_LEN;
1913 case HAL_ENCRYPT_TYPE_WEP_40:
1914 case HAL_ENCRYPT_TYPE_WEP_104:
1915 case HAL_ENCRYPT_TYPE_WEP_128:
1916 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1917 case HAL_ENCRYPT_TYPE_WAPI:
1918 break;
1919 }
1920
1921 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1922 return 0;
1923 }
1924
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1925 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1926 enum hal_encrypt_type enctype)
1927 {
1928 switch (enctype) {
1929 case HAL_ENCRYPT_TYPE_OPEN:
1930 case HAL_ENCRYPT_TYPE_CCMP_128:
1931 case HAL_ENCRYPT_TYPE_CCMP_256:
1932 case HAL_ENCRYPT_TYPE_GCMP_128:
1933 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1934 return 0;
1935 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1936 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1937 return IEEE80211_TKIP_ICV_LEN;
1938 case HAL_ENCRYPT_TYPE_WEP_40:
1939 case HAL_ENCRYPT_TYPE_WEP_104:
1940 case HAL_ENCRYPT_TYPE_WEP_128:
1941 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1942 case HAL_ENCRYPT_TYPE_WAPI:
1943 break;
1944 }
1945
1946 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1947 return 0;
1948 }
1949
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1950 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1951 struct sk_buff *msdu,
1952 u8 *first_hdr,
1953 enum hal_encrypt_type enctype,
1954 struct ieee80211_rx_status *status)
1955 {
1956 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1957 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1958 struct ieee80211_hdr *hdr;
1959 size_t hdr_len;
1960 u8 da[ETH_ALEN];
1961 u8 sa[ETH_ALEN];
1962 u16 qos_ctl = 0;
1963 u8 *qos;
1964
1965 /* copy SA & DA and pull decapped header */
1966 hdr = (struct ieee80211_hdr *)msdu->data;
1967 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1968 ether_addr_copy(da, ieee80211_get_DA(hdr));
1969 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1970 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1971
1972 if (rxcb->is_first_msdu) {
1973 /* original 802.11 header is valid for the first msdu
1974 * hence we can reuse the same header
1975 */
1976 hdr = (struct ieee80211_hdr *)first_hdr;
1977 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1978
1979 /* Each A-MSDU subframe will be reported as a separate MSDU,
1980 * so strip the A-MSDU bit from QoS Ctl.
1981 */
1982 if (ieee80211_is_data_qos(hdr->frame_control)) {
1983 qos = ieee80211_get_qos_ctl(hdr);
1984 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1985 }
1986 } else {
1987 /* Rebuild qos header if this is a middle/last msdu */
1988 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1989
1990 /* Reset the order bit as the HT_Control header is stripped */
1991 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1992
1993 qos_ctl = rxcb->tid;
1994
1995 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1996 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1997
1998 /* TODO Add other QoS ctl fields when required */
1999
2000 /* copy decap header before overwriting for reuse below */
2001 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2002 }
2003
2004 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2005 memcpy(skb_push(msdu,
2006 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2007 (void *)hdr + hdr_len,
2008 ath11k_dp_rx_crypto_param_len(ar, enctype));
2009 }
2010
2011 if (!rxcb->is_first_msdu) {
2012 memcpy(skb_push(msdu,
2013 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2014 IEEE80211_QOS_CTL_LEN);
2015 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2016 return;
2017 }
2018
2019 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2020
2021 /* original 802.11 header has a different DA and in
2022 * case of 4addr it may also have different SA
2023 */
2024 hdr = (struct ieee80211_hdr *)msdu->data;
2025 ether_addr_copy(ieee80211_get_DA(hdr), da);
2026 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2027 }
2028
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2029 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2030 enum hal_encrypt_type enctype,
2031 struct ieee80211_rx_status *status,
2032 bool decrypted)
2033 {
2034 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2035 struct ieee80211_hdr *hdr;
2036 size_t hdr_len;
2037 size_t crypto_len;
2038
2039 if (!rxcb->is_first_msdu ||
2040 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2041 WARN_ON_ONCE(1);
2042 return;
2043 }
2044
2045 skb_trim(msdu, msdu->len - FCS_LEN);
2046
2047 if (!decrypted)
2048 return;
2049
2050 hdr = (void *)msdu->data;
2051
2052 /* Tail */
2053 if (status->flag & RX_FLAG_IV_STRIPPED) {
2054 skb_trim(msdu, msdu->len -
2055 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2056
2057 skb_trim(msdu, msdu->len -
2058 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2059 } else {
2060 /* MIC */
2061 if (status->flag & RX_FLAG_MIC_STRIPPED)
2062 skb_trim(msdu, msdu->len -
2063 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2064
2065 /* ICV */
2066 if (status->flag & RX_FLAG_ICV_STRIPPED)
2067 skb_trim(msdu, msdu->len -
2068 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2069 }
2070
2071 /* MMIC */
2072 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2073 !ieee80211_has_morefrags(hdr->frame_control) &&
2074 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2075 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2076
2077 /* Head */
2078 if (status->flag & RX_FLAG_IV_STRIPPED) {
2079 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2080 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2081
2082 memmove((void *)msdu->data + crypto_len,
2083 (void *)msdu->data, hdr_len);
2084 skb_pull(msdu, crypto_len);
2085 }
2086 }
2087
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2088 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2089 struct sk_buff *msdu,
2090 enum hal_encrypt_type enctype)
2091 {
2092 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2093 struct ieee80211_hdr *hdr;
2094 size_t hdr_len, crypto_len;
2095 void *rfc1042;
2096 bool is_amsdu;
2097
2098 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2099 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2100 rfc1042 = hdr;
2101
2102 if (rxcb->is_first_msdu) {
2103 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2104 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2105
2106 rfc1042 += hdr_len + crypto_len;
2107 }
2108
2109 if (is_amsdu)
2110 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2111
2112 return rfc1042;
2113 }
2114
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2115 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2116 struct sk_buff *msdu,
2117 u8 *first_hdr,
2118 enum hal_encrypt_type enctype,
2119 struct ieee80211_rx_status *status)
2120 {
2121 struct ieee80211_hdr *hdr;
2122 struct ethhdr *eth;
2123 size_t hdr_len;
2124 u8 da[ETH_ALEN];
2125 u8 sa[ETH_ALEN];
2126 void *rfc1042;
2127
2128 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2129 if (WARN_ON_ONCE(!rfc1042))
2130 return;
2131
2132 /* pull decapped header and copy SA & DA */
2133 eth = (struct ethhdr *)msdu->data;
2134 ether_addr_copy(da, eth->h_dest);
2135 ether_addr_copy(sa, eth->h_source);
2136 skb_pull(msdu, sizeof(struct ethhdr));
2137
2138 /* push rfc1042/llc/snap */
2139 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2140 sizeof(struct ath11k_dp_rfc1042_hdr));
2141
2142 /* push original 802.11 header */
2143 hdr = (struct ieee80211_hdr *)first_hdr;
2144 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2145
2146 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2147 memcpy(skb_push(msdu,
2148 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2149 (void *)hdr + hdr_len,
2150 ath11k_dp_rx_crypto_param_len(ar, enctype));
2151 }
2152
2153 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2154
2155 /* original 802.11 header has a different DA and in
2156 * case of 4addr it may also have different SA
2157 */
2158 hdr = (struct ieee80211_hdr *)msdu->data;
2159 ether_addr_copy(ieee80211_get_DA(hdr), da);
2160 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2161 }
2162
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2163 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2164 struct hal_rx_desc *rx_desc,
2165 enum hal_encrypt_type enctype,
2166 struct ieee80211_rx_status *status,
2167 bool decrypted)
2168 {
2169 u8 *first_hdr;
2170 u8 decap;
2171 struct ethhdr *ehdr;
2172
2173 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2174 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2175
2176 switch (decap) {
2177 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2178 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2179 enctype, status);
2180 break;
2181 case DP_RX_DECAP_TYPE_RAW:
2182 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2183 decrypted);
2184 break;
2185 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2186 ehdr = (struct ethhdr *)msdu->data;
2187
2188 /* mac80211 allows fast path only for authorized STA */
2189 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2190 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2191 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2192 enctype, status);
2193 break;
2194 }
2195
2196 /* PN for mcast packets will be validated in mac80211;
2197 * remove eth header and add 802.11 header.
2198 */
2199 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2200 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2201 enctype, status);
2202 break;
2203 case DP_RX_DECAP_TYPE_8023:
2204 /* TODO: Handle undecap for these formats */
2205 break;
2206 }
2207 }
2208
2209 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2210 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2211 {
2212 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2213 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2214 struct ath11k_peer *peer = NULL;
2215
2216 lockdep_assert_held(&ab->base_lock);
2217
2218 if (rxcb->peer_id)
2219 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2220
2221 if (peer)
2222 return peer;
2223
2224 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2225 return NULL;
2226
2227 peer = ath11k_peer_find_by_addr(ab,
2228 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2229 return peer;
2230 }
2231
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2232 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2233 struct sk_buff *msdu,
2234 struct hal_rx_desc *rx_desc,
2235 struct ieee80211_rx_status *rx_status)
2236 {
2237 bool fill_crypto_hdr;
2238 enum hal_encrypt_type enctype;
2239 bool is_decrypted = false;
2240 struct ath11k_skb_rxcb *rxcb;
2241 struct ieee80211_hdr *hdr;
2242 struct ath11k_peer *peer;
2243 struct rx_attention *rx_attention;
2244 u32 err_bitmap;
2245
2246 /* PN for multicast packets will be checked in mac80211 */
2247 rxcb = ATH11K_SKB_RXCB(msdu);
2248 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2249 rxcb->is_mcbc = fill_crypto_hdr;
2250
2251 if (rxcb->is_mcbc) {
2252 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2253 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2254 }
2255
2256 spin_lock_bh(&ar->ab->base_lock);
2257 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2258 if (peer) {
2259 if (rxcb->is_mcbc)
2260 enctype = peer->sec_type_grp;
2261 else
2262 enctype = peer->sec_type;
2263 } else {
2264 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2265 }
2266 spin_unlock_bh(&ar->ab->base_lock);
2267
2268 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2269 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2270 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2271 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2272
2273 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2274 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2275 RX_FLAG_MMIC_ERROR |
2276 RX_FLAG_DECRYPTED |
2277 RX_FLAG_IV_STRIPPED |
2278 RX_FLAG_MMIC_STRIPPED);
2279
2280 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2281 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2282 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2283 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2284
2285 if (is_decrypted) {
2286 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2287
2288 if (fill_crypto_hdr)
2289 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2290 RX_FLAG_ICV_STRIPPED;
2291 else
2292 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2293 RX_FLAG_PN_VALIDATED;
2294 }
2295
2296 ath11k_dp_rx_h_csum_offload(ar, msdu);
2297 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2298 enctype, rx_status, is_decrypted);
2299
2300 if (!is_decrypted || fill_crypto_hdr)
2301 return;
2302
2303 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2304 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2305 hdr = (void *)msdu->data;
2306 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2307 }
2308 }
2309
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2310 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2311 struct ieee80211_rx_status *rx_status)
2312 {
2313 struct ieee80211_supported_band *sband;
2314 enum rx_msdu_start_pkt_type pkt_type;
2315 u8 bw;
2316 u8 rate_mcs, nss;
2317 u8 sgi;
2318 bool is_cck, is_ldpc;
2319
2320 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2321 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2322 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2323 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2324 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2325
2326 switch (pkt_type) {
2327 case RX_MSDU_START_PKT_TYPE_11A:
2328 case RX_MSDU_START_PKT_TYPE_11B:
2329 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2330 sband = &ar->mac.sbands[rx_status->band];
2331 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2332 is_cck);
2333 break;
2334 case RX_MSDU_START_PKT_TYPE_11N:
2335 rx_status->encoding = RX_ENC_HT;
2336 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2337 ath11k_warn(ar->ab,
2338 "Received with invalid mcs in HT mode %d\n",
2339 rate_mcs);
2340 break;
2341 }
2342 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2343 if (sgi)
2344 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2345 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2346 break;
2347 case RX_MSDU_START_PKT_TYPE_11AC:
2348 rx_status->encoding = RX_ENC_VHT;
2349 rx_status->rate_idx = rate_mcs;
2350 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2351 ath11k_warn(ar->ab,
2352 "Received with invalid mcs in VHT mode %d\n",
2353 rate_mcs);
2354 break;
2355 }
2356 rx_status->nss = nss;
2357 if (sgi)
2358 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2359 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2360 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2361 if (is_ldpc)
2362 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2363 break;
2364 case RX_MSDU_START_PKT_TYPE_11AX:
2365 rx_status->rate_idx = rate_mcs;
2366 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2367 ath11k_warn(ar->ab,
2368 "Received with invalid mcs in HE mode %d\n",
2369 rate_mcs);
2370 break;
2371 }
2372 rx_status->encoding = RX_ENC_HE;
2373 rx_status->nss = nss;
2374 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2375 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2376 break;
2377 }
2378 }
2379
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2380 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2381 struct ieee80211_rx_status *rx_status)
2382 {
2383 u8 channel_num;
2384 u32 center_freq, meta_data;
2385 struct ieee80211_channel *channel;
2386
2387 rx_status->freq = 0;
2388 rx_status->rate_idx = 0;
2389 rx_status->nss = 0;
2390 rx_status->encoding = RX_ENC_LEGACY;
2391 rx_status->bw = RATE_INFO_BW_20;
2392
2393 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2394
2395 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2396 channel_num = meta_data;
2397 center_freq = meta_data >> 16;
2398
2399 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2400 center_freq <= ATH11K_MAX_6G_FREQ) {
2401 rx_status->band = NL80211_BAND_6GHZ;
2402 rx_status->freq = center_freq;
2403 } else if (channel_num >= 1 && channel_num <= 14) {
2404 rx_status->band = NL80211_BAND_2GHZ;
2405 } else if (channel_num >= 36 && channel_num <= 177) {
2406 rx_status->band = NL80211_BAND_5GHZ;
2407 } else {
2408 spin_lock_bh(&ar->data_lock);
2409 channel = ar->rx_channel;
2410 if (channel) {
2411 rx_status->band = channel->band;
2412 channel_num =
2413 ieee80211_frequency_to_channel(channel->center_freq);
2414 }
2415 spin_unlock_bh(&ar->data_lock);
2416 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2417 rx_desc, sizeof(struct hal_rx_desc));
2418 }
2419
2420 if (rx_status->band != NL80211_BAND_6GHZ)
2421 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2422 rx_status->band);
2423
2424 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2425 }
2426
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2427 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2428 struct sk_buff *msdu,
2429 struct ieee80211_rx_status *status)
2430 {
2431 static const struct ieee80211_radiotap_he known = {
2432 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2433 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2434 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2435 };
2436 struct ieee80211_rx_status *rx_status;
2437 struct ieee80211_radiotap_he *he = NULL;
2438 struct ieee80211_sta *pubsta = NULL;
2439 struct ath11k_peer *peer;
2440 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2441 u8 decap = DP_RX_DECAP_TYPE_RAW;
2442 bool is_mcbc = rxcb->is_mcbc;
2443 bool is_eapol = rxcb->is_eapol;
2444
2445 if (status->encoding == RX_ENC_HE &&
2446 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2447 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2448 he = skb_push(msdu, sizeof(known));
2449 memcpy(he, &known, sizeof(known));
2450 status->flag |= RX_FLAG_RADIOTAP_HE;
2451 }
2452
2453 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2454 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2455
2456 spin_lock_bh(&ar->ab->base_lock);
2457 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2458 if (peer && peer->sta)
2459 pubsta = peer->sta;
2460 spin_unlock_bh(&ar->ab->base_lock);
2461
2462 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2463 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2464 msdu,
2465 msdu->len,
2466 peer ? peer->addr : NULL,
2467 rxcb->tid,
2468 is_mcbc ? "mcast" : "ucast",
2469 rxcb->seq_no,
2470 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2471 (status->encoding == RX_ENC_HT) ? "ht" : "",
2472 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2473 (status->encoding == RX_ENC_HE) ? "he" : "",
2474 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2475 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2476 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2477 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2478 status->rate_idx,
2479 status->nss,
2480 status->freq,
2481 status->band, status->flag,
2482 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2483 !!(status->flag & RX_FLAG_MMIC_ERROR),
2484 !!(status->flag & RX_FLAG_AMSDU_MORE));
2485
2486 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2487 msdu->data, msdu->len);
2488
2489 rx_status = IEEE80211_SKB_RXCB(msdu);
2490 *rx_status = *status;
2491
2492 /* TODO: trace rx packet */
2493
2494 /* PN for multicast packets are not validate in HW,
2495 * so skip 802.3 rx path
2496 * Also, fast_rx expects the STA to be authorized, hence
2497 * eapol packets are sent in slow path.
2498 */
2499 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2500 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2501 rx_status->flag |= RX_FLAG_8023;
2502
2503 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2504 }
2505
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2506 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2507 struct sk_buff *msdu,
2508 struct sk_buff_head *msdu_list,
2509 struct ieee80211_rx_status *rx_status)
2510 {
2511 struct ath11k_base *ab = ar->ab;
2512 struct hal_rx_desc *rx_desc, *lrx_desc;
2513 struct rx_attention *rx_attention;
2514 struct ath11k_skb_rxcb *rxcb;
2515 struct sk_buff *last_buf;
2516 u8 l3_pad_bytes;
2517 u8 *hdr_status;
2518 u16 msdu_len;
2519 int ret;
2520 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2521
2522 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2523 if (!last_buf) {
2524 ath11k_warn(ab,
2525 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2526 ret = -EIO;
2527 goto free_out;
2528 }
2529
2530 rx_desc = (struct hal_rx_desc *)msdu->data;
2531 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2532 ath11k_warn(ar->ab, "msdu len not valid\n");
2533 ret = -EIO;
2534 goto free_out;
2535 }
2536
2537 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2538 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2539 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2540 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2541 ret = -EIO;
2542 goto free_out;
2543 }
2544
2545 rxcb = ATH11K_SKB_RXCB(msdu);
2546 rxcb->rx_desc = rx_desc;
2547 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2548 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2549
2550 if (rxcb->is_frag) {
2551 skb_pull(msdu, hal_rx_desc_sz);
2552 } else if (!rxcb->is_continuation) {
2553 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2554 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2555 ret = -EINVAL;
2556 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2557 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2558 sizeof(struct ieee80211_hdr));
2559 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2560 sizeof(struct hal_rx_desc));
2561 goto free_out;
2562 }
2563 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2564 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2565 } else {
2566 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2567 msdu, last_buf,
2568 l3_pad_bytes, msdu_len);
2569 if (ret) {
2570 ath11k_warn(ab,
2571 "failed to coalesce msdu rx buffer%d\n", ret);
2572 goto free_out;
2573 }
2574 }
2575
2576 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2577 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2578
2579 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2580
2581 return 0;
2582
2583 free_out:
2584 return ret;
2585 }
2586
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2587 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2588 struct napi_struct *napi,
2589 struct sk_buff_head *msdu_list,
2590 int mac_id)
2591 {
2592 struct sk_buff *msdu;
2593 struct ath11k *ar;
2594 struct ieee80211_rx_status rx_status = {0};
2595 int ret;
2596
2597 if (skb_queue_empty(msdu_list))
2598 return;
2599
2600 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2601 __skb_queue_purge(msdu_list);
2602 return;
2603 }
2604
2605 ar = ab->pdevs[mac_id].ar;
2606 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2607 __skb_queue_purge(msdu_list);
2608 return;
2609 }
2610
2611 while ((msdu = __skb_dequeue(msdu_list))) {
2612 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2613 if (unlikely(ret)) {
2614 ath11k_dbg(ab, ATH11K_DBG_DATA,
2615 "Unable to process msdu %d", ret);
2616 dev_kfree_skb_any(msdu);
2617 continue;
2618 }
2619
2620 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2621 }
2622 }
2623
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2624 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2625 struct napi_struct *napi, int budget)
2626 {
2627 struct ath11k_dp *dp = &ab->dp;
2628 struct dp_rxdma_ring *rx_ring;
2629 int num_buffs_reaped[MAX_RADIOS] = {0};
2630 struct sk_buff_head msdu_list[MAX_RADIOS];
2631 struct ath11k_skb_rxcb *rxcb;
2632 int total_msdu_reaped = 0;
2633 struct hal_srng *srng;
2634 struct sk_buff *msdu;
2635 bool done = false;
2636 int buf_id, mac_id;
2637 struct ath11k *ar;
2638 struct hal_reo_dest_ring *desc;
2639 enum hal_reo_dest_ring_push_reason push_reason;
2640 u32 cookie, info0, rx_msdu_info0, rx_mpdu_info0;
2641 int i;
2642
2643 for (i = 0; i < MAX_RADIOS; i++)
2644 __skb_queue_head_init(&msdu_list[i]);
2645
2646 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2647
2648 spin_lock_bh(&srng->lock);
2649
2650 try_again:
2651 ath11k_hal_srng_access_begin(ab, srng);
2652
2653 while (likely(desc =
2654 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2655 srng))) {
2656 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2657 READ_ONCE(desc->buf_addr_info.info1));
2658 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2659 cookie);
2660 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2661
2662 if (unlikely(buf_id == 0))
2663 continue;
2664
2665 ar = ab->pdevs[mac_id].ar;
2666 rx_ring = &ar->dp.rx_refill_buf_ring;
2667 spin_lock_bh(&rx_ring->idr_lock);
2668 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2669 if (unlikely(!msdu)) {
2670 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2671 buf_id);
2672 spin_unlock_bh(&rx_ring->idr_lock);
2673 continue;
2674 }
2675
2676 idr_remove(&rx_ring->bufs_idr, buf_id);
2677 spin_unlock_bh(&rx_ring->idr_lock);
2678
2679 rxcb = ATH11K_SKB_RXCB(msdu);
2680 dma_unmap_single(ab->dev, rxcb->paddr,
2681 msdu->len + skb_tailroom(msdu),
2682 DMA_FROM_DEVICE);
2683
2684 num_buffs_reaped[mac_id]++;
2685
2686 info0 = READ_ONCE(desc->info0);
2687 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2688 info0);
2689 if (unlikely(push_reason !=
2690 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2691 dev_kfree_skb_any(msdu);
2692 ab->soc_stats.hal_reo_error[ring_id]++;
2693 continue;
2694 }
2695
2696 rx_msdu_info0 = READ_ONCE(desc->rx_msdu_info.info0);
2697 rx_mpdu_info0 = READ_ONCE(desc->rx_mpdu_info.info0);
2698
2699 rxcb->is_first_msdu = !!(rx_msdu_info0 &
2700 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2701 rxcb->is_last_msdu = !!(rx_msdu_info0 &
2702 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2703 rxcb->is_continuation = !!(rx_msdu_info0 &
2704 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2705 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2706 READ_ONCE(desc->rx_mpdu_info.meta_data));
2707 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2708 rx_mpdu_info0);
2709 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2710 info0);
2711
2712 rxcb->mac_id = mac_id;
2713 __skb_queue_tail(&msdu_list[mac_id], msdu);
2714
2715 if (rxcb->is_continuation) {
2716 done = false;
2717 } else {
2718 total_msdu_reaped++;
2719 done = true;
2720 }
2721
2722 if (total_msdu_reaped >= budget)
2723 break;
2724 }
2725
2726 /* Hw might have updated the head pointer after we cached it.
2727 * In this case, even though there are entries in the ring we'll
2728 * get rx_desc NULL. Give the read another try with updated cached
2729 * head pointer so that we can reap complete MPDU in the current
2730 * rx processing.
2731 */
2732 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2733 ath11k_hal_srng_access_end(ab, srng);
2734 goto try_again;
2735 }
2736
2737 ath11k_hal_srng_access_end(ab, srng);
2738
2739 spin_unlock_bh(&srng->lock);
2740
2741 if (unlikely(!total_msdu_reaped))
2742 goto exit;
2743
2744 for (i = 0; i < ab->num_radios; i++) {
2745 if (!num_buffs_reaped[i])
2746 continue;
2747
2748 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2749
2750 ar = ab->pdevs[i].ar;
2751 rx_ring = &ar->dp.rx_refill_buf_ring;
2752
2753 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2754 ab->hw_params.hal_params->rx_buf_rbm);
2755 }
2756 exit:
2757 return total_msdu_reaped;
2758 }
2759
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2760 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2761 struct hal_rx_mon_ppdu_info *ppdu_info)
2762 {
2763 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2764 u32 num_msdu;
2765 int i;
2766
2767 if (!rx_stats)
2768 return;
2769
2770 arsta->rssi_comb = ppdu_info->rssi_comb;
2771 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2772
2773 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2774 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2775
2776 rx_stats->num_msdu += num_msdu;
2777 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2778 ppdu_info->tcp_ack_msdu_count;
2779 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2780 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2781
2782 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2783 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2784 ppdu_info->nss = 1;
2785 ppdu_info->mcs = HAL_RX_MAX_MCS;
2786 ppdu_info->tid = IEEE80211_NUM_TIDS;
2787 }
2788
2789 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2790 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2791
2792 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2793 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2794
2795 if (ppdu_info->gi < HAL_RX_GI_MAX)
2796 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2797
2798 if (ppdu_info->bw < HAL_RX_BW_MAX)
2799 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2800
2801 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2802 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2803
2804 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2805 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2806
2807 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2808 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2809
2810 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2811 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2812
2813 if (ppdu_info->is_stbc)
2814 rx_stats->stbc_count += num_msdu;
2815
2816 if (ppdu_info->beamformed)
2817 rx_stats->beamformed_count += num_msdu;
2818
2819 if (ppdu_info->num_mpdu_fcs_ok > 1)
2820 rx_stats->ampdu_msdu_count += num_msdu;
2821 else
2822 rx_stats->non_ampdu_msdu_count += num_msdu;
2823
2824 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2825 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2826 rx_stats->dcm_count += ppdu_info->dcm;
2827 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2828
2829 arsta->rssi_comb = ppdu_info->rssi_comb;
2830
2831 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2832 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2833
2834 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2835 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2836
2837 rx_stats->rx_duration += ppdu_info->rx_duration;
2838 arsta->rx_duration = rx_stats->rx_duration;
2839 }
2840
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2841 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2842 struct dp_rxdma_ring *rx_ring,
2843 int *buf_id)
2844 {
2845 struct sk_buff *skb;
2846 dma_addr_t paddr;
2847
2848 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2849 DP_RX_BUFFER_ALIGN_SIZE);
2850
2851 if (!skb)
2852 goto fail_alloc_skb;
2853
2854 if (!IS_ALIGNED((unsigned long)skb->data,
2855 DP_RX_BUFFER_ALIGN_SIZE)) {
2856 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2857 skb->data);
2858 }
2859
2860 paddr = dma_map_single(ab->dev, skb->data,
2861 skb->len + skb_tailroom(skb),
2862 DMA_FROM_DEVICE);
2863 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2864 goto fail_free_skb;
2865
2866 spin_lock_bh(&rx_ring->idr_lock);
2867 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2868 rx_ring->bufs_max, GFP_ATOMIC);
2869 spin_unlock_bh(&rx_ring->idr_lock);
2870 if (*buf_id < 0)
2871 goto fail_dma_unmap;
2872
2873 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2874 return skb;
2875
2876 fail_dma_unmap:
2877 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2878 DMA_FROM_DEVICE);
2879 fail_free_skb:
2880 dev_kfree_skb_any(skb);
2881 fail_alloc_skb:
2882 return NULL;
2883 }
2884
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2885 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2886 struct dp_rxdma_ring *rx_ring,
2887 int req_entries,
2888 enum hal_rx_buf_return_buf_manager mgr)
2889 {
2890 struct hal_srng *srng;
2891 u32 *desc;
2892 struct sk_buff *skb;
2893 int num_free;
2894 int num_remain;
2895 int buf_id;
2896 u32 cookie;
2897 dma_addr_t paddr;
2898
2899 req_entries = min(req_entries, rx_ring->bufs_max);
2900
2901 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2902
2903 spin_lock_bh(&srng->lock);
2904
2905 ath11k_hal_srng_access_begin(ab, srng);
2906
2907 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2908
2909 req_entries = min(num_free, req_entries);
2910 num_remain = req_entries;
2911
2912 while (num_remain > 0) {
2913 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2914 &buf_id);
2915 if (!skb)
2916 break;
2917 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2918
2919 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2920 if (!desc)
2921 goto fail_desc_get;
2922
2923 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2924 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2925
2926 num_remain--;
2927
2928 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2929 }
2930
2931 ath11k_hal_srng_access_end(ab, srng);
2932
2933 spin_unlock_bh(&srng->lock);
2934
2935 return req_entries - num_remain;
2936
2937 fail_desc_get:
2938 spin_lock_bh(&rx_ring->idr_lock);
2939 idr_remove(&rx_ring->bufs_idr, buf_id);
2940 spin_unlock_bh(&rx_ring->idr_lock);
2941 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2942 DMA_FROM_DEVICE);
2943 dev_kfree_skb_any(skb);
2944 ath11k_hal_srng_access_end(ab, srng);
2945 spin_unlock_bh(&srng->lock);
2946
2947 return req_entries - num_remain;
2948 }
2949
2950 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2951
2952 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2953 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2954 struct hal_tlv_hdr *tlv)
2955 {
2956 struct hal_rx_ppdu_start *ppdu_start;
2957 u16 ppdu_id_diff, ppdu_id, tlv_len;
2958 u8 *ptr;
2959
2960 /* PPDU id is part of second tlv, move ptr to second tlv */
2961 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2962 ptr = (u8 *)tlv;
2963 ptr += sizeof(*tlv) + tlv_len;
2964 tlv = (struct hal_tlv_hdr *)ptr;
2965
2966 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2967 return;
2968
2969 ptr += sizeof(*tlv);
2970 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2971 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2972 __le32_to_cpu(ppdu_start->info0));
2973
2974 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2975 pmon->buf_state = DP_MON_STATUS_LEAD;
2976 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2977 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2978 pmon->buf_state = DP_MON_STATUS_LAG;
2979 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2980 pmon->buf_state = DP_MON_STATUS_LAG;
2981 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2982 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2983 pmon->buf_state = DP_MON_STATUS_LEAD;
2984 }
2985 }
2986
2987 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)2988 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
2989 struct dp_rxdma_ring *rx_ring)
2990 {
2991 struct ath11k_skb_rxcb *rxcb;
2992 struct hal_tlv_hdr *tlv;
2993 struct sk_buff *skb;
2994 void *status_desc;
2995 dma_addr_t paddr;
2996 u32 cookie;
2997 int buf_id;
2998 u8 rbm;
2999
3000 status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
3001 if (!status_desc)
3002 return DP_MON_STATUS_NO_DMA;
3003
3004 ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
3005
3006 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3007
3008 spin_lock_bh(&rx_ring->idr_lock);
3009 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3010 spin_unlock_bh(&rx_ring->idr_lock);
3011
3012 if (!skb)
3013 return DP_MON_STATUS_NO_DMA;
3014
3015 rxcb = ATH11K_SKB_RXCB(skb);
3016 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3017 skb->len + skb_tailroom(skb),
3018 DMA_FROM_DEVICE);
3019
3020 tlv = (struct hal_tlv_hdr *)skb->data;
3021 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3022 return DP_MON_STATUS_NO_DMA;
3023
3024 return DP_MON_STATUS_REPLINISH;
3025 }
3026
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3027 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3028 int *budget, struct sk_buff_head *skb_list)
3029 {
3030 struct ath11k *ar;
3031 const struct ath11k_hw_hal_params *hal_params;
3032 enum dp_mon_status_buf_state reap_status;
3033 struct ath11k_pdev_dp *dp;
3034 struct dp_rxdma_ring *rx_ring;
3035 struct ath11k_mon_data *pmon;
3036 struct hal_srng *srng;
3037 void *rx_mon_status_desc;
3038 struct sk_buff *skb;
3039 struct ath11k_skb_rxcb *rxcb;
3040 struct hal_tlv_hdr *tlv;
3041 u32 cookie;
3042 int buf_id, srng_id;
3043 dma_addr_t paddr;
3044 u8 rbm;
3045 int num_buffs_reaped = 0;
3046
3047 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3048 dp = &ar->dp;
3049 pmon = &dp->mon_data;
3050 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3051 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3052
3053 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3054
3055 spin_lock_bh(&srng->lock);
3056
3057 ath11k_hal_srng_access_begin(ab, srng);
3058 while (*budget) {
3059 *budget -= 1;
3060 rx_mon_status_desc =
3061 ath11k_hal_srng_src_peek(ab, srng);
3062 if (!rx_mon_status_desc) {
3063 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3064 break;
3065 }
3066
3067 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3068 &cookie, &rbm);
3069 if (paddr) {
3070 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3071
3072 spin_lock_bh(&rx_ring->idr_lock);
3073 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3074 spin_unlock_bh(&rx_ring->idr_lock);
3075
3076 if (!skb) {
3077 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3078 buf_id);
3079 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3080 goto move_next;
3081 }
3082
3083 rxcb = ATH11K_SKB_RXCB(skb);
3084
3085 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3086 skb->len + skb_tailroom(skb),
3087 DMA_FROM_DEVICE);
3088
3089 tlv = (struct hal_tlv_hdr *)skb->data;
3090 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3091 HAL_RX_STATUS_BUFFER_DONE) {
3092 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3093 FIELD_GET(HAL_TLV_HDR_TAG,
3094 tlv->tl), buf_id);
3095 /* RxDMA status done bit might not be set even
3096 * though tp is moved by HW.
3097 */
3098
3099 /* If done status is missing:
3100 * 1. As per MAC team's suggestion,
3101 * when HP + 1 entry is peeked and if DMA
3102 * is not done and if HP + 2 entry's DMA done
3103 * is set. skip HP + 1 entry and
3104 * start processing in next interrupt.
3105 * 2. If HP + 2 entry's DMA done is not set,
3106 * poll onto HP + 1 entry DMA done to be set.
3107 * Check status for same buffer for next time
3108 * dp_rx_mon_status_srng_process
3109 */
3110
3111 reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3112 rx_ring);
3113 if (reap_status == DP_MON_STATUS_NO_DMA)
3114 continue;
3115
3116 spin_lock_bh(&rx_ring->idr_lock);
3117 idr_remove(&rx_ring->bufs_idr, buf_id);
3118 spin_unlock_bh(&rx_ring->idr_lock);
3119
3120 dma_unmap_single(ab->dev, rxcb->paddr,
3121 skb->len + skb_tailroom(skb),
3122 DMA_FROM_DEVICE);
3123
3124 dev_kfree_skb_any(skb);
3125 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3126 goto move_next;
3127 }
3128
3129 spin_lock_bh(&rx_ring->idr_lock);
3130 idr_remove(&rx_ring->bufs_idr, buf_id);
3131 spin_unlock_bh(&rx_ring->idr_lock);
3132 if (ab->hw_params.full_monitor_mode) {
3133 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3134 if (paddr == pmon->mon_status_paddr)
3135 pmon->buf_state = DP_MON_STATUS_MATCH;
3136 }
3137
3138 dma_unmap_single(ab->dev, rxcb->paddr,
3139 skb->len + skb_tailroom(skb),
3140 DMA_FROM_DEVICE);
3141
3142 __skb_queue_tail(skb_list, skb);
3143 } else {
3144 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3145 }
3146 move_next:
3147 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3148 &buf_id);
3149
3150 if (!skb) {
3151 hal_params = ab->hw_params.hal_params;
3152 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3153 hal_params->rx_buf_rbm);
3154 num_buffs_reaped++;
3155 break;
3156 }
3157 rxcb = ATH11K_SKB_RXCB(skb);
3158
3159 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3160 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3161
3162 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3163 cookie,
3164 ab->hw_params.hal_params->rx_buf_rbm);
3165 ath11k_hal_srng_src_get_next_entry(ab, srng);
3166 num_buffs_reaped++;
3167 }
3168 ath11k_hal_srng_access_end(ab, srng);
3169 spin_unlock_bh(&srng->lock);
3170
3171 return num_buffs_reaped;
3172 }
3173
ath11k_dp_rx_frag_timer(struct timer_list * timer)3174 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3175 {
3176 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3177
3178 spin_lock_bh(&rx_tid->ab->base_lock);
3179 if (rx_tid->last_frag_no &&
3180 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3181 spin_unlock_bh(&rx_tid->ab->base_lock);
3182 return;
3183 }
3184 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3185 spin_unlock_bh(&rx_tid->ab->base_lock);
3186 }
3187
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3188 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3189 {
3190 struct ath11k_base *ab = ar->ab;
3191 struct crypto_shash *tfm;
3192 struct ath11k_peer *peer;
3193 struct dp_rx_tid *rx_tid;
3194 int i;
3195
3196 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3197 if (IS_ERR(tfm)) {
3198 ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3199 PTR_ERR(tfm));
3200 return PTR_ERR(tfm);
3201 }
3202
3203 spin_lock_bh(&ab->base_lock);
3204
3205 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3206 if (!peer) {
3207 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3208 spin_unlock_bh(&ab->base_lock);
3209 crypto_free_shash(tfm);
3210 return -ENOENT;
3211 }
3212
3213 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3214 rx_tid = &peer->rx_tid[i];
3215 rx_tid->ab = ab;
3216 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3217 skb_queue_head_init(&rx_tid->rx_frags);
3218 }
3219
3220 peer->tfm_mmic = tfm;
3221 peer->dp_setup_done = true;
3222 spin_unlock_bh(&ab->base_lock);
3223
3224 return 0;
3225 }
3226
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3227 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3228 struct ieee80211_hdr *hdr, u8 *data,
3229 size_t data_len, u8 *mic)
3230 {
3231 SHASH_DESC_ON_STACK(desc, tfm);
3232 u8 mic_hdr[16] = {0};
3233 u8 tid = 0;
3234 int ret;
3235
3236 if (!tfm)
3237 return -EINVAL;
3238
3239 desc->tfm = tfm;
3240
3241 ret = crypto_shash_setkey(tfm, key, 8);
3242 if (ret)
3243 goto out;
3244
3245 ret = crypto_shash_init(desc);
3246 if (ret)
3247 goto out;
3248
3249 /* TKIP MIC header */
3250 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3251 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3252 if (ieee80211_is_data_qos(hdr->frame_control))
3253 tid = ieee80211_get_tid(hdr);
3254 mic_hdr[12] = tid;
3255
3256 ret = crypto_shash_update(desc, mic_hdr, 16);
3257 if (ret)
3258 goto out;
3259 ret = crypto_shash_update(desc, data, data_len);
3260 if (ret)
3261 goto out;
3262 ret = crypto_shash_final(desc, mic);
3263 out:
3264 shash_desc_zero(desc);
3265 return ret;
3266 }
3267
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3268 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3269 struct sk_buff *msdu)
3270 {
3271 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3272 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3273 struct ieee80211_key_conf *key_conf;
3274 struct ieee80211_hdr *hdr;
3275 u8 mic[IEEE80211_CCMP_MIC_LEN];
3276 int head_len, tail_len, ret;
3277 size_t data_len;
3278 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3279 u8 *key, *data;
3280 u8 key_idx;
3281
3282 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3283 HAL_ENCRYPT_TYPE_TKIP_MIC)
3284 return 0;
3285
3286 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3287 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3288 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3289 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3290
3291 if (!is_multicast_ether_addr(hdr->addr1))
3292 key_idx = peer->ucast_keyidx;
3293 else
3294 key_idx = peer->mcast_keyidx;
3295
3296 key_conf = peer->keys[key_idx];
3297
3298 data = msdu->data + head_len;
3299 data_len = msdu->len - head_len - tail_len;
3300 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3301
3302 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3303 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3304 goto mic_fail;
3305
3306 return 0;
3307
3308 mic_fail:
3309 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3310 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3311
3312 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3313 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3314 skb_pull(msdu, hal_rx_desc_sz);
3315
3316 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3317 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3318 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3319 ieee80211_rx(ar->hw, msdu);
3320 return -EINVAL;
3321 }
3322
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3323 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3324 enum hal_encrypt_type enctype, u32 flags)
3325 {
3326 struct ieee80211_hdr *hdr;
3327 size_t hdr_len;
3328 size_t crypto_len;
3329 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3330
3331 if (!flags)
3332 return;
3333
3334 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3335
3336 if (flags & RX_FLAG_MIC_STRIPPED)
3337 skb_trim(msdu, msdu->len -
3338 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3339
3340 if (flags & RX_FLAG_ICV_STRIPPED)
3341 skb_trim(msdu, msdu->len -
3342 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3343
3344 if (flags & RX_FLAG_IV_STRIPPED) {
3345 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3346 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3347
3348 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3349 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3350 skb_pull(msdu, crypto_len);
3351 }
3352 }
3353
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3354 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3355 struct ath11k_peer *peer,
3356 struct dp_rx_tid *rx_tid,
3357 struct sk_buff **defrag_skb)
3358 {
3359 struct hal_rx_desc *rx_desc;
3360 struct sk_buff *skb, *first_frag, *last_frag;
3361 struct ieee80211_hdr *hdr;
3362 struct rx_attention *rx_attention;
3363 enum hal_encrypt_type enctype;
3364 bool is_decrypted = false;
3365 int msdu_len = 0;
3366 int extra_space;
3367 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3368
3369 first_frag = skb_peek(&rx_tid->rx_frags);
3370 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3371
3372 skb_queue_walk(&rx_tid->rx_frags, skb) {
3373 flags = 0;
3374 rx_desc = (struct hal_rx_desc *)skb->data;
3375 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3376
3377 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3378 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3379 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3380 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3381 }
3382
3383 if (is_decrypted) {
3384 if (skb != first_frag)
3385 flags |= RX_FLAG_IV_STRIPPED;
3386 if (skb != last_frag)
3387 flags |= RX_FLAG_ICV_STRIPPED |
3388 RX_FLAG_MIC_STRIPPED;
3389 }
3390
3391 /* RX fragments are always raw packets */
3392 if (skb != last_frag)
3393 skb_trim(skb, skb->len - FCS_LEN);
3394 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3395
3396 if (skb != first_frag)
3397 skb_pull(skb, hal_rx_desc_sz +
3398 ieee80211_hdrlen(hdr->frame_control));
3399 msdu_len += skb->len;
3400 }
3401
3402 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3403 if (extra_space > 0 &&
3404 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3405 return -ENOMEM;
3406
3407 __skb_unlink(first_frag, &rx_tid->rx_frags);
3408 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3409 skb_put_data(first_frag, skb->data, skb->len);
3410 dev_kfree_skb_any(skb);
3411 }
3412
3413 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3414 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3415 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3416
3417 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3418 first_frag = NULL;
3419
3420 *defrag_skb = first_frag;
3421 return 0;
3422 }
3423
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3424 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3425 struct sk_buff *defrag_skb)
3426 {
3427 struct ath11k_base *ab = ar->ab;
3428 struct ath11k_pdev_dp *dp = &ar->dp;
3429 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3430 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3431 struct hal_reo_entrance_ring *reo_ent_ring;
3432 struct hal_reo_dest_ring *reo_dest_ring;
3433 struct dp_link_desc_bank *link_desc_banks;
3434 struct hal_rx_msdu_link *msdu_link;
3435 struct hal_rx_msdu_details *msdu0;
3436 struct hal_srng *srng;
3437 dma_addr_t paddr;
3438 u32 desc_bank, msdu_info, mpdu_info;
3439 u32 dst_idx, cookie, hal_rx_desc_sz;
3440 int ret, buf_id;
3441
3442 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3443 link_desc_banks = ab->dp.link_desc_banks;
3444 reo_dest_ring = rx_tid->dst_ring_desc;
3445
3446 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3447 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3448 (paddr - link_desc_banks[desc_bank].paddr));
3449 msdu0 = &msdu_link->msdu_link[0];
3450 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3451 memset(msdu0, 0, sizeof(*msdu0));
3452
3453 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3454 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3455 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3456 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3457 defrag_skb->len - hal_rx_desc_sz) |
3458 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3459 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3460 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3461 msdu0->rx_msdu_info.info0 = msdu_info;
3462
3463 /* change msdu len in hal rx desc */
3464 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3465
3466 paddr = dma_map_single(ab->dev, defrag_skb->data,
3467 defrag_skb->len + skb_tailroom(defrag_skb),
3468 DMA_TO_DEVICE);
3469 if (dma_mapping_error(ab->dev, paddr))
3470 return -ENOMEM;
3471
3472 spin_lock_bh(&rx_refill_ring->idr_lock);
3473 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3474 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3475 spin_unlock_bh(&rx_refill_ring->idr_lock);
3476 if (buf_id < 0) {
3477 ret = -ENOMEM;
3478 goto err_unmap_dma;
3479 }
3480
3481 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3482 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3483 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3484
3485 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3486 ab->hw_params.hal_params->rx_buf_rbm);
3487
3488 /* Fill mpdu details into reo entrance ring */
3489 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3490
3491 spin_lock_bh(&srng->lock);
3492 ath11k_hal_srng_access_begin(ab, srng);
3493
3494 reo_ent_ring = (struct hal_reo_entrance_ring *)
3495 ath11k_hal_srng_src_get_next_entry(ab, srng);
3496 if (!reo_ent_ring) {
3497 ath11k_hal_srng_access_end(ab, srng);
3498 spin_unlock_bh(&srng->lock);
3499 ret = -ENOSPC;
3500 goto err_free_idr;
3501 }
3502 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3503
3504 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3505 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3506 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3507
3508 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3509 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3510 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3511 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3512 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3513 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3514 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3515
3516 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3517 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3518 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3519 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3520 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3521 reo_dest_ring->info0)) |
3522 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3523 ath11k_hal_srng_access_end(ab, srng);
3524 spin_unlock_bh(&srng->lock);
3525
3526 return 0;
3527
3528 err_free_idr:
3529 spin_lock_bh(&rx_refill_ring->idr_lock);
3530 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3531 spin_unlock_bh(&rx_refill_ring->idr_lock);
3532 err_unmap_dma:
3533 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3534 DMA_TO_DEVICE);
3535 return ret;
3536 }
3537
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3538 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3539 struct sk_buff *a, struct sk_buff *b)
3540 {
3541 int frag1, frag2;
3542
3543 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3544 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3545
3546 return frag1 - frag2;
3547 }
3548
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3549 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3550 struct sk_buff_head *frag_list,
3551 struct sk_buff *cur_frag)
3552 {
3553 struct sk_buff *skb;
3554 int cmp;
3555
3556 skb_queue_walk(frag_list, skb) {
3557 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3558 if (cmp < 0)
3559 continue;
3560 __skb_queue_before(frag_list, skb, cur_frag);
3561 return;
3562 }
3563 __skb_queue_tail(frag_list, cur_frag);
3564 }
3565
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3566 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3567 {
3568 struct ieee80211_hdr *hdr;
3569 u64 pn = 0;
3570 u8 *ehdr;
3571 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3572
3573 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3574 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3575
3576 pn = ehdr[0];
3577 pn |= (u64)ehdr[1] << 8;
3578 pn |= (u64)ehdr[4] << 16;
3579 pn |= (u64)ehdr[5] << 24;
3580 pn |= (u64)ehdr[6] << 32;
3581 pn |= (u64)ehdr[7] << 40;
3582
3583 return pn;
3584 }
3585
3586 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3587 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3588 {
3589 enum hal_encrypt_type encrypt_type;
3590 struct sk_buff *first_frag, *skb;
3591 struct hal_rx_desc *desc;
3592 u64 last_pn;
3593 u64 cur_pn;
3594
3595 first_frag = skb_peek(&rx_tid->rx_frags);
3596 desc = (struct hal_rx_desc *)first_frag->data;
3597
3598 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3599 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3600 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3601 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3602 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3603 return true;
3604
3605 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3606 skb_queue_walk(&rx_tid->rx_frags, skb) {
3607 if (skb == first_frag)
3608 continue;
3609
3610 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3611 if (cur_pn != last_pn + 1)
3612 return false;
3613 last_pn = cur_pn;
3614 }
3615 return true;
3616 }
3617
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3618 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3619 struct sk_buff *msdu,
3620 u32 *ring_desc)
3621 {
3622 struct ath11k_base *ab = ar->ab;
3623 struct hal_rx_desc *rx_desc;
3624 struct ath11k_peer *peer;
3625 struct dp_rx_tid *rx_tid;
3626 struct sk_buff *defrag_skb = NULL;
3627 u32 peer_id;
3628 u16 seqno, frag_no;
3629 u8 tid;
3630 int ret = 0;
3631 bool more_frags;
3632 bool is_mcbc;
3633
3634 rx_desc = (struct hal_rx_desc *)msdu->data;
3635 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3636 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3637 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3638 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3639 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3640 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3641
3642 /* Multicast/Broadcast fragments are not expected */
3643 if (is_mcbc)
3644 return -EINVAL;
3645
3646 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3647 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3648 tid > IEEE80211_NUM_TIDS)
3649 return -EINVAL;
3650
3651 /* received unfragmented packet in reo
3652 * exception ring, this shouldn't happen
3653 * as these packets typically come from
3654 * reo2sw srngs.
3655 */
3656 if (WARN_ON_ONCE(!frag_no && !more_frags))
3657 return -EINVAL;
3658
3659 spin_lock_bh(&ab->base_lock);
3660 peer = ath11k_peer_find_by_id(ab, peer_id);
3661 if (!peer) {
3662 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3663 peer_id);
3664 ret = -ENOENT;
3665 goto out_unlock;
3666 }
3667 if (!peer->dp_setup_done) {
3668 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3669 peer->addr, peer_id);
3670 ret = -ENOENT;
3671 goto out_unlock;
3672 }
3673
3674 rx_tid = &peer->rx_tid[tid];
3675
3676 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3677 skb_queue_empty(&rx_tid->rx_frags)) {
3678 /* Flush stored fragments and start a new sequence */
3679 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3680 rx_tid->cur_sn = seqno;
3681 }
3682
3683 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3684 /* Fragment already present */
3685 ret = -EINVAL;
3686 goto out_unlock;
3687 }
3688
3689 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3690 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3691 else
3692 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3693
3694 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3695 if (!more_frags)
3696 rx_tid->last_frag_no = frag_no;
3697
3698 if (frag_no == 0) {
3699 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3700 sizeof(*rx_tid->dst_ring_desc),
3701 GFP_ATOMIC);
3702 if (!rx_tid->dst_ring_desc) {
3703 ret = -ENOMEM;
3704 goto out_unlock;
3705 }
3706 } else {
3707 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3708 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3709 }
3710
3711 if (!rx_tid->last_frag_no ||
3712 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3713 mod_timer(&rx_tid->frag_timer, jiffies +
3714 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3715 goto out_unlock;
3716 }
3717
3718 spin_unlock_bh(&ab->base_lock);
3719 del_timer_sync(&rx_tid->frag_timer);
3720 spin_lock_bh(&ab->base_lock);
3721
3722 peer = ath11k_peer_find_by_id(ab, peer_id);
3723 if (!peer)
3724 goto err_frags_cleanup;
3725
3726 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3727 goto err_frags_cleanup;
3728
3729 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3730 goto err_frags_cleanup;
3731
3732 if (!defrag_skb)
3733 goto err_frags_cleanup;
3734
3735 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3736 goto err_frags_cleanup;
3737
3738 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3739 goto out_unlock;
3740
3741 err_frags_cleanup:
3742 dev_kfree_skb_any(defrag_skb);
3743 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3744 out_unlock:
3745 spin_unlock_bh(&ab->base_lock);
3746 return ret;
3747 }
3748
3749 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3750 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3751 {
3752 struct ath11k_pdev_dp *dp = &ar->dp;
3753 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3754 struct sk_buff *msdu;
3755 struct ath11k_skb_rxcb *rxcb;
3756 struct hal_rx_desc *rx_desc;
3757 u8 *hdr_status;
3758 u16 msdu_len;
3759 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3760
3761 spin_lock_bh(&rx_ring->idr_lock);
3762 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3763 if (!msdu) {
3764 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3765 buf_id);
3766 spin_unlock_bh(&rx_ring->idr_lock);
3767 return -EINVAL;
3768 }
3769
3770 idr_remove(&rx_ring->bufs_idr, buf_id);
3771 spin_unlock_bh(&rx_ring->idr_lock);
3772
3773 rxcb = ATH11K_SKB_RXCB(msdu);
3774 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3775 msdu->len + skb_tailroom(msdu),
3776 DMA_FROM_DEVICE);
3777
3778 if (drop) {
3779 dev_kfree_skb_any(msdu);
3780 return 0;
3781 }
3782
3783 rcu_read_lock();
3784 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3785 dev_kfree_skb_any(msdu);
3786 goto exit;
3787 }
3788
3789 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3790 dev_kfree_skb_any(msdu);
3791 goto exit;
3792 }
3793
3794 rx_desc = (struct hal_rx_desc *)msdu->data;
3795 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3796 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3797 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3798 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3799 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3800 sizeof(struct ieee80211_hdr));
3801 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3802 sizeof(struct hal_rx_desc));
3803 dev_kfree_skb_any(msdu);
3804 goto exit;
3805 }
3806
3807 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3808
3809 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3810 dev_kfree_skb_any(msdu);
3811 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3812 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3813 }
3814 exit:
3815 rcu_read_unlock();
3816 return 0;
3817 }
3818
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3819 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3820 int budget)
3821 {
3822 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3823 struct dp_link_desc_bank *link_desc_banks;
3824 enum hal_rx_buf_return_buf_manager rbm;
3825 int tot_n_bufs_reaped, quota, ret, i;
3826 int n_bufs_reaped[MAX_RADIOS] = {0};
3827 struct dp_rxdma_ring *rx_ring;
3828 struct dp_srng *reo_except;
3829 u32 desc_bank, num_msdus;
3830 struct hal_srng *srng;
3831 struct ath11k_dp *dp;
3832 void *link_desc_va;
3833 int buf_id, mac_id;
3834 struct ath11k *ar;
3835 dma_addr_t paddr;
3836 u32 *desc;
3837 bool is_frag;
3838 u8 drop = 0;
3839
3840 tot_n_bufs_reaped = 0;
3841 quota = budget;
3842
3843 dp = &ab->dp;
3844 reo_except = &dp->reo_except_ring;
3845 link_desc_banks = dp->link_desc_banks;
3846
3847 srng = &ab->hal.srng_list[reo_except->ring_id];
3848
3849 spin_lock_bh(&srng->lock);
3850
3851 ath11k_hal_srng_access_begin(ab, srng);
3852
3853 while (budget &&
3854 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3855 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3856
3857 ab->soc_stats.err_ring_pkts++;
3858 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3859 &desc_bank);
3860 if (ret) {
3861 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3862 ret);
3863 continue;
3864 }
3865 link_desc_va = link_desc_banks[desc_bank].vaddr +
3866 (paddr - link_desc_banks[desc_bank].paddr);
3867 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3868 &rbm);
3869 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3870 rbm != HAL_RX_BUF_RBM_SW1_BM &&
3871 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3872 ab->soc_stats.invalid_rbm++;
3873 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3874 ath11k_dp_rx_link_desc_return(ab, desc,
3875 HAL_WBM_REL_BM_ACT_REL_MSDU);
3876 continue;
3877 }
3878
3879 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3880
3881 /* Process only rx fragments with one msdu per link desc below, and drop
3882 * msdu's indicated due to error reasons.
3883 */
3884 if (!is_frag || num_msdus > 1) {
3885 drop = 1;
3886 /* Return the link desc back to wbm idle list */
3887 ath11k_dp_rx_link_desc_return(ab, desc,
3888 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3889 }
3890
3891 for (i = 0; i < num_msdus; i++) {
3892 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3893 msdu_cookies[i]);
3894
3895 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3896 msdu_cookies[i]);
3897
3898 ar = ab->pdevs[mac_id].ar;
3899
3900 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3901 n_bufs_reaped[mac_id]++;
3902 tot_n_bufs_reaped++;
3903 }
3904 }
3905
3906 if (tot_n_bufs_reaped >= quota) {
3907 tot_n_bufs_reaped = quota;
3908 goto exit;
3909 }
3910
3911 budget = quota - tot_n_bufs_reaped;
3912 }
3913
3914 exit:
3915 ath11k_hal_srng_access_end(ab, srng);
3916
3917 spin_unlock_bh(&srng->lock);
3918
3919 for (i = 0; i < ab->num_radios; i++) {
3920 if (!n_bufs_reaped[i])
3921 continue;
3922
3923 ar = ab->pdevs[i].ar;
3924 rx_ring = &ar->dp.rx_refill_buf_ring;
3925
3926 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3927 ab->hw_params.hal_params->rx_buf_rbm);
3928 }
3929
3930 return tot_n_bufs_reaped;
3931 }
3932
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3933 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3934 int msdu_len,
3935 struct sk_buff_head *msdu_list)
3936 {
3937 struct sk_buff *skb, *tmp;
3938 struct ath11k_skb_rxcb *rxcb;
3939 int n_buffs;
3940
3941 n_buffs = DIV_ROUND_UP(msdu_len,
3942 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3943
3944 skb_queue_walk_safe(msdu_list, skb, tmp) {
3945 rxcb = ATH11K_SKB_RXCB(skb);
3946 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3947 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3948 if (!n_buffs)
3949 break;
3950 __skb_unlink(skb, msdu_list);
3951 dev_kfree_skb_any(skb);
3952 n_buffs--;
3953 }
3954 }
3955 }
3956
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3957 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3958 struct ieee80211_rx_status *status,
3959 struct sk_buff_head *msdu_list)
3960 {
3961 u16 msdu_len;
3962 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3963 struct rx_attention *rx_attention;
3964 u8 l3pad_bytes;
3965 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3966 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3967
3968 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3969
3970 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3971 /* First buffer will be freed by the caller, so deduct it's length */
3972 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3973 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3974 return -EINVAL;
3975 }
3976
3977 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3978 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3979 ath11k_warn(ar->ab,
3980 "msdu_done bit not set in null_q_des processing\n");
3981 __skb_queue_purge(msdu_list);
3982 return -EIO;
3983 }
3984
3985 /* Handle NULL queue descriptor violations arising out a missing
3986 * REO queue for a given peer or a given TID. This typically
3987 * may happen if a packet is received on a QOS enabled TID before the
3988 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3989 * it may also happen for MC/BC frames if they are not routed to the
3990 * non-QOS TID queue, in the absence of any other default TID queue.
3991 * This error can show up both in a REO destination or WBM release ring.
3992 */
3993
3994 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3995 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3996
3997 if (rxcb->is_frag) {
3998 skb_pull(msdu, hal_rx_desc_sz);
3999 } else {
4000 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4001
4002 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
4003 return -EINVAL;
4004
4005 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4006 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4007 }
4008 ath11k_dp_rx_h_ppdu(ar, desc, status);
4009
4010 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
4011
4012 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
4013
4014 /* Please note that caller will having the access to msdu and completing
4015 * rx with mac80211. Need not worry about cleaning up amsdu_list.
4016 */
4017
4018 return 0;
4019 }
4020
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4021 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
4022 struct ieee80211_rx_status *status,
4023 struct sk_buff_head *msdu_list)
4024 {
4025 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4026 bool drop = false;
4027
4028 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
4029
4030 switch (rxcb->err_code) {
4031 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4032 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4033 drop = true;
4034 break;
4035 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4036 /* TODO: Do not drop PN failed packets in the driver;
4037 * instead, it is good to drop such packets in mac80211
4038 * after incrementing the replay counters.
4039 */
4040 fallthrough;
4041 default:
4042 /* TODO: Review other errors and process them to mac80211
4043 * as appropriate.
4044 */
4045 drop = true;
4046 break;
4047 }
4048
4049 return drop;
4050 }
4051
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4052 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4053 struct ieee80211_rx_status *status)
4054 {
4055 u16 msdu_len;
4056 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4057 u8 l3pad_bytes;
4058 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4059 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4060
4061 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4062 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4063
4064 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4065 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4066 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4067 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4068
4069 ath11k_dp_rx_h_ppdu(ar, desc, status);
4070
4071 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4072 RX_FLAG_DECRYPTED);
4073
4074 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4075 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4076 }
4077
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4078 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4079 struct ieee80211_rx_status *status)
4080 {
4081 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4082 bool drop = false;
4083
4084 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4085
4086 switch (rxcb->err_code) {
4087 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4088 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4089 break;
4090 default:
4091 /* TODO: Review other rxdma error code to check if anything is
4092 * worth reporting to mac80211
4093 */
4094 drop = true;
4095 break;
4096 }
4097
4098 return drop;
4099 }
4100
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4101 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4102 struct napi_struct *napi,
4103 struct sk_buff *msdu,
4104 struct sk_buff_head *msdu_list)
4105 {
4106 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4107 struct ieee80211_rx_status rxs = {0};
4108 bool drop = true;
4109
4110 switch (rxcb->err_rel_src) {
4111 case HAL_WBM_REL_SRC_MODULE_REO:
4112 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4113 break;
4114 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4115 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4116 break;
4117 default:
4118 /* msdu will get freed */
4119 break;
4120 }
4121
4122 if (drop) {
4123 dev_kfree_skb_any(msdu);
4124 return;
4125 }
4126
4127 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4128 }
4129
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4130 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4131 struct napi_struct *napi, int budget)
4132 {
4133 struct ath11k *ar;
4134 struct ath11k_dp *dp = &ab->dp;
4135 struct dp_rxdma_ring *rx_ring;
4136 struct hal_rx_wbm_rel_info err_info;
4137 struct hal_srng *srng;
4138 struct sk_buff *msdu;
4139 struct sk_buff_head msdu_list[MAX_RADIOS];
4140 struct ath11k_skb_rxcb *rxcb;
4141 u32 *rx_desc;
4142 int buf_id, mac_id;
4143 int num_buffs_reaped[MAX_RADIOS] = {0};
4144 int total_num_buffs_reaped = 0;
4145 int ret, i;
4146
4147 for (i = 0; i < ab->num_radios; i++)
4148 __skb_queue_head_init(&msdu_list[i]);
4149
4150 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4151
4152 spin_lock_bh(&srng->lock);
4153
4154 ath11k_hal_srng_access_begin(ab, srng);
4155
4156 while (budget) {
4157 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4158 if (!rx_desc)
4159 break;
4160
4161 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4162 if (ret) {
4163 ath11k_warn(ab,
4164 "failed to parse rx error in wbm_rel ring desc %d\n",
4165 ret);
4166 continue;
4167 }
4168
4169 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4170 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4171
4172 ar = ab->pdevs[mac_id].ar;
4173 rx_ring = &ar->dp.rx_refill_buf_ring;
4174
4175 spin_lock_bh(&rx_ring->idr_lock);
4176 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4177 if (!msdu) {
4178 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4179 buf_id, mac_id);
4180 spin_unlock_bh(&rx_ring->idr_lock);
4181 continue;
4182 }
4183
4184 idr_remove(&rx_ring->bufs_idr, buf_id);
4185 spin_unlock_bh(&rx_ring->idr_lock);
4186
4187 rxcb = ATH11K_SKB_RXCB(msdu);
4188 dma_unmap_single(ab->dev, rxcb->paddr,
4189 msdu->len + skb_tailroom(msdu),
4190 DMA_FROM_DEVICE);
4191
4192 num_buffs_reaped[mac_id]++;
4193 total_num_buffs_reaped++;
4194 budget--;
4195
4196 if (err_info.push_reason !=
4197 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4198 dev_kfree_skb_any(msdu);
4199 continue;
4200 }
4201
4202 rxcb->err_rel_src = err_info.err_rel_src;
4203 rxcb->err_code = err_info.err_code;
4204 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4205 __skb_queue_tail(&msdu_list[mac_id], msdu);
4206 }
4207
4208 ath11k_hal_srng_access_end(ab, srng);
4209
4210 spin_unlock_bh(&srng->lock);
4211
4212 if (!total_num_buffs_reaped)
4213 goto done;
4214
4215 for (i = 0; i < ab->num_radios; i++) {
4216 if (!num_buffs_reaped[i])
4217 continue;
4218
4219 ar = ab->pdevs[i].ar;
4220 rx_ring = &ar->dp.rx_refill_buf_ring;
4221
4222 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4223 ab->hw_params.hal_params->rx_buf_rbm);
4224 }
4225
4226 rcu_read_lock();
4227 for (i = 0; i < ab->num_radios; i++) {
4228 if (!rcu_dereference(ab->pdevs_active[i])) {
4229 __skb_queue_purge(&msdu_list[i]);
4230 continue;
4231 }
4232
4233 ar = ab->pdevs[i].ar;
4234
4235 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4236 __skb_queue_purge(&msdu_list[i]);
4237 continue;
4238 }
4239
4240 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4241 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4242 }
4243 rcu_read_unlock();
4244 done:
4245 return total_num_buffs_reaped;
4246 }
4247
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4248 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4249 {
4250 struct ath11k *ar;
4251 struct dp_srng *err_ring;
4252 struct dp_rxdma_ring *rx_ring;
4253 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4254 struct hal_srng *srng;
4255 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4256 enum hal_rx_buf_return_buf_manager rbm;
4257 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4258 struct ath11k_skb_rxcb *rxcb;
4259 struct sk_buff *skb;
4260 struct hal_reo_entrance_ring *entr_ring;
4261 void *desc;
4262 int num_buf_freed = 0;
4263 int quota = budget;
4264 dma_addr_t paddr;
4265 u32 desc_bank;
4266 void *link_desc_va;
4267 int num_msdus;
4268 int i;
4269 int buf_id;
4270
4271 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4272 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4273 mac_id)];
4274 rx_ring = &ar->dp.rx_refill_buf_ring;
4275
4276 srng = &ab->hal.srng_list[err_ring->ring_id];
4277
4278 spin_lock_bh(&srng->lock);
4279
4280 ath11k_hal_srng_access_begin(ab, srng);
4281
4282 while (quota-- &&
4283 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4284 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4285
4286 entr_ring = (struct hal_reo_entrance_ring *)desc;
4287 rxdma_err_code =
4288 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4289 entr_ring->info1);
4290 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4291
4292 link_desc_va = link_desc_banks[desc_bank].vaddr +
4293 (paddr - link_desc_banks[desc_bank].paddr);
4294 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4295 msdu_cookies, &rbm);
4296
4297 for (i = 0; i < num_msdus; i++) {
4298 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4299 msdu_cookies[i]);
4300
4301 spin_lock_bh(&rx_ring->idr_lock);
4302 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4303 if (!skb) {
4304 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4305 buf_id);
4306 spin_unlock_bh(&rx_ring->idr_lock);
4307 continue;
4308 }
4309
4310 idr_remove(&rx_ring->bufs_idr, buf_id);
4311 spin_unlock_bh(&rx_ring->idr_lock);
4312
4313 rxcb = ATH11K_SKB_RXCB(skb);
4314 dma_unmap_single(ab->dev, rxcb->paddr,
4315 skb->len + skb_tailroom(skb),
4316 DMA_FROM_DEVICE);
4317 dev_kfree_skb_any(skb);
4318
4319 num_buf_freed++;
4320 }
4321
4322 ath11k_dp_rx_link_desc_return(ab, desc,
4323 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4324 }
4325
4326 ath11k_hal_srng_access_end(ab, srng);
4327
4328 spin_unlock_bh(&srng->lock);
4329
4330 if (num_buf_freed)
4331 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4332 ab->hw_params.hal_params->rx_buf_rbm);
4333
4334 return budget - quota;
4335 }
4336
ath11k_dp_process_reo_status(struct ath11k_base * ab)4337 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4338 {
4339 struct ath11k_dp *dp = &ab->dp;
4340 struct hal_srng *srng;
4341 struct dp_reo_cmd *cmd, *tmp;
4342 bool found = false;
4343 u32 *reo_desc;
4344 u16 tag;
4345 struct hal_reo_status reo_status;
4346
4347 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4348
4349 memset(&reo_status, 0, sizeof(reo_status));
4350
4351 spin_lock_bh(&srng->lock);
4352
4353 ath11k_hal_srng_access_begin(ab, srng);
4354
4355 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4356 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4357
4358 switch (tag) {
4359 case HAL_REO_GET_QUEUE_STATS_STATUS:
4360 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4361 &reo_status);
4362 break;
4363 case HAL_REO_FLUSH_QUEUE_STATUS:
4364 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4365 &reo_status);
4366 break;
4367 case HAL_REO_FLUSH_CACHE_STATUS:
4368 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4369 &reo_status);
4370 break;
4371 case HAL_REO_UNBLOCK_CACHE_STATUS:
4372 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4373 &reo_status);
4374 break;
4375 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4376 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4377 &reo_status);
4378 break;
4379 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4380 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4381 &reo_status);
4382 break;
4383 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4384 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4385 &reo_status);
4386 break;
4387 default:
4388 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4389 continue;
4390 }
4391
4392 spin_lock_bh(&dp->reo_cmd_lock);
4393 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4394 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4395 found = true;
4396 list_del(&cmd->list);
4397 break;
4398 }
4399 }
4400 spin_unlock_bh(&dp->reo_cmd_lock);
4401
4402 if (found) {
4403 cmd->handler(dp, (void *)&cmd->data,
4404 reo_status.uniform_hdr.cmd_status);
4405 kfree(cmd);
4406 }
4407
4408 found = false;
4409 }
4410
4411 ath11k_hal_srng_access_end(ab, srng);
4412
4413 spin_unlock_bh(&srng->lock);
4414 }
4415
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4416 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4417 {
4418 struct ath11k *ar = ab->pdevs[mac_id].ar;
4419
4420 ath11k_dp_rx_pdev_srng_free(ar);
4421 ath11k_dp_rxdma_pdev_buf_free(ar);
4422 }
4423
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4424 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4425 {
4426 struct ath11k *ar = ab->pdevs[mac_id].ar;
4427 struct ath11k_pdev_dp *dp = &ar->dp;
4428 u32 ring_id;
4429 int i;
4430 int ret;
4431
4432 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4433 if (ret) {
4434 ath11k_warn(ab, "failed to setup rx srngs\n");
4435 return ret;
4436 }
4437
4438 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4439 if (ret) {
4440 ath11k_warn(ab, "failed to setup rxdma ring\n");
4441 return ret;
4442 }
4443
4444 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4445 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4446 if (ret) {
4447 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4448 ret);
4449 return ret;
4450 }
4451
4452 if (ab->hw_params.rx_mac_buf_ring) {
4453 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4454 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4455 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4456 mac_id + i, HAL_RXDMA_BUF);
4457 if (ret) {
4458 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4459 i, ret);
4460 return ret;
4461 }
4462 }
4463 }
4464
4465 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4466 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4467 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4468 mac_id + i, HAL_RXDMA_DST);
4469 if (ret) {
4470 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4471 i, ret);
4472 return ret;
4473 }
4474 }
4475
4476 if (!ab->hw_params.rxdma1_enable)
4477 goto config_refill_ring;
4478
4479 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4480 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4481 mac_id, HAL_RXDMA_MONITOR_BUF);
4482 if (ret) {
4483 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4484 ret);
4485 return ret;
4486 }
4487 ret = ath11k_dp_tx_htt_srng_setup(ab,
4488 dp->rxdma_mon_dst_ring.ring_id,
4489 mac_id, HAL_RXDMA_MONITOR_DST);
4490 if (ret) {
4491 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4492 ret);
4493 return ret;
4494 }
4495 ret = ath11k_dp_tx_htt_srng_setup(ab,
4496 dp->rxdma_mon_desc_ring.ring_id,
4497 mac_id, HAL_RXDMA_MONITOR_DESC);
4498 if (ret) {
4499 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4500 ret);
4501 return ret;
4502 }
4503
4504 config_refill_ring:
4505 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4506 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4507 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4508 HAL_RXDMA_MONITOR_STATUS);
4509 if (ret) {
4510 ath11k_warn(ab,
4511 "failed to configure mon_status_refill_ring%d %d\n",
4512 i, ret);
4513 return ret;
4514 }
4515 }
4516
4517 return 0;
4518 }
4519
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4520 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4521 {
4522 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4523 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4524 *total_len -= *frag_len;
4525 } else {
4526 *frag_len = *total_len;
4527 *total_len = 0;
4528 }
4529 }
4530
4531 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4532 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4533 void *p_last_buf_addr_info,
4534 u8 mac_id)
4535 {
4536 struct ath11k_pdev_dp *dp = &ar->dp;
4537 struct dp_srng *dp_srng;
4538 void *hal_srng;
4539 void *src_srng_desc;
4540 int ret = 0;
4541
4542 if (ar->ab->hw_params.rxdma1_enable) {
4543 dp_srng = &dp->rxdma_mon_desc_ring;
4544 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4545 } else {
4546 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4547 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4548 }
4549
4550 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4551
4552 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4553
4554 if (src_srng_desc) {
4555 struct ath11k_buffer_addr *src_desc = src_srng_desc;
4556
4557 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4558 } else {
4559 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4560 "Monitor Link Desc Ring %d Full", mac_id);
4561 ret = -ENOMEM;
4562 }
4563
4564 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4565 return ret;
4566 }
4567
4568 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4569 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4570 dma_addr_t *paddr, u32 *sw_cookie,
4571 u8 *rbm,
4572 void **pp_buf_addr_info)
4573 {
4574 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4575 struct ath11k_buffer_addr *buf_addr_info;
4576
4577 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4578
4579 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4580
4581 *pp_buf_addr_info = (void *)buf_addr_info;
4582 }
4583
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4584 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4585 {
4586 if (skb->len > len) {
4587 skb_trim(skb, len);
4588 } else {
4589 if (skb_tailroom(skb) < len - skb->len) {
4590 if ((pskb_expand_head(skb, 0,
4591 len - skb->len - skb_tailroom(skb),
4592 GFP_ATOMIC))) {
4593 dev_kfree_skb_any(skb);
4594 return -ENOMEM;
4595 }
4596 }
4597 skb_put(skb, (len - skb->len));
4598 }
4599 return 0;
4600 }
4601
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4602 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4603 void *msdu_link_desc,
4604 struct hal_rx_msdu_list *msdu_list,
4605 u16 *num_msdus)
4606 {
4607 struct hal_rx_msdu_details *msdu_details = NULL;
4608 struct rx_msdu_desc *msdu_desc_info = NULL;
4609 struct hal_rx_msdu_link *msdu_link = NULL;
4610 int i;
4611 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4612 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4613 u8 tmp = 0;
4614
4615 msdu_link = msdu_link_desc;
4616 msdu_details = &msdu_link->msdu_link[0];
4617
4618 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4619 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4620 msdu_details[i].buf_addr_info.info0) == 0) {
4621 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4622 msdu_desc_info->info0 |= last;
4623 ;
4624 break;
4625 }
4626 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4627
4628 if (!i)
4629 msdu_desc_info->info0 |= first;
4630 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4631 msdu_desc_info->info0 |= last;
4632 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4633 msdu_list->msdu_info[i].msdu_len =
4634 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4635 msdu_list->sw_cookie[i] =
4636 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4637 msdu_details[i].buf_addr_info.info1);
4638 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4639 msdu_details[i].buf_addr_info.info1);
4640 msdu_list->rbm[i] = tmp;
4641 }
4642 *num_msdus = i;
4643 }
4644
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4645 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4646 u32 *rx_bufs_used)
4647 {
4648 u32 ret = 0;
4649
4650 if ((*ppdu_id < msdu_ppdu_id) &&
4651 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4652 *ppdu_id = msdu_ppdu_id;
4653 ret = msdu_ppdu_id;
4654 } else if ((*ppdu_id > msdu_ppdu_id) &&
4655 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4656 /* mon_dst is behind than mon_status
4657 * skip dst_ring and free it
4658 */
4659 *rx_bufs_used += 1;
4660 *ppdu_id = msdu_ppdu_id;
4661 ret = msdu_ppdu_id;
4662 }
4663 return ret;
4664 }
4665
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4666 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4667 bool *is_frag, u32 *total_len,
4668 u32 *frag_len, u32 *msdu_cnt)
4669 {
4670 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4671 if (!*is_frag) {
4672 *total_len = info->msdu_len;
4673 *is_frag = true;
4674 }
4675 ath11k_dp_mon_set_frag_len(total_len,
4676 frag_len);
4677 } else {
4678 if (*is_frag) {
4679 ath11k_dp_mon_set_frag_len(total_len,
4680 frag_len);
4681 } else {
4682 *frag_len = info->msdu_len;
4683 }
4684 *is_frag = false;
4685 *msdu_cnt -= 1;
4686 }
4687 }
4688
4689 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4690 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4691 void *ring_entry, struct sk_buff **head_msdu,
4692 struct sk_buff **tail_msdu, u32 *npackets,
4693 u32 *ppdu_id)
4694 {
4695 struct ath11k_pdev_dp *dp = &ar->dp;
4696 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4697 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4698 struct sk_buff *msdu = NULL, *last = NULL;
4699 struct hal_rx_msdu_list msdu_list;
4700 void *p_buf_addr_info, *p_last_buf_addr_info;
4701 struct hal_rx_desc *rx_desc;
4702 void *rx_msdu_link_desc;
4703 dma_addr_t paddr;
4704 u16 num_msdus = 0;
4705 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4706 u32 rx_bufs_used = 0, i = 0;
4707 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4708 u32 total_len = 0, frag_len = 0;
4709 bool is_frag, is_first_msdu;
4710 bool drop_mpdu = false;
4711 struct ath11k_skb_rxcb *rxcb;
4712 struct hal_reo_entrance_ring *ent_desc = ring_entry;
4713 int buf_id;
4714 u32 rx_link_buf_info[2];
4715 u8 rbm;
4716
4717 if (!ar->ab->hw_params.rxdma1_enable)
4718 rx_ring = &dp->rx_refill_buf_ring;
4719
4720 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4721 &sw_cookie,
4722 &p_last_buf_addr_info, &rbm,
4723 &msdu_cnt);
4724
4725 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4726 ent_desc->info1) ==
4727 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4728 u8 rxdma_err =
4729 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4730 ent_desc->info1);
4731 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4732 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4733 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4734 drop_mpdu = true;
4735 pmon->rx_mon_stats.dest_mpdu_drop++;
4736 }
4737 }
4738
4739 is_frag = false;
4740 is_first_msdu = true;
4741
4742 do {
4743 if (pmon->mon_last_linkdesc_paddr == paddr) {
4744 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4745 return rx_bufs_used;
4746 }
4747
4748 if (ar->ab->hw_params.rxdma1_enable)
4749 rx_msdu_link_desc =
4750 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4751 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4752 else
4753 rx_msdu_link_desc =
4754 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4755 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4756
4757 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4758 &num_msdus);
4759
4760 for (i = 0; i < num_msdus; i++) {
4761 u32 l2_hdr_offset;
4762
4763 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4764 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4765 "i %d last_cookie %d is same\n",
4766 i, pmon->mon_last_buf_cookie);
4767 drop_mpdu = true;
4768 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4769 continue;
4770 }
4771 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4772 msdu_list.sw_cookie[i]);
4773
4774 spin_lock_bh(&rx_ring->idr_lock);
4775 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4776 spin_unlock_bh(&rx_ring->idr_lock);
4777 if (!msdu) {
4778 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4779 "msdu_pop: invalid buf_id %d\n", buf_id);
4780 break;
4781 }
4782 rxcb = ATH11K_SKB_RXCB(msdu);
4783 if (!rxcb->unmapped) {
4784 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4785 msdu->len +
4786 skb_tailroom(msdu),
4787 DMA_FROM_DEVICE);
4788 rxcb->unmapped = 1;
4789 }
4790 if (drop_mpdu) {
4791 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4792 "i %d drop msdu %p *ppdu_id %x\n",
4793 i, msdu, *ppdu_id);
4794 dev_kfree_skb_any(msdu);
4795 msdu = NULL;
4796 goto next_msdu;
4797 }
4798
4799 rx_desc = (struct hal_rx_desc *)msdu->data;
4800
4801 rx_pkt_offset = sizeof(struct hal_rx_desc);
4802 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4803
4804 if (is_first_msdu) {
4805 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4806 drop_mpdu = true;
4807 dev_kfree_skb_any(msdu);
4808 msdu = NULL;
4809 pmon->mon_last_linkdesc_paddr = paddr;
4810 goto next_msdu;
4811 }
4812
4813 msdu_ppdu_id =
4814 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4815
4816 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4817 ppdu_id,
4818 &rx_bufs_used)) {
4819 if (rx_bufs_used) {
4820 drop_mpdu = true;
4821 dev_kfree_skb_any(msdu);
4822 msdu = NULL;
4823 goto next_msdu;
4824 }
4825 return rx_bufs_used;
4826 }
4827 pmon->mon_last_linkdesc_paddr = paddr;
4828 is_first_msdu = false;
4829 }
4830 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4831 &is_frag, &total_len,
4832 &frag_len, &msdu_cnt);
4833 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4834
4835 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4836
4837 if (!(*head_msdu))
4838 *head_msdu = msdu;
4839 else if (last)
4840 last->next = msdu;
4841
4842 last = msdu;
4843 next_msdu:
4844 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4845 rx_bufs_used++;
4846 spin_lock_bh(&rx_ring->idr_lock);
4847 idr_remove(&rx_ring->bufs_idr, buf_id);
4848 spin_unlock_bh(&rx_ring->idr_lock);
4849 }
4850
4851 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4852
4853 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4854 &sw_cookie, &rbm,
4855 &p_buf_addr_info);
4856
4857 if (ar->ab->hw_params.rxdma1_enable) {
4858 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4859 p_last_buf_addr_info,
4860 dp->mac_id))
4861 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4862 "dp_rx_monitor_link_desc_return failed");
4863 } else {
4864 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4865 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4866 }
4867
4868 p_last_buf_addr_info = p_buf_addr_info;
4869
4870 } while (paddr && msdu_cnt);
4871
4872 if (last)
4873 last->next = NULL;
4874
4875 *tail_msdu = msdu;
4876
4877 if (msdu_cnt == 0)
4878 *npackets = 1;
4879
4880 return rx_bufs_used;
4881 }
4882
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4883 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4884 {
4885 u32 rx_pkt_offset, l2_hdr_offset;
4886
4887 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4888 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4889 (struct hal_rx_desc *)msdu->data);
4890 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4891 }
4892
4893 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4894 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4895 u32 mac_id, struct sk_buff *head_msdu,
4896 struct sk_buff *last_msdu,
4897 struct ieee80211_rx_status *rxs, bool *fcs_err)
4898 {
4899 struct ath11k_base *ab = ar->ab;
4900 struct sk_buff *msdu, *prev_buf;
4901 struct hal_rx_desc *rx_desc;
4902 char *hdr_desc;
4903 u8 *dest, decap_format;
4904 struct ieee80211_hdr_3addr *wh;
4905 struct rx_attention *rx_attention;
4906 u32 err_bitmap;
4907
4908 if (!head_msdu)
4909 goto err_merge_fail;
4910
4911 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4912 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4913 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4914
4915 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4916 *fcs_err = true;
4917
4918 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4919 return NULL;
4920
4921 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4922
4923 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4924
4925 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4926 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4927
4928 prev_buf = head_msdu;
4929 msdu = head_msdu->next;
4930
4931 while (msdu) {
4932 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4933
4934 prev_buf = msdu;
4935 msdu = msdu->next;
4936 }
4937
4938 prev_buf->next = NULL;
4939
4940 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4941 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4942 u8 qos_pkt = 0;
4943
4944 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4945 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4946
4947 /* Base size */
4948 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4949
4950 if (ieee80211_is_data_qos(wh->frame_control))
4951 qos_pkt = 1;
4952
4953 msdu = head_msdu;
4954
4955 while (msdu) {
4956 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4957 if (qos_pkt) {
4958 dest = skb_push(msdu, sizeof(__le16));
4959 if (!dest)
4960 goto err_merge_fail;
4961 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4962 }
4963 prev_buf = msdu;
4964 msdu = msdu->next;
4965 }
4966 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4967 if (!dest)
4968 goto err_merge_fail;
4969
4970 ath11k_dbg(ab, ATH11K_DBG_DATA,
4971 "mpdu_buf %p mpdu_buf->len %u",
4972 prev_buf, prev_buf->len);
4973 } else {
4974 ath11k_dbg(ab, ATH11K_DBG_DATA,
4975 "decap format %d is not supported!\n",
4976 decap_format);
4977 goto err_merge_fail;
4978 }
4979
4980 return head_msdu;
4981
4982 err_merge_fail:
4983 return NULL;
4984 }
4985
4986 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4987 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4988 u8 *rtap_buf)
4989 {
4990 u32 rtap_len = 0;
4991
4992 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4993 rtap_len += 2;
4994
4995 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4996 rtap_len += 2;
4997
4998 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
4999 rtap_len += 2;
5000
5001 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
5002 rtap_len += 2;
5003
5004 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
5005 rtap_len += 2;
5006
5007 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
5008 }
5009
5010 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5011 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
5012 u8 *rtap_buf)
5013 {
5014 u32 rtap_len = 0;
5015
5016 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
5017 rtap_len += 2;
5018
5019 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
5020 rtap_len += 2;
5021
5022 rtap_buf[rtap_len] = rx_status->he_RU[0];
5023 rtap_len += 1;
5024
5025 rtap_buf[rtap_len] = rx_status->he_RU[1];
5026 rtap_len += 1;
5027
5028 rtap_buf[rtap_len] = rx_status->he_RU[2];
5029 rtap_len += 1;
5030
5031 rtap_buf[rtap_len] = rx_status->he_RU[3];
5032 }
5033
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)5034 static void ath11k_update_radiotap(struct ath11k *ar,
5035 struct hal_rx_mon_ppdu_info *ppduinfo,
5036 struct sk_buff *mon_skb,
5037 struct ieee80211_rx_status *rxs)
5038 {
5039 struct ieee80211_supported_band *sband;
5040 u8 *ptr = NULL;
5041
5042 rxs->flag |= RX_FLAG_MACTIME_START;
5043 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
5044
5045 if (ppduinfo->nss)
5046 rxs->nss = ppduinfo->nss;
5047
5048 if (ppduinfo->he_mu_flags) {
5049 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5050 rxs->encoding = RX_ENC_HE;
5051 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5052 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5053 } else if (ppduinfo->he_flags) {
5054 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5055 rxs->encoding = RX_ENC_HE;
5056 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5057 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5058 rxs->rate_idx = ppduinfo->rate;
5059 } else if (ppduinfo->vht_flags) {
5060 rxs->encoding = RX_ENC_VHT;
5061 rxs->rate_idx = ppduinfo->rate;
5062 } else if (ppduinfo->ht_flags) {
5063 rxs->encoding = RX_ENC_HT;
5064 rxs->rate_idx = ppduinfo->rate;
5065 } else {
5066 rxs->encoding = RX_ENC_LEGACY;
5067 sband = &ar->mac.sbands[rxs->band];
5068 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5069 ppduinfo->cck_flag);
5070 }
5071
5072 rxs->mactime = ppduinfo->tsft;
5073 }
5074
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5075 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5076 struct sk_buff *head_msdu,
5077 struct hal_rx_mon_ppdu_info *ppduinfo,
5078 struct sk_buff *tail_msdu,
5079 struct napi_struct *napi)
5080 {
5081 struct ath11k_pdev_dp *dp = &ar->dp;
5082 struct sk_buff *mon_skb, *skb_next, *header;
5083 struct ieee80211_rx_status *rxs = &dp->rx_status;
5084 bool fcs_err = false;
5085
5086 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5087 tail_msdu, rxs, &fcs_err);
5088
5089 if (!mon_skb)
5090 goto mon_deliver_fail;
5091
5092 header = mon_skb;
5093
5094 rxs->flag = 0;
5095
5096 if (fcs_err)
5097 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5098
5099 do {
5100 skb_next = mon_skb->next;
5101 if (!skb_next)
5102 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5103 else
5104 rxs->flag |= RX_FLAG_AMSDU_MORE;
5105
5106 if (mon_skb == header) {
5107 header = NULL;
5108 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5109 } else {
5110 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5111 }
5112 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5113 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5114
5115 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5116 mon_skb = skb_next;
5117 } while (mon_skb);
5118 rxs->flag = 0;
5119
5120 return 0;
5121
5122 mon_deliver_fail:
5123 mon_skb = head_msdu;
5124 while (mon_skb) {
5125 skb_next = mon_skb->next;
5126 dev_kfree_skb_any(mon_skb);
5127 mon_skb = skb_next;
5128 }
5129 return -EINVAL;
5130 }
5131
5132 /* The destination ring processing is stuck if the destination is not
5133 * moving while status ring moves 16 PPDU. The destination ring processing
5134 * skips this destination ring PPDU as a workaround.
5135 */
5136 #define MON_DEST_RING_STUCK_MAX_CNT 16
5137
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5138 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5139 u32 quota, struct napi_struct *napi)
5140 {
5141 struct ath11k_pdev_dp *dp = &ar->dp;
5142 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5143 const struct ath11k_hw_hal_params *hal_params;
5144 void *ring_entry;
5145 void *mon_dst_srng;
5146 u32 ppdu_id;
5147 u32 rx_bufs_used;
5148 u32 ring_id;
5149 struct ath11k_pdev_mon_stats *rx_mon_stats;
5150 u32 npackets = 0;
5151 u32 mpdu_rx_bufs_used;
5152
5153 if (ar->ab->hw_params.rxdma1_enable)
5154 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5155 else
5156 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5157
5158 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5159
5160 spin_lock_bh(&pmon->mon_lock);
5161
5162 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5163
5164 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5165 rx_bufs_used = 0;
5166 rx_mon_stats = &pmon->rx_mon_stats;
5167
5168 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5169 struct sk_buff *head_msdu, *tail_msdu;
5170
5171 head_msdu = NULL;
5172 tail_msdu = NULL;
5173
5174 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5175 &head_msdu,
5176 &tail_msdu,
5177 &npackets, &ppdu_id);
5178
5179 rx_bufs_used += mpdu_rx_bufs_used;
5180
5181 if (mpdu_rx_bufs_used) {
5182 dp->mon_dest_ring_stuck_cnt = 0;
5183 } else {
5184 dp->mon_dest_ring_stuck_cnt++;
5185 rx_mon_stats->dest_mon_not_reaped++;
5186 }
5187
5188 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5189 rx_mon_stats->dest_mon_stuck++;
5190 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5191 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5192 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5193 dp->mon_dest_ring_stuck_cnt,
5194 rx_mon_stats->dest_mon_not_reaped,
5195 rx_mon_stats->dest_mon_stuck);
5196 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5197 continue;
5198 }
5199
5200 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5201 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5202 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5203 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5204 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5205 rx_mon_stats->dest_mon_not_reaped,
5206 rx_mon_stats->dest_mon_stuck);
5207 break;
5208 }
5209 if (head_msdu && tail_msdu) {
5210 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5211 &pmon->mon_ppdu_info,
5212 tail_msdu, napi);
5213 rx_mon_stats->dest_mpdu_done++;
5214 }
5215
5216 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5217 mon_dst_srng);
5218 }
5219 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5220
5221 spin_unlock_bh(&pmon->mon_lock);
5222
5223 if (rx_bufs_used) {
5224 rx_mon_stats->dest_ppdu_done++;
5225 hal_params = ar->ab->hw_params.hal_params;
5226
5227 if (ar->ab->hw_params.rxdma1_enable)
5228 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5229 &dp->rxdma_mon_buf_ring,
5230 rx_bufs_used,
5231 hal_params->rx_buf_rbm);
5232 else
5233 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5234 &dp->rx_refill_buf_ring,
5235 rx_bufs_used,
5236 hal_params->rx_buf_rbm);
5237 }
5238 }
5239
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5240 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5241 struct napi_struct *napi, int budget)
5242 {
5243 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5244 enum hal_rx_mon_status hal_status;
5245 struct sk_buff *skb;
5246 struct sk_buff_head skb_list;
5247 struct ath11k_peer *peer;
5248 struct ath11k_sta *arsta;
5249 int num_buffs_reaped = 0;
5250 u32 rx_buf_sz;
5251 u16 log_type;
5252 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5253 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5254 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5255
5256 __skb_queue_head_init(&skb_list);
5257
5258 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5259 &skb_list);
5260 if (!num_buffs_reaped)
5261 goto exit;
5262
5263 memset(ppdu_info, 0, sizeof(*ppdu_info));
5264 ppdu_info->peer_id = HAL_INVALID_PEERID;
5265
5266 while ((skb = __skb_dequeue(&skb_list))) {
5267 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5268 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5269 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5270 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5271 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5272 rx_buf_sz = DP_RX_BUFFER_SIZE;
5273 } else {
5274 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5275 rx_buf_sz = 0;
5276 }
5277
5278 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5279 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5280
5281 memset(ppdu_info, 0, sizeof(*ppdu_info));
5282 ppdu_info->peer_id = HAL_INVALID_PEERID;
5283 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5284
5285 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5286 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5287 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5288 rx_mon_stats->status_ppdu_done++;
5289 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5290 if (!ab->hw_params.full_monitor_mode) {
5291 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5292 budget, napi);
5293 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5294 }
5295 }
5296
5297 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5298 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5299 dev_kfree_skb_any(skb);
5300 continue;
5301 }
5302
5303 rcu_read_lock();
5304 spin_lock_bh(&ab->base_lock);
5305 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5306
5307 if (!peer || !peer->sta) {
5308 ath11k_dbg(ab, ATH11K_DBG_DATA,
5309 "failed to find the peer with peer_id %d\n",
5310 ppdu_info->peer_id);
5311 goto next_skb;
5312 }
5313
5314 arsta = ath11k_sta_to_arsta(peer->sta);
5315 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5316
5317 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5318 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5319
5320 next_skb:
5321 spin_unlock_bh(&ab->base_lock);
5322 rcu_read_unlock();
5323
5324 dev_kfree_skb_any(skb);
5325 memset(ppdu_info, 0, sizeof(*ppdu_info));
5326 ppdu_info->peer_id = HAL_INVALID_PEERID;
5327 }
5328 exit:
5329 return num_buffs_reaped;
5330 }
5331
5332 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5333 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5334 void *ring_entry, struct sk_buff **head_msdu,
5335 struct sk_buff **tail_msdu,
5336 struct hal_sw_mon_ring_entries *sw_mon_entries)
5337 {
5338 struct ath11k_pdev_dp *dp = &ar->dp;
5339 struct ath11k_mon_data *pmon = &dp->mon_data;
5340 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5341 struct sk_buff *msdu = NULL, *last = NULL;
5342 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5343 struct hal_rx_msdu_list msdu_list;
5344 struct hal_rx_desc *rx_desc;
5345 struct ath11k_skb_rxcb *rxcb;
5346 void *rx_msdu_link_desc;
5347 void *p_buf_addr_info, *p_last_buf_addr_info;
5348 int buf_id, i = 0;
5349 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5350 u32 rx_bufs_used = 0, msdu_cnt = 0;
5351 u32 total_len = 0, frag_len = 0, sw_cookie;
5352 u16 num_msdus = 0;
5353 u8 rxdma_err, rbm;
5354 bool is_frag, is_first_msdu;
5355 bool drop_mpdu = false;
5356
5357 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5358
5359 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5360 sw_mon_entries->end_of_ppdu = false;
5361 sw_mon_entries->drop_ppdu = false;
5362 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5363 msdu_cnt = sw_mon_entries->msdu_cnt;
5364
5365 sw_mon_entries->end_of_ppdu =
5366 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5367 if (sw_mon_entries->end_of_ppdu)
5368 return rx_bufs_used;
5369
5370 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5371 sw_desc->info0) ==
5372 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5373 rxdma_err =
5374 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5375 sw_desc->info0);
5376 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5377 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5378 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5379 pmon->rx_mon_stats.dest_mpdu_drop++;
5380 drop_mpdu = true;
5381 }
5382 }
5383
5384 is_frag = false;
5385 is_first_msdu = true;
5386
5387 do {
5388 rx_msdu_link_desc =
5389 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5390 (sw_mon_entries->mon_dst_paddr -
5391 pmon->link_desc_banks[sw_cookie].paddr);
5392
5393 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5394 &num_msdus);
5395
5396 for (i = 0; i < num_msdus; i++) {
5397 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5398 msdu_list.sw_cookie[i]);
5399
5400 spin_lock_bh(&rx_ring->idr_lock);
5401 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5402 if (!msdu) {
5403 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5404 "full mon msdu_pop: invalid buf_id %d\n",
5405 buf_id);
5406 spin_unlock_bh(&rx_ring->idr_lock);
5407 break;
5408 }
5409 idr_remove(&rx_ring->bufs_idr, buf_id);
5410 spin_unlock_bh(&rx_ring->idr_lock);
5411
5412 rxcb = ATH11K_SKB_RXCB(msdu);
5413 if (!rxcb->unmapped) {
5414 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5415 msdu->len +
5416 skb_tailroom(msdu),
5417 DMA_FROM_DEVICE);
5418 rxcb->unmapped = 1;
5419 }
5420 if (drop_mpdu) {
5421 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5422 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5423 i, msdu, sw_mon_entries->ppdu_id);
5424 dev_kfree_skb_any(msdu);
5425 msdu_cnt--;
5426 goto next_msdu;
5427 }
5428
5429 rx_desc = (struct hal_rx_desc *)msdu->data;
5430
5431 rx_pkt_offset = sizeof(struct hal_rx_desc);
5432 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5433
5434 if (is_first_msdu) {
5435 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5436 drop_mpdu = true;
5437 dev_kfree_skb_any(msdu);
5438 msdu = NULL;
5439 goto next_msdu;
5440 }
5441 is_first_msdu = false;
5442 }
5443
5444 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5445 &is_frag, &total_len,
5446 &frag_len, &msdu_cnt);
5447
5448 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5449
5450 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5451
5452 if (!(*head_msdu))
5453 *head_msdu = msdu;
5454 else if (last)
5455 last->next = msdu;
5456
5457 last = msdu;
5458 next_msdu:
5459 rx_bufs_used++;
5460 }
5461
5462 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5463 &sw_mon_entries->mon_dst_paddr,
5464 &sw_mon_entries->mon_dst_sw_cookie,
5465 &rbm,
5466 &p_buf_addr_info);
5467
5468 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5469 p_last_buf_addr_info,
5470 dp->mac_id))
5471 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5472 "full mon: dp_rx_monitor_link_desc_return failed\n");
5473
5474 p_last_buf_addr_info = p_buf_addr_info;
5475
5476 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5477
5478 if (last)
5479 last->next = NULL;
5480
5481 *tail_msdu = msdu;
5482
5483 return rx_bufs_used;
5484 }
5485
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5486 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5487 struct dp_full_mon_mpdu *mon_mpdu,
5488 struct sk_buff *head,
5489 struct sk_buff *tail)
5490 {
5491 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5492 if (!mon_mpdu)
5493 return -ENOMEM;
5494
5495 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5496 mon_mpdu->head = head;
5497 mon_mpdu->tail = tail;
5498
5499 return 0;
5500 }
5501
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5502 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5503 struct dp_full_mon_mpdu *mon_mpdu)
5504 {
5505 struct dp_full_mon_mpdu *tmp;
5506 struct sk_buff *tmp_msdu, *skb_next;
5507
5508 if (list_empty(&dp->dp_full_mon_mpdu_list))
5509 return;
5510
5511 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5512 list_del(&mon_mpdu->list);
5513
5514 tmp_msdu = mon_mpdu->head;
5515 while (tmp_msdu) {
5516 skb_next = tmp_msdu->next;
5517 dev_kfree_skb_any(tmp_msdu);
5518 tmp_msdu = skb_next;
5519 }
5520
5521 kfree(mon_mpdu);
5522 }
5523 }
5524
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5525 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5526 int mac_id,
5527 struct ath11k_mon_data *pmon,
5528 struct napi_struct *napi)
5529 {
5530 struct ath11k_pdev_mon_stats *rx_mon_stats;
5531 struct dp_full_mon_mpdu *tmp;
5532 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5533 struct sk_buff *head_msdu, *tail_msdu;
5534 struct ath11k_base *ab = ar->ab;
5535 struct ath11k_dp *dp = &ab->dp;
5536 int ret;
5537
5538 rx_mon_stats = &pmon->rx_mon_stats;
5539
5540 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5541 list_del(&mon_mpdu->list);
5542 head_msdu = mon_mpdu->head;
5543 tail_msdu = mon_mpdu->tail;
5544 if (head_msdu && tail_msdu) {
5545 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5546 &pmon->mon_ppdu_info,
5547 tail_msdu, napi);
5548 rx_mon_stats->dest_mpdu_done++;
5549 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5550 }
5551 kfree(mon_mpdu);
5552 }
5553
5554 return ret;
5555 }
5556
5557 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5558 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5559 struct napi_struct *napi, int budget)
5560 {
5561 struct ath11k *ar = ab->pdevs[mac_id].ar;
5562 struct ath11k_pdev_dp *dp = &ar->dp;
5563 struct ath11k_mon_data *pmon = &dp->mon_data;
5564 struct hal_sw_mon_ring_entries *sw_mon_entries;
5565 int quota = 0, work = 0, count;
5566
5567 sw_mon_entries = &pmon->sw_mon_entries;
5568
5569 while (pmon->hold_mon_dst_ring) {
5570 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5571 napi, 1);
5572 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5573 count = sw_mon_entries->status_buf_count;
5574 if (count > 1) {
5575 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5576 napi, count);
5577 }
5578
5579 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5580 pmon, napi);
5581 pmon->hold_mon_dst_ring = false;
5582 } else if (!pmon->mon_status_paddr ||
5583 pmon->buf_state == DP_MON_STATUS_LEAD) {
5584 sw_mon_entries->drop_ppdu = true;
5585 pmon->hold_mon_dst_ring = false;
5586 }
5587
5588 if (!quota)
5589 break;
5590
5591 work += quota;
5592 }
5593
5594 if (sw_mon_entries->drop_ppdu)
5595 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5596
5597 return work;
5598 }
5599
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5600 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5601 struct napi_struct *napi, int budget)
5602 {
5603 struct ath11k *ar = ab->pdevs[mac_id].ar;
5604 struct ath11k_pdev_dp *dp = &ar->dp;
5605 struct ath11k_mon_data *pmon = &dp->mon_data;
5606 struct hal_sw_mon_ring_entries *sw_mon_entries;
5607 struct ath11k_pdev_mon_stats *rx_mon_stats;
5608 struct sk_buff *head_msdu, *tail_msdu;
5609 void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5610 void *ring_entry;
5611 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5612 int quota = 0, ret;
5613 bool break_dst_ring = false;
5614
5615 spin_lock_bh(&pmon->mon_lock);
5616
5617 sw_mon_entries = &pmon->sw_mon_entries;
5618 rx_mon_stats = &pmon->rx_mon_stats;
5619
5620 if (pmon->hold_mon_dst_ring) {
5621 spin_unlock_bh(&pmon->mon_lock);
5622 goto reap_status_ring;
5623 }
5624
5625 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5626 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5627 head_msdu = NULL;
5628 tail_msdu = NULL;
5629
5630 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5631 &head_msdu,
5632 &tail_msdu,
5633 sw_mon_entries);
5634 rx_bufs_used += mpdu_rx_bufs_used;
5635
5636 if (!sw_mon_entries->end_of_ppdu) {
5637 if (head_msdu) {
5638 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5639 pmon->mon_mpdu,
5640 head_msdu,
5641 tail_msdu);
5642 if (ret)
5643 break_dst_ring = true;
5644 }
5645
5646 goto next_entry;
5647 } else {
5648 if (!sw_mon_entries->ppdu_id &&
5649 !sw_mon_entries->mon_status_paddr) {
5650 break_dst_ring = true;
5651 goto next_entry;
5652 }
5653 }
5654
5655 rx_mon_stats->dest_ppdu_done++;
5656 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5657 pmon->buf_state = DP_MON_STATUS_LAG;
5658 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5659 pmon->hold_mon_dst_ring = true;
5660 next_entry:
5661 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5662 mon_dst_srng);
5663 if (break_dst_ring)
5664 break;
5665 }
5666
5667 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5668 spin_unlock_bh(&pmon->mon_lock);
5669
5670 if (rx_bufs_used) {
5671 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5672 &dp->rxdma_mon_buf_ring,
5673 rx_bufs_used,
5674 HAL_RX_BUF_RBM_SW3_BM);
5675 }
5676
5677 reap_status_ring:
5678 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5679 napi, budget);
5680
5681 return quota;
5682 }
5683
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5684 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5685 struct napi_struct *napi, int budget)
5686 {
5687 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5688 int ret = 0;
5689
5690 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5691 ab->hw_params.full_monitor_mode)
5692 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5693 else
5694 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5695
5696 return ret;
5697 }
5698
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5699 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5700 {
5701 struct ath11k_pdev_dp *dp = &ar->dp;
5702 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5703
5704 skb_queue_head_init(&pmon->rx_status_q);
5705
5706 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5707
5708 memset(&pmon->rx_mon_stats, 0,
5709 sizeof(pmon->rx_mon_stats));
5710 return 0;
5711 }
5712
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5713 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5714 {
5715 struct ath11k_pdev_dp *dp = &ar->dp;
5716 struct ath11k_mon_data *pmon = &dp->mon_data;
5717 struct hal_srng *mon_desc_srng = NULL;
5718 struct dp_srng *dp_srng;
5719 int ret = 0;
5720 u32 n_link_desc = 0;
5721
5722 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5723 if (ret) {
5724 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5725 return ret;
5726 }
5727
5728 /* if rxdma1_enable is false, no need to setup
5729 * rxdma_mon_desc_ring.
5730 */
5731 if (!ar->ab->hw_params.rxdma1_enable)
5732 return 0;
5733
5734 dp_srng = &dp->rxdma_mon_desc_ring;
5735 n_link_desc = dp_srng->size /
5736 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5737 mon_desc_srng =
5738 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5739
5740 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5741 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5742 n_link_desc);
5743 if (ret) {
5744 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5745 return ret;
5746 }
5747 pmon->mon_last_linkdesc_paddr = 0;
5748 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5749 spin_lock_init(&pmon->mon_lock);
5750
5751 return 0;
5752 }
5753
ath11k_dp_mon_link_free(struct ath11k * ar)5754 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5755 {
5756 struct ath11k_pdev_dp *dp = &ar->dp;
5757 struct ath11k_mon_data *pmon = &dp->mon_data;
5758
5759 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5760 HAL_RXDMA_MONITOR_DESC,
5761 &dp->rxdma_mon_desc_ring);
5762 return 0;
5763 }
5764
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5765 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5766 {
5767 ath11k_dp_mon_link_free(ar);
5768 return 0;
5769 }
5770
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5771 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5772 {
5773 /* start reap timer */
5774 mod_timer(&ab->mon_reap_timer,
5775 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5776
5777 return 0;
5778 }
5779
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5780 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5781 {
5782 int ret;
5783
5784 if (stop_timer)
5785 del_timer_sync(&ab->mon_reap_timer);
5786
5787 /* reap all the monitor related rings */
5788 ret = ath11k_dp_purge_mon_ring(ab);
5789 if (ret) {
5790 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5791 return ret;
5792 }
5793
5794 return 0;
5795 }
5796