1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_rx.h"
8 #include "debug.h"
9 #include "hif.h"
10
11 const struct ce_attr ath12k_host_ce_config_qcn9274[] = {
12 /* CE0: host->target HTC control and raw streams */
13 {
14 .flags = CE_ATTR_FLAGS,
15 .src_nentries = 16,
16 .src_sz_max = 2048,
17 .dest_nentries = 0,
18 },
19
20 /* CE1: target->host HTT + HTC control */
21 {
22 .flags = CE_ATTR_FLAGS,
23 .src_nentries = 0,
24 .src_sz_max = 2048,
25 .dest_nentries = 512,
26 .recv_cb = ath12k_htc_rx_completion_handler,
27 },
28
29 /* CE2: target->host WMI */
30 {
31 .flags = CE_ATTR_FLAGS,
32 .src_nentries = 0,
33 .src_sz_max = 2048,
34 .dest_nentries = 128,
35 .recv_cb = ath12k_htc_rx_completion_handler,
36 },
37
38 /* CE3: host->target WMI (mac0) */
39 {
40 .flags = CE_ATTR_FLAGS,
41 .src_nentries = 32,
42 .src_sz_max = 2048,
43 .dest_nentries = 0,
44 },
45
46 /* CE4: host->target HTT */
47 {
48 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
49 .src_nentries = 2048,
50 .src_sz_max = 256,
51 .dest_nentries = 0,
52 },
53
54 /* CE5: target->host pktlog */
55 {
56 .flags = CE_ATTR_FLAGS,
57 .src_nentries = 0,
58 .src_sz_max = 2048,
59 .dest_nentries = 512,
60 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler,
61 },
62
63 /* CE6: target autonomous hif_memcpy */
64 {
65 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
66 .src_nentries = 0,
67 .src_sz_max = 0,
68 .dest_nentries = 0,
69 },
70
71 /* CE7: host->target WMI (mac1) */
72 {
73 .flags = CE_ATTR_FLAGS,
74 .src_nentries = 32,
75 .src_sz_max = 2048,
76 .dest_nentries = 0,
77 },
78
79 /* CE8: target autonomous hif_memcpy */
80 {
81 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
82 .src_nentries = 0,
83 .src_sz_max = 0,
84 .dest_nentries = 0,
85 },
86
87 /* CE9: MHI */
88 {
89 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
90 .src_nentries = 0,
91 .src_sz_max = 0,
92 .dest_nentries = 0,
93 },
94
95 /* CE10: MHI */
96 {
97 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
98 .src_nentries = 0,
99 .src_sz_max = 0,
100 .dest_nentries = 0,
101 },
102
103 /* CE11: MHI */
104 {
105 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
106 .src_nentries = 0,
107 .src_sz_max = 0,
108 .dest_nentries = 0,
109 },
110
111 /* CE12: CV Prefetch */
112 {
113 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
114 .src_nentries = 0,
115 .src_sz_max = 0,
116 .dest_nentries = 0,
117 },
118
119 /* CE13: CV Prefetch */
120 {
121 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
122 .src_nentries = 0,
123 .src_sz_max = 0,
124 .dest_nentries = 0,
125 },
126
127 /* CE14: target->host dbg log */
128 {
129 .flags = CE_ATTR_FLAGS,
130 .src_nentries = 0,
131 .src_sz_max = 2048,
132 .dest_nentries = 512,
133 .recv_cb = ath12k_htc_rx_completion_handler,
134 },
135
136 /* CE15: reserved for future use */
137 {
138 .flags = (CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
139 .src_nentries = 0,
140 .src_sz_max = 0,
141 .dest_nentries = 0,
142 },
143 };
144
145 const struct ce_attr ath12k_host_ce_config_wcn7850[] = {
146 /* CE0: host->target HTC control and raw streams */
147 {
148 .flags = CE_ATTR_FLAGS,
149 .src_nentries = 16,
150 .src_sz_max = 2048,
151 .dest_nentries = 0,
152 },
153
154 /* CE1: target->host HTT + HTC control */
155 {
156 .flags = CE_ATTR_FLAGS,
157 .src_nentries = 0,
158 .src_sz_max = 2048,
159 .dest_nentries = 512,
160 .recv_cb = ath12k_htc_rx_completion_handler,
161 },
162
163 /* CE2: target->host WMI */
164 {
165 .flags = CE_ATTR_FLAGS,
166 .src_nentries = 0,
167 .src_sz_max = 2048,
168 .dest_nentries = 64,
169 .recv_cb = ath12k_htc_rx_completion_handler,
170 },
171
172 /* CE3: host->target WMI (mac0) */
173 {
174 .flags = CE_ATTR_FLAGS,
175 .src_nentries = 32,
176 .src_sz_max = 2048,
177 .dest_nentries = 0,
178 },
179
180 /* CE4: host->target HTT */
181 {
182 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
183 .src_nentries = 2048,
184 .src_sz_max = 256,
185 .dest_nentries = 0,
186 },
187
188 /* CE5: target->host pktlog */
189 {
190 .flags = CE_ATTR_FLAGS,
191 .src_nentries = 0,
192 .src_sz_max = 0,
193 .dest_nentries = 0,
194 },
195
196 /* CE6: target autonomous hif_memcpy */
197 {
198 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
199 .src_nentries = 0,
200 .src_sz_max = 0,
201 .dest_nentries = 0,
202 },
203
204 /* CE7: host->target WMI (mac1) */
205 {
206 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
207 .src_nentries = 0,
208 .src_sz_max = 2048,
209 .dest_nentries = 0,
210 },
211
212 /* CE8: target autonomous hif_memcpy */
213 {
214 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
215 .src_nentries = 0,
216 .src_sz_max = 0,
217 .dest_nentries = 0,
218 },
219
220 };
221
ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe * pipe,struct sk_buff * skb,dma_addr_t paddr)222 static int ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe *pipe,
223 struct sk_buff *skb, dma_addr_t paddr)
224 {
225 struct ath12k_base *ab = pipe->ab;
226 struct ath12k_ce_ring *ring = pipe->dest_ring;
227 struct hal_srng *srng;
228 unsigned int write_index;
229 unsigned int nentries_mask = ring->nentries_mask;
230 struct hal_ce_srng_dest_desc *desc;
231 int ret;
232
233 lockdep_assert_held(&ab->ce.ce_lock);
234
235 write_index = ring->write_index;
236
237 srng = &ab->hal.srng_list[ring->hal_ring_id];
238
239 spin_lock_bh(&srng->lock);
240
241 ath12k_hal_srng_access_begin(ab, srng);
242
243 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
244 ret = -ENOSPC;
245 goto exit;
246 }
247
248 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
249 if (!desc) {
250 ret = -ENOSPC;
251 goto exit;
252 }
253
254 ath12k_hal_ce_dst_set_desc(desc, paddr);
255
256 ring->skb[write_index] = skb;
257 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
258 ring->write_index = write_index;
259
260 pipe->rx_buf_needed--;
261
262 ret = 0;
263 exit:
264 ath12k_hal_srng_access_end(ab, srng);
265
266 spin_unlock_bh(&srng->lock);
267
268 return ret;
269 }
270
ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe * pipe)271 static int ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe *pipe)
272 {
273 struct ath12k_base *ab = pipe->ab;
274 struct sk_buff *skb;
275 dma_addr_t paddr;
276 int ret = 0;
277
278 if (!(pipe->dest_ring || pipe->status_ring))
279 return 0;
280
281 spin_lock_bh(&ab->ce.ce_lock);
282 while (pipe->rx_buf_needed) {
283 skb = dev_alloc_skb(pipe->buf_sz);
284 if (!skb) {
285 ret = -ENOMEM;
286 goto exit;
287 }
288
289 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4));
290
291 paddr = dma_map_single(ab->dev, skb->data,
292 skb->len + skb_tailroom(skb),
293 DMA_FROM_DEVICE);
294 if (unlikely(dma_mapping_error(ab->dev, paddr))) {
295 ath12k_warn(ab, "failed to dma map ce rx buf\n");
296 dev_kfree_skb_any(skb);
297 ret = -EIO;
298 goto exit;
299 }
300
301 ATH12K_SKB_RXCB(skb)->paddr = paddr;
302
303 ret = ath12k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr);
304 if (ret) {
305 ath12k_warn(ab, "failed to enqueue rx buf: %d\n", ret);
306 dma_unmap_single(ab->dev, paddr,
307 skb->len + skb_tailroom(skb),
308 DMA_FROM_DEVICE);
309 dev_kfree_skb_any(skb);
310 goto exit;
311 }
312 }
313
314 exit:
315 spin_unlock_bh(&ab->ce.ce_lock);
316 return ret;
317 }
318
ath12k_ce_completed_recv_next(struct ath12k_ce_pipe * pipe,struct sk_buff ** skb,int * nbytes)319 static int ath12k_ce_completed_recv_next(struct ath12k_ce_pipe *pipe,
320 struct sk_buff **skb, int *nbytes)
321 {
322 struct ath12k_base *ab = pipe->ab;
323 struct hal_ce_srng_dst_status_desc *desc;
324 struct hal_srng *srng;
325 unsigned int sw_index;
326 unsigned int nentries_mask;
327 int ret = 0;
328
329 spin_lock_bh(&ab->ce.ce_lock);
330
331 sw_index = pipe->dest_ring->sw_index;
332 nentries_mask = pipe->dest_ring->nentries_mask;
333
334 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id];
335
336 spin_lock_bh(&srng->lock);
337
338 ath12k_hal_srng_access_begin(ab, srng);
339
340 desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
341 if (!desc) {
342 ret = -EIO;
343 goto err;
344 }
345
346 *nbytes = ath12k_hal_ce_dst_status_get_length(desc);
347
348 *skb = pipe->dest_ring->skb[sw_index];
349 pipe->dest_ring->skb[sw_index] = NULL;
350
351 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
352 pipe->dest_ring->sw_index = sw_index;
353
354 pipe->rx_buf_needed++;
355 err:
356 ath12k_hal_srng_access_end(ab, srng);
357
358 spin_unlock_bh(&srng->lock);
359
360 spin_unlock_bh(&ab->ce.ce_lock);
361
362 return ret;
363 }
364
ath12k_ce_recv_process_cb(struct ath12k_ce_pipe * pipe)365 static void ath12k_ce_recv_process_cb(struct ath12k_ce_pipe *pipe)
366 {
367 struct ath12k_base *ab = pipe->ab;
368 struct sk_buff *skb;
369 struct sk_buff_head list;
370 unsigned int nbytes, max_nbytes;
371 int ret;
372
373 __skb_queue_head_init(&list);
374 while (ath12k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) {
375 max_nbytes = skb->len + skb_tailroom(skb);
376 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
377 max_nbytes, DMA_FROM_DEVICE);
378
379 if (unlikely(max_nbytes < nbytes || nbytes == 0)) {
380 ath12k_warn(ab, "unexpected rx length (nbytes %d, max %d)",
381 nbytes, max_nbytes);
382 dev_kfree_skb_any(skb);
383 continue;
384 }
385
386 skb_put(skb, nbytes);
387 __skb_queue_tail(&list, skb);
388 }
389
390 while ((skb = __skb_dequeue(&list))) {
391 ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n",
392 pipe->pipe_num, skb->len);
393 pipe->recv_cb(ab, skb);
394 }
395
396 ret = ath12k_ce_rx_post_pipe(pipe);
397 if (ret && ret != -ENOSPC) {
398 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
399 pipe->pipe_num, ret);
400 mod_timer(&ab->rx_replenish_retry,
401 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
402 }
403 }
404
ath12k_ce_completed_send_next(struct ath12k_ce_pipe * pipe)405 static struct sk_buff *ath12k_ce_completed_send_next(struct ath12k_ce_pipe *pipe)
406 {
407 struct ath12k_base *ab = pipe->ab;
408 struct hal_ce_srng_src_desc *desc;
409 struct hal_srng *srng;
410 unsigned int sw_index;
411 unsigned int nentries_mask;
412 struct sk_buff *skb;
413
414 spin_lock_bh(&ab->ce.ce_lock);
415
416 sw_index = pipe->src_ring->sw_index;
417 nentries_mask = pipe->src_ring->nentries_mask;
418
419 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
420
421 spin_lock_bh(&srng->lock);
422
423 ath12k_hal_srng_access_begin(ab, srng);
424
425 desc = ath12k_hal_srng_src_reap_next(ab, srng);
426 if (!desc) {
427 skb = ERR_PTR(-EIO);
428 goto err_unlock;
429 }
430
431 skb = pipe->src_ring->skb[sw_index];
432
433 pipe->src_ring->skb[sw_index] = NULL;
434
435 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
436 pipe->src_ring->sw_index = sw_index;
437
438 err_unlock:
439 spin_unlock_bh(&srng->lock);
440
441 spin_unlock_bh(&ab->ce.ce_lock);
442
443 return skb;
444 }
445
ath12k_ce_send_done_cb(struct ath12k_ce_pipe * pipe)446 static void ath12k_ce_send_done_cb(struct ath12k_ce_pipe *pipe)
447 {
448 struct ath12k_base *ab = pipe->ab;
449 struct sk_buff *skb;
450
451 while (!IS_ERR(skb = ath12k_ce_completed_send_next(pipe))) {
452 if (!skb)
453 continue;
454
455 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len,
456 DMA_TO_DEVICE);
457 dev_kfree_skb_any(skb);
458 }
459 }
460
ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base * ab,u32 ce_id,struct hal_srng_params * ring_params)461 static void ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base *ab, u32 ce_id,
462 struct hal_srng_params *ring_params)
463 {
464 u32 msi_data_start;
465 u32 msi_data_count, msi_data_idx;
466 u32 msi_irq_start;
467 u32 addr_lo;
468 u32 addr_hi;
469 int ret;
470
471 ret = ath12k_hif_get_user_msi_vector(ab, "CE",
472 &msi_data_count, &msi_data_start,
473 &msi_irq_start);
474
475 if (ret)
476 return;
477
478 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
479 ath12k_hif_get_ce_msi_idx(ab, ce_id, &msi_data_idx);
480
481 ring_params->msi_addr = addr_lo;
482 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
483 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start;
484 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
485 }
486
ath12k_ce_init_ring(struct ath12k_base * ab,struct ath12k_ce_ring * ce_ring,int ce_id,enum hal_ring_type type)487 static int ath12k_ce_init_ring(struct ath12k_base *ab,
488 struct ath12k_ce_ring *ce_ring,
489 int ce_id, enum hal_ring_type type)
490 {
491 struct hal_srng_params params = { 0 };
492 int ret;
493
494 params.ring_base_paddr = ce_ring->base_addr_ce_space;
495 params.ring_base_vaddr = ce_ring->base_addr_owner_space;
496 params.num_entries = ce_ring->nentries;
497
498 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
499 ath12k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms);
500
501 switch (type) {
502 case HAL_CE_SRC:
503 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
504 params.intr_batch_cntr_thres_entries = 1;
505 break;
506 case HAL_CE_DST:
507 params.max_buffer_len = ab->hw_params->host_ce_config[ce_id].src_sz_max;
508 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
509 params.intr_timer_thres_us = 1024;
510 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
511 params.low_threshold = ce_ring->nentries - 3;
512 }
513 break;
514 case HAL_CE_DST_STATUS:
515 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
516 params.intr_batch_cntr_thres_entries = 1;
517 params.intr_timer_thres_us = 0x1000;
518 }
519 break;
520 default:
521 ath12k_warn(ab, "Invalid CE ring type %d\n", type);
522 return -EINVAL;
523 }
524
525 /* TODO: Init other params needed by HAL to init the ring */
526
527 ret = ath12k_hal_srng_setup(ab, type, ce_id, 0, ¶ms);
528 if (ret < 0) {
529 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
530 ret, ce_id);
531 return ret;
532 }
533
534 ce_ring->hal_ring_id = ret;
535
536 return 0;
537 }
538
539 static struct ath12k_ce_ring *
ath12k_ce_alloc_ring(struct ath12k_base * ab,int nentries,int desc_sz)540 ath12k_ce_alloc_ring(struct ath12k_base *ab, int nentries, int desc_sz)
541 {
542 struct ath12k_ce_ring *ce_ring;
543 dma_addr_t base_addr;
544
545 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL);
546 if (!ce_ring)
547 return ERR_PTR(-ENOMEM);
548
549 ce_ring->nentries = nentries;
550 ce_ring->nentries_mask = nentries - 1;
551
552 /* Legacy platforms that do not support cache
553 * coherent DMA are unsupported
554 */
555 ce_ring->base_addr_owner_space_unaligned =
556 dma_alloc_coherent(ab->dev,
557 nentries * desc_sz + CE_DESC_RING_ALIGN,
558 &base_addr, GFP_KERNEL);
559 if (!ce_ring->base_addr_owner_space_unaligned) {
560 kfree(ce_ring);
561 return ERR_PTR(-ENOMEM);
562 }
563
564 ce_ring->base_addr_ce_space_unaligned = base_addr;
565
566 ce_ring->base_addr_owner_space =
567 PTR_ALIGN(ce_ring->base_addr_owner_space_unaligned,
568 CE_DESC_RING_ALIGN);
569
570 ce_ring->base_addr_ce_space = ALIGN(ce_ring->base_addr_ce_space_unaligned,
571 CE_DESC_RING_ALIGN);
572
573 return ce_ring;
574 }
575
ath12k_ce_alloc_pipe(struct ath12k_base * ab,int ce_id)576 static int ath12k_ce_alloc_pipe(struct ath12k_base *ab, int ce_id)
577 {
578 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
579 const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id];
580 struct ath12k_ce_ring *ring;
581 int nentries;
582 int desc_sz;
583
584 pipe->attr_flags = attr->flags;
585
586 if (attr->src_nentries) {
587 pipe->send_cb = ath12k_ce_send_done_cb;
588 nentries = roundup_pow_of_two(attr->src_nentries);
589 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
590 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
591 if (IS_ERR(ring))
592 return PTR_ERR(ring);
593 pipe->src_ring = ring;
594 }
595
596 if (attr->dest_nentries) {
597 pipe->recv_cb = attr->recv_cb;
598 nentries = roundup_pow_of_two(attr->dest_nentries);
599 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
600 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
601 if (IS_ERR(ring))
602 return PTR_ERR(ring);
603 pipe->dest_ring = ring;
604
605 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
606 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
607 if (IS_ERR(ring))
608 return PTR_ERR(ring);
609 pipe->status_ring = ring;
610 }
611
612 return 0;
613 }
614
ath12k_ce_per_engine_service(struct ath12k_base * ab,u16 ce_id)615 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id)
616 {
617 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
618
619 if (pipe->send_cb)
620 pipe->send_cb(pipe);
621
622 if (pipe->recv_cb)
623 ath12k_ce_recv_process_cb(pipe);
624 }
625
ath12k_ce_poll_send_completed(struct ath12k_base * ab,u8 pipe_id)626 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id)
627 {
628 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
629
630 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb)
631 pipe->send_cb(pipe);
632 }
633
ath12k_ce_send(struct ath12k_base * ab,struct sk_buff * skb,u8 pipe_id,u16 transfer_id)634 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id,
635 u16 transfer_id)
636 {
637 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
638 struct hal_ce_srng_src_desc *desc;
639 struct hal_srng *srng;
640 unsigned int write_index, sw_index;
641 unsigned int nentries_mask;
642 int ret = 0;
643 u8 byte_swap_data = 0;
644 int num_used;
645
646 /* Check if some entries could be regained by handling tx completion if
647 * the CE has interrupts disabled and the used entries is more than the
648 * defined usage threshold.
649 */
650 if (pipe->attr_flags & CE_ATTR_DIS_INTR) {
651 spin_lock_bh(&ab->ce.ce_lock);
652 write_index = pipe->src_ring->write_index;
653
654 sw_index = pipe->src_ring->sw_index;
655
656 if (write_index >= sw_index)
657 num_used = write_index - sw_index;
658 else
659 num_used = pipe->src_ring->nentries - sw_index +
660 write_index;
661
662 spin_unlock_bh(&ab->ce.ce_lock);
663
664 if (num_used > ATH12K_CE_USAGE_THRESHOLD)
665 ath12k_ce_poll_send_completed(ab, pipe->pipe_num);
666 }
667
668 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags))
669 return -ESHUTDOWN;
670
671 spin_lock_bh(&ab->ce.ce_lock);
672
673 write_index = pipe->src_ring->write_index;
674 nentries_mask = pipe->src_ring->nentries_mask;
675
676 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
677
678 spin_lock_bh(&srng->lock);
679
680 ath12k_hal_srng_access_begin(ab, srng);
681
682 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
683 ath12k_hal_srng_access_end(ab, srng);
684 ret = -ENOBUFS;
685 goto unlock;
686 }
687
688 desc = ath12k_hal_srng_src_get_next_reaped(ab, srng);
689 if (!desc) {
690 ath12k_hal_srng_access_end(ab, srng);
691 ret = -ENOBUFS;
692 goto unlock;
693 }
694
695 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)
696 byte_swap_data = 1;
697
698 ath12k_hal_ce_src_set_desc(desc, ATH12K_SKB_CB(skb)->paddr,
699 skb->len, transfer_id, byte_swap_data);
700
701 pipe->src_ring->skb[write_index] = skb;
702 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,
703 write_index);
704
705 ath12k_hal_srng_access_end(ab, srng);
706
707 unlock:
708 spin_unlock_bh(&srng->lock);
709
710 spin_unlock_bh(&ab->ce.ce_lock);
711
712 return ret;
713 }
714
ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe * pipe)715 static void ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe *pipe)
716 {
717 struct ath12k_base *ab = pipe->ab;
718 struct ath12k_ce_ring *ring = pipe->dest_ring;
719 struct sk_buff *skb;
720 int i;
721
722 if (!(ring && pipe->buf_sz))
723 return;
724
725 for (i = 0; i < ring->nentries; i++) {
726 skb = ring->skb[i];
727 if (!skb)
728 continue;
729
730 ring->skb[i] = NULL;
731 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
732 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
733 dev_kfree_skb_any(skb);
734 }
735 }
736
ath12k_ce_cleanup_pipes(struct ath12k_base * ab)737 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab)
738 {
739 struct ath12k_ce_pipe *pipe;
740 int pipe_num;
741
742 for (pipe_num = 0; pipe_num < ab->hw_params->ce_count; pipe_num++) {
743 pipe = &ab->ce.ce_pipe[pipe_num];
744 ath12k_ce_rx_pipe_cleanup(pipe);
745
746 /* Cleanup any src CE's which have interrupts disabled */
747 ath12k_ce_poll_send_completed(ab, pipe_num);
748
749 /* NOTE: Should we also clean up tx buffer in all pipes? */
750 }
751 }
752
ath12k_ce_rx_post_buf(struct ath12k_base * ab)753 void ath12k_ce_rx_post_buf(struct ath12k_base *ab)
754 {
755 struct ath12k_ce_pipe *pipe;
756 int i;
757 int ret;
758
759 for (i = 0; i < ab->hw_params->ce_count; i++) {
760 pipe = &ab->ce.ce_pipe[i];
761 ret = ath12k_ce_rx_post_pipe(pipe);
762 if (ret) {
763 if (ret == -ENOSPC)
764 continue;
765
766 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
767 i, ret);
768 mod_timer(&ab->rx_replenish_retry,
769 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
770
771 return;
772 }
773 }
774 }
775
ath12k_ce_rx_replenish_retry(struct timer_list * t)776 void ath12k_ce_rx_replenish_retry(struct timer_list *t)
777 {
778 struct ath12k_base *ab = from_timer(ab, t, rx_replenish_retry);
779
780 ath12k_ce_rx_post_buf(ab);
781 }
782
ath12k_ce_shadow_config(struct ath12k_base * ab)783 static void ath12k_ce_shadow_config(struct ath12k_base *ab)
784 {
785 int i;
786
787 for (i = 0; i < ab->hw_params->ce_count; i++) {
788 if (ab->hw_params->host_ce_config[i].src_nentries)
789 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_SRC, i);
790
791 if (ab->hw_params->host_ce_config[i].dest_nentries) {
792 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST, i);
793 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST_STATUS, i);
794 }
795 }
796 }
797
ath12k_ce_get_shadow_config(struct ath12k_base * ab,u32 ** shadow_cfg,u32 * shadow_cfg_len)798 void ath12k_ce_get_shadow_config(struct ath12k_base *ab,
799 u32 **shadow_cfg, u32 *shadow_cfg_len)
800 {
801 if (!ab->hw_params->supports_shadow_regs)
802 return;
803
804 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
805
806 /* shadow is already configured */
807 if (*shadow_cfg_len)
808 return;
809
810 /* shadow isn't configured yet, configure now.
811 * non-CE srngs are configured firstly, then
812 * all CE srngs.
813 */
814 ath12k_hal_srng_shadow_config(ab);
815 ath12k_ce_shadow_config(ab);
816
817 /* get the shadow configuration */
818 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
819 }
820
ath12k_ce_init_pipes(struct ath12k_base * ab)821 int ath12k_ce_init_pipes(struct ath12k_base *ab)
822 {
823 struct ath12k_ce_pipe *pipe;
824 int i;
825 int ret;
826
827 ath12k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v3,
828 &ab->qmi.ce_cfg.shadow_reg_v3_len);
829
830 for (i = 0; i < ab->hw_params->ce_count; i++) {
831 pipe = &ab->ce.ce_pipe[i];
832
833 if (pipe->src_ring) {
834 ret = ath12k_ce_init_ring(ab, pipe->src_ring, i,
835 HAL_CE_SRC);
836 if (ret) {
837 ath12k_warn(ab, "failed to init src ring: %d\n",
838 ret);
839 /* Should we clear any partial init */
840 return ret;
841 }
842
843 pipe->src_ring->write_index = 0;
844 pipe->src_ring->sw_index = 0;
845 }
846
847 if (pipe->dest_ring) {
848 ret = ath12k_ce_init_ring(ab, pipe->dest_ring, i,
849 HAL_CE_DST);
850 if (ret) {
851 ath12k_warn(ab, "failed to init dest ring: %d\n",
852 ret);
853 /* Should we clear any partial init */
854 return ret;
855 }
856
857 pipe->rx_buf_needed = pipe->dest_ring->nentries ?
858 pipe->dest_ring->nentries - 2 : 0;
859
860 pipe->dest_ring->write_index = 0;
861 pipe->dest_ring->sw_index = 0;
862 }
863
864 if (pipe->status_ring) {
865 ret = ath12k_ce_init_ring(ab, pipe->status_ring, i,
866 HAL_CE_DST_STATUS);
867 if (ret) {
868 ath12k_warn(ab, "failed to init dest status ing: %d\n",
869 ret);
870 /* Should we clear any partial init */
871 return ret;
872 }
873
874 pipe->status_ring->write_index = 0;
875 pipe->status_ring->sw_index = 0;
876 }
877 }
878
879 return 0;
880 }
881
ath12k_ce_free_pipes(struct ath12k_base * ab)882 void ath12k_ce_free_pipes(struct ath12k_base *ab)
883 {
884 struct ath12k_ce_pipe *pipe;
885 int desc_sz;
886 int i;
887
888 for (i = 0; i < ab->hw_params->ce_count; i++) {
889 pipe = &ab->ce.ce_pipe[i];
890
891 if (pipe->src_ring) {
892 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
893 dma_free_coherent(ab->dev,
894 pipe->src_ring->nentries * desc_sz +
895 CE_DESC_RING_ALIGN,
896 pipe->src_ring->base_addr_owner_space,
897 pipe->src_ring->base_addr_ce_space);
898 kfree(pipe->src_ring);
899 pipe->src_ring = NULL;
900 }
901
902 if (pipe->dest_ring) {
903 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
904 dma_free_coherent(ab->dev,
905 pipe->dest_ring->nentries * desc_sz +
906 CE_DESC_RING_ALIGN,
907 pipe->dest_ring->base_addr_owner_space,
908 pipe->dest_ring->base_addr_ce_space);
909 kfree(pipe->dest_ring);
910 pipe->dest_ring = NULL;
911 }
912
913 if (pipe->status_ring) {
914 desc_sz =
915 ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
916 dma_free_coherent(ab->dev,
917 pipe->status_ring->nentries * desc_sz +
918 CE_DESC_RING_ALIGN,
919 pipe->status_ring->base_addr_owner_space,
920 pipe->status_ring->base_addr_ce_space);
921 kfree(pipe->status_ring);
922 pipe->status_ring = NULL;
923 }
924 }
925 }
926
ath12k_ce_alloc_pipes(struct ath12k_base * ab)927 int ath12k_ce_alloc_pipes(struct ath12k_base *ab)
928 {
929 struct ath12k_ce_pipe *pipe;
930 int i;
931 int ret;
932 const struct ce_attr *attr;
933
934 spin_lock_init(&ab->ce.ce_lock);
935
936 for (i = 0; i < ab->hw_params->ce_count; i++) {
937 attr = &ab->hw_params->host_ce_config[i];
938 pipe = &ab->ce.ce_pipe[i];
939 pipe->pipe_num = i;
940 pipe->ab = ab;
941 pipe->buf_sz = attr->src_sz_max;
942
943 ret = ath12k_ce_alloc_pipe(ab, i);
944 if (ret) {
945 /* Free any partial successful allocation */
946 ath12k_ce_free_pipes(ab);
947 return ret;
948 }
949 }
950
951 return 0;
952 }
953
ath12k_ce_get_attr_flags(struct ath12k_base * ab,int ce_id)954 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id)
955 {
956 if (ce_id >= ab->hw_params->ce_count)
957 return -EINVAL;
958
959 return ab->hw_params->host_ce_config[ce_id].flags;
960 }
961