1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/firmware.h>
17 #include <linux/panic_notifier.h>
18 #include "qmi.h"
19 #include "htc.h"
20 #include "wmi.h"
21 #include "hal.h"
22 #include "dp.h"
23 #include "ce.h"
24 #include "mac.h"
25 #include "hw.h"
26 #include "hal_rx.h"
27 #include "reg.h"
28 #include "dbring.h"
29 #include "fw.h"
30 #include "acpi.h"
31 #include "wow.h"
32 #include "debugfs_htt_stats.h"
33
34 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
35
36 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
37
38 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
39
40 /* Pending management packets threshold for dropping probe responses */
41 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
42
43 /* SMBIOS type containing Board Data File Name Extension */
44 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
45
46 /* SMBIOS type structure length (excluding strings-set) */
47 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
48
49 /* The magic used by QCA spec */
50 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
51
52 #define ATH12K_INVALID_HW_MAC_ID 0xFF
53 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ)
54 #define ATH12K_RX_RATE_TABLE_NUM 320
55 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576
56
57 #define ATH12K_MON_TIMER_INTERVAL 10
58 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
59 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
60 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
61 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
62 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
63 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
64
65 enum ath12k_bdf_search {
66 ATH12K_BDF_SEARCH_DEFAULT,
67 ATH12K_BDF_SEARCH_BUS_AND_BOARD,
68 };
69
70 enum wme_ac {
71 WME_AC_BE,
72 WME_AC_BK,
73 WME_AC_VI,
74 WME_AC_VO,
75 WME_NUM_AC
76 };
77
78 #define ATH12K_HT_MCS_MAX 7
79 #define ATH12K_VHT_MCS_MAX 9
80 #define ATH12K_HE_MCS_MAX 11
81
82 enum ath12k_crypt_mode {
83 /* Only use hardware crypto engine */
84 ATH12K_CRYPT_MODE_HW,
85 /* Only use software crypto */
86 ATH12K_CRYPT_MODE_SW,
87 };
88
ath12k_tid_to_ac(u32 tid)89 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
90 {
91 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
92 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
93 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
94 WME_AC_VO);
95 }
96
97 enum ath12k_skb_flags {
98 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
99 ATH12K_SKB_CIPHER_SET = BIT(1),
100 };
101
102 struct ath12k_skb_cb {
103 dma_addr_t paddr;
104 struct ath12k *ar;
105 struct ieee80211_vif *vif;
106 dma_addr_t paddr_ext_desc;
107 u32 cipher;
108 u8 flags;
109 };
110
111 struct ath12k_skb_rxcb {
112 dma_addr_t paddr;
113 bool is_first_msdu;
114 bool is_last_msdu;
115 bool is_continuation;
116 bool is_mcbc;
117 bool is_eapol;
118 struct hal_rx_desc *rx_desc;
119 u8 err_rel_src;
120 u8 err_code;
121 u8 mac_id;
122 u8 unmapped;
123 u8 is_frag;
124 u8 tid;
125 u16 peer_id;
126 };
127
128 enum ath12k_hw_rev {
129 ATH12K_HW_QCN9274_HW10,
130 ATH12K_HW_QCN9274_HW20,
131 ATH12K_HW_WCN7850_HW20
132 };
133
134 enum ath12k_firmware_mode {
135 /* the default mode, standard 802.11 functionality */
136 ATH12K_FIRMWARE_MODE_NORMAL,
137
138 /* factory tests etc */
139 ATH12K_FIRMWARE_MODE_FTM,
140 };
141
142 #define ATH12K_IRQ_NUM_MAX 57
143 #define ATH12K_EXT_IRQ_NUM_MAX 16
144
145 struct ath12k_ext_irq_grp {
146 struct ath12k_base *ab;
147 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
148 u32 num_irq;
149 u32 grp_id;
150 u64 timestamp;
151 bool napi_enabled;
152 struct napi_struct napi;
153 struct net_device *napi_ndev;
154 };
155
156 struct ath12k_smbios_bdf {
157 struct dmi_header hdr;
158 u32 padding;
159 u8 bdf_enabled;
160 u8 bdf_ext[];
161 } __packed;
162
163 #define HEHANDLE_CAP_PHYINFO_SIZE 3
164 #define HECAP_PHYINFO_SIZE 9
165 #define HECAP_MACINFO_SIZE 5
166 #define HECAP_TXRX_MCS_NSS_SIZE 2
167 #define HECAP_PPET16_PPET8_MAX_SIZE 25
168
169 #define HE_PPET16_PPET8_SIZE 8
170
171 /* 802.11ax PPE (PPDU packet Extension) threshold */
172 struct he_ppe_threshold {
173 u32 numss_m1;
174 u32 ru_mask;
175 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
176 };
177
178 struct ath12k_he {
179 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
180 u32 hecap_rxmcsnssmap;
181 u32 hecap_txmcsnssmap;
182 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
183 struct he_ppe_threshold hecap_ppet;
184 u32 heop_param;
185 };
186
187 enum {
188 WMI_HOST_TP_SCALE_MAX = 0,
189 WMI_HOST_TP_SCALE_50 = 1,
190 WMI_HOST_TP_SCALE_25 = 2,
191 WMI_HOST_TP_SCALE_12 = 3,
192 WMI_HOST_TP_SCALE_MIN = 4,
193 WMI_HOST_TP_SCALE_SIZE = 5,
194 };
195
196 enum ath12k_scan_state {
197 ATH12K_SCAN_IDLE,
198 ATH12K_SCAN_STARTING,
199 ATH12K_SCAN_RUNNING,
200 ATH12K_SCAN_ABORTING,
201 };
202
203 enum ath12k_dev_flags {
204 ATH12K_CAC_RUNNING,
205 ATH12K_FLAG_CRASH_FLUSH,
206 ATH12K_FLAG_RAW_MODE,
207 ATH12K_FLAG_HW_CRYPTO_DISABLED,
208 ATH12K_FLAG_RECOVERY,
209 ATH12K_FLAG_UNREGISTERING,
210 ATH12K_FLAG_REGISTERED,
211 ATH12K_FLAG_QMI_FAIL,
212 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
213 ATH12K_FLAG_CE_IRQ_ENABLED,
214 ATH12K_FLAG_EXT_IRQ_ENABLED,
215 };
216
217 struct ath12k_tx_conf {
218 bool changed;
219 u16 ac;
220 struct ieee80211_tx_queue_params tx_queue_params;
221 };
222
223 struct ath12k_key_conf {
224 bool changed;
225 enum set_key_cmd cmd;
226 struct ieee80211_key_conf *key;
227 };
228
229 struct ath12k_vif_cache {
230 struct ath12k_tx_conf tx_conf;
231 struct ath12k_key_conf key_conf;
232 u32 bss_conf_changed;
233 };
234
235 struct ath12k_rekey_data {
236 u8 kck[NL80211_KCK_LEN];
237 u8 kek[NL80211_KCK_LEN];
238 u64 replay_ctr;
239 bool enable_offload;
240 };
241
242 struct ath12k_vif {
243 u32 vdev_id;
244 enum wmi_vdev_type vdev_type;
245 enum wmi_vdev_subtype vdev_subtype;
246 u32 beacon_interval;
247 u32 dtim_period;
248 u16 ast_hash;
249 u16 ast_idx;
250 u16 tcl_metadata;
251 u8 hal_addr_search_flags;
252 u8 search_type;
253
254 struct ath12k *ar;
255 struct ieee80211_vif *vif;
256
257 int bank_id;
258 u8 vdev_id_check_en;
259
260 struct wmi_wmm_params_all_arg wmm_params;
261 struct list_head list;
262 union {
263 struct {
264 u32 uapsd;
265 } sta;
266 struct {
267 /* 127 stations; wmi limit */
268 u8 tim_bitmap[16];
269 u8 tim_len;
270 u32 ssid_len;
271 u8 ssid[IEEE80211_MAX_SSID_LEN];
272 bool hidden_ssid;
273 /* P2P_IE with NoA attribute for P2P_GO case */
274 u32 noa_len;
275 u8 *noa_data;
276 } ap;
277 } u;
278
279 bool is_created;
280 bool is_started;
281 bool is_up;
282 u32 aid;
283 u8 bssid[ETH_ALEN];
284 struct cfg80211_bitrate_mask bitrate_mask;
285 struct delayed_work connection_loss_work;
286 int num_legacy_stations;
287 int rtscts_prot_mode;
288 int txpower;
289 bool rsnie_present;
290 bool wpaie_present;
291 u32 key_cipher;
292 u8 tx_encap_type;
293 u8 vdev_stats_id;
294 u32 punct_bitmap;
295 bool ps;
296 struct ath12k_vif_cache *cache;
297 struct ath12k_rekey_data rekey_data;
298
299 /* Must be last - ends in a flexible-array member.
300 *
301 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
302 * especially because it has a flexible array. Find a better way.
303 */
304 struct ieee80211_chanctx_conf chanctx;
305 };
306
307 struct ath12k_vif_iter {
308 u32 vdev_id;
309 struct ath12k *ar;
310 struct ath12k_vif *arvif;
311 };
312
313 #define HAL_AST_IDX_INVALID 0xFFFF
314 #define HAL_RX_MAX_MCS 12
315 #define HAL_RX_MAX_MCS_HT 31
316 #define HAL_RX_MAX_MCS_VHT 9
317 #define HAL_RX_MAX_MCS_HE 11
318 #define HAL_RX_MAX_NSS 8
319 #define HAL_RX_MAX_NUM_LEGACY_RATES 12
320 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576
321 #define ATH12K_RX_RATE_TABLE_NUM 320
322
323 struct ath12k_rx_peer_rate_stats {
324 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
325 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
326 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
327 u64 nss_count[HAL_RX_MAX_NSS];
328 u64 bw_count[HAL_RX_BW_MAX];
329 u64 gi_count[HAL_RX_GI_MAX];
330 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
331 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM];
332 };
333
334 struct ath12k_rx_peer_stats {
335 u64 num_msdu;
336 u64 num_mpdu_fcs_ok;
337 u64 num_mpdu_fcs_err;
338 u64 tcp_msdu_count;
339 u64 udp_msdu_count;
340 u64 other_msdu_count;
341 u64 ampdu_msdu_count;
342 u64 non_ampdu_msdu_count;
343 u64 stbc_count;
344 u64 beamformed_count;
345 u64 mcs_count[HAL_RX_MAX_MCS + 1];
346 u64 nss_count[HAL_RX_MAX_NSS];
347 u64 bw_count[HAL_RX_BW_MAX];
348 u64 gi_count[HAL_RX_GI_MAX];
349 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
350 u64 tid_count[IEEE80211_NUM_TIDS + 1];
351 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
352 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
353 u64 rx_duration;
354 u64 dcm_count;
355 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
356 struct ath12k_rx_peer_rate_stats pkt_stats;
357 struct ath12k_rx_peer_rate_stats byte_stats;
358 };
359
360 #define ATH12K_HE_MCS_NUM 12
361 #define ATH12K_VHT_MCS_NUM 10
362 #define ATH12K_BW_NUM 5
363 #define ATH12K_NSS_NUM 4
364 #define ATH12K_LEGACY_NUM 12
365 #define ATH12K_GI_NUM 4
366 #define ATH12K_HT_MCS_NUM 32
367
368 enum ath12k_pkt_rx_err {
369 ATH12K_PKT_RX_ERR_FCS,
370 ATH12K_PKT_RX_ERR_TKIP,
371 ATH12K_PKT_RX_ERR_CRYPT,
372 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
373 ATH12K_PKT_RX_ERR_MAX,
374 };
375
376 enum ath12k_ampdu_subfrm_num {
377 ATH12K_AMPDU_SUBFRM_NUM_10,
378 ATH12K_AMPDU_SUBFRM_NUM_20,
379 ATH12K_AMPDU_SUBFRM_NUM_30,
380 ATH12K_AMPDU_SUBFRM_NUM_40,
381 ATH12K_AMPDU_SUBFRM_NUM_50,
382 ATH12K_AMPDU_SUBFRM_NUM_60,
383 ATH12K_AMPDU_SUBFRM_NUM_MORE,
384 ATH12K_AMPDU_SUBFRM_NUM_MAX,
385 };
386
387 enum ath12k_amsdu_subfrm_num {
388 ATH12K_AMSDU_SUBFRM_NUM_1,
389 ATH12K_AMSDU_SUBFRM_NUM_2,
390 ATH12K_AMSDU_SUBFRM_NUM_3,
391 ATH12K_AMSDU_SUBFRM_NUM_4,
392 ATH12K_AMSDU_SUBFRM_NUM_MORE,
393 ATH12K_AMSDU_SUBFRM_NUM_MAX,
394 };
395
396 enum ath12k_counter_type {
397 ATH12K_COUNTER_TYPE_BYTES,
398 ATH12K_COUNTER_TYPE_PKTS,
399 ATH12K_COUNTER_TYPE_MAX,
400 };
401
402 enum ath12k_stats_type {
403 ATH12K_STATS_TYPE_SUCC,
404 ATH12K_STATS_TYPE_FAIL,
405 ATH12K_STATS_TYPE_RETRY,
406 ATH12K_STATS_TYPE_AMPDU,
407 ATH12K_STATS_TYPE_MAX,
408 };
409
410 struct ath12k_htt_data_stats {
411 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
412 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
413 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
414 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
415 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
416 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
417 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
418 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
419 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
420 };
421
422 struct ath12k_htt_tx_stats {
423 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
424 u64 tx_duration;
425 u64 ba_fails;
426 u64 ack_fails;
427 u16 ru_start;
428 u16 ru_tones;
429 u32 mu_group[MAX_MU_GROUP_ID];
430 };
431
432 struct ath12k_per_ppdu_tx_stats {
433 u16 succ_pkts;
434 u16 failed_pkts;
435 u16 retry_pkts;
436 u32 succ_bytes;
437 u32 failed_bytes;
438 u32 retry_bytes;
439 };
440
441 struct ath12k_wbm_tx_stats {
442 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
443 };
444
445 struct ath12k_sta {
446 struct ath12k_vif *arvif;
447
448 /* the following are protected by ar->data_lock */
449 u32 changed; /* IEEE80211_RC_* */
450 u32 bw;
451 u32 nss;
452 u32 smps;
453 enum hal_pn_type pn_type;
454
455 struct work_struct update_wk;
456 struct rate_info txrate;
457 struct rate_info last_txrate;
458 u64 rx_duration;
459 u64 tx_duration;
460 u8 rssi_comb;
461 struct ath12k_rx_peer_stats *rx_stats;
462 struct ath12k_wbm_tx_stats *wbm_tx_stats;
463 u32 bw_prev;
464 };
465
466 #define ATH12K_MIN_5G_FREQ 4150
467 #define ATH12K_MIN_6G_FREQ 5925
468 #define ATH12K_MAX_6G_FREQ 7115
469 #define ATH12K_NUM_CHANS 101
470 #define ATH12K_MAX_5G_CHAN 173
471
472 enum ath12k_hw_state {
473 ATH12K_HW_STATE_OFF,
474 ATH12K_HW_STATE_ON,
475 ATH12K_HW_STATE_RESTARTING,
476 ATH12K_HW_STATE_RESTARTED,
477 ATH12K_HW_STATE_WEDGED,
478 /* Add other states as required */
479 };
480
481 /* Antenna noise floor */
482 #define ATH12K_DEFAULT_NOISE_FLOOR -95
483
484 struct ath12k_fw_stats {
485 u32 pdev_id;
486 u32 stats_id;
487 struct list_head pdevs;
488 struct list_head vdevs;
489 struct list_head bcn;
490 };
491
492 struct ath12k_dbg_htt_stats {
493 enum ath12k_dbg_htt_ext_stats_type type;
494 u32 cfg_param[4];
495 u8 reset;
496 struct debug_htt_stats_req *stats_req;
497 };
498
499 struct ath12k_debug {
500 struct dentry *debugfs_pdev;
501 struct dentry *debugfs_pdev_symlink;
502 struct ath12k_dbg_htt_stats htt_stats;
503 };
504
505 struct ath12k_per_peer_tx_stats {
506 u32 succ_bytes;
507 u32 retry_bytes;
508 u32 failed_bytes;
509 u32 duration;
510 u16 succ_pkts;
511 u16 retry_pkts;
512 u16 failed_pkts;
513 u16 ru_start;
514 u16 ru_tones;
515 u8 ba_fails;
516 u8 ppdu_type;
517 u32 mu_grpid;
518 u32 mu_pos;
519 bool is_ampdu;
520 };
521
522 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
523 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
524
525 struct ath12k {
526 struct ath12k_base *ab;
527 struct ath12k_pdev *pdev;
528 struct ath12k_hw *ah;
529 struct ath12k_wmi_pdev *wmi;
530 struct ath12k_pdev_dp dp;
531 u8 mac_addr[ETH_ALEN];
532 u32 ht_cap_info;
533 u32 vht_cap_info;
534 struct ath12k_he ar_he;
535 bool supports_6ghz;
536 struct {
537 struct completion started;
538 struct completion completed;
539 struct completion on_channel;
540 struct delayed_work timeout;
541 enum ath12k_scan_state state;
542 bool is_roc;
543 int vdev_id;
544 int roc_freq;
545 bool roc_notify;
546 } scan;
547
548 struct {
549 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
550 struct ieee80211_sband_iftype_data
551 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
552 } mac;
553
554 unsigned long dev_flags;
555 unsigned int filter_flags;
556 u32 min_tx_power;
557 u32 max_tx_power;
558 u32 txpower_limit_2g;
559 u32 txpower_limit_5g;
560 u32 txpower_scale;
561 u32 power_scale;
562 u32 chan_tx_pwr;
563 u32 num_stations;
564 u32 max_num_stations;
565 bool monitor_present;
566 /* To synchronize concurrent synchronous mac80211 callback operations,
567 * concurrent debugfs configuration and concurrent FW statistics events.
568 */
569 struct mutex conf_mutex;
570 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
571 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info,
572 * channel context data, survey info, test mode data.
573 */
574 spinlock_t data_lock;
575
576 struct list_head arvifs;
577 /* should never be NULL; needed for regular htt rx */
578 struct ieee80211_channel *rx_channel;
579
580 /* valid during scan; needed for mgmt rx during scan */
581 struct ieee80211_channel *scan_channel;
582
583 u8 cfg_tx_chainmask;
584 u8 cfg_rx_chainmask;
585 u8 num_rx_chains;
586 u8 num_tx_chains;
587 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
588 u8 pdev_idx;
589 u8 lmac_id;
590 u8 hw_link_id;
591
592 struct completion peer_assoc_done;
593 struct completion peer_delete_done;
594
595 int install_key_status;
596 struct completion install_key_done;
597
598 int last_wmi_vdev_start_status;
599 struct completion vdev_setup_done;
600 struct completion vdev_delete_done;
601
602 int num_peers;
603 int max_num_peers;
604 u32 num_started_vdevs;
605 u32 num_created_vdevs;
606 unsigned long long allocated_vdev_map;
607
608 struct idr txmgmt_idr;
609 /* protects txmgmt_idr data */
610 spinlock_t txmgmt_idr_lock;
611 atomic_t num_pending_mgmt_tx;
612 wait_queue_head_t txmgmt_empty_waitq;
613
614 /* cycle count is reported twice for each visited channel during scan.
615 * access protected by data_lock
616 */
617 u32 survey_last_rx_clear_count;
618 u32 survey_last_cycle_count;
619
620 /* Channel info events are expected to come in pairs without and with
621 * COMPLETE flag set respectively for each channel visit during scan.
622 *
623 * However there are deviations from this rule. This flag is used to
624 * avoid reporting garbage data.
625 */
626 bool ch_info_can_report_survey;
627 struct survey_info survey[ATH12K_NUM_CHANS];
628 struct completion bss_survey_done;
629
630 struct work_struct regd_update_work;
631
632 struct work_struct wmi_mgmt_tx_work;
633 struct sk_buff_head wmi_mgmt_tx_queue;
634
635 struct ath12k_wow wow;
636 struct completion target_suspend;
637 bool target_suspend_ack;
638 struct ath12k_per_peer_tx_stats peer_tx_stats;
639 struct list_head ppdu_stats_info;
640 u32 ppdu_stat_list_depth;
641
642 struct ath12k_per_peer_tx_stats cached_stats;
643 u32 last_ppdu_id;
644 u32 cached_ppdu_id;
645 #ifdef CONFIG_ATH12K_DEBUGFS
646 struct ath12k_debug debug;
647 #endif
648
649 bool dfs_block_radar_events;
650 bool monitor_conf_enabled;
651 bool monitor_vdev_created;
652 bool monitor_started;
653 int monitor_vdev_id;
654
655 u32 freq_low;
656 u32 freq_high;
657
658 bool nlo_enabled;
659 };
660
661 struct ath12k_hw {
662 struct ieee80211_hw *hw;
663 /* Protect the write operation of the hardware state ath12k_hw::state
664 * between hardware start<=>reconfigure<=>stop transitions.
665 */
666 struct mutex hw_mutex;
667 enum ath12k_hw_state state;
668 bool regd_updated;
669 bool use_6ghz_regd;
670 u8 num_radio;
671
672 /* Keep last */
673 struct ath12k radio[] __aligned(sizeof(void *));
674 };
675
676 struct ath12k_band_cap {
677 u32 phy_id;
678 u32 max_bw_supported;
679 u32 ht_cap_info;
680 u32 he_cap_info[2];
681 u32 he_mcs;
682 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
683 struct ath12k_wmi_ppe_threshold_arg he_ppet;
684 u16 he_6ghz_capa;
685 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
686 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
687 u32 eht_mcs_20_only;
688 u32 eht_mcs_80;
689 u32 eht_mcs_160;
690 u32 eht_mcs_320;
691 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
692 u32 eht_cap_info_internal;
693 };
694
695 struct ath12k_pdev_cap {
696 u32 supported_bands;
697 u32 ampdu_density;
698 u32 vht_cap;
699 u32 vht_mcs;
700 u32 he_mcs;
701 u32 tx_chain_mask;
702 u32 rx_chain_mask;
703 u32 tx_chain_mask_shift;
704 u32 rx_chain_mask_shift;
705 struct ath12k_band_cap band[NUM_NL80211_BANDS];
706 };
707
708 struct mlo_timestamp {
709 u32 info;
710 u32 sync_timestamp_lo_us;
711 u32 sync_timestamp_hi_us;
712 u32 mlo_offset_lo;
713 u32 mlo_offset_hi;
714 u32 mlo_offset_clks;
715 u32 mlo_comp_clks;
716 u32 mlo_comp_timer;
717 };
718
719 struct ath12k_pdev {
720 struct ath12k *ar;
721 u32 pdev_id;
722 u32 hw_link_id;
723 struct ath12k_pdev_cap cap;
724 u8 mac_addr[ETH_ALEN];
725 struct mlo_timestamp timestamp;
726 };
727
728 struct ath12k_fw_pdev {
729 u32 pdev_id;
730 u32 phy_id;
731 u32 supported_bands;
732 };
733
734 struct ath12k_board_data {
735 const struct firmware *fw;
736 const void *data;
737 size_t len;
738 };
739
740 struct ath12k_soc_dp_tx_err_stats {
741 /* TCL Ring Descriptor unavailable */
742 u32 desc_na[DP_TCL_NUM_RING_MAX];
743 /* Other failures during dp_tx due to mem allocation failure
744 * idr unavailable etc.
745 */
746 atomic_t misc_fail;
747 };
748
749 struct ath12k_soc_dp_stats {
750 u32 err_ring_pkts;
751 u32 invalid_rbm;
752 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
753 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
754 u32 hal_reo_error[DP_REO_DST_RING_MAX];
755 struct ath12k_soc_dp_tx_err_stats tx_err;
756 };
757
758 /**
759 * enum ath12k_link_capable_flags - link capable flags
760 *
761 * Single/Multi link capability information
762 *
763 * @ATH12K_INTRA_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all
764 * the links (radios) present within a device.
765 * @ATH12K_INTER_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all
766 * the links (radios) present across the devices.
767 */
768 enum ath12k_link_capable_flags {
769 ATH12K_INTRA_DEVICE_MLO_SUPPORT = BIT(0),
770 ATH12K_INTER_DEVICE_MLO_SUPPORT = BIT(1),
771 };
772
773 /* Master structure to hold the hw data which may be used in core module */
774 struct ath12k_base {
775 enum ath12k_hw_rev hw_rev;
776 struct platform_device *pdev;
777 struct device *dev;
778 struct ath12k_qmi qmi;
779 struct ath12k_wmi_base wmi_ab;
780 struct completion fw_ready;
781 u8 device_id;
782 int num_radios;
783 /* HW channel counters frequency value in hertz common to all MACs */
784 u32 cc_freq_hz;
785
786 struct ath12k_htc htc;
787
788 struct ath12k_dp dp;
789
790 void __iomem *mem;
791 unsigned long mem_len;
792
793 struct {
794 enum ath12k_bus bus;
795 const struct ath12k_hif_ops *ops;
796 } hif;
797
798 struct {
799 struct completion wakeup_completed;
800 u32 wmi_conf_rx_decap_mode;
801 } wow;
802
803 struct ath12k_ce ce;
804 struct timer_list rx_replenish_retry;
805 struct ath12k_hal hal;
806 /* To synchronize core_start/core_stop */
807 struct mutex core_lock;
808 /* Protects data like peers */
809 spinlock_t base_lock;
810
811 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
812 *
813 * Firmware maintains data for all bands but advertises a single
814 * phy to the host which is stored as a single element in this
815 * array.
816 *
817 * Other devices:
818 *
819 * This array will contain as many elements as the number of
820 * radios.
821 */
822 struct ath12k_pdev pdevs[MAX_RADIOS];
823
824 /* struct ath12k_hw_params::single_pdev_only devices use this to
825 * store phy specific data
826 */
827 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
828 u8 fw_pdev_count;
829
830 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
831
832 /* Holds information of wiphy (hw) registration.
833 *
834 * In Multi/Single Link Operation case, all pdevs are registered as
835 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
836 * registered as separate wiphys.
837 */
838 struct ath12k_hw *ah[MAX_RADIOS];
839 u8 num_hw;
840
841 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
842 unsigned long long free_vdev_map;
843 unsigned long long free_vdev_stats_id_map;
844 struct list_head peers;
845 wait_queue_head_t peer_mapping_wq;
846 u8 mac_addr[ETH_ALEN];
847 bool wmi_ready;
848 u32 wlan_init_status;
849 int irq_num[ATH12K_IRQ_NUM_MAX];
850 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
851 struct napi_struct *napi;
852 struct ath12k_wmi_target_cap_arg target_caps;
853 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
854 bool pdevs_macaddr_valid;
855
856 const struct ath12k_hw_params *hw_params;
857
858 const struct firmware *cal_file;
859
860 /* Below regd's are protected by ab->data_lock */
861 /* This is the regd set for every radio
862 * by the firmware during initialization
863 */
864 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
865 /* This regd is set during dynamic country setting
866 * This may or may not be used during the runtime
867 */
868 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
869
870 /* Current DFS Regulatory */
871 enum ath12k_dfs_region dfs_region;
872 struct ath12k_soc_dp_stats soc_stats;
873 #ifdef CONFIG_ATH12K_DEBUGFS
874 struct dentry *debugfs_soc;
875 #endif
876
877 unsigned long dev_flags;
878 struct completion driver_recovery;
879 struct workqueue_struct *workqueue;
880 struct work_struct restart_work;
881 struct workqueue_struct *workqueue_aux;
882 struct work_struct reset_work;
883 atomic_t reset_count;
884 atomic_t recovery_count;
885 bool is_reset;
886 struct completion reset_complete;
887 /* continuous recovery fail count */
888 atomic_t fail_cont_count;
889 unsigned long reset_fail_timeout;
890 struct {
891 /* protected by data_lock */
892 u32 fw_crash_counter;
893 } stats;
894 u32 pktlog_defs_checksum;
895
896 struct ath12k_dbring_cap *db_caps;
897 u32 num_db_cap;
898
899 struct timer_list mon_reap_timer;
900
901 struct completion htc_suspend;
902
903 u64 fw_soc_drop_count;
904 bool static_window_map;
905
906 struct work_struct rfkill_work;
907 /* true means radio is on */
908 bool rfkill_radio_on;
909
910 struct {
911 enum ath12k_bdf_search bdf_search;
912 u32 vendor;
913 u32 device;
914 u32 subsystem_vendor;
915 u32 subsystem_device;
916 } id;
917
918 struct {
919 u32 api_version;
920
921 const struct firmware *fw;
922 const u8 *amss_data;
923 size_t amss_len;
924 const u8 *amss_dualmac_data;
925 size_t amss_dualmac_len;
926 const u8 *m3_data;
927 size_t m3_len;
928
929 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
930 } fw;
931
932 const struct hal_rx_ops *hal_rx_ops;
933
934 /* mlo_capable_flags denotes the single/multi link operation
935 * capabilities of the Device.
936 *
937 * See enum ath12k_link_capable_flags
938 */
939 u8 mlo_capable_flags;
940
941 struct completion restart_completed;
942
943 #ifdef CONFIG_ACPI
944
945 struct {
946 bool started;
947 u32 func_bit;
948 bool acpi_tas_enable;
949 bool acpi_bios_sar_enable;
950 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE];
951 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE];
952 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE];
953 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE];
954 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE];
955 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE];
956 } acpi;
957
958 #endif /* CONFIG_ACPI */
959
960 struct notifier_block panic_nb;
961
962 /* must be last */
963 u8 drv_priv[] __aligned(sizeof(void *));
964 };
965
966 struct ath12k_pdev_map {
967 struct ath12k_base *ab;
968 u8 pdev_idx;
969 };
970
971 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
972 int ath12k_core_pre_init(struct ath12k_base *ab);
973 int ath12k_core_init(struct ath12k_base *ath12k);
974 void ath12k_core_deinit(struct ath12k_base *ath12k);
975 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
976 enum ath12k_bus bus);
977 void ath12k_core_free(struct ath12k_base *ath12k);
978 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
979 struct ath12k_board_data *bd,
980 char *filename);
981 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
982 struct ath12k_board_data *bd);
983 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
984 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
985 int ath12k_core_check_dt(struct ath12k_base *ath12k);
986 int ath12k_core_check_smbios(struct ath12k_base *ab);
987 void ath12k_core_halt(struct ath12k *ar);
988 int ath12k_core_resume_early(struct ath12k_base *ab);
989 int ath12k_core_resume(struct ath12k_base *ab);
990 int ath12k_core_suspend(struct ath12k_base *ab);
991 int ath12k_core_suspend_late(struct ath12k_base *ab);
992
993 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
994 const char *filename);
995 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
996 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
997 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab);
998
ath12k_scan_state_str(enum ath12k_scan_state state)999 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
1000 {
1001 switch (state) {
1002 case ATH12K_SCAN_IDLE:
1003 return "idle";
1004 case ATH12K_SCAN_STARTING:
1005 return "starting";
1006 case ATH12K_SCAN_RUNNING:
1007 return "running";
1008 case ATH12K_SCAN_ABORTING:
1009 return "aborting";
1010 }
1011
1012 return "unknown";
1013 }
1014
ATH12K_SKB_CB(struct sk_buff * skb)1015 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
1016 {
1017 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
1018 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1019 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1020 }
1021
ATH12K_SKB_RXCB(struct sk_buff * skb)1022 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
1023 {
1024 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
1025 return (struct ath12k_skb_rxcb *)skb->cb;
1026 }
1027
ath12k_vif_to_arvif(struct ieee80211_vif * vif)1028 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif)
1029 {
1030 return (struct ath12k_vif *)vif->drv_priv;
1031 }
1032
ath12k_sta_to_arsta(struct ieee80211_sta * sta)1033 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta)
1034 {
1035 return (struct ath12k_sta *)sta->drv_priv;
1036 }
1037
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)1038 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
1039 int mac_id)
1040 {
1041 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
1042 }
1043
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)1044 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
1045 const char *filename,
1046 void *buf, size_t buf_len)
1047 {
1048 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
1049 ab->hw_params->fw.dir, filename);
1050 }
1051
ath12k_bus_str(enum ath12k_bus bus)1052 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
1053 {
1054 switch (bus) {
1055 case ATH12K_BUS_PCI:
1056 return "pci";
1057 }
1058
1059 return "unknown";
1060 }
1061
ath12k_hw_to_ah(struct ieee80211_hw * hw)1062 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw)
1063 {
1064 return hw->priv;
1065 }
1066
ath12k_ah_to_ar(struct ath12k_hw * ah,u8 hw_link_id)1067 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id)
1068 {
1069 if (WARN(hw_link_id >= ah->num_radio,
1070 "bad hw link id %d, so switch to default link\n", hw_link_id))
1071 hw_link_id = 0;
1072
1073 return &ah->radio[hw_link_id];
1074 }
1075
ath12k_ar_to_ah(struct ath12k * ar)1076 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar)
1077 {
1078 return ar->ah;
1079 }
1080
ath12k_ar_to_hw(struct ath12k * ar)1081 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
1082 {
1083 return ar->ah->hw;
1084 }
1085
1086 #define for_each_ar(ah, ar, index) \
1087 for ((index) = 0; ((index) < (ah)->num_radio && \
1088 ((ar) = &(ah)->radio[(index)])); (index)++)
1089 #endif /* _CORE_H_ */
1090