1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_mon.h"
8 #include "debug.h"
9 #include "dp_rx.h"
10 #include "dp_tx.h"
11 #include "peer.h"
12
ath12k_dp_mon_rx_handle_ofdma_info(void * rx_tlv,struct hal_rx_user_status * rx_user_status)13 static void ath12k_dp_mon_rx_handle_ofdma_info(void *rx_tlv,
14 struct hal_rx_user_status *rx_user_status)
15 {
16 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = rx_tlv;
17
18 rx_user_status->ul_ofdma_user_v0_word0 =
19 __le32_to_cpu(ppdu_end_user->usr_resp_ref);
20 rx_user_status->ul_ofdma_user_v0_word1 =
21 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);
22 }
23
24 static void
ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats * stats,void * ppduinfo,struct hal_rx_user_status * rx_user_status)25 ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,
26 void *ppduinfo,
27 struct hal_rx_user_status *rx_user_status)
28 {
29 u32 mpdu_ok_byte_count = __le32_to_cpu(stats->mpdu_ok_cnt);
30 u32 mpdu_err_byte_count = __le32_to_cpu(stats->mpdu_err_cnt);
31
32 rx_user_status->mpdu_ok_byte_count =
33 u32_get_bits(mpdu_ok_byte_count,
34 HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT);
35 rx_user_status->mpdu_err_byte_count =
36 u32_get_bits(mpdu_err_byte_count,
37 HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT);
38 }
39
40 static void
ath12k_dp_mon_rx_populate_mu_user_info(void * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)41 ath12k_dp_mon_rx_populate_mu_user_info(void *rx_tlv,
42 struct hal_rx_mon_ppdu_info *ppdu_info,
43 struct hal_rx_user_status *rx_user_status)
44 {
45 rx_user_status->ast_index = ppdu_info->ast_index;
46 rx_user_status->tid = ppdu_info->tid;
47 rx_user_status->tcp_ack_msdu_count =
48 ppdu_info->tcp_ack_msdu_count;
49 rx_user_status->tcp_msdu_count =
50 ppdu_info->tcp_msdu_count;
51 rx_user_status->udp_msdu_count =
52 ppdu_info->udp_msdu_count;
53 rx_user_status->other_msdu_count =
54 ppdu_info->other_msdu_count;
55 rx_user_status->frame_control = ppdu_info->frame_control;
56 rx_user_status->frame_control_info_valid =
57 ppdu_info->frame_control_info_valid;
58 rx_user_status->data_sequence_control_info_valid =
59 ppdu_info->data_sequence_control_info_valid;
60 rx_user_status->first_data_seq_ctrl =
61 ppdu_info->first_data_seq_ctrl;
62 rx_user_status->preamble_type = ppdu_info->preamble_type;
63 rx_user_status->ht_flags = ppdu_info->ht_flags;
64 rx_user_status->vht_flags = ppdu_info->vht_flags;
65 rx_user_status->he_flags = ppdu_info->he_flags;
66 rx_user_status->rs_flags = ppdu_info->rs_flags;
67
68 rx_user_status->mpdu_cnt_fcs_ok =
69 ppdu_info->num_mpdu_fcs_ok;
70 rx_user_status->mpdu_cnt_fcs_err =
71 ppdu_info->num_mpdu_fcs_err;
72 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],
73 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
74 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
75
76 ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
77 }
78
ath12k_dp_mon_parse_vht_sig_a(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)79 static void ath12k_dp_mon_parse_vht_sig_a(u8 *tlv_data,
80 struct hal_rx_mon_ppdu_info *ppdu_info)
81 {
82 struct hal_rx_vht_sig_a_info *vht_sig =
83 (struct hal_rx_vht_sig_a_info *)tlv_data;
84 u32 nsts, group_id, info0, info1;
85 u8 gi_setting;
86
87 info0 = __le32_to_cpu(vht_sig->info0);
88 info1 = __le32_to_cpu(vht_sig->info1);
89
90 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
91 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS);
92 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING);
93 switch (gi_setting) {
94 case HAL_RX_VHT_SIG_A_NORMAL_GI:
95 ppdu_info->gi = HAL_RX_GI_0_8_US;
96 break;
97 case HAL_RX_VHT_SIG_A_SHORT_GI:
98 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
99 ppdu_info->gi = HAL_RX_GI_0_4_US;
100 break;
101 }
102
103 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC);
104 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS);
105 if (ppdu_info->is_stbc && nsts > 0)
106 nsts = ((nsts + 1) >> 1) - 1;
107
108 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK);
109 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW);
110 ppdu_info->beamformed = u32_get_bits(info1,
111 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED);
112 group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID);
113 if (group_id == 0 || group_id == 63)
114 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
115 else
116 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
117 ppdu_info->vht_flag_values5 = group_id;
118 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
119 ppdu_info->nss);
120 ppdu_info->vht_flag_values2 = ppdu_info->bw;
121 ppdu_info->vht_flag_values4 =
122 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
123 }
124
ath12k_dp_mon_parse_ht_sig(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)125 static void ath12k_dp_mon_parse_ht_sig(u8 *tlv_data,
126 struct hal_rx_mon_ppdu_info *ppdu_info)
127 {
128 struct hal_rx_ht_sig_info *ht_sig =
129 (struct hal_rx_ht_sig_info *)tlv_data;
130 u32 info0 = __le32_to_cpu(ht_sig->info0);
131 u32 info1 = __le32_to_cpu(ht_sig->info1);
132
133 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS);
134 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW);
135 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC);
136 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING);
137 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI);
138 ppdu_info->nss = (ppdu_info->mcs >> 3);
139 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
140 }
141
ath12k_dp_mon_parse_l_sig_b(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)142 static void ath12k_dp_mon_parse_l_sig_b(u8 *tlv_data,
143 struct hal_rx_mon_ppdu_info *ppdu_info)
144 {
145 struct hal_rx_lsig_b_info *lsigb =
146 (struct hal_rx_lsig_b_info *)tlv_data;
147 u32 info0 = __le32_to_cpu(lsigb->info0);
148 u8 rate;
149
150 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE);
151 switch (rate) {
152 case 1:
153 rate = HAL_RX_LEGACY_RATE_1_MBPS;
154 break;
155 case 2:
156 case 5:
157 rate = HAL_RX_LEGACY_RATE_2_MBPS;
158 break;
159 case 3:
160 case 6:
161 rate = HAL_RX_LEGACY_RATE_5_5_MBPS;
162 break;
163 case 4:
164 case 7:
165 rate = HAL_RX_LEGACY_RATE_11_MBPS;
166 break;
167 default:
168 rate = HAL_RX_LEGACY_RATE_INVALID;
169 }
170
171 ppdu_info->rate = rate;
172 ppdu_info->cck_flag = 1;
173 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
174 }
175
ath12k_dp_mon_parse_l_sig_a(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)176 static void ath12k_dp_mon_parse_l_sig_a(u8 *tlv_data,
177 struct hal_rx_mon_ppdu_info *ppdu_info)
178 {
179 struct hal_rx_lsig_a_info *lsiga =
180 (struct hal_rx_lsig_a_info *)tlv_data;
181 u32 info0 = __le32_to_cpu(lsiga->info0);
182 u8 rate;
183
184 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE);
185 switch (rate) {
186 case 8:
187 rate = HAL_RX_LEGACY_RATE_48_MBPS;
188 break;
189 case 9:
190 rate = HAL_RX_LEGACY_RATE_24_MBPS;
191 break;
192 case 10:
193 rate = HAL_RX_LEGACY_RATE_12_MBPS;
194 break;
195 case 11:
196 rate = HAL_RX_LEGACY_RATE_6_MBPS;
197 break;
198 case 12:
199 rate = HAL_RX_LEGACY_RATE_54_MBPS;
200 break;
201 case 13:
202 rate = HAL_RX_LEGACY_RATE_36_MBPS;
203 break;
204 case 14:
205 rate = HAL_RX_LEGACY_RATE_18_MBPS;
206 break;
207 case 15:
208 rate = HAL_RX_LEGACY_RATE_9_MBPS;
209 break;
210 default:
211 rate = HAL_RX_LEGACY_RATE_INVALID;
212 }
213
214 ppdu_info->rate = rate;
215 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
216 }
217
ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)218 static void ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 *tlv_data,
219 struct hal_rx_mon_ppdu_info *ppdu_info)
220 {
221 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
222 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
223 u32 info0, value;
224
225 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
226
227 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN;
228
229 /* HE-data2 */
230 ppdu_info->he_data2 |= HE_TXBF_KNOWN;
231
232 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS);
233 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
234 ppdu_info->he_data3 |= value;
235
236 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM);
237 value = value << HE_DCM_SHIFT;
238 ppdu_info->he_data3 |= value;
239
240 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING);
241 ppdu_info->ldpc = value;
242 value = value << HE_CODING_SHIFT;
243 ppdu_info->he_data3 |= value;
244
245 /* HE-data4 */
246 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID);
247 value = value << HE_STA_ID_SHIFT;
248 ppdu_info->he_data4 |= value;
249
250 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS);
251 ppdu_info->beamformed = u32_get_bits(info0,
252 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF);
253 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
254 }
255
ath12k_dp_mon_parse_he_sig_b2_mu(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)256 static void ath12k_dp_mon_parse_he_sig_b2_mu(u8 *tlv_data,
257 struct hal_rx_mon_ppdu_info *ppdu_info)
258 {
259 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
260 (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
261 u32 info0, value;
262
263 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
264
265 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN;
266
267 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS);
268 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
269 ppdu_info->he_data3 |= value;
270
271 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING);
272 ppdu_info->ldpc = value;
273 value = value << HE_CODING_SHIFT;
274 ppdu_info->he_data3 |= value;
275
276 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID);
277 value = value << HE_STA_ID_SHIFT;
278 ppdu_info->he_data4 |= value;
279
280 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS);
281 }
282
ath12k_dp_mon_parse_he_sig_b1_mu(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)283 static void ath12k_dp_mon_parse_he_sig_b1_mu(u8 *tlv_data,
284 struct hal_rx_mon_ppdu_info *ppdu_info)
285 {
286 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
287 (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
288 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
289 u16 ru_tones;
290
291 ru_tones = u32_get_bits(info0,
292 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION);
293 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
294 ppdu_info->he_RU[0] = ru_tones;
295 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
296 }
297
ath12k_dp_mon_parse_he_sig_mu(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)298 static void ath12k_dp_mon_parse_he_sig_mu(u8 *tlv_data,
299 struct hal_rx_mon_ppdu_info *ppdu_info)
300 {
301 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
302 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
303 u32 info0, info1, value;
304 u16 he_gi = 0, he_ltf = 0;
305
306 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
307 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
308
309 ppdu_info->he_mu_flags = 1;
310
311 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE;
312 ppdu_info->he_data1 |=
313 HE_BSS_COLOR_KNOWN |
314 HE_DL_UL_KNOWN |
315 HE_LDPC_EXTRA_SYMBOL_KNOWN |
316 HE_STBC_KNOWN |
317 HE_DATA_BW_RU_KNOWN |
318 HE_DOPPLER_KNOWN;
319
320 ppdu_info->he_data2 =
321 HE_GI_KNOWN |
322 HE_LTF_SYMBOLS_KNOWN |
323 HE_PRE_FEC_PADDING_KNOWN |
324 HE_PE_DISAMBIGUITY_KNOWN |
325 HE_TXOP_KNOWN |
326 HE_MIDABLE_PERIODICITY_KNOWN;
327
328 /* data3 */
329 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR);
330 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG);
331 value = value << HE_DL_UL_SHIFT;
332 ppdu_info->he_data3 |= value;
333
334 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA);
335 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
336 ppdu_info->he_data3 |= value;
337
338 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC);
339 value = value << HE_STBC_SHIFT;
340 ppdu_info->he_data3 |= value;
341
342 /* data4 */
343 ppdu_info->he_data4 = u32_get_bits(info0,
344 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE);
345 ppdu_info->he_data4 = value;
346
347 /* data5 */
348 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
349 ppdu_info->he_data5 = value;
350 ppdu_info->bw = value;
351
352 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE);
353 switch (value) {
354 case 0:
355 he_gi = HE_GI_0_8;
356 he_ltf = HE_LTF_4_X;
357 break;
358 case 1:
359 he_gi = HE_GI_0_8;
360 he_ltf = HE_LTF_2_X;
361 break;
362 case 2:
363 he_gi = HE_GI_1_6;
364 he_ltf = HE_LTF_2_X;
365 break;
366 case 3:
367 he_gi = HE_GI_3_2;
368 he_ltf = HE_LTF_4_X;
369 break;
370 }
371
372 ppdu_info->gi = he_gi;
373 value = he_gi << HE_GI_SHIFT;
374 ppdu_info->he_data5 |= value;
375
376 value = he_ltf << HE_LTF_SIZE_SHIFT;
377 ppdu_info->he_data5 |= value;
378
379 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB);
380 value = (value << HE_LTF_SYM_SHIFT);
381 ppdu_info->he_data5 |= value;
382
383 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR);
384 value = value << HE_PRE_FEC_PAD_SHIFT;
385 ppdu_info->he_data5 |= value;
386
387 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM);
388 value = value << HE_PE_DISAMBIGUITY_SHIFT;
389 ppdu_info->he_data5 |= value;
390
391 /*data6*/
392 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION);
393 value = value << HE_DOPPLER_SHIFT;
394 ppdu_info->he_data6 |= value;
395
396 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION);
397 value = value << HE_TXOP_SHIFT;
398 ppdu_info->he_data6 |= value;
399
400 /* HE-MU Flags */
401 /* HE-MU-flags1 */
402 ppdu_info->he_flags1 =
403 HE_SIG_B_MCS_KNOWN |
404 HE_SIG_B_DCM_KNOWN |
405 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN |
406 HE_SIG_B_SYM_NUM_KNOWN |
407 HE_RU_0_KNOWN;
408
409 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB);
410 ppdu_info->he_flags1 |= value;
411 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB);
412 value = value << HE_DCM_FLAG_1_SHIFT;
413 ppdu_info->he_flags1 |= value;
414
415 /* HE-MU-flags2 */
416 ppdu_info->he_flags2 = HE_BW_KNOWN;
417
418 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
419 ppdu_info->he_flags2 |= value;
420 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB);
421 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT;
422 ppdu_info->he_flags2 |= value;
423 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB);
424 value = value - 1;
425 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT;
426 ppdu_info->he_flags2 |= value;
427
428 ppdu_info->is_stbc = info1 &
429 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC;
430 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
431 }
432
ath12k_dp_mon_parse_he_sig_su(u8 * tlv_data,struct hal_rx_mon_ppdu_info * ppdu_info)433 static void ath12k_dp_mon_parse_he_sig_su(u8 *tlv_data,
434 struct hal_rx_mon_ppdu_info *ppdu_info)
435 {
436 struct hal_rx_he_sig_a_su_info *he_sig_a =
437 (struct hal_rx_he_sig_a_su_info *)tlv_data;
438 u32 info0, info1, value;
439 u32 dcm;
440 u8 he_dcm = 0, he_stbc = 0;
441 u16 he_gi = 0, he_ltf = 0;
442
443 ppdu_info->he_flags = 1;
444
445 info0 = __le32_to_cpu(he_sig_a->info0);
446 info1 = __le32_to_cpu(he_sig_a->info1);
447
448 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND);
449 if (value == 0)
450 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE;
451 else
452 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE;
453
454 ppdu_info->he_data1 |=
455 HE_BSS_COLOR_KNOWN |
456 HE_BEAM_CHANGE_KNOWN |
457 HE_DL_UL_KNOWN |
458 HE_MCS_KNOWN |
459 HE_DCM_KNOWN |
460 HE_CODING_KNOWN |
461 HE_LDPC_EXTRA_SYMBOL_KNOWN |
462 HE_STBC_KNOWN |
463 HE_DATA_BW_RU_KNOWN |
464 HE_DOPPLER_KNOWN;
465
466 ppdu_info->he_data2 |=
467 HE_GI_KNOWN |
468 HE_TXBF_KNOWN |
469 HE_PE_DISAMBIGUITY_KNOWN |
470 HE_TXOP_KNOWN |
471 HE_LTF_SYMBOLS_KNOWN |
472 HE_PRE_FEC_PADDING_KNOWN |
473 HE_MIDABLE_PERIODICITY_KNOWN;
474
475 ppdu_info->he_data3 = u32_get_bits(info0,
476 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR);
477 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE);
478 value = value << HE_BEAM_CHANGE_SHIFT;
479 ppdu_info->he_data3 |= value;
480 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG);
481 value = value << HE_DL_UL_SHIFT;
482 ppdu_info->he_data3 |= value;
483
484 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
485 ppdu_info->mcs = value;
486 value = value << HE_TRANSMIT_MCS_SHIFT;
487 ppdu_info->he_data3 |= value;
488
489 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
490 he_dcm = value;
491 value = value << HE_DCM_SHIFT;
492 ppdu_info->he_data3 |= value;
493 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
494 value = value << HE_CODING_SHIFT;
495 ppdu_info->he_data3 |= value;
496 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA);
497 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
498 ppdu_info->he_data3 |= value;
499 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
500 he_stbc = value;
501 value = value << HE_STBC_SHIFT;
502 ppdu_info->he_data3 |= value;
503
504 /* data4 */
505 ppdu_info->he_data4 = u32_get_bits(info0,
506 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE);
507
508 /* data5 */
509 value = u32_get_bits(info0,
510 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
511 ppdu_info->he_data5 = value;
512 ppdu_info->bw = value;
513 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE);
514 switch (value) {
515 case 0:
516 he_gi = HE_GI_0_8;
517 he_ltf = HE_LTF_1_X;
518 break;
519 case 1:
520 he_gi = HE_GI_0_8;
521 he_ltf = HE_LTF_2_X;
522 break;
523 case 2:
524 he_gi = HE_GI_1_6;
525 he_ltf = HE_LTF_2_X;
526 break;
527 case 3:
528 if (he_dcm && he_stbc) {
529 he_gi = HE_GI_0_8;
530 he_ltf = HE_LTF_4_X;
531 } else {
532 he_gi = HE_GI_3_2;
533 he_ltf = HE_LTF_4_X;
534 }
535 break;
536 }
537 ppdu_info->gi = he_gi;
538 value = he_gi << HE_GI_SHIFT;
539 ppdu_info->he_data5 |= value;
540 value = he_ltf << HE_LTF_SIZE_SHIFT;
541 ppdu_info->ltf_size = he_ltf;
542 ppdu_info->he_data5 |= value;
543
544 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
545 value = (value << HE_LTF_SYM_SHIFT);
546 ppdu_info->he_data5 |= value;
547
548 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR);
549 value = value << HE_PRE_FEC_PAD_SHIFT;
550 ppdu_info->he_data5 |= value;
551
552 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
553 value = value << HE_TXBF_SHIFT;
554 ppdu_info->he_data5 |= value;
555 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM);
556 value = value << HE_PE_DISAMBIGUITY_SHIFT;
557 ppdu_info->he_data5 |= value;
558
559 /* data6 */
560 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
561 value++;
562 ppdu_info->he_data6 = value;
563 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND);
564 value = value << HE_DOPPLER_SHIFT;
565 ppdu_info->he_data6 |= value;
566 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION);
567 value = value << HE_TXOP_SHIFT;
568 ppdu_info->he_data6 |= value;
569
570 ppdu_info->mcs =
571 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
572 ppdu_info->bw =
573 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
574 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
575 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
576 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
577 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
578 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
579 ppdu_info->dcm = dcm;
580 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
581 }
582
583 static enum hal_rx_mon_status
ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base * ab,struct ath12k_mon_data * pmon,u32 tlv_tag,u8 * tlv_data,u32 userid)584 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab,
585 struct ath12k_mon_data *pmon,
586 u32 tlv_tag, u8 *tlv_data, u32 userid)
587 {
588 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
589 u32 info[7];
590
591 switch (tlv_tag) {
592 case HAL_RX_PPDU_START: {
593 struct hal_rx_ppdu_start *ppdu_start =
594 (struct hal_rx_ppdu_start *)tlv_data;
595
596 info[0] = __le32_to_cpu(ppdu_start->info0);
597
598 ppdu_info->ppdu_id =
599 u32_get_bits(info[0], HAL_RX_PPDU_START_INFO0_PPDU_ID);
600 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num);
601 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts);
602
603 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) {
604 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id;
605 ppdu_info->num_users = 0;
606 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0,
607 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
608 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
609 }
610 break;
611 }
612 case HAL_RX_PPDU_END_USER_STATS: {
613 struct hal_rx_ppdu_end_user_stats *eu_stats =
614 (struct hal_rx_ppdu_end_user_stats *)tlv_data;
615
616 info[0] = __le32_to_cpu(eu_stats->info0);
617 info[1] = __le32_to_cpu(eu_stats->info1);
618 info[2] = __le32_to_cpu(eu_stats->info2);
619 info[4] = __le32_to_cpu(eu_stats->info4);
620 info[5] = __le32_to_cpu(eu_stats->info5);
621 info[6] = __le32_to_cpu(eu_stats->info6);
622
623 ppdu_info->ast_index =
624 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX);
625 ppdu_info->fc_valid =
626 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID);
627 ppdu_info->tid =
628 ffs(u32_get_bits(info[6],
629 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP)
630 - 1);
631 ppdu_info->tcp_msdu_count =
632 u32_get_bits(info[4],
633 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT);
634 ppdu_info->udp_msdu_count =
635 u32_get_bits(info[4],
636 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT);
637 ppdu_info->other_msdu_count =
638 u32_get_bits(info[5],
639 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT);
640 ppdu_info->tcp_ack_msdu_count =
641 u32_get_bits(info[5],
642 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT);
643 ppdu_info->preamble_type =
644 u32_get_bits(info[1],
645 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE);
646 ppdu_info->num_mpdu_fcs_ok =
647 u32_get_bits(info[1],
648 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK);
649 ppdu_info->num_mpdu_fcs_err =
650 u32_get_bits(info[0],
651 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR);
652 switch (ppdu_info->preamble_type) {
653 case HAL_RX_PREAMBLE_11N:
654 ppdu_info->ht_flags = 1;
655 break;
656 case HAL_RX_PREAMBLE_11AC:
657 ppdu_info->vht_flags = 1;
658 break;
659 case HAL_RX_PREAMBLE_11AX:
660 ppdu_info->he_flags = 1;
661 break;
662 default:
663 break;
664 }
665
666 if (userid < HAL_MAX_UL_MU_USERS) {
667 struct hal_rx_user_status *rxuser_stats =
668 &ppdu_info->userstats[userid];
669
670 if (ppdu_info->num_mpdu_fcs_ok > 1 ||
671 ppdu_info->num_mpdu_fcs_err > 1)
672 ppdu_info->userstats[userid].ampdu_present = true;
673
674 ppdu_info->num_users += 1;
675
676 ath12k_dp_mon_rx_handle_ofdma_info(tlv_data, rxuser_stats);
677 ath12k_dp_mon_rx_populate_mu_user_info(tlv_data, ppdu_info,
678 rxuser_stats);
679 }
680 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
681 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]);
682 break;
683 }
684 case HAL_RX_PPDU_END_USER_STATS_EXT: {
685 struct hal_rx_ppdu_end_user_stats_ext *eu_stats =
686 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data;
687 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1);
688 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2);
689 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3);
690 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4);
691 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5);
692 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6);
693 break;
694 }
695 case HAL_PHYRX_HT_SIG:
696 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info);
697 break;
698
699 case HAL_PHYRX_L_SIG_B:
700 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info);
701 break;
702
703 case HAL_PHYRX_L_SIG_A:
704 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info);
705 break;
706
707 case HAL_PHYRX_VHT_SIG_A:
708 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info);
709 break;
710
711 case HAL_PHYRX_HE_SIG_A_SU:
712 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info);
713 break;
714
715 case HAL_PHYRX_HE_SIG_A_MU_DL:
716 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info);
717 break;
718
719 case HAL_PHYRX_HE_SIG_B1_MU:
720 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info);
721 break;
722
723 case HAL_PHYRX_HE_SIG_B2_MU:
724 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info);
725 break;
726
727 case HAL_PHYRX_HE_SIG_B2_OFDMA:
728 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info);
729 break;
730
731 case HAL_PHYRX_RSSI_LEGACY: {
732 struct hal_rx_phyrx_rssi_legacy_info *rssi =
733 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
734 u32 reception_type = 0;
735 u32 rssi_legacy_info = __le32_to_cpu(rssi->rsvd[0]);
736
737 info[0] = __le32_to_cpu(rssi->info0);
738
739 /* TODO: Please note that the combined rssi will not be accurate
740 * in MU case. Rssi in MU needs to be retrieved from
741 * PHYRX_OTHER_RECEIVE_INFO TLV.
742 */
743 ppdu_info->rssi_comb =
744 u32_get_bits(info[0],
745 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB);
746 reception_type =
747 u32_get_bits(rssi_legacy_info,
748 HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION);
749
750 switch (reception_type) {
751 case HAL_RECEPTION_TYPE_ULOFMDA:
752 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
753 break;
754 case HAL_RECEPTION_TYPE_ULMIMO:
755 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
756 break;
757 default:
758 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
759 break;
760 }
761 break;
762 }
763 case HAL_RXPCU_PPDU_END_INFO: {
764 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
765 (struct hal_rx_ppdu_end_duration *)tlv_data;
766
767 info[0] = __le32_to_cpu(ppdu_rx_duration->info0);
768 ppdu_info->rx_duration =
769 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION);
770 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
771 ppdu_info->tsft = (ppdu_info->tsft << 32) |
772 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
773 break;
774 }
775 case HAL_RX_MPDU_START: {
776 struct hal_rx_mpdu_start *mpdu_start =
777 (struct hal_rx_mpdu_start *)tlv_data;
778 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
779 u16 peer_id;
780
781 info[1] = __le32_to_cpu(mpdu_start->info1);
782 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID);
783 if (peer_id)
784 ppdu_info->peer_id = peer_id;
785
786 ppdu_info->mpdu_len += u32_get_bits(info[1],
787 HAL_RX_MPDU_START_INFO2_MPDU_LEN);
788 if (userid < HAL_MAX_UL_MU_USERS) {
789 info[0] = __le32_to_cpu(mpdu_start->info0);
790 ppdu_info->userid = userid;
791 ppdu_info->userstats[userid].ampdu_id =
792 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO0_PPDU_ID);
793 }
794
795 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
796 if (!mon_mpdu)
797 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
798
799 break;
800 }
801 case HAL_RX_MSDU_START:
802 /* TODO: add msdu start parsing logic */
803 break;
804 case HAL_MON_BUF_ADDR: {
805 struct dp_rxdma_mon_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring;
806 struct dp_mon_packet_info *packet_info =
807 (struct dp_mon_packet_info *)tlv_data;
808 int buf_id = u32_get_bits(packet_info->cookie,
809 DP_RXDMA_BUF_COOKIE_BUF_ID);
810 struct sk_buff *msdu;
811 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
812 struct ath12k_skb_rxcb *rxcb;
813
814 spin_lock_bh(&buf_ring->idr_lock);
815 msdu = idr_remove(&buf_ring->bufs_idr, buf_id);
816 spin_unlock_bh(&buf_ring->idr_lock);
817
818 if (unlikely(!msdu)) {
819 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
820 buf_id);
821 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
822 }
823
824 rxcb = ATH12K_SKB_RXCB(msdu);
825 dma_unmap_single(ab->dev, rxcb->paddr,
826 msdu->len + skb_tailroom(msdu),
827 DMA_FROM_DEVICE);
828
829 if (mon_mpdu->tail)
830 mon_mpdu->tail->next = msdu;
831 else
832 mon_mpdu->tail = msdu;
833
834 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
835
836 break;
837 }
838 case HAL_RX_MSDU_END: {
839 struct rx_msdu_end_qcn9274 *msdu_end =
840 (struct rx_msdu_end_qcn9274 *)tlv_data;
841 bool is_first_msdu_in_mpdu;
842 u16 msdu_end_info;
843
844 msdu_end_info = __le16_to_cpu(msdu_end->info5);
845 is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info,
846 RX_MSDU_END_INFO5_FIRST_MSDU);
847 if (is_first_msdu_in_mpdu) {
848 pmon->mon_mpdu->head = pmon->mon_mpdu->tail;
849 pmon->mon_mpdu->tail = NULL;
850 }
851 break;
852 }
853 case HAL_RX_MPDU_END:
854 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list);
855 break;
856 case HAL_DUMMY:
857 return HAL_RX_MON_STATUS_BUF_DONE;
858 case HAL_RX_PPDU_END_STATUS_DONE:
859 case 0:
860 return HAL_RX_MON_STATUS_PPDU_DONE;
861 default:
862 break;
863 }
864
865 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
866 }
867
ath12k_dp_mon_rx_msdus_set_payload(struct ath12k * ar,struct sk_buff * msdu)868 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar, struct sk_buff *msdu)
869 {
870 u32 rx_pkt_offset, l2_hdr_offset;
871
872 rx_pkt_offset = ar->ab->hal.hal_desc_sz;
873 l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab,
874 (struct hal_rx_desc *)msdu->data);
875 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
876 }
877
878 static struct sk_buff *
ath12k_dp_mon_rx_merg_msdus(struct ath12k * ar,u32 mac_id,struct sk_buff * head_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)879 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar,
880 u32 mac_id, struct sk_buff *head_msdu,
881 struct ieee80211_rx_status *rxs, bool *fcs_err)
882 {
883 struct ath12k_base *ab = ar->ab;
884 struct sk_buff *msdu, *mpdu_buf, *prev_buf;
885 struct hal_rx_desc *rx_desc;
886 u8 *hdr_desc, *dest, decap_format;
887 struct ieee80211_hdr_3addr *wh;
888 u32 err_bitmap;
889
890 mpdu_buf = NULL;
891
892 if (!head_msdu)
893 goto err_merge_fail;
894
895 rx_desc = (struct hal_rx_desc *)head_msdu->data;
896 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
897
898 if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
899 *fcs_err = true;
900
901 decap_format = ath12k_dp_rx_h_decap_type(ab, rx_desc);
902
903 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
904
905 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
906 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu);
907
908 prev_buf = head_msdu;
909 msdu = head_msdu->next;
910
911 while (msdu) {
912 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu);
913
914 prev_buf = msdu;
915 msdu = msdu->next;
916 }
917
918 prev_buf->next = NULL;
919
920 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
921 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
922 u8 qos_pkt = 0;
923
924 rx_desc = (struct hal_rx_desc *)head_msdu->data;
925 hdr_desc =
926 ab->hal_rx_ops->rx_desc_get_msdu_payload(rx_desc);
927
928 /* Base size */
929 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
930
931 if (ieee80211_is_data_qos(wh->frame_control))
932 qos_pkt = 1;
933
934 msdu = head_msdu;
935
936 while (msdu) {
937 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu);
938 if (qos_pkt) {
939 dest = skb_push(msdu, sizeof(__le16));
940 if (!dest)
941 goto err_merge_fail;
942 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
943 }
944 prev_buf = msdu;
945 msdu = msdu->next;
946 }
947 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
948 if (!dest)
949 goto err_merge_fail;
950
951 ath12k_dbg(ab, ATH12K_DBG_DATA,
952 "mpdu_buf %p mpdu_buf->len %u",
953 prev_buf, prev_buf->len);
954 } else {
955 ath12k_dbg(ab, ATH12K_DBG_DATA,
956 "decap format %d is not supported!\n",
957 decap_format);
958 goto err_merge_fail;
959 }
960
961 return head_msdu;
962
963 err_merge_fail:
964 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
965 ath12k_dbg(ab, ATH12K_DBG_DATA,
966 "err_merge_fail mpdu_buf %p", mpdu_buf);
967 /* Free the head buffer */
968 dev_kfree_skb_any(mpdu_buf);
969 }
970 return NULL;
971 }
972
973 static void
ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)974 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
975 u8 *rtap_buf)
976 {
977 u32 rtap_len = 0;
978
979 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
980 rtap_len += 2;
981
982 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
983 rtap_len += 2;
984
985 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
986 rtap_len += 2;
987
988 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
989 rtap_len += 2;
990
991 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
992 rtap_len += 2;
993
994 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
995 }
996
997 static void
ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)998 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
999 u8 *rtap_buf)
1000 {
1001 u32 rtap_len = 0;
1002
1003 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
1004 rtap_len += 2;
1005
1006 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
1007 rtap_len += 2;
1008
1009 rtap_buf[rtap_len] = rx_status->he_RU[0];
1010 rtap_len += 1;
1011
1012 rtap_buf[rtap_len] = rx_status->he_RU[1];
1013 rtap_len += 1;
1014
1015 rtap_buf[rtap_len] = rx_status->he_RU[2];
1016 rtap_len += 1;
1017
1018 rtap_buf[rtap_len] = rx_status->he_RU[3];
1019 }
1020
ath12k_dp_mon_update_radiotap(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)1021 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar,
1022 struct hal_rx_mon_ppdu_info *ppduinfo,
1023 struct sk_buff *mon_skb,
1024 struct ieee80211_rx_status *rxs)
1025 {
1026 struct ieee80211_supported_band *sband;
1027 u8 *ptr = NULL;
1028
1029 rxs->flag |= RX_FLAG_MACTIME_START;
1030 rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR;
1031 rxs->nss = ppduinfo->nss + 1;
1032
1033 if (ppduinfo->userstats[ppduinfo->userid].ampdu_present) {
1034 rxs->flag |= RX_FLAG_AMPDU_DETAILS;
1035 rxs->ampdu_reference = ppduinfo->userstats[ppduinfo->userid].ampdu_id;
1036 }
1037
1038 if (ppduinfo->he_mu_flags) {
1039 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
1040 rxs->encoding = RX_ENC_HE;
1041 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
1042 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr);
1043 } else if (ppduinfo->he_flags) {
1044 rxs->flag |= RX_FLAG_RADIOTAP_HE;
1045 rxs->encoding = RX_ENC_HE;
1046 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
1047 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr);
1048 rxs->rate_idx = ppduinfo->rate;
1049 } else if (ppduinfo->vht_flags) {
1050 rxs->encoding = RX_ENC_VHT;
1051 rxs->rate_idx = ppduinfo->rate;
1052 } else if (ppduinfo->ht_flags) {
1053 rxs->encoding = RX_ENC_HT;
1054 rxs->rate_idx = ppduinfo->rate;
1055 } else {
1056 rxs->encoding = RX_ENC_LEGACY;
1057 sband = &ar->mac.sbands[rxs->band];
1058 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
1059 ppduinfo->cck_flag);
1060 }
1061
1062 rxs->mactime = ppduinfo->tsft;
1063 }
1064
ath12k_dp_mon_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)1065 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
1066 struct sk_buff *msdu,
1067 struct ieee80211_rx_status *status)
1068 {
1069 static const struct ieee80211_radiotap_he known = {
1070 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1071 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
1072 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
1073 };
1074 struct ieee80211_rx_status *rx_status;
1075 struct ieee80211_radiotap_he *he = NULL;
1076 struct ieee80211_sta *pubsta = NULL;
1077 struct ath12k_peer *peer;
1078 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1079 u8 decap = DP_RX_DECAP_TYPE_RAW;
1080 bool is_mcbc = rxcb->is_mcbc;
1081 bool is_eapol_tkip = rxcb->is_eapol;
1082
1083 status->link_valid = 0;
1084
1085 if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
1086 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
1087 he = skb_push(msdu, sizeof(known));
1088 memcpy(he, &known, sizeof(known));
1089 status->flag |= RX_FLAG_RADIOTAP_HE;
1090 }
1091
1092 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
1093 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc);
1094 spin_lock_bh(&ar->ab->base_lock);
1095 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
1096 if (peer && peer->sta)
1097 pubsta = peer->sta;
1098 spin_unlock_bh(&ar->ab->base_lock);
1099
1100 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
1101 "rx skb %p len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
1102 msdu,
1103 msdu->len,
1104 peer ? peer->addr : NULL,
1105 rxcb->tid,
1106 (is_mcbc) ? "mcast" : "ucast",
1107 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
1108 (status->encoding == RX_ENC_HT) ? "ht" : "",
1109 (status->encoding == RX_ENC_VHT) ? "vht" : "",
1110 (status->encoding == RX_ENC_HE) ? "he" : "",
1111 (status->bw == RATE_INFO_BW_40) ? "40" : "",
1112 (status->bw == RATE_INFO_BW_80) ? "80" : "",
1113 (status->bw == RATE_INFO_BW_160) ? "160" : "",
1114 (status->bw == RATE_INFO_BW_320) ? "320" : "",
1115 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
1116 status->rate_idx,
1117 status->nss,
1118 status->freq,
1119 status->band, status->flag,
1120 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
1121 !!(status->flag & RX_FLAG_MMIC_ERROR),
1122 !!(status->flag & RX_FLAG_AMSDU_MORE));
1123
1124 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
1125 msdu->data, msdu->len);
1126 rx_status = IEEE80211_SKB_RXCB(msdu);
1127 *rx_status = *status;
1128
1129 /* TODO: trace rx packet */
1130
1131 /* PN for multicast packets are not validate in HW,
1132 * so skip 802.3 rx path
1133 * Also, fast_rx expects the STA to be authorized, hence
1134 * eapol packets are sent in slow path.
1135 */
1136 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip &&
1137 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
1138 rx_status->flag |= RX_FLAG_8023;
1139
1140 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
1141 }
1142
ath12k_dp_mon_rx_deliver(struct ath12k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct napi_struct * napi)1143 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id,
1144 struct sk_buff *head_msdu,
1145 struct hal_rx_mon_ppdu_info *ppduinfo,
1146 struct napi_struct *napi)
1147 {
1148 struct ath12k_pdev_dp *dp = &ar->dp;
1149 struct sk_buff *mon_skb, *skb_next, *header;
1150 struct ieee80211_rx_status *rxs = &dp->rx_status;
1151 bool fcs_err = false;
1152
1153 mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id, head_msdu,
1154 rxs, &fcs_err);
1155 if (!mon_skb)
1156 goto mon_deliver_fail;
1157
1158 header = mon_skb;
1159 rxs->flag = 0;
1160
1161 if (fcs_err)
1162 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
1163
1164 do {
1165 skb_next = mon_skb->next;
1166 if (!skb_next)
1167 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
1168 else
1169 rxs->flag |= RX_FLAG_AMSDU_MORE;
1170
1171 if (mon_skb == header) {
1172 header = NULL;
1173 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
1174 } else {
1175 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
1176 }
1177 rxs->flag |= RX_FLAG_ONLY_MONITOR;
1178 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs);
1179 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs);
1180 mon_skb = skb_next;
1181 } while (mon_skb);
1182 rxs->flag = 0;
1183
1184 return 0;
1185
1186 mon_deliver_fail:
1187 mon_skb = head_msdu;
1188 while (mon_skb) {
1189 skb_next = mon_skb->next;
1190 dev_kfree_skb_any(mon_skb);
1191 mon_skb = skb_next;
1192 }
1193 return -EINVAL;
1194 }
1195
1196 static enum hal_rx_mon_status
ath12k_dp_mon_parse_rx_dest(struct ath12k_base * ab,struct ath12k_mon_data * pmon,struct sk_buff * skb)1197 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon,
1198 struct sk_buff *skb)
1199 {
1200 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1201 struct hal_tlv_hdr *tlv;
1202 enum hal_rx_mon_status hal_status;
1203 u32 tlv_userid = 0;
1204 u16 tlv_tag, tlv_len;
1205 u8 *ptr = skb->data;
1206
1207 memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info));
1208
1209 do {
1210 tlv = (struct hal_tlv_hdr *)ptr;
1211 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1212 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
1213 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
1214 ptr += sizeof(*tlv);
1215
1216 /* The actual length of PPDU_END is the combined length of many PHY
1217 * TLVs that follow. Skip the TLV header and
1218 * rx_rxpcu_classification_overview that follows the header to get to
1219 * next TLV.
1220 */
1221
1222 if (tlv_tag == HAL_RX_PPDU_END)
1223 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1224
1225 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon,
1226 tlv_tag, ptr, tlv_userid);
1227 ptr += tlv_len;
1228 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1229
1230 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1231 break;
1232
1233 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1234
1235 return hal_status;
1236 }
1237
1238 enum hal_rx_mon_status
ath12k_dp_mon_rx_parse_mon_status(struct ath12k * ar,struct ath12k_mon_data * pmon,int mac_id,struct sk_buff * skb,struct napi_struct * napi)1239 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,
1240 struct ath12k_mon_data *pmon,
1241 int mac_id,
1242 struct sk_buff *skb,
1243 struct napi_struct *napi)
1244 {
1245 struct ath12k_base *ab = ar->ab;
1246 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1247 struct dp_mon_mpdu *tmp;
1248 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
1249 struct sk_buff *head_msdu, *tail_msdu;
1250 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1251
1252 ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
1253
1254 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) {
1255 list_del(&mon_mpdu->list);
1256 head_msdu = mon_mpdu->head;
1257 tail_msdu = mon_mpdu->tail;
1258
1259 if (head_msdu && tail_msdu) {
1260 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu,
1261 ppdu_info, napi);
1262 }
1263
1264 kfree(mon_mpdu);
1265 }
1266 return hal_status;
1267 }
1268
ath12k_dp_mon_buf_replenish(struct ath12k_base * ab,struct dp_rxdma_mon_ring * buf_ring,int req_entries)1269 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,
1270 struct dp_rxdma_mon_ring *buf_ring,
1271 int req_entries)
1272 {
1273 struct hal_mon_buf_ring *mon_buf;
1274 struct sk_buff *skb;
1275 struct hal_srng *srng;
1276 dma_addr_t paddr;
1277 u32 cookie;
1278 int buf_id;
1279
1280 srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id];
1281 spin_lock_bh(&srng->lock);
1282 ath12k_hal_srng_access_begin(ab, srng);
1283
1284 while (req_entries > 0) {
1285 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE);
1286 if (unlikely(!skb))
1287 goto fail_alloc_skb;
1288
1289 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) {
1290 skb_pull(skb,
1291 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
1292 skb->data);
1293 }
1294
1295 paddr = dma_map_single(ab->dev, skb->data,
1296 skb->len + skb_tailroom(skb),
1297 DMA_FROM_DEVICE);
1298
1299 if (unlikely(dma_mapping_error(ab->dev, paddr)))
1300 goto fail_free_skb;
1301
1302 spin_lock_bh(&buf_ring->idr_lock);
1303 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0,
1304 buf_ring->bufs_max * 3, GFP_ATOMIC);
1305 spin_unlock_bh(&buf_ring->idr_lock);
1306
1307 if (unlikely(buf_id < 0))
1308 goto fail_dma_unmap;
1309
1310 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng);
1311 if (unlikely(!mon_buf))
1312 goto fail_idr_remove;
1313
1314 ATH12K_SKB_RXCB(skb)->paddr = paddr;
1315
1316 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
1317
1318 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr));
1319 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr));
1320 mon_buf->cookie = cpu_to_le64(cookie);
1321
1322 req_entries--;
1323 }
1324
1325 ath12k_hal_srng_access_end(ab, srng);
1326 spin_unlock_bh(&srng->lock);
1327 return 0;
1328
1329 fail_idr_remove:
1330 spin_lock_bh(&buf_ring->idr_lock);
1331 idr_remove(&buf_ring->bufs_idr, buf_id);
1332 spin_unlock_bh(&buf_ring->idr_lock);
1333 fail_dma_unmap:
1334 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
1335 DMA_FROM_DEVICE);
1336 fail_free_skb:
1337 dev_kfree_skb_any(skb);
1338 fail_alloc_skb:
1339 ath12k_hal_srng_access_end(ab, srng);
1340 spin_unlock_bh(&srng->lock);
1341 return -ENOMEM;
1342 }
1343
1344 static struct dp_mon_tx_ppdu_info *
ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data * pmon,unsigned int ppdu_id,enum dp_mon_tx_ppdu_info_type type)1345 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon,
1346 unsigned int ppdu_id,
1347 enum dp_mon_tx_ppdu_info_type type)
1348 {
1349 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1350
1351 if (type == DP_MON_TX_PROT_PPDU_INFO) {
1352 tx_ppdu_info = pmon->tx_prot_ppdu_info;
1353
1354 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1355 return tx_ppdu_info;
1356 kfree(tx_ppdu_info);
1357 } else {
1358 tx_ppdu_info = pmon->tx_data_ppdu_info;
1359
1360 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1361 return tx_ppdu_info;
1362 kfree(tx_ppdu_info);
1363 }
1364
1365 /* allocate new tx_ppdu_info */
1366 tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC);
1367 if (!tx_ppdu_info)
1368 return NULL;
1369
1370 tx_ppdu_info->is_used = 0;
1371 tx_ppdu_info->ppdu_id = ppdu_id;
1372
1373 if (type == DP_MON_TX_PROT_PPDU_INFO)
1374 pmon->tx_prot_ppdu_info = tx_ppdu_info;
1375 else
1376 pmon->tx_data_ppdu_info = tx_ppdu_info;
1377
1378 return tx_ppdu_info;
1379 }
1380
1381 static struct dp_mon_tx_ppdu_info *
ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data * pmon,u16 tlv_tag)1382 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon,
1383 u16 tlv_tag)
1384 {
1385 switch (tlv_tag) {
1386 case HAL_TX_FES_SETUP:
1387 case HAL_TX_FLUSH:
1388 case HAL_PCU_PPDU_SETUP_INIT:
1389 case HAL_TX_PEER_ENTRY:
1390 case HAL_TX_QUEUE_EXTENSION:
1391 case HAL_TX_MPDU_START:
1392 case HAL_TX_MSDU_START:
1393 case HAL_TX_DATA:
1394 case HAL_MON_BUF_ADDR:
1395 case HAL_TX_MPDU_END:
1396 case HAL_TX_LAST_MPDU_FETCHED:
1397 case HAL_TX_LAST_MPDU_END:
1398 case HAL_COEX_TX_REQ:
1399 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP:
1400 case HAL_SCH_CRITICAL_TLV_REFERENCE:
1401 case HAL_TX_FES_SETUP_COMPLETE:
1402 case HAL_TQM_MPDU_GLOBAL_START:
1403 case HAL_SCHEDULER_END:
1404 case HAL_TX_FES_STATUS_USER_PPDU:
1405 break;
1406 case HAL_TX_FES_STATUS_PROT: {
1407 if (!pmon->tx_prot_ppdu_info->is_used)
1408 pmon->tx_prot_ppdu_info->is_used = true;
1409
1410 return pmon->tx_prot_ppdu_info;
1411 }
1412 }
1413
1414 if (!pmon->tx_data_ppdu_info->is_used)
1415 pmon->tx_data_ppdu_info->is_used = true;
1416
1417 return pmon->tx_data_ppdu_info;
1418 }
1419
1420 #define MAX_MONITOR_HEADER 512
1421 #define MAX_DUMMY_FRM_BODY 128
1422
ath12k_dp_mon_tx_alloc_skb(void)1423 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void)
1424 {
1425 struct sk_buff *skb;
1426
1427 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY);
1428 if (!skb)
1429 return NULL;
1430
1431 skb_reserve(skb, MAX_MONITOR_HEADER);
1432
1433 if (!IS_ALIGNED((unsigned long)skb->data, 4))
1434 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data);
1435
1436 return skb;
1437 }
1438
1439 static int
ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1440 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1441 {
1442 struct sk_buff *skb;
1443 struct ieee80211_cts *cts;
1444
1445 skb = ath12k_dp_mon_tx_alloc_skb();
1446 if (!skb)
1447 return -ENOMEM;
1448
1449 cts = (struct ieee80211_cts *)skb->data;
1450 memset(cts, 0, MAX_DUMMY_FRM_BODY);
1451 cts->frame_control =
1452 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS);
1453 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1454 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra));
1455
1456 skb_put(skb, sizeof(*cts));
1457 tx_ppdu_info->tx_mon_mpdu->head = skb;
1458 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1459 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1460 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1461
1462 return 0;
1463 }
1464
1465 static int
ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1466 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1467 {
1468 struct sk_buff *skb;
1469 struct ieee80211_rts *rts;
1470
1471 skb = ath12k_dp_mon_tx_alloc_skb();
1472 if (!skb)
1473 return -ENOMEM;
1474
1475 rts = (struct ieee80211_rts *)skb->data;
1476 memset(rts, 0, MAX_DUMMY_FRM_BODY);
1477 rts->frame_control =
1478 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS);
1479 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1480 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra));
1481 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta));
1482
1483 skb_put(skb, sizeof(*rts));
1484 tx_ppdu_info->tx_mon_mpdu->head = skb;
1485 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1486 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1487 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1488
1489 return 0;
1490 }
1491
1492 static int
ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1493 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1494 {
1495 struct sk_buff *skb;
1496 struct ieee80211_qos_hdr *qhdr;
1497
1498 skb = ath12k_dp_mon_tx_alloc_skb();
1499 if (!skb)
1500 return -ENOMEM;
1501
1502 qhdr = (struct ieee80211_qos_hdr *)skb->data;
1503 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1504 qhdr->frame_control =
1505 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1506 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1507 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1508 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1509 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1510
1511 skb_put(skb, sizeof(*qhdr));
1512 tx_ppdu_info->tx_mon_mpdu->head = skb;
1513 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1514 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1515 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1516
1517 return 0;
1518 }
1519
1520 static int
ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1521 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1522 {
1523 struct sk_buff *skb;
1524 struct dp_mon_qosframe_addr4 *qhdr;
1525
1526 skb = ath12k_dp_mon_tx_alloc_skb();
1527 if (!skb)
1528 return -ENOMEM;
1529
1530 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data;
1531 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1532 qhdr->frame_control =
1533 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1534 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1535 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1536 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1537 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1538 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN);
1539
1540 skb_put(skb, sizeof(*qhdr));
1541 tx_ppdu_info->tx_mon_mpdu->head = skb;
1542 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1543 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1544 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1545
1546 return 0;
1547 }
1548
1549 static int
ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1550 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1551 {
1552 struct sk_buff *skb;
1553 struct dp_mon_frame_min_one *fbmhdr;
1554
1555 skb = ath12k_dp_mon_tx_alloc_skb();
1556 if (!skb)
1557 return -ENOMEM;
1558
1559 fbmhdr = (struct dp_mon_frame_min_one *)skb->data;
1560 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY);
1561 fbmhdr->frame_control =
1562 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK);
1563 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1564
1565 /* set duration zero for ack frame */
1566 fbmhdr->duration = 0;
1567
1568 skb_put(skb, sizeof(*fbmhdr));
1569 tx_ppdu_info->tx_mon_mpdu->head = skb;
1570 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1571 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1572 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1573
1574 return 0;
1575 }
1576
1577 static int
ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1578 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1579 {
1580 int ret = 0;
1581
1582 switch (tx_ppdu_info->rx_status.medium_prot_type) {
1583 case DP_MON_TX_MEDIUM_RTS_LEGACY:
1584 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW:
1585 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW:
1586 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info);
1587 break;
1588 case DP_MON_TX_MEDIUM_CTS2SELF:
1589 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1590 break;
1591 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR:
1592 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info);
1593 break;
1594 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR:
1595 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info);
1596 break;
1597 }
1598
1599 return ret;
1600 }
1601
1602 static enum dp_mon_tx_tlv_status
ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base * ab,struct ath12k_mon_data * pmon,u16 tlv_tag,u8 * tlv_data,u32 userid)1603 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,
1604 struct ath12k_mon_data *pmon,
1605 u16 tlv_tag, u8 *tlv_data, u32 userid)
1606 {
1607 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1608 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1609 u32 info[7];
1610
1611 tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag);
1612
1613 switch (tlv_tag) {
1614 case HAL_TX_FES_SETUP: {
1615 struct hal_tx_fes_setup *tx_fes_setup =
1616 (struct hal_tx_fes_setup *)tlv_data;
1617
1618 info[0] = __le32_to_cpu(tx_fes_setup->info0);
1619 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id);
1620 tx_ppdu_info->num_users =
1621 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1622 status = DP_MON_TX_FES_SETUP;
1623 break;
1624 }
1625
1626 case HAL_TX_FES_STATUS_END: {
1627 struct hal_tx_fes_status_end *tx_fes_status_end =
1628 (struct hal_tx_fes_status_end *)tlv_data;
1629 u32 tst_15_0, tst_31_16;
1630
1631 info[0] = __le32_to_cpu(tx_fes_status_end->info0);
1632 tst_15_0 =
1633 u32_get_bits(info[0],
1634 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0);
1635 tst_31_16 =
1636 u32_get_bits(info[0],
1637 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16);
1638
1639 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16));
1640 status = DP_MON_TX_FES_STATUS_END;
1641 break;
1642 }
1643
1644 case HAL_RX_RESPONSE_REQUIRED_INFO: {
1645 struct hal_rx_resp_req_info *rx_resp_req_info =
1646 (struct hal_rx_resp_req_info *)tlv_data;
1647 u32 addr_32;
1648 u16 addr_16;
1649
1650 info[0] = __le32_to_cpu(rx_resp_req_info->info0);
1651 info[1] = __le32_to_cpu(rx_resp_req_info->info1);
1652 info[2] = __le32_to_cpu(rx_resp_req_info->info2);
1653 info[3] = __le32_to_cpu(rx_resp_req_info->info3);
1654 info[4] = __le32_to_cpu(rx_resp_req_info->info4);
1655 info[5] = __le32_to_cpu(rx_resp_req_info->info5);
1656
1657 tx_ppdu_info->rx_status.ppdu_id =
1658 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID);
1659 tx_ppdu_info->rx_status.reception_type =
1660 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE);
1661 tx_ppdu_info->rx_status.rx_duration =
1662 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION);
1663 tx_ppdu_info->rx_status.mcs =
1664 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS);
1665 tx_ppdu_info->rx_status.sgi =
1666 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI);
1667 tx_ppdu_info->rx_status.is_stbc =
1668 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC);
1669 tx_ppdu_info->rx_status.ldpc =
1670 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC);
1671 tx_ppdu_info->rx_status.is_ampdu =
1672 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU);
1673 tx_ppdu_info->rx_status.num_users =
1674 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER);
1675
1676 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0);
1677 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32);
1678 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1679
1680 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0);
1681 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16);
1682 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1683
1684 if (tx_ppdu_info->rx_status.reception_type == 0)
1685 ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
1686 status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1687 break;
1688 }
1689
1690 case HAL_PCU_PPDU_SETUP_INIT: {
1691 struct hal_tx_pcu_ppdu_setup_init *ppdu_setup =
1692 (struct hal_tx_pcu_ppdu_setup_init *)tlv_data;
1693 u32 addr_32;
1694 u16 addr_16;
1695
1696 info[0] = __le32_to_cpu(ppdu_setup->info0);
1697 info[1] = __le32_to_cpu(ppdu_setup->info1);
1698 info[2] = __le32_to_cpu(ppdu_setup->info2);
1699 info[3] = __le32_to_cpu(ppdu_setup->info3);
1700 info[4] = __le32_to_cpu(ppdu_setup->info4);
1701 info[5] = __le32_to_cpu(ppdu_setup->info5);
1702 info[6] = __le32_to_cpu(ppdu_setup->info6);
1703
1704 /* protection frame address 1 */
1705 addr_32 = u32_get_bits(info[1],
1706 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0);
1707 addr_16 = u32_get_bits(info[2],
1708 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32);
1709 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1710
1711 /* protection frame address 2 */
1712 addr_16 = u32_get_bits(info[2],
1713 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0);
1714 addr_32 = u32_get_bits(info[3],
1715 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16);
1716 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
1717
1718 /* protection frame address 3 */
1719 addr_32 = u32_get_bits(info[4],
1720 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0);
1721 addr_16 = u32_get_bits(info[5],
1722 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32);
1723 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3);
1724
1725 /* protection frame address 4 */
1726 addr_16 = u32_get_bits(info[5],
1727 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0);
1728 addr_32 = u32_get_bits(info[6],
1729 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16);
1730 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4);
1731
1732 status = u32_get_bits(info[0],
1733 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE);
1734 break;
1735 }
1736
1737 case HAL_TX_QUEUE_EXTENSION: {
1738 struct hal_tx_queue_exten *tx_q_exten =
1739 (struct hal_tx_queue_exten *)tlv_data;
1740
1741 info[0] = __le32_to_cpu(tx_q_exten->info0);
1742
1743 tx_ppdu_info->rx_status.frame_control =
1744 u32_get_bits(info[0],
1745 HAL_TX_Q_EXT_INFO0_FRAME_CTRL);
1746 tx_ppdu_info->rx_status.fc_valid = true;
1747 break;
1748 }
1749
1750 case HAL_TX_FES_STATUS_START: {
1751 struct hal_tx_fes_status_start *tx_fes_start =
1752 (struct hal_tx_fes_status_start *)tlv_data;
1753
1754 info[0] = __le32_to_cpu(tx_fes_start->info0);
1755
1756 tx_ppdu_info->rx_status.medium_prot_type =
1757 u32_get_bits(info[0],
1758 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE);
1759 break;
1760 }
1761
1762 case HAL_TX_FES_STATUS_PROT: {
1763 struct hal_tx_fes_status_prot *tx_fes_status =
1764 (struct hal_tx_fes_status_prot *)tlv_data;
1765 u32 start_timestamp;
1766 u32 end_timestamp;
1767
1768 info[0] = __le32_to_cpu(tx_fes_status->info0);
1769 info[1] = __le32_to_cpu(tx_fes_status->info1);
1770
1771 start_timestamp =
1772 u32_get_bits(info[0],
1773 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0);
1774 start_timestamp |=
1775 u32_get_bits(info[0],
1776 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15;
1777 end_timestamp =
1778 u32_get_bits(info[1],
1779 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0);
1780 end_timestamp |=
1781 u32_get_bits(info[1],
1782 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15;
1783 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp;
1784
1785 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info);
1786 break;
1787 }
1788
1789 case HAL_TX_FES_STATUS_START_PPDU:
1790 case HAL_TX_FES_STATUS_START_PROT: {
1791 struct hal_tx_fes_status_start_prot *tx_fes_stat_start =
1792 (struct hal_tx_fes_status_start_prot *)tlv_data;
1793 u64 ppdu_ts;
1794
1795 info[0] = __le32_to_cpu(tx_fes_stat_start->info0);
1796
1797 tx_ppdu_info->rx_status.ppdu_ts =
1798 u32_get_bits(info[0],
1799 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32);
1800 ppdu_ts = (u32_get_bits(info[1],
1801 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32));
1802 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32;
1803 break;
1804 }
1805
1806 case HAL_TX_FES_STATUS_USER_PPDU: {
1807 struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu =
1808 (struct hal_tx_fes_status_user_ppdu *)tlv_data;
1809
1810 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0);
1811
1812 tx_ppdu_info->rx_status.rx_duration =
1813 u32_get_bits(info[0],
1814 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION);
1815 break;
1816 }
1817
1818 case HAL_MACTX_HE_SIG_A_SU:
1819 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status);
1820 break;
1821
1822 case HAL_MACTX_HE_SIG_A_MU_DL:
1823 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status);
1824 break;
1825
1826 case HAL_MACTX_HE_SIG_B1_MU:
1827 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status);
1828 break;
1829
1830 case HAL_MACTX_HE_SIG_B2_MU:
1831 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status);
1832 break;
1833
1834 case HAL_MACTX_HE_SIG_B2_OFDMA:
1835 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status);
1836 break;
1837
1838 case HAL_MACTX_VHT_SIG_A:
1839 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1840 break;
1841
1842 case HAL_MACTX_L_SIG_A:
1843 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status);
1844 break;
1845
1846 case HAL_MACTX_L_SIG_B:
1847 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status);
1848 break;
1849
1850 case HAL_RX_FRAME_BITMAP_ACK: {
1851 struct hal_rx_frame_bitmap_ack *fbm_ack =
1852 (struct hal_rx_frame_bitmap_ack *)tlv_data;
1853 u32 addr_32;
1854 u16 addr_16;
1855
1856 info[0] = __le32_to_cpu(fbm_ack->info0);
1857 info[1] = __le32_to_cpu(fbm_ack->info1);
1858
1859 addr_32 = u32_get_bits(info[0],
1860 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0);
1861 addr_16 = u32_get_bits(info[1],
1862 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32);
1863 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
1864
1865 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info);
1866 break;
1867 }
1868
1869 case HAL_MACTX_PHY_DESC: {
1870 struct hal_tx_phy_desc *tx_phy_desc =
1871 (struct hal_tx_phy_desc *)tlv_data;
1872
1873 info[0] = __le32_to_cpu(tx_phy_desc->info0);
1874 info[1] = __le32_to_cpu(tx_phy_desc->info1);
1875 info[2] = __le32_to_cpu(tx_phy_desc->info2);
1876 info[3] = __le32_to_cpu(tx_phy_desc->info3);
1877
1878 tx_ppdu_info->rx_status.beamformed =
1879 u32_get_bits(info[0],
1880 HAL_TX_PHY_DESC_INFO0_BF_TYPE);
1881 tx_ppdu_info->rx_status.preamble_type =
1882 u32_get_bits(info[0],
1883 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B);
1884 tx_ppdu_info->rx_status.mcs =
1885 u32_get_bits(info[1],
1886 HAL_TX_PHY_DESC_INFO1_MCS);
1887 tx_ppdu_info->rx_status.ltf_size =
1888 u32_get_bits(info[3],
1889 HAL_TX_PHY_DESC_INFO3_LTF_SIZE);
1890 tx_ppdu_info->rx_status.nss =
1891 u32_get_bits(info[2],
1892 HAL_TX_PHY_DESC_INFO2_NSS);
1893 tx_ppdu_info->rx_status.chan_num =
1894 u32_get_bits(info[3],
1895 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL);
1896 tx_ppdu_info->rx_status.bw =
1897 u32_get_bits(info[0],
1898 HAL_TX_PHY_DESC_INFO0_BANDWIDTH);
1899 break;
1900 }
1901
1902 case HAL_TX_MPDU_START: {
1903 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
1904
1905 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
1906 if (!mon_mpdu)
1907 return DP_MON_TX_STATUS_PPDU_NOT_DONE;
1908 status = DP_MON_TX_MPDU_START;
1909 break;
1910 }
1911
1912 case HAL_TX_MPDU_END:
1913 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1914 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1915 break;
1916 }
1917
1918 return status;
1919 }
1920
1921 enum dp_mon_tx_tlv_status
ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,struct hal_tlv_hdr * tx_tlv,u8 * num_users)1922 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,
1923 struct hal_tlv_hdr *tx_tlv,
1924 u8 *num_users)
1925 {
1926 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1927 u32 info0;
1928
1929 switch (tlv_tag) {
1930 case HAL_TX_FES_SETUP: {
1931 struct hal_tx_fes_setup *tx_fes_setup =
1932 (struct hal_tx_fes_setup *)tx_tlv;
1933
1934 info0 = __le32_to_cpu(tx_fes_setup->info0);
1935
1936 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
1937 tlv_status = DP_MON_TX_FES_SETUP;
1938 break;
1939 }
1940
1941 case HAL_RX_RESPONSE_REQUIRED_INFO: {
1942 /* TODO: need to update *num_users */
1943 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
1944 break;
1945 }
1946 }
1947
1948 return tlv_status;
1949 }
1950
1951 static void
ath12k_dp_mon_tx_process_ppdu_info(struct ath12k * ar,int mac_id,struct napi_struct * napi,struct dp_mon_tx_ppdu_info * tx_ppdu_info)1952 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id,
1953 struct napi_struct *napi,
1954 struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1955 {
1956 struct dp_mon_mpdu *tmp, *mon_mpdu;
1957 struct sk_buff *head_msdu;
1958
1959 list_for_each_entry_safe(mon_mpdu, tmp,
1960 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) {
1961 list_del(&mon_mpdu->list);
1962 head_msdu = mon_mpdu->head;
1963
1964 if (head_msdu)
1965 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu,
1966 &tx_ppdu_info->rx_status, napi);
1967
1968 kfree(mon_mpdu);
1969 }
1970 }
1971
1972 enum hal_rx_mon_status
ath12k_dp_mon_tx_parse_mon_status(struct ath12k * ar,struct ath12k_mon_data * pmon,int mac_id,struct sk_buff * skb,struct napi_struct * napi,u32 ppdu_id)1973 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar,
1974 struct ath12k_mon_data *pmon,
1975 int mac_id,
1976 struct sk_buff *skb,
1977 struct napi_struct *napi,
1978 u32 ppdu_id)
1979 {
1980 struct ath12k_base *ab = ar->ab;
1981 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info;
1982 struct hal_tlv_hdr *tlv;
1983 u8 *ptr = skb->data;
1984 u16 tlv_tag;
1985 u16 tlv_len;
1986 u32 tlv_userid = 0;
1987 u8 num_user;
1988 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
1989
1990 tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
1991 DP_MON_TX_PROT_PPDU_INFO);
1992 if (!tx_prot_ppdu_info)
1993 return -ENOMEM;
1994
1995 tlv = (struct hal_tlv_hdr *)ptr;
1996 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
1997
1998 tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user);
1999 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user)
2000 return -EINVAL;
2001
2002 tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2003 DP_MON_TX_DATA_PPDU_INFO);
2004 if (!tx_data_ppdu_info)
2005 return -ENOMEM;
2006
2007 do {
2008 tlv = (struct hal_tlv_hdr *)ptr;
2009 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2010 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
2011 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
2012
2013 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon,
2014 tlv_tag, ptr,
2015 tlv_userid);
2016 ptr += tlv_len;
2017 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
2018 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE)
2019 break;
2020 } while (tlv_status != DP_MON_TX_FES_STATUS_END);
2021
2022 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info);
2023 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info);
2024
2025 return tlv_status;
2026 }
2027
ath12k_dp_mon_srng_process(struct ath12k * ar,int mac_id,int * budget,enum dp_monitor_mode monitor_mode,struct napi_struct * napi)2028 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget,
2029 enum dp_monitor_mode monitor_mode,
2030 struct napi_struct *napi)
2031 {
2032 struct hal_mon_dest_desc *mon_dst_desc;
2033 struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2034 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2035 struct ath12k_base *ab = ar->ab;
2036 struct ath12k_dp *dp = &ab->dp;
2037 struct sk_buff *skb;
2038 struct ath12k_skb_rxcb *rxcb;
2039 struct dp_srng *mon_dst_ring;
2040 struct hal_srng *srng;
2041 struct dp_rxdma_mon_ring *buf_ring;
2042 u64 cookie;
2043 u32 ppdu_id;
2044 int num_buffs_reaped = 0, srng_id, buf_id;
2045 u8 dest_idx = 0, i;
2046 bool end_of_ppdu;
2047 struct hal_rx_mon_ppdu_info *ppdu_info;
2048 struct ath12k_peer *peer = NULL;
2049
2050 ppdu_info = &pmon->mon_ppdu_info;
2051 memset(ppdu_info, 0, sizeof(*ppdu_info));
2052 ppdu_info->peer_id = HAL_INVALID_PEERID;
2053
2054 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2055
2056 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) {
2057 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2058 buf_ring = &dp->rxdma_mon_buf_ring;
2059 } else {
2060 return 0;
2061 }
2062
2063 srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2064
2065 spin_lock_bh(&srng->lock);
2066 ath12k_hal_srng_access_begin(ab, srng);
2067
2068 while (likely(*budget)) {
2069 *budget -= 1;
2070 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2071 if (unlikely(!mon_dst_desc))
2072 break;
2073
2074 cookie = le32_to_cpu(mon_dst_desc->cookie);
2075 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2076
2077 spin_lock_bh(&buf_ring->idr_lock);
2078 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2079 spin_unlock_bh(&buf_ring->idr_lock);
2080
2081 if (unlikely(!skb)) {
2082 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2083 buf_id);
2084 goto move_next;
2085 }
2086
2087 rxcb = ATH12K_SKB_RXCB(skb);
2088 dma_unmap_single(ab->dev, rxcb->paddr,
2089 skb->len + skb_tailroom(skb),
2090 DMA_FROM_DEVICE);
2091
2092 pmon->dest_skb_q[dest_idx] = skb;
2093 dest_idx++;
2094 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id);
2095 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2096 HAL_MON_DEST_INFO0_END_OF_PPDU);
2097 if (!end_of_ppdu)
2098 continue;
2099
2100 for (i = 0; i < dest_idx; i++) {
2101 skb = pmon->dest_skb_q[i];
2102
2103 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE)
2104 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id,
2105 skb, napi);
2106 else
2107 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id,
2108 skb, napi, ppdu_id);
2109
2110 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2111
2112 if (!peer || !peer->sta) {
2113 ath12k_dbg(ab, ATH12K_DBG_DATA,
2114 "failed to find the peer with peer_id %d\n",
2115 ppdu_info->peer_id);
2116 dev_kfree_skb_any(skb);
2117 continue;
2118 }
2119
2120 dev_kfree_skb_any(skb);
2121 pmon->dest_skb_q[i] = NULL;
2122 }
2123
2124 dest_idx = 0;
2125 move_next:
2126 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2127 ath12k_hal_srng_dst_get_next_entry(ab, srng);
2128 num_buffs_reaped++;
2129 }
2130
2131 ath12k_hal_srng_access_end(ab, srng);
2132 spin_unlock_bh(&srng->lock);
2133
2134 return num_buffs_reaped;
2135 }
2136
2137 static void
ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats * rx_stats,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * user_stats,u32 num_msdu)2138 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats,
2139 struct hal_rx_mon_ppdu_info *ppdu_info,
2140 struct hal_rx_user_status *user_stats,
2141 u32 num_msdu)
2142 {
2143 u32 rate_idx = 0;
2144 u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs;
2145 u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1;
2146 u32 bw_idx = ppdu_info->bw;
2147 u32 gi_idx = ppdu_info->gi;
2148
2149 if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) ||
2150 (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) {
2151 return;
2152 }
2153
2154 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N ||
2155 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) {
2156 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx;
2157 rate_idx += bw_idx * 2 + gi_idx;
2158 } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) {
2159 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi);
2160 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx;
2161 rate_idx += bw_idx * 3 + gi_idx;
2162 } else {
2163 return;
2164 }
2165
2166 rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu;
2167 if (user_stats)
2168 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count;
2169 else
2170 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len;
2171 }
2172
ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k * ar,struct ath12k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2173 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar,
2174 struct ath12k_sta *arsta,
2175 struct hal_rx_mon_ppdu_info *ppdu_info)
2176 {
2177 struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats;
2178 u32 num_msdu;
2179
2180 if (!rx_stats)
2181 return;
2182
2183 arsta->rssi_comb = ppdu_info->rssi_comb;
2184
2185 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2186 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2187
2188 rx_stats->num_msdu += num_msdu;
2189 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2190 ppdu_info->tcp_ack_msdu_count;
2191 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2192 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2193
2194 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2195 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2196 ppdu_info->nss = 1;
2197 ppdu_info->mcs = HAL_RX_MAX_MCS;
2198 ppdu_info->tid = IEEE80211_NUM_TIDS;
2199 }
2200
2201 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2202 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2203
2204 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2205 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2206
2207 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2208 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2209
2210 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2211 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2212
2213 if (ppdu_info->is_stbc)
2214 rx_stats->stbc_count += num_msdu;
2215
2216 if (ppdu_info->beamformed)
2217 rx_stats->beamformed_count += num_msdu;
2218
2219 if (ppdu_info->num_mpdu_fcs_ok > 1)
2220 rx_stats->ampdu_msdu_count += num_msdu;
2221 else
2222 rx_stats->non_ampdu_msdu_count += num_msdu;
2223
2224 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2225 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2226 rx_stats->dcm_count += ppdu_info->dcm;
2227
2228 rx_stats->rx_duration += ppdu_info->rx_duration;
2229 arsta->rx_duration = rx_stats->rx_duration;
2230
2231 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) {
2232 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu;
2233 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len;
2234 }
2235
2236 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N &&
2237 ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) {
2238 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu;
2239 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2240 /* To fit into rate table for HT packets */
2241 ppdu_info->mcs = ppdu_info->mcs % 8;
2242 }
2243
2244 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC &&
2245 ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) {
2246 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu;
2247 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2248 }
2249
2250 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX &&
2251 ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) {
2252 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu;
2253 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
2254 }
2255
2256 if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2257 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) &&
2258 ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) {
2259 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu;
2260 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len;
2261 }
2262
2263 if (ppdu_info->gi < HAL_RX_GI_MAX) {
2264 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2265 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len;
2266 }
2267
2268 if (ppdu_info->bw < HAL_RX_BW_MAX) {
2269 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2270 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len;
2271 }
2272
2273 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2274 NULL, num_msdu);
2275 }
2276
ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info * ppdu_info)2277 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info)
2278 {
2279 struct hal_rx_user_status *rx_user_status;
2280 u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size;
2281
2282 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
2283 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2284 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
2285 return;
2286
2287 num_users = ppdu_info->num_users;
2288 if (num_users > HAL_MAX_UL_MU_USERS)
2289 num_users = HAL_MAX_UL_MU_USERS;
2290
2291 for (i = 0; i < num_users; i++) {
2292 rx_user_status = &ppdu_info->userstats[i];
2293 mu_ul_user_v0_word0 =
2294 rx_user_status->ul_ofdma_user_v0_word0;
2295 mu_ul_user_v0_word1 =
2296 rx_user_status->ul_ofdma_user_v0_word1;
2297
2298 if (u32_get_bits(mu_ul_user_v0_word0,
2299 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) &&
2300 !u32_get_bits(mu_ul_user_v0_word0,
2301 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) {
2302 rx_user_status->mcs =
2303 u32_get_bits(mu_ul_user_v0_word1,
2304 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS);
2305 rx_user_status->nss =
2306 u32_get_bits(mu_ul_user_v0_word1,
2307 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1;
2308
2309 rx_user_status->ofdma_info_valid = 1;
2310 rx_user_status->ul_ofdma_ru_start_index =
2311 u32_get_bits(mu_ul_user_v0_word1,
2312 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START);
2313
2314 ru_size = u32_get_bits(mu_ul_user_v0_word1,
2315 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE);
2316 rx_user_status->ul_ofdma_ru_width = ru_size;
2317 rx_user_status->ul_ofdma_ru_size = ru_size;
2318 }
2319 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1,
2320 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC);
2321 }
2322 ppdu_info->ldpc = 1;
2323 }
2324
2325 static void
ath12k_dp_mon_rx_update_user_stats(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppdu_info,u32 uid)2326 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar,
2327 struct hal_rx_mon_ppdu_info *ppdu_info,
2328 u32 uid)
2329 {
2330 struct ath12k_sta *arsta = NULL;
2331 struct ath12k_rx_peer_stats *rx_stats = NULL;
2332 struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid];
2333 struct ath12k_peer *peer;
2334 u32 num_msdu;
2335
2336 if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF)
2337 return;
2338
2339 peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index);
2340
2341 if (!peer) {
2342 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n",
2343 user_stats->ast_index);
2344 return;
2345 }
2346
2347 arsta = ath12k_sta_to_arsta(peer->sta);
2348 rx_stats = arsta->rx_stats;
2349
2350 if (!rx_stats)
2351 return;
2352
2353 arsta->rssi_comb = ppdu_info->rssi_comb;
2354
2355 num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count +
2356 user_stats->udp_msdu_count + user_stats->other_msdu_count;
2357
2358 rx_stats->num_msdu += num_msdu;
2359 rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count +
2360 user_stats->tcp_ack_msdu_count;
2361 rx_stats->udp_msdu_count += user_stats->udp_msdu_count;
2362 rx_stats->other_msdu_count += user_stats->other_msdu_count;
2363
2364 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2365 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2366
2367 if (user_stats->tid <= IEEE80211_NUM_TIDS)
2368 rx_stats->tid_count[user_stats->tid] += num_msdu;
2369
2370 if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX)
2371 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu;
2372
2373 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2374 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2375
2376 if (ppdu_info->is_stbc)
2377 rx_stats->stbc_count += num_msdu;
2378
2379 if (ppdu_info->beamformed)
2380 rx_stats->beamformed_count += num_msdu;
2381
2382 if (user_stats->mpdu_cnt_fcs_ok > 1)
2383 rx_stats->ampdu_msdu_count += num_msdu;
2384 else
2385 rx_stats->non_ampdu_msdu_count += num_msdu;
2386
2387 rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok;
2388 rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err;
2389 rx_stats->dcm_count += ppdu_info->dcm;
2390 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
2391 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)
2392 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu;
2393
2394 rx_stats->rx_duration += ppdu_info->rx_duration;
2395 arsta->rx_duration = rx_stats->rx_duration;
2396
2397 if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) {
2398 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu;
2399 rx_stats->byte_stats.nss_count[user_stats->nss - 1] +=
2400 user_stats->mpdu_ok_byte_count;
2401 }
2402
2403 if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX &&
2404 user_stats->mcs <= HAL_RX_MAX_MCS_HE) {
2405 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu;
2406 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] +=
2407 user_stats->mpdu_ok_byte_count;
2408 }
2409
2410 if (ppdu_info->gi < HAL_RX_GI_MAX) {
2411 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
2412 rx_stats->byte_stats.gi_count[ppdu_info->gi] +=
2413 user_stats->mpdu_ok_byte_count;
2414 }
2415
2416 if (ppdu_info->bw < HAL_RX_BW_MAX) {
2417 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
2418 rx_stats->byte_stats.bw_count[ppdu_info->bw] +=
2419 user_stats->mpdu_ok_byte_count;
2420 }
2421
2422 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
2423 user_stats, num_msdu);
2424 }
2425
2426 static void
ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppdu_info)2427 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar,
2428 struct hal_rx_mon_ppdu_info *ppdu_info)
2429 {
2430 u32 num_users, i;
2431
2432 num_users = ppdu_info->num_users;
2433 if (num_users > HAL_MAX_UL_MU_USERS)
2434 num_users = HAL_MAX_UL_MU_USERS;
2435
2436 for (i = 0; i < num_users; i++)
2437 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i);
2438 }
2439
ath12k_dp_mon_rx_process_stats(struct ath12k * ar,int mac_id,struct napi_struct * napi,int * budget)2440 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id,
2441 struct napi_struct *napi, int *budget)
2442 {
2443 struct ath12k_base *ab = ar->ab;
2444 struct ath12k_pdev_dp *pdev_dp = &ar->dp;
2445 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
2446 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
2447 struct ath12k_dp *dp = &ab->dp;
2448 struct hal_mon_dest_desc *mon_dst_desc;
2449 struct sk_buff *skb;
2450 struct ath12k_skb_rxcb *rxcb;
2451 struct dp_srng *mon_dst_ring;
2452 struct hal_srng *srng;
2453 struct dp_rxdma_mon_ring *buf_ring;
2454 struct ath12k_sta *arsta = NULL;
2455 struct ath12k_peer *peer;
2456 u64 cookie;
2457 int num_buffs_reaped = 0, srng_id, buf_id;
2458 u8 dest_idx = 0, i;
2459 bool end_of_ppdu;
2460 u32 hal_status;
2461
2462 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
2463 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
2464 buf_ring = &dp->rxdma_mon_buf_ring;
2465
2466 srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
2467 spin_lock_bh(&srng->lock);
2468 ath12k_hal_srng_access_begin(ab, srng);
2469
2470 while (likely(*budget)) {
2471 *budget -= 1;
2472 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
2473 if (unlikely(!mon_dst_desc))
2474 break;
2475 cookie = le32_to_cpu(mon_dst_desc->cookie);
2476 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2477
2478 spin_lock_bh(&buf_ring->idr_lock);
2479 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
2480 spin_unlock_bh(&buf_ring->idr_lock);
2481
2482 if (unlikely(!skb)) {
2483 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
2484 buf_id);
2485 goto move_next;
2486 }
2487
2488 rxcb = ATH12K_SKB_RXCB(skb);
2489 dma_unmap_single(ab->dev, rxcb->paddr,
2490 skb->len + skb_tailroom(skb),
2491 DMA_FROM_DEVICE);
2492 pmon->dest_skb_q[dest_idx] = skb;
2493 dest_idx++;
2494 end_of_ppdu = le32_get_bits(mon_dst_desc->info0,
2495 HAL_MON_DEST_INFO0_END_OF_PPDU);
2496 if (!end_of_ppdu)
2497 continue;
2498
2499 for (i = 0; i < dest_idx; i++) {
2500 skb = pmon->dest_skb_q[i];
2501 hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb);
2502
2503 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
2504 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2505 dev_kfree_skb_any(skb);
2506 continue;
2507 }
2508
2509 rcu_read_lock();
2510 spin_lock_bh(&ab->base_lock);
2511 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
2512 if (!peer || !peer->sta) {
2513 ath12k_dbg(ab, ATH12K_DBG_DATA,
2514 "failed to find the peer with peer_id %d\n",
2515 ppdu_info->peer_id);
2516 spin_unlock_bh(&ab->base_lock);
2517 rcu_read_unlock();
2518 dev_kfree_skb_any(skb);
2519 continue;
2520 }
2521
2522 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) {
2523 arsta = ath12k_sta_to_arsta(peer->sta);
2524 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta,
2525 ppdu_info);
2526 } else if ((ppdu_info->fc_valid) &&
2527 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) {
2528 ath12k_dp_mon_rx_process_ulofdma(ppdu_info);
2529 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info);
2530 }
2531
2532 spin_unlock_bh(&ab->base_lock);
2533 rcu_read_unlock();
2534 dev_kfree_skb_any(skb);
2535 memset(ppdu_info, 0, sizeof(*ppdu_info));
2536 ppdu_info->peer_id = HAL_INVALID_PEERID;
2537 }
2538
2539 dest_idx = 0;
2540 move_next:
2541 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
2542 ath12k_hal_srng_src_get_next_entry(ab, srng);
2543 num_buffs_reaped++;
2544 }
2545
2546 ath12k_hal_srng_access_end(ab, srng);
2547 spin_unlock_bh(&srng->lock);
2548 return num_buffs_reaped;
2549 }
2550
ath12k_dp_mon_process_ring(struct ath12k_base * ab,int mac_id,struct napi_struct * napi,int budget,enum dp_monitor_mode monitor_mode)2551 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id,
2552 struct napi_struct *napi, int budget,
2553 enum dp_monitor_mode monitor_mode)
2554 {
2555 struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id);
2556 int num_buffs_reaped = 0;
2557
2558 if (!ar->monitor_started)
2559 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget);
2560 else
2561 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget,
2562 monitor_mode, napi);
2563
2564 return num_buffs_reaped;
2565 }
2566