1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "hal_desc.h"
14 #include "hw.h"
15 #include "dp_rx.h"
16 #include "hal_rx.h"
17 #include "dp_tx.h"
18 #include "peer.h"
19 #include "dp_mon.h"
20 #include "debugfs_htt_stats.h"
21
22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
ath12k_dp_rx_h_enctype(struct ath12k_base * ab,struct hal_rx_desc * desc)24 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab,
25 struct hal_rx_desc *desc)
26 {
27 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc))
28 return HAL_ENCRYPT_TYPE_OPEN;
29
30 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc);
31 }
32
ath12k_dp_rx_h_decap_type(struct ath12k_base * ab,struct hal_rx_desc * desc)33 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab,
34 struct hal_rx_desc *desc)
35 {
36 return ab->hal_rx_ops->rx_desc_get_decap_type(desc);
37 }
38
ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base * ab,struct hal_rx_desc * desc)39 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab,
40 struct hal_rx_desc *desc)
41 {
42 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc);
43 }
44
ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)45 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab,
46 struct hal_rx_desc *desc)
47 {
48 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
49 }
50
ath12k_dp_rx_h_fc_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)51 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab,
52 struct hal_rx_desc *desc)
53 {
54 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc);
55 }
56
ath12k_dp_rx_h_more_frags(struct ath12k_base * ab,struct sk_buff * skb)57 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab,
58 struct sk_buff *skb)
59 {
60 struct ieee80211_hdr *hdr;
61
62 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
63 return ieee80211_has_morefrags(hdr->frame_control);
64 }
65
ath12k_dp_rx_h_frag_no(struct ath12k_base * ab,struct sk_buff * skb)66 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab,
67 struct sk_buff *skb)
68 {
69 struct ieee80211_hdr *hdr;
70
71 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
72 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
73 }
74
ath12k_dp_rx_h_seq_no(struct ath12k_base * ab,struct hal_rx_desc * desc)75 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab,
76 struct hal_rx_desc *desc)
77 {
78 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc);
79 }
80
ath12k_dp_rx_h_msdu_done(struct ath12k_base * ab,struct hal_rx_desc * desc)81 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab,
82 struct hal_rx_desc *desc)
83 {
84 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc);
85 }
86
ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)87 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab,
88 struct hal_rx_desc *desc)
89 {
90 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc);
91 }
92
ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)93 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab,
94 struct hal_rx_desc *desc)
95 {
96 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc);
97 }
98
ath12k_dp_rx_h_is_decrypted(struct ath12k_base * ab,struct hal_rx_desc * desc)99 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab,
100 struct hal_rx_desc *desc)
101 {
102 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc);
103 }
104
ath12k_dp_rx_h_mpdu_err(struct ath12k_base * ab,struct hal_rx_desc * desc)105 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab,
106 struct hal_rx_desc *desc)
107 {
108 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc);
109 }
110
ath12k_dp_rx_h_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc)111 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab,
112 struct hal_rx_desc *desc)
113 {
114 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc);
115 }
116
ath12k_dp_rx_h_sgi(struct ath12k_base * ab,struct hal_rx_desc * desc)117 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab,
118 struct hal_rx_desc *desc)
119 {
120 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc);
121 }
122
ath12k_dp_rx_h_rate_mcs(struct ath12k_base * ab,struct hal_rx_desc * desc)123 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab,
124 struct hal_rx_desc *desc)
125 {
126 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc);
127 }
128
ath12k_dp_rx_h_rx_bw(struct ath12k_base * ab,struct hal_rx_desc * desc)129 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab,
130 struct hal_rx_desc *desc)
131 {
132 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc);
133 }
134
ath12k_dp_rx_h_freq(struct ath12k_base * ab,struct hal_rx_desc * desc)135 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab,
136 struct hal_rx_desc *desc)
137 {
138 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc);
139 }
140
ath12k_dp_rx_h_pkt_type(struct ath12k_base * ab,struct hal_rx_desc * desc)141 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab,
142 struct hal_rx_desc *desc)
143 {
144 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc);
145 }
146
ath12k_dp_rx_h_nss(struct ath12k_base * ab,struct hal_rx_desc * desc)147 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab,
148 struct hal_rx_desc *desc)
149 {
150 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc));
151 }
152
ath12k_dp_rx_h_tid(struct ath12k_base * ab,struct hal_rx_desc * desc)153 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab,
154 struct hal_rx_desc *desc)
155 {
156 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc);
157 }
158
ath12k_dp_rx_h_peer_id(struct ath12k_base * ab,struct hal_rx_desc * desc)159 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab,
160 struct hal_rx_desc *desc)
161 {
162 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc);
163 }
164
ath12k_dp_rx_h_l3pad(struct ath12k_base * ab,struct hal_rx_desc * desc)165 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab,
166 struct hal_rx_desc *desc)
167 {
168 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc);
169 }
170
ath12k_dp_rx_h_first_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)171 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab,
172 struct hal_rx_desc *desc)
173 {
174 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc);
175 }
176
ath12k_dp_rx_h_last_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)177 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab,
178 struct hal_rx_desc *desc)
179 {
180 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc);
181 }
182
ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)183 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab,
184 struct hal_rx_desc *fdesc,
185 struct hal_rx_desc *ldesc)
186 {
187 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc);
188 }
189
ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc,u16 len)190 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab,
191 struct hal_rx_desc *desc,
192 u16 len)
193 {
194 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len);
195 }
196
ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base * ab,struct hal_rx_desc * desc)197 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab,
198 struct hal_rx_desc *desc)
199 {
200 return (ath12k_dp_rx_h_first_msdu(ab, desc) &&
201 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc));
202 }
203
ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)204 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab,
205 struct hal_rx_desc *desc)
206 {
207 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc);
208 }
209
ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base * ab,struct hal_rx_desc * desc)210 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab,
211 struct hal_rx_desc *desc)
212 {
213 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc);
214 }
215
ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base * ab,struct hal_rx_desc * desc,struct ieee80211_hdr * hdr)216 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab,
217 struct hal_rx_desc *desc,
218 struct ieee80211_hdr *hdr)
219 {
220 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr);
221 }
222
ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base * ab,struct hal_rx_desc * desc,u8 * crypto_hdr,enum hal_encrypt_type enctype)223 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab,
224 struct hal_rx_desc *desc,
225 u8 *crypto_hdr,
226 enum hal_encrypt_type enctype)
227 {
228 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype);
229 }
230
ath12k_dp_rx_get_msdu_src_link(struct ath12k_base * ab,struct hal_rx_desc * desc)231 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab,
232 struct hal_rx_desc *desc)
233 {
234 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc);
235 }
236
ath12k_dp_clean_up_skb_list(struct sk_buff_head * skb_list)237 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list)
238 {
239 struct sk_buff *skb;
240
241 while ((skb = __skb_dequeue(skb_list)))
242 dev_kfree_skb_any(skb);
243 }
244
ath12k_dp_list_cut_nodes(struct list_head * list,struct list_head * head,size_t count)245 static size_t ath12k_dp_list_cut_nodes(struct list_head *list,
246 struct list_head *head,
247 size_t count)
248 {
249 struct list_head *cur;
250 struct ath12k_rx_desc_info *rx_desc;
251 size_t nodes = 0;
252
253 if (!count) {
254 INIT_LIST_HEAD(list);
255 goto out;
256 }
257
258 list_for_each(cur, head) {
259 if (!count)
260 break;
261
262 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list);
263 rx_desc->in_use = true;
264
265 count--;
266 nodes++;
267 }
268
269 list_cut_before(list, head, cur);
270 out:
271 return nodes;
272 }
273
ath12k_dp_rx_enqueue_free(struct ath12k_dp * dp,struct list_head * used_list)274 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp,
275 struct list_head *used_list)
276 {
277 struct ath12k_rx_desc_info *rx_desc, *safe;
278
279 /* Reset the use flag */
280 list_for_each_entry_safe(rx_desc, safe, used_list, list)
281 rx_desc->in_use = false;
282
283 spin_lock_bh(&dp->rx_desc_lock);
284 list_splice_tail(used_list, &dp->rx_desc_free_list);
285 spin_unlock_bh(&dp->rx_desc_lock);
286 }
287
288 /* Returns number of Rx buffers replenished */
ath12k_dp_rx_bufs_replenish(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring,struct list_head * used_list,int req_entries)289 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,
290 struct dp_rxdma_ring *rx_ring,
291 struct list_head *used_list,
292 int req_entries)
293 {
294 struct ath12k_buffer_addr *desc;
295 struct hal_srng *srng;
296 struct sk_buff *skb;
297 int num_free;
298 int num_remain;
299 u32 cookie;
300 dma_addr_t paddr;
301 struct ath12k_dp *dp = &ab->dp;
302 struct ath12k_rx_desc_info *rx_desc;
303 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm;
304
305 req_entries = min(req_entries, rx_ring->bufs_max);
306
307 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
308
309 spin_lock_bh(&srng->lock);
310
311 ath12k_hal_srng_access_begin(ab, srng);
312
313 num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
314 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
315 req_entries = num_free;
316
317 req_entries = min(num_free, req_entries);
318 num_remain = req_entries;
319
320 if (!num_remain)
321 goto out;
322
323 /* Get the descriptor from free list */
324 if (list_empty(used_list)) {
325 spin_lock_bh(&dp->rx_desc_lock);
326 req_entries = ath12k_dp_list_cut_nodes(used_list,
327 &dp->rx_desc_free_list,
328 num_remain);
329 spin_unlock_bh(&dp->rx_desc_lock);
330 num_remain = req_entries;
331 }
332
333 while (num_remain > 0) {
334 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
335 DP_RX_BUFFER_ALIGN_SIZE);
336 if (!skb)
337 break;
338
339 if (!IS_ALIGNED((unsigned long)skb->data,
340 DP_RX_BUFFER_ALIGN_SIZE)) {
341 skb_pull(skb,
342 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
343 skb->data);
344 }
345
346 paddr = dma_map_single(ab->dev, skb->data,
347 skb->len + skb_tailroom(skb),
348 DMA_FROM_DEVICE);
349 if (dma_mapping_error(ab->dev, paddr))
350 goto fail_free_skb;
351
352 rx_desc = list_first_entry_or_null(used_list,
353 struct ath12k_rx_desc_info,
354 list);
355 if (!rx_desc)
356 goto fail_dma_unmap;
357
358 rx_desc->skb = skb;
359 cookie = rx_desc->cookie;
360
361 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
362 if (!desc)
363 goto fail_dma_unmap;
364
365 list_del(&rx_desc->list);
366 ATH12K_SKB_RXCB(skb)->paddr = paddr;
367
368 num_remain--;
369
370 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
371 }
372
373 goto out;
374
375 fail_dma_unmap:
376 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
377 DMA_FROM_DEVICE);
378 fail_free_skb:
379 dev_kfree_skb_any(skb);
380 out:
381 ath12k_hal_srng_access_end(ab, srng);
382
383 if (!list_empty(used_list))
384 ath12k_dp_rx_enqueue_free(dp, used_list);
385
386 spin_unlock_bh(&srng->lock);
387
388 return req_entries - num_remain;
389 }
390
ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring)391 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab,
392 struct dp_rxdma_mon_ring *rx_ring)
393 {
394 struct sk_buff *skb;
395 int buf_id;
396
397 spin_lock_bh(&rx_ring->idr_lock);
398 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
399 idr_remove(&rx_ring->bufs_idr, buf_id);
400 /* TODO: Understand where internal driver does this dma_unmap
401 * of rxdma_buffer.
402 */
403 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
404 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
405 dev_kfree_skb_any(skb);
406 }
407
408 idr_destroy(&rx_ring->bufs_idr);
409 spin_unlock_bh(&rx_ring->idr_lock);
410
411 return 0;
412 }
413
ath12k_dp_rxdma_buf_free(struct ath12k_base * ab)414 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab)
415 {
416 struct ath12k_dp *dp = &ab->dp;
417
418 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring);
419
420 return 0;
421 }
422
ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring,u32 ringtype)423 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab,
424 struct dp_rxdma_mon_ring *rx_ring,
425 u32 ringtype)
426 {
427 int num_entries;
428
429 num_entries = rx_ring->refill_buf_ring.size /
430 ath12k_hal_srng_get_entrysize(ab, ringtype);
431
432 rx_ring->bufs_max = num_entries;
433 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);
434
435 return 0;
436 }
437
ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring)438 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab,
439 struct dp_rxdma_ring *rx_ring)
440 {
441 LIST_HEAD(list);
442
443 rx_ring->bufs_max = rx_ring->refill_buf_ring.size /
444 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF);
445
446 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
447
448 return 0;
449 }
450
ath12k_dp_rxdma_buf_setup(struct ath12k_base * ab)451 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)
452 {
453 struct ath12k_dp *dp = &ab->dp;
454 int ret;
455
456 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring);
457 if (ret) {
458 ath12k_warn(ab,
459 "failed to setup HAL_RXDMA_BUF\n");
460 return ret;
461 }
462
463 if (ab->hw_params->rxdma1_enable) {
464 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,
465 &dp->rxdma_mon_buf_ring,
466 HAL_RXDMA_MONITOR_BUF);
467 if (ret) {
468 ath12k_warn(ab,
469 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
470 return ret;
471 }
472 }
473
474 return 0;
475 }
476
ath12k_dp_rx_pdev_srng_free(struct ath12k * ar)477 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar)
478 {
479 struct ath12k_pdev_dp *dp = &ar->dp;
480 struct ath12k_base *ab = ar->ab;
481 int i;
482
483 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++)
484 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]);
485 }
486
ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base * ab)487 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab)
488 {
489 struct ath12k_dp *dp = &ab->dp;
490 int i;
491
492 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
493 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
494 }
495
ath12k_dp_rx_pdev_reo_setup(struct ath12k_base * ab)496 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab)
497 {
498 struct ath12k_dp *dp = &ab->dp;
499 int ret;
500 int i;
501
502 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
503 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
504 HAL_REO_DST, i, 0,
505 DP_REO_DST_RING_SIZE);
506 if (ret) {
507 ath12k_warn(ab, "failed to setup reo_dst_ring\n");
508 goto err_reo_cleanup;
509 }
510 }
511
512 return 0;
513
514 err_reo_cleanup:
515 ath12k_dp_rx_pdev_reo_cleanup(ab);
516
517 return ret;
518 }
519
ath12k_dp_rx_pdev_srng_alloc(struct ath12k * ar)520 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar)
521 {
522 struct ath12k_pdev_dp *dp = &ar->dp;
523 struct ath12k_base *ab = ar->ab;
524 int i;
525 int ret;
526 u32 mac_id = dp->mac_id;
527
528 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
529 ret = ath12k_dp_srng_setup(ar->ab,
530 &dp->rxdma_mon_dst_ring[i],
531 HAL_RXDMA_MONITOR_DST,
532 0, mac_id + i,
533 DP_RXDMA_MONITOR_DST_RING_SIZE);
534 if (ret) {
535 ath12k_warn(ar->ab,
536 "failed to setup HAL_RXDMA_MONITOR_DST\n");
537 return ret;
538 }
539 }
540
541 return 0;
542 }
543
ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base * ab)544 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab)
545 {
546 struct ath12k_dp *dp = &ab->dp;
547 struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
548 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache;
549
550 spin_lock_bh(&dp->reo_cmd_lock);
551 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
552 list_del(&cmd->list);
553 dma_unmap_single(ab->dev, cmd->data.paddr,
554 cmd->data.size, DMA_BIDIRECTIONAL);
555 kfree(cmd->data.vaddr);
556 kfree(cmd);
557 }
558
559 list_for_each_entry_safe(cmd_cache, tmp_cache,
560 &dp->reo_cmd_cache_flush_list, list) {
561 list_del(&cmd_cache->list);
562 dp->reo_cmd_cache_flush_count--;
563 dma_unmap_single(ab->dev, cmd_cache->data.paddr,
564 cmd_cache->data.size, DMA_BIDIRECTIONAL);
565 kfree(cmd_cache->data.vaddr);
566 kfree(cmd_cache);
567 }
568 spin_unlock_bh(&dp->reo_cmd_lock);
569 }
570
ath12k_dp_reo_cmd_free(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)571 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx,
572 enum hal_reo_cmd_status status)
573 {
574 struct ath12k_dp_rx_tid *rx_tid = ctx;
575
576 if (status != HAL_REO_CMD_SUCCESS)
577 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
578 rx_tid->tid, status);
579
580 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
581 DMA_BIDIRECTIONAL);
582 kfree(rx_tid->vaddr);
583 rx_tid->vaddr = NULL;
584 }
585
ath12k_dp_reo_cmd_send(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath12k_hal_reo_cmd * cmd,void (* cb)(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status))586 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid,
587 enum hal_reo_cmd_type type,
588 struct ath12k_hal_reo_cmd *cmd,
589 void (*cb)(struct ath12k_dp *dp, void *ctx,
590 enum hal_reo_cmd_status status))
591 {
592 struct ath12k_dp *dp = &ab->dp;
593 struct ath12k_dp_rx_reo_cmd *dp_cmd;
594 struct hal_srng *cmd_ring;
595 int cmd_num;
596
597 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
598 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
599
600 /* cmd_num should start from 1, during failure return the error code */
601 if (cmd_num < 0)
602 return cmd_num;
603
604 /* reo cmd ring descriptors has cmd_num starting from 1 */
605 if (cmd_num == 0)
606 return -EINVAL;
607
608 if (!cb)
609 return 0;
610
611 /* Can this be optimized so that we keep the pending command list only
612 * for tid delete command to free up the resource on the command status
613 * indication?
614 */
615 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
616
617 if (!dp_cmd)
618 return -ENOMEM;
619
620 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid));
621 dp_cmd->cmd_num = cmd_num;
622 dp_cmd->handler = cb;
623
624 spin_lock_bh(&dp->reo_cmd_lock);
625 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
626 spin_unlock_bh(&dp->reo_cmd_lock);
627
628 return 0;
629 }
630
ath12k_dp_reo_cache_flush(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid)631 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab,
632 struct ath12k_dp_rx_tid *rx_tid)
633 {
634 struct ath12k_hal_reo_cmd cmd = {0};
635 unsigned long tot_desc_sz, desc_sz;
636 int ret;
637
638 tot_desc_sz = rx_tid->size;
639 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
640
641 while (tot_desc_sz > desc_sz) {
642 tot_desc_sz -= desc_sz;
643 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
644 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
645 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
646 HAL_REO_CMD_FLUSH_CACHE, &cmd,
647 NULL);
648 if (ret)
649 ath12k_warn(ab,
650 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
651 rx_tid->tid, ret);
652 }
653
654 memset(&cmd, 0, sizeof(cmd));
655 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
656 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
657 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
658 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
659 HAL_REO_CMD_FLUSH_CACHE,
660 &cmd, ath12k_dp_reo_cmd_free);
661 if (ret) {
662 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
663 rx_tid->tid, ret);
664 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
665 DMA_BIDIRECTIONAL);
666 kfree(rx_tid->vaddr);
667 rx_tid->vaddr = NULL;
668 }
669 }
670
ath12k_dp_rx_tid_del_func(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)671 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx,
672 enum hal_reo_cmd_status status)
673 {
674 struct ath12k_base *ab = dp->ab;
675 struct ath12k_dp_rx_tid *rx_tid = ctx;
676 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp;
677
678 if (status == HAL_REO_CMD_DRAIN) {
679 goto free_desc;
680 } else if (status != HAL_REO_CMD_SUCCESS) {
681 /* Shouldn't happen! Cleanup in case of other failure? */
682 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
683 rx_tid->tid, status);
684 return;
685 }
686
687 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
688 if (!elem)
689 goto free_desc;
690
691 elem->ts = jiffies;
692 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
693
694 spin_lock_bh(&dp->reo_cmd_lock);
695 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
696 dp->reo_cmd_cache_flush_count++;
697
698 /* Flush and invalidate aged REO desc from HW cache */
699 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
700 list) {
701 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES ||
702 time_after(jiffies, elem->ts +
703 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) {
704 list_del(&elem->list);
705 dp->reo_cmd_cache_flush_count--;
706
707 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send()
708 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list
709 * is used in only two contexts, one is in this function called
710 * from napi and the other in ath12k_dp_free during core destroy.
711 * Before dp_free, the irqs would be disabled and would wait to
712 * synchronize. Hence there wouldn’t be any race against add or
713 * delete to this list. Hence unlock-lock is safe here.
714 */
715 spin_unlock_bh(&dp->reo_cmd_lock);
716
717 ath12k_dp_reo_cache_flush(ab, &elem->data);
718 kfree(elem);
719 spin_lock_bh(&dp->reo_cmd_lock);
720 }
721 }
722 spin_unlock_bh(&dp->reo_cmd_lock);
723
724 return;
725 free_desc:
726 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
727 DMA_BIDIRECTIONAL);
728 kfree(rx_tid->vaddr);
729 rx_tid->vaddr = NULL;
730 }
731
ath12k_peer_rx_tid_qref_setup(struct ath12k_base * ab,u16 peer_id,u16 tid,dma_addr_t paddr)732 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid,
733 dma_addr_t paddr)
734 {
735 struct ath12k_reo_queue_ref *qref;
736 struct ath12k_dp *dp = &ab->dp;
737
738 if (!ab->hw_params->reoq_lut_support)
739 return;
740
741 /* TODO: based on ML peer or not, select the LUT. below assumes non
742 * ML peer
743 */
744 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
745 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
746
747 qref->info0 = u32_encode_bits(lower_32_bits(paddr),
748 BUFFER_ADDR_INFO0_ADDR);
749 qref->info1 = u32_encode_bits(upper_32_bits(paddr),
750 BUFFER_ADDR_INFO1_ADDR) |
751 u32_encode_bits(tid, DP_REO_QREF_NUM);
752 }
753
ath12k_peer_rx_tid_qref_reset(struct ath12k_base * ab,u16 peer_id,u16 tid)754 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid)
755 {
756 struct ath12k_reo_queue_ref *qref;
757 struct ath12k_dp *dp = &ab->dp;
758
759 if (!ab->hw_params->reoq_lut_support)
760 return;
761
762 /* TODO: based on ML peer or not, select the LUT. below assumes non
763 * ML peer
764 */
765 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
766 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
767
768 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR);
769 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) |
770 u32_encode_bits(tid, DP_REO_QREF_NUM);
771 }
772
ath12k_dp_rx_peer_tid_delete(struct ath12k * ar,struct ath12k_peer * peer,u8 tid)773 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar,
774 struct ath12k_peer *peer, u8 tid)
775 {
776 struct ath12k_hal_reo_cmd cmd = {0};
777 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid];
778 int ret;
779
780 if (!rx_tid->active)
781 return;
782
783 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
784 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
785 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
786 cmd.upd0 = HAL_REO_CMD_UPD0_VLD;
787 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
788 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
789 ath12k_dp_rx_tid_del_func);
790 if (ret) {
791 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
792 tid, ret);
793 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
794 DMA_BIDIRECTIONAL);
795 kfree(rx_tid->vaddr);
796 rx_tid->vaddr = NULL;
797 }
798
799 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid);
800
801 rx_tid->active = false;
802 }
803
804 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted
805 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind
806 * that.
807 */
ath12k_dp_rx_link_desc_return(struct ath12k_base * ab,struct hal_reo_dest_ring * ring,enum hal_wbm_rel_bm_act action)808 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab,
809 struct hal_reo_dest_ring *ring,
810 enum hal_wbm_rel_bm_act action)
811 {
812 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring;
813 struct hal_wbm_release_ring *desc;
814 struct ath12k_dp *dp = &ab->dp;
815 struct hal_srng *srng;
816 int ret = 0;
817
818 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
819
820 spin_lock_bh(&srng->lock);
821
822 ath12k_hal_srng_access_begin(ab, srng);
823
824 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
825 if (!desc) {
826 ret = -ENOBUFS;
827 goto exit;
828 }
829
830 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action);
831
832 exit:
833 ath12k_hal_srng_access_end(ab, srng);
834
835 spin_unlock_bh(&srng->lock);
836
837 return ret;
838 }
839
ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid * rx_tid,bool rel_link_desc)840 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid,
841 bool rel_link_desc)
842 {
843 struct ath12k_base *ab = rx_tid->ab;
844
845 lockdep_assert_held(&ab->base_lock);
846
847 if (rx_tid->dst_ring_desc) {
848 if (rel_link_desc)
849 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc,
850 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
851 kfree(rx_tid->dst_ring_desc);
852 rx_tid->dst_ring_desc = NULL;
853 }
854
855 rx_tid->cur_sn = 0;
856 rx_tid->last_frag_no = 0;
857 rx_tid->rx_frag_bitmap = 0;
858 __skb_queue_purge(&rx_tid->rx_frags);
859 }
860
ath12k_dp_rx_peer_tid_cleanup(struct ath12k * ar,struct ath12k_peer * peer)861 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer)
862 {
863 struct ath12k_dp_rx_tid *rx_tid;
864 int i;
865
866 lockdep_assert_held(&ar->ab->base_lock);
867
868 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
869 rx_tid = &peer->rx_tid[i];
870
871 ath12k_dp_rx_peer_tid_delete(ar, peer, i);
872 ath12k_dp_rx_frags_cleanup(rx_tid, true);
873
874 spin_unlock_bh(&ar->ab->base_lock);
875 del_timer_sync(&rx_tid->frag_timer);
876 spin_lock_bh(&ar->ab->base_lock);
877 }
878 }
879
ath12k_peer_rx_tid_reo_update(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)880 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar,
881 struct ath12k_peer *peer,
882 struct ath12k_dp_rx_tid *rx_tid,
883 u32 ba_win_sz, u16 ssn,
884 bool update_ssn)
885 {
886 struct ath12k_hal_reo_cmd cmd = {0};
887 int ret;
888
889 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
890 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
891 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
892 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
893 cmd.ba_window_size = ba_win_sz;
894
895 if (update_ssn) {
896 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
897 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN);
898 }
899
900 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
901 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
902 NULL);
903 if (ret) {
904 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
905 rx_tid->tid, ret);
906 return ret;
907 }
908
909 rx_tid->ba_win_sz = ba_win_sz;
910
911 return 0;
912 }
913
ath12k_dp_rx_peer_tid_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)914 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id,
915 u8 tid, u32 ba_win_sz, u16 ssn,
916 enum hal_pn_type pn_type)
917 {
918 struct ath12k_base *ab = ar->ab;
919 struct ath12k_dp *dp = &ab->dp;
920 struct hal_rx_reo_queue *addr_aligned;
921 struct ath12k_peer *peer;
922 struct ath12k_dp_rx_tid *rx_tid;
923 u32 hw_desc_sz;
924 void *vaddr;
925 dma_addr_t paddr;
926 int ret;
927
928 spin_lock_bh(&ab->base_lock);
929
930 peer = ath12k_peer_find(ab, vdev_id, peer_mac);
931 if (!peer) {
932 spin_unlock_bh(&ab->base_lock);
933 ath12k_warn(ab, "failed to find the peer to set up rx tid\n");
934 return -ENOENT;
935 }
936
937 if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) {
938 spin_unlock_bh(&ab->base_lock);
939 ath12k_warn(ab, "reo qref table is not setup\n");
940 return -EINVAL;
941 }
942
943 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) {
944 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n",
945 peer->peer_id, tid);
946 spin_unlock_bh(&ab->base_lock);
947 return -EINVAL;
948 }
949
950 rx_tid = &peer->rx_tid[tid];
951 /* Update the tid queue if it is already setup */
952 if (rx_tid->active) {
953 paddr = rx_tid->paddr;
954 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid,
955 ba_win_sz, ssn, true);
956 spin_unlock_bh(&ab->base_lock);
957 if (ret) {
958 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid);
959 return ret;
960 }
961
962 if (!ab->hw_params->reoq_lut_support) {
963 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
964 peer_mac,
965 paddr, tid, 1,
966 ba_win_sz);
967 if (ret) {
968 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n",
969 tid, ret);
970 return ret;
971 }
972 }
973
974 return 0;
975 }
976
977 rx_tid->tid = tid;
978
979 rx_tid->ba_win_sz = ba_win_sz;
980
981 /* TODO: Optimize the memory allocation for qos tid based on
982 * the actual BA window size in REO tid update path.
983 */
984 if (tid == HAL_DESC_REO_NON_QOS_TID)
985 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid);
986 else
987 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
988
989 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
990 if (!vaddr) {
991 spin_unlock_bh(&ab->base_lock);
992 return -ENOMEM;
993 }
994
995 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
996
997 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
998 ssn, pn_type);
999
1000 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1001 DMA_BIDIRECTIONAL);
1002
1003 ret = dma_mapping_error(ab->dev, paddr);
1004 if (ret) {
1005 spin_unlock_bh(&ab->base_lock);
1006 goto err_mem_free;
1007 }
1008
1009 rx_tid->vaddr = vaddr;
1010 rx_tid->paddr = paddr;
1011 rx_tid->size = hw_desc_sz;
1012 rx_tid->active = true;
1013
1014 if (ab->hw_params->reoq_lut_support) {
1015 /* Update the REO queue LUT at the corresponding peer id
1016 * and tid with qaddr.
1017 */
1018 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr);
1019 spin_unlock_bh(&ab->base_lock);
1020 } else {
1021 spin_unlock_bh(&ab->base_lock);
1022 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1023 paddr, tid, 1, ba_win_sz);
1024 }
1025
1026 return ret;
1027
1028 err_mem_free:
1029 kfree(vaddr);
1030
1031 return ret;
1032 }
1033
ath12k_dp_rx_ampdu_start(struct ath12k * ar,struct ieee80211_ampdu_params * params)1034 int ath12k_dp_rx_ampdu_start(struct ath12k *ar,
1035 struct ieee80211_ampdu_params *params)
1036 {
1037 struct ath12k_base *ab = ar->ab;
1038 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta);
1039 int vdev_id = arsta->arvif->vdev_id;
1040 int ret;
1041
1042 ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id,
1043 params->tid, params->buf_size,
1044 params->ssn, arsta->pn_type);
1045 if (ret)
1046 ath12k_warn(ab, "failed to setup rx tid %d\n", ret);
1047
1048 return ret;
1049 }
1050
ath12k_dp_rx_ampdu_stop(struct ath12k * ar,struct ieee80211_ampdu_params * params)1051 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar,
1052 struct ieee80211_ampdu_params *params)
1053 {
1054 struct ath12k_base *ab = ar->ab;
1055 struct ath12k_peer *peer;
1056 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta);
1057 int vdev_id = arsta->arvif->vdev_id;
1058 bool active;
1059 int ret;
1060
1061 spin_lock_bh(&ab->base_lock);
1062
1063 peer = ath12k_peer_find(ab, vdev_id, params->sta->addr);
1064 if (!peer) {
1065 spin_unlock_bh(&ab->base_lock);
1066 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1067 return -ENOENT;
1068 }
1069
1070 active = peer->rx_tid[params->tid].active;
1071
1072 if (!active) {
1073 spin_unlock_bh(&ab->base_lock);
1074 return 0;
1075 }
1076
1077 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1078 spin_unlock_bh(&ab->base_lock);
1079 if (ret) {
1080 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1081 params->tid, ret);
1082 return ret;
1083 }
1084
1085 return ret;
1086 }
1087
ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1088 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif,
1089 const u8 *peer_addr,
1090 enum set_key_cmd key_cmd,
1091 struct ieee80211_key_conf *key)
1092 {
1093 struct ath12k *ar = arvif->ar;
1094 struct ath12k_base *ab = ar->ab;
1095 struct ath12k_hal_reo_cmd cmd = {0};
1096 struct ath12k_peer *peer;
1097 struct ath12k_dp_rx_tid *rx_tid;
1098 u8 tid;
1099 int ret = 0;
1100
1101 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1102 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1103 * for now.
1104 */
1105 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1106 return 0;
1107
1108 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
1109 cmd.upd0 = HAL_REO_CMD_UPD0_PN |
1110 HAL_REO_CMD_UPD0_PN_SIZE |
1111 HAL_REO_CMD_UPD0_PN_VALID |
1112 HAL_REO_CMD_UPD0_PN_CHECK |
1113 HAL_REO_CMD_UPD0_SVLD;
1114
1115 switch (key->cipher) {
1116 case WLAN_CIPHER_SUITE_TKIP:
1117 case WLAN_CIPHER_SUITE_CCMP:
1118 case WLAN_CIPHER_SUITE_CCMP_256:
1119 case WLAN_CIPHER_SUITE_GCMP:
1120 case WLAN_CIPHER_SUITE_GCMP_256:
1121 if (key_cmd == SET_KEY) {
1122 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1123 cmd.pn_size = 48;
1124 }
1125 break;
1126 default:
1127 break;
1128 }
1129
1130 spin_lock_bh(&ab->base_lock);
1131
1132 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr);
1133 if (!peer) {
1134 spin_unlock_bh(&ab->base_lock);
1135 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n",
1136 peer_addr);
1137 return -ENOENT;
1138 }
1139
1140 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1141 rx_tid = &peer->rx_tid[tid];
1142 if (!rx_tid->active)
1143 continue;
1144 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1145 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1146 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
1147 HAL_REO_CMD_UPDATE_RX_QUEUE,
1148 &cmd, NULL);
1149 if (ret) {
1150 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n",
1151 tid, peer_addr, ret);
1152 break;
1153 }
1154 }
1155
1156 spin_unlock_bh(&ab->base_lock);
1157
1158 return ret;
1159 }
1160
ath12k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1161 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1162 u16 peer_id)
1163 {
1164 int i;
1165
1166 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1167 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1168 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1169 return i;
1170 } else {
1171 return i;
1172 }
1173 }
1174
1175 return -EINVAL;
1176 }
1177
ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1178 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab,
1179 u16 tag, u16 len, const void *ptr,
1180 void *data)
1181 {
1182 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status;
1183 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn;
1184 const struct htt_ppdu_stats_user_rate *user_rate;
1185 struct htt_ppdu_stats_info *ppdu_info;
1186 struct htt_ppdu_user_stats *user_stats;
1187 int cur_user;
1188 u16 peer_id;
1189
1190 ppdu_info = data;
1191
1192 switch (tag) {
1193 case HTT_PPDU_STATS_TAG_COMMON:
1194 if (len < sizeof(struct htt_ppdu_stats_common)) {
1195 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1196 len, tag);
1197 return -EINVAL;
1198 }
1199 memcpy(&ppdu_info->ppdu_stats.common, ptr,
1200 sizeof(struct htt_ppdu_stats_common));
1201 break;
1202 case HTT_PPDU_STATS_TAG_USR_RATE:
1203 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1204 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1205 len, tag);
1206 return -EINVAL;
1207 }
1208 user_rate = ptr;
1209 peer_id = le16_to_cpu(user_rate->sw_peer_id);
1210 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1211 peer_id);
1212 if (cur_user < 0)
1213 return -EINVAL;
1214 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1215 user_stats->peer_id = peer_id;
1216 user_stats->is_valid_peer_id = true;
1217 memcpy(&user_stats->rate, ptr,
1218 sizeof(struct htt_ppdu_stats_user_rate));
1219 user_stats->tlv_flags |= BIT(tag);
1220 break;
1221 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1222 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1223 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1224 len, tag);
1225 return -EINVAL;
1226 }
1227
1228 cmplt_cmn = ptr;
1229 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id);
1230 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1231 peer_id);
1232 if (cur_user < 0)
1233 return -EINVAL;
1234 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1235 user_stats->peer_id = peer_id;
1236 user_stats->is_valid_peer_id = true;
1237 memcpy(&user_stats->cmpltn_cmn, ptr,
1238 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1239 user_stats->tlv_flags |= BIT(tag);
1240 break;
1241 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1242 if (len <
1243 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1244 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1245 len, tag);
1246 return -EINVAL;
1247 }
1248
1249 ba_status = ptr;
1250 peer_id = le16_to_cpu(ba_status->sw_peer_id);
1251 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1252 peer_id);
1253 if (cur_user < 0)
1254 return -EINVAL;
1255 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1256 user_stats->peer_id = peer_id;
1257 user_stats->is_valid_peer_id = true;
1258 memcpy(&user_stats->ack_ba, ptr,
1259 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1260 user_stats->tlv_flags |= BIT(tag);
1261 break;
1262 }
1263 return 0;
1264 }
1265
ath12k_dp_htt_tlv_iter(struct ath12k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath12k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1266 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
1267 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
1268 const void *ptr, void *data),
1269 void *data)
1270 {
1271 const struct htt_tlv *tlv;
1272 const void *begin = ptr;
1273 u16 tlv_tag, tlv_len;
1274 int ret = -EINVAL;
1275
1276 while (len > 0) {
1277 if (len < sizeof(*tlv)) {
1278 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1279 ptr - begin, len, sizeof(*tlv));
1280 return -EINVAL;
1281 }
1282 tlv = (struct htt_tlv *)ptr;
1283 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG);
1284 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN);
1285 ptr += sizeof(*tlv);
1286 len -= sizeof(*tlv);
1287
1288 if (tlv_len > len) {
1289 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1290 tlv_tag, ptr - begin, len, tlv_len);
1291 return -EINVAL;
1292 }
1293 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1294 if (ret == -ENOMEM)
1295 return ret;
1296
1297 ptr += tlv_len;
1298 len -= tlv_len;
1299 }
1300 return 0;
1301 }
1302
1303 static void
ath12k_update_per_peer_tx_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1304 ath12k_update_per_peer_tx_stats(struct ath12k *ar,
1305 struct htt_ppdu_stats *ppdu_stats, u8 user)
1306 {
1307 struct ath12k_base *ab = ar->ab;
1308 struct ath12k_peer *peer;
1309 struct ieee80211_sta *sta;
1310 struct ath12k_sta *arsta;
1311 struct htt_ppdu_stats_user_rate *user_rate;
1312 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1313 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1314 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1315 int ret;
1316 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1317 u32 v, succ_bytes = 0;
1318 u16 tones, rate = 0, succ_pkts = 0;
1319 u32 tx_duration = 0;
1320 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1321 bool is_ampdu = false;
1322
1323 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1324 return;
1325
1326 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1327 is_ampdu =
1328 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1329
1330 if (usr_stats->tlv_flags &
1331 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1332 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes);
1333 succ_pkts = le32_get_bits(usr_stats->ack_ba.info,
1334 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M);
1335 tid = le32_get_bits(usr_stats->ack_ba.info,
1336 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM);
1337 }
1338
1339 if (common->fes_duration_us)
1340 tx_duration = le32_to_cpu(common->fes_duration_us);
1341
1342 user_rate = &usr_stats->rate;
1343 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1344 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1345 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1346 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1347 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1348 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1349
1350 /* Note: If host configured fixed rates and in some other special
1351 * cases, the broadcast/management frames are sent in different rates.
1352 * Firmware rate's control to be skipped for this?
1353 */
1354
1355 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) {
1356 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1357 return;
1358 }
1359
1360 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) {
1361 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1362 return;
1363 }
1364
1365 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) {
1366 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1367 mcs, nss);
1368 return;
1369 }
1370
1371 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1372 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs,
1373 flags,
1374 &rate_idx,
1375 &rate);
1376 if (ret < 0)
1377 return;
1378 }
1379
1380 rcu_read_lock();
1381 spin_lock_bh(&ab->base_lock);
1382 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id);
1383
1384 if (!peer || !peer->sta) {
1385 spin_unlock_bh(&ab->base_lock);
1386 rcu_read_unlock();
1387 return;
1388 }
1389
1390 sta = peer->sta;
1391 arsta = ath12k_sta_to_arsta(sta);
1392
1393 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1394
1395 switch (flags) {
1396 case WMI_RATE_PREAMBLE_OFDM:
1397 arsta->txrate.legacy = rate;
1398 break;
1399 case WMI_RATE_PREAMBLE_CCK:
1400 arsta->txrate.legacy = rate;
1401 break;
1402 case WMI_RATE_PREAMBLE_HT:
1403 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1404 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1405 if (sgi)
1406 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1407 break;
1408 case WMI_RATE_PREAMBLE_VHT:
1409 arsta->txrate.mcs = mcs;
1410 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1411 if (sgi)
1412 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1413 break;
1414 case WMI_RATE_PREAMBLE_HE:
1415 arsta->txrate.mcs = mcs;
1416 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1417 arsta->txrate.he_dcm = dcm;
1418 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
1419 tones = le16_to_cpu(user_rate->ru_end) -
1420 le16_to_cpu(user_rate->ru_start) + 1;
1421 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones);
1422 arsta->txrate.he_ru_alloc = v;
1423 break;
1424 }
1425
1426 arsta->txrate.nss = nss;
1427 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw);
1428 arsta->tx_duration += tx_duration;
1429 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1430
1431 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1432 * So skip peer stats update for mgmt packets.
1433 */
1434 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1435 memset(peer_stats, 0, sizeof(*peer_stats));
1436 peer_stats->succ_pkts = succ_pkts;
1437 peer_stats->succ_bytes = succ_bytes;
1438 peer_stats->is_ampdu = is_ampdu;
1439 peer_stats->duration = tx_duration;
1440 peer_stats->ba_fails =
1441 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1442 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1443 }
1444
1445 spin_unlock_bh(&ab->base_lock);
1446 rcu_read_unlock();
1447 }
1448
ath12k_htt_update_ppdu_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats)1449 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar,
1450 struct htt_ppdu_stats *ppdu_stats)
1451 {
1452 u8 user;
1453
1454 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1455 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1456 }
1457
1458 static
ath12k_dp_htt_get_ppdu_desc(struct ath12k * ar,u32 ppdu_id)1459 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar,
1460 u32 ppdu_id)
1461 {
1462 struct htt_ppdu_stats_info *ppdu_info;
1463
1464 lockdep_assert_held(&ar->data_lock);
1465 if (!list_empty(&ar->ppdu_stats_info)) {
1466 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1467 if (ppdu_info->ppdu_id == ppdu_id)
1468 return ppdu_info;
1469 }
1470
1471 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1472 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1473 typeof(*ppdu_info), list);
1474 list_del(&ppdu_info->list);
1475 ar->ppdu_stat_list_depth--;
1476 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1477 kfree(ppdu_info);
1478 }
1479 }
1480
1481 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1482 if (!ppdu_info)
1483 return NULL;
1484
1485 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1486 ar->ppdu_stat_list_depth++;
1487
1488 return ppdu_info;
1489 }
1490
ath12k_copy_to_delay_stats(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1491 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer,
1492 struct htt_ppdu_user_stats *usr_stats)
1493 {
1494 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id);
1495 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0);
1496 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end);
1497 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start);
1498 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1);
1499 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags);
1500 peer->ppdu_stats_delayba.resp_rate_flags =
1501 le32_to_cpu(usr_stats->rate.resp_rate_flags);
1502
1503 peer->delayba_flag = true;
1504 }
1505
ath12k_copy_to_bar(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1506 static void ath12k_copy_to_bar(struct ath12k_peer *peer,
1507 struct htt_ppdu_user_stats *usr_stats)
1508 {
1509 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id);
1510 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0);
1511 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end);
1512 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start);
1513 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1);
1514 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags);
1515 usr_stats->rate.resp_rate_flags =
1516 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags);
1517
1518 peer->delayba_flag = false;
1519 }
1520
ath12k_htt_pull_ppdu_stats(struct ath12k_base * ab,struct sk_buff * skb)1521 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab,
1522 struct sk_buff *skb)
1523 {
1524 struct ath12k_htt_ppdu_stats_msg *msg;
1525 struct htt_ppdu_stats_info *ppdu_info;
1526 struct ath12k_peer *peer = NULL;
1527 struct htt_ppdu_user_stats *usr_stats = NULL;
1528 u32 peer_id = 0;
1529 struct ath12k *ar;
1530 int ret, i;
1531 u8 pdev_id;
1532 u32 ppdu_id, len;
1533
1534 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data;
1535 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE);
1536 if (len > (skb->len - struct_size(msg, data, 0))) {
1537 ath12k_warn(ab,
1538 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n",
1539 len, skb->len);
1540 return -EINVAL;
1541 }
1542
1543 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID);
1544 ppdu_id = le32_to_cpu(msg->ppdu_id);
1545
1546 rcu_read_lock();
1547 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1548 if (!ar) {
1549 ret = -EINVAL;
1550 goto exit;
1551 }
1552
1553 spin_lock_bh(&ar->data_lock);
1554 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1555 if (!ppdu_info) {
1556 spin_unlock_bh(&ar->data_lock);
1557 ret = -EINVAL;
1558 goto exit;
1559 }
1560
1561 ppdu_info->ppdu_id = ppdu_id;
1562 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len,
1563 ath12k_htt_tlv_ppdu_stats_parse,
1564 (void *)ppdu_info);
1565 if (ret) {
1566 spin_unlock_bh(&ar->data_lock);
1567 ath12k_warn(ab, "Failed to parse tlv %d\n", ret);
1568 goto exit;
1569 }
1570
1571 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) {
1572 spin_unlock_bh(&ar->data_lock);
1573 ath12k_warn(ab,
1574 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n",
1575 ppdu_info->ppdu_stats.common.num_users,
1576 HTT_PPDU_STATS_MAX_USERS);
1577 ret = -EINVAL;
1578 goto exit;
1579 }
1580
1581 /* back up data rate tlv for all peers */
1582 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA &&
1583 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) &&
1584 ppdu_info->delay_ba) {
1585 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) {
1586 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1587 spin_lock_bh(&ab->base_lock);
1588 peer = ath12k_peer_find_by_id(ab, peer_id);
1589 if (!peer) {
1590 spin_unlock_bh(&ab->base_lock);
1591 continue;
1592 }
1593
1594 usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1595 if (usr_stats->delay_ba)
1596 ath12k_copy_to_delay_stats(peer, usr_stats);
1597 spin_unlock_bh(&ab->base_lock);
1598 }
1599 }
1600
1601 /* restore all peers' data rate tlv to mu-bar tlv */
1602 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR &&
1603 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) {
1604 for (i = 0; i < ppdu_info->bar_num_users; i++) {
1605 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1606 spin_lock_bh(&ab->base_lock);
1607 peer = ath12k_peer_find_by_id(ab, peer_id);
1608 if (!peer) {
1609 spin_unlock_bh(&ab->base_lock);
1610 continue;
1611 }
1612
1613 usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1614 if (peer->delayba_flag)
1615 ath12k_copy_to_bar(peer, usr_stats);
1616 spin_unlock_bh(&ab->base_lock);
1617 }
1618 }
1619
1620 spin_unlock_bh(&ar->data_lock);
1621
1622 exit:
1623 rcu_read_unlock();
1624
1625 return ret;
1626 }
1627
ath12k_htt_mlo_offset_event_handler(struct ath12k_base * ab,struct sk_buff * skb)1628 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab,
1629 struct sk_buff *skb)
1630 {
1631 struct ath12k_htt_mlo_offset_msg *msg;
1632 struct ath12k_pdev *pdev;
1633 struct ath12k *ar;
1634 u8 pdev_id;
1635
1636 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data;
1637 pdev_id = u32_get_bits(__le32_to_cpu(msg->info),
1638 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID);
1639
1640 rcu_read_lock();
1641 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1642 if (!ar) {
1643 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id);
1644 goto exit;
1645 }
1646
1647 spin_lock_bh(&ar->data_lock);
1648 pdev = ar->pdev;
1649
1650 pdev->timestamp.info = __le32_to_cpu(msg->info);
1651 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us);
1652 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us);
1653 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo);
1654 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi);
1655 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks);
1656 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks);
1657 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer);
1658
1659 spin_unlock_bh(&ar->data_lock);
1660 exit:
1661 rcu_read_unlock();
1662 }
1663
ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base * ab,struct sk_buff * skb)1664 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
1665 struct sk_buff *skb)
1666 {
1667 struct ath12k_dp *dp = &ab->dp;
1668 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1669 enum htt_t2h_msg_type type;
1670 u16 peer_id;
1671 u8 vdev_id;
1672 u8 mac_addr[ETH_ALEN];
1673 u16 peer_mac_h16;
1674 u16 ast_hash = 0;
1675 u16 hw_peer_id;
1676
1677 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE);
1678
1679 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1680
1681 switch (type) {
1682 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1683 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version,
1684 HTT_T2H_VERSION_CONF_MAJOR);
1685 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version,
1686 HTT_T2H_VERSION_CONF_MINOR);
1687 complete(&dp->htt_tgt_version_received);
1688 break;
1689 /* TODO: remove unused peer map versions after testing */
1690 case HTT_T2H_MSG_TYPE_PEER_MAP:
1691 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1692 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1693 peer_id = le32_get_bits(resp->peer_map_ev.info,
1694 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1695 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1696 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1697 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1698 peer_mac_h16, mac_addr);
1699 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1700 break;
1701 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1702 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1703 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1704 peer_id = le32_get_bits(resp->peer_map_ev.info,
1705 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1706 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1707 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1708 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1709 peer_mac_h16, mac_addr);
1710 ast_hash = le32_get_bits(resp->peer_map_ev.info2,
1711 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL);
1712 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1,
1713 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID);
1714 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1715 hw_peer_id);
1716 break;
1717 case HTT_T2H_MSG_TYPE_PEER_MAP3:
1718 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1719 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1720 peer_id = le32_get_bits(resp->peer_map_ev.info,
1721 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1722 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1723 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1724 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1725 peer_mac_h16, mac_addr);
1726 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1727 peer_id);
1728 break;
1729 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1730 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1731 peer_id = le32_get_bits(resp->peer_unmap_ev.info,
1732 HTT_T2H_PEER_UNMAP_INFO_PEER_ID);
1733 ath12k_peer_unmap_event(ab, peer_id);
1734 break;
1735 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1736 ath12k_htt_pull_ppdu_stats(ab, skb);
1737 break;
1738 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1739 ath12k_debugfs_htt_ext_stats_handler(ab, skb);
1740 break;
1741 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND:
1742 ath12k_htt_mlo_offset_event_handler(ab, skb);
1743 break;
1744 default:
1745 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n",
1746 type);
1747 break;
1748 }
1749
1750 dev_kfree_skb_any(skb);
1751 }
1752
ath12k_dp_rx_msdu_coalesce(struct ath12k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1753 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar,
1754 struct sk_buff_head *msdu_list,
1755 struct sk_buff *first, struct sk_buff *last,
1756 u8 l3pad_bytes, int msdu_len)
1757 {
1758 struct ath12k_base *ab = ar->ab;
1759 struct sk_buff *skb;
1760 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1761 int buf_first_hdr_len, buf_first_len;
1762 struct hal_rx_desc *ldesc;
1763 int space_extra, rem_len, buf_len;
1764 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
1765 bool is_continuation;
1766
1767 /* As the msdu is spread across multiple rx buffers,
1768 * find the offset to the start of msdu for computing
1769 * the length of the msdu in the first buffer.
1770 */
1771 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1772 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1773
1774 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1775 skb_put(first, buf_first_hdr_len + msdu_len);
1776 skb_pull(first, buf_first_hdr_len);
1777 return 0;
1778 }
1779
1780 ldesc = (struct hal_rx_desc *)last->data;
1781 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc);
1782 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc);
1783
1784 /* MSDU spans over multiple buffers because the length of the MSDU
1785 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1786 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1787 */
1788 skb_put(first, DP_RX_BUFFER_SIZE);
1789 skb_pull(first, buf_first_hdr_len);
1790
1791 /* When an MSDU spread over multiple buffers MSDU_END
1792 * tlvs are valid only in the last buffer. Copy those tlvs.
1793 */
1794 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1795
1796 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1797 if (space_extra > 0 &&
1798 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1799 /* Free up all buffers of the MSDU */
1800 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1801 rxcb = ATH12K_SKB_RXCB(skb);
1802 if (!rxcb->is_continuation) {
1803 dev_kfree_skb_any(skb);
1804 break;
1805 }
1806 dev_kfree_skb_any(skb);
1807 }
1808 return -ENOMEM;
1809 }
1810
1811 rem_len = msdu_len - buf_first_len;
1812 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1813 rxcb = ATH12K_SKB_RXCB(skb);
1814 is_continuation = rxcb->is_continuation;
1815 if (is_continuation)
1816 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1817 else
1818 buf_len = rem_len;
1819
1820 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1821 WARN_ON_ONCE(1);
1822 dev_kfree_skb_any(skb);
1823 return -EINVAL;
1824 }
1825
1826 skb_put(skb, buf_len + hal_rx_desc_sz);
1827 skb_pull(skb, hal_rx_desc_sz);
1828 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1829 buf_len);
1830 dev_kfree_skb_any(skb);
1831
1832 rem_len -= buf_len;
1833 if (!is_continuation)
1834 break;
1835 }
1836
1837 return 0;
1838 }
1839
ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1840 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1841 struct sk_buff *first)
1842 {
1843 struct sk_buff *skb;
1844 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1845
1846 if (!rxcb->is_continuation)
1847 return first;
1848
1849 skb_queue_walk(msdu_list, skb) {
1850 rxcb = ATH12K_SKB_RXCB(skb);
1851 if (!rxcb->is_continuation)
1852 return skb;
1853 }
1854
1855 return NULL;
1856 }
1857
ath12k_dp_rx_h_csum_offload(struct ath12k * ar,struct sk_buff * msdu)1858 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu)
1859 {
1860 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1861 struct ath12k_base *ab = ar->ab;
1862 bool ip_csum_fail, l4_csum_fail;
1863
1864 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc);
1865 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc);
1866
1867 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1868 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1869 }
1870
ath12k_dp_rx_crypto_mic_len(struct ath12k * ar,enum hal_encrypt_type enctype)1871 int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, enum hal_encrypt_type enctype)
1872 {
1873 switch (enctype) {
1874 case HAL_ENCRYPT_TYPE_OPEN:
1875 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1876 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1877 return 0;
1878 case HAL_ENCRYPT_TYPE_CCMP_128:
1879 return IEEE80211_CCMP_MIC_LEN;
1880 case HAL_ENCRYPT_TYPE_CCMP_256:
1881 return IEEE80211_CCMP_256_MIC_LEN;
1882 case HAL_ENCRYPT_TYPE_GCMP_128:
1883 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1884 return IEEE80211_GCMP_MIC_LEN;
1885 case HAL_ENCRYPT_TYPE_WEP_40:
1886 case HAL_ENCRYPT_TYPE_WEP_104:
1887 case HAL_ENCRYPT_TYPE_WEP_128:
1888 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1889 case HAL_ENCRYPT_TYPE_WAPI:
1890 break;
1891 }
1892
1893 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1894 return 0;
1895 }
1896
ath12k_dp_rx_crypto_param_len(struct ath12k * ar,enum hal_encrypt_type enctype)1897 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar,
1898 enum hal_encrypt_type enctype)
1899 {
1900 switch (enctype) {
1901 case HAL_ENCRYPT_TYPE_OPEN:
1902 return 0;
1903 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1904 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1905 return IEEE80211_TKIP_IV_LEN;
1906 case HAL_ENCRYPT_TYPE_CCMP_128:
1907 return IEEE80211_CCMP_HDR_LEN;
1908 case HAL_ENCRYPT_TYPE_CCMP_256:
1909 return IEEE80211_CCMP_256_HDR_LEN;
1910 case HAL_ENCRYPT_TYPE_GCMP_128:
1911 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1912 return IEEE80211_GCMP_HDR_LEN;
1913 case HAL_ENCRYPT_TYPE_WEP_40:
1914 case HAL_ENCRYPT_TYPE_WEP_104:
1915 case HAL_ENCRYPT_TYPE_WEP_128:
1916 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1917 case HAL_ENCRYPT_TYPE_WAPI:
1918 break;
1919 }
1920
1921 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1922 return 0;
1923 }
1924
ath12k_dp_rx_crypto_icv_len(struct ath12k * ar,enum hal_encrypt_type enctype)1925 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar,
1926 enum hal_encrypt_type enctype)
1927 {
1928 switch (enctype) {
1929 case HAL_ENCRYPT_TYPE_OPEN:
1930 case HAL_ENCRYPT_TYPE_CCMP_128:
1931 case HAL_ENCRYPT_TYPE_CCMP_256:
1932 case HAL_ENCRYPT_TYPE_GCMP_128:
1933 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1934 return 0;
1935 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1936 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1937 return IEEE80211_TKIP_ICV_LEN;
1938 case HAL_ENCRYPT_TYPE_WEP_40:
1939 case HAL_ENCRYPT_TYPE_WEP_104:
1940 case HAL_ENCRYPT_TYPE_WEP_128:
1941 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1942 case HAL_ENCRYPT_TYPE_WAPI:
1943 break;
1944 }
1945
1946 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1947 return 0;
1948 }
1949
ath12k_dp_rx_h_undecap_nwifi(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1950 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar,
1951 struct sk_buff *msdu,
1952 enum hal_encrypt_type enctype,
1953 struct ieee80211_rx_status *status)
1954 {
1955 struct ath12k_base *ab = ar->ab;
1956 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1957 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1958 struct ieee80211_hdr *hdr;
1959 size_t hdr_len;
1960 u8 *crypto_hdr;
1961 u16 qos_ctl;
1962
1963 /* pull decapped header */
1964 hdr = (struct ieee80211_hdr *)msdu->data;
1965 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1966 skb_pull(msdu, hdr_len);
1967
1968 /* Rebuild qos header */
1969 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1970
1971 /* Reset the order bit as the HT_Control header is stripped */
1972 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1973
1974 qos_ctl = rxcb->tid;
1975
1976 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc))
1977 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1978
1979 /* TODO: Add other QoS ctl fields when required */
1980
1981 /* copy decap header before overwriting for reuse below */
1982 memcpy(decap_hdr, hdr, hdr_len);
1983
1984 /* Rebuild crypto header for mac80211 use */
1985 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
1986 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype));
1987 ath12k_dp_rx_desc_get_crypto_header(ar->ab,
1988 rxcb->rx_desc, crypto_hdr,
1989 enctype);
1990 }
1991
1992 memcpy(skb_push(msdu,
1993 IEEE80211_QOS_CTL_LEN), &qos_ctl,
1994 IEEE80211_QOS_CTL_LEN);
1995 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
1996 }
1997
ath12k_dp_rx_h_undecap_raw(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)1998 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu,
1999 enum hal_encrypt_type enctype,
2000 struct ieee80211_rx_status *status,
2001 bool decrypted)
2002 {
2003 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2004 struct ieee80211_hdr *hdr;
2005 size_t hdr_len;
2006 size_t crypto_len;
2007
2008 if (!rxcb->is_first_msdu ||
2009 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2010 WARN_ON_ONCE(1);
2011 return;
2012 }
2013
2014 skb_trim(msdu, msdu->len - FCS_LEN);
2015
2016 if (!decrypted)
2017 return;
2018
2019 hdr = (void *)msdu->data;
2020
2021 /* Tail */
2022 if (status->flag & RX_FLAG_IV_STRIPPED) {
2023 skb_trim(msdu, msdu->len -
2024 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2025
2026 skb_trim(msdu, msdu->len -
2027 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2028 } else {
2029 /* MIC */
2030 if (status->flag & RX_FLAG_MIC_STRIPPED)
2031 skb_trim(msdu, msdu->len -
2032 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2033
2034 /* ICV */
2035 if (status->flag & RX_FLAG_ICV_STRIPPED)
2036 skb_trim(msdu, msdu->len -
2037 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2038 }
2039
2040 /* MMIC */
2041 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2042 !ieee80211_has_morefrags(hdr->frame_control) &&
2043 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2044 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2045
2046 /* Head */
2047 if (status->flag & RX_FLAG_IV_STRIPPED) {
2048 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2049 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2050
2051 memmove(msdu->data + crypto_len, msdu->data, hdr_len);
2052 skb_pull(msdu, crypto_len);
2053 }
2054 }
2055
ath12k_get_dot11_hdr_from_rx_desc(struct ath12k * ar,struct sk_buff * msdu,struct ath12k_skb_rxcb * rxcb,struct ieee80211_rx_status * status,enum hal_encrypt_type enctype)2056 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar,
2057 struct sk_buff *msdu,
2058 struct ath12k_skb_rxcb *rxcb,
2059 struct ieee80211_rx_status *status,
2060 enum hal_encrypt_type enctype)
2061 {
2062 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2063 struct ath12k_base *ab = ar->ab;
2064 size_t hdr_len, crypto_len;
2065 struct ieee80211_hdr hdr;
2066 __le16 qos_ctl;
2067 u8 *crypto_hdr, mesh_ctrl;
2068
2069 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, &hdr);
2070 hdr_len = ieee80211_hdrlen(hdr.frame_control);
2071 mesh_ctrl = ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc);
2072
2073 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2074 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2075 crypto_hdr = skb_push(msdu, crypto_len);
2076 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype);
2077 }
2078
2079 skb_push(msdu, hdr_len);
2080 memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr)));
2081
2082 if (rxcb->is_mcbc)
2083 status->flag &= ~RX_FLAG_PN_VALIDATED;
2084
2085 /* Add QOS header */
2086 if (ieee80211_is_data_qos(hdr.frame_control)) {
2087 struct ieee80211_hdr *qos_ptr = (struct ieee80211_hdr *)msdu->data;
2088
2089 qos_ctl = cpu_to_le16(rxcb->tid & IEEE80211_QOS_CTL_TID_MASK);
2090 if (mesh_ctrl)
2091 qos_ctl |= cpu_to_le16(IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT);
2092
2093 memcpy(ieee80211_get_qos_ctl(qos_ptr), &qos_ctl, IEEE80211_QOS_CTL_LEN);
2094 }
2095 }
2096
ath12k_dp_rx_h_undecap_eth(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2097 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar,
2098 struct sk_buff *msdu,
2099 enum hal_encrypt_type enctype,
2100 struct ieee80211_rx_status *status)
2101 {
2102 struct ieee80211_hdr *hdr;
2103 struct ethhdr *eth;
2104 u8 da[ETH_ALEN];
2105 u8 sa[ETH_ALEN];
2106 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2107 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}};
2108
2109 eth = (struct ethhdr *)msdu->data;
2110 ether_addr_copy(da, eth->h_dest);
2111 ether_addr_copy(sa, eth->h_source);
2112 rfc.snap_type = eth->h_proto;
2113 skb_pull(msdu, sizeof(*eth));
2114 memcpy(skb_push(msdu, sizeof(rfc)), &rfc,
2115 sizeof(rfc));
2116 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype);
2117
2118 /* original 802.11 header has a different DA and in
2119 * case of 4addr it may also have different SA
2120 */
2121 hdr = (struct ieee80211_hdr *)msdu->data;
2122 ether_addr_copy(ieee80211_get_DA(hdr), da);
2123 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2124 }
2125
ath12k_dp_rx_h_undecap(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2126 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu,
2127 struct hal_rx_desc *rx_desc,
2128 enum hal_encrypt_type enctype,
2129 struct ieee80211_rx_status *status,
2130 bool decrypted)
2131 {
2132 struct ath12k_base *ab = ar->ab;
2133 u8 decap;
2134 struct ethhdr *ehdr;
2135
2136 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2137
2138 switch (decap) {
2139 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2140 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status);
2141 break;
2142 case DP_RX_DECAP_TYPE_RAW:
2143 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2144 decrypted);
2145 break;
2146 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2147 ehdr = (struct ethhdr *)msdu->data;
2148
2149 /* mac80211 allows fast path only for authorized STA */
2150 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2151 ATH12K_SKB_RXCB(msdu)->is_eapol = true;
2152 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2153 break;
2154 }
2155
2156 /* PN for mcast packets will be validated in mac80211;
2157 * remove eth header and add 802.11 header.
2158 */
2159 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2160 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2161 break;
2162 case DP_RX_DECAP_TYPE_8023:
2163 /* TODO: Handle undecap for these formats */
2164 break;
2165 }
2166 }
2167
2168 struct ath12k_peer *
ath12k_dp_rx_h_find_peer(struct ath12k_base * ab,struct sk_buff * msdu)2169 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu)
2170 {
2171 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2172 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2173 struct ath12k_peer *peer = NULL;
2174
2175 lockdep_assert_held(&ab->base_lock);
2176
2177 if (rxcb->peer_id)
2178 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id);
2179
2180 if (peer)
2181 return peer;
2182
2183 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2184 return NULL;
2185
2186 peer = ath12k_peer_find_by_addr(ab,
2187 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab,
2188 rx_desc));
2189 return peer;
2190 }
2191
ath12k_dp_rx_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2192 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar,
2193 struct sk_buff *msdu,
2194 struct hal_rx_desc *rx_desc,
2195 struct ieee80211_rx_status *rx_status)
2196 {
2197 bool fill_crypto_hdr;
2198 struct ath12k_base *ab = ar->ab;
2199 struct ath12k_skb_rxcb *rxcb;
2200 enum hal_encrypt_type enctype;
2201 bool is_decrypted = false;
2202 struct ieee80211_hdr *hdr;
2203 struct ath12k_peer *peer;
2204 u32 err_bitmap;
2205
2206 /* PN for multicast packets will be checked in mac80211 */
2207 rxcb = ATH12K_SKB_RXCB(msdu);
2208 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc);
2209 rxcb->is_mcbc = fill_crypto_hdr;
2210
2211 if (rxcb->is_mcbc)
2212 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc);
2213
2214 spin_lock_bh(&ar->ab->base_lock);
2215 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
2216 if (peer) {
2217 if (rxcb->is_mcbc)
2218 enctype = peer->sec_type_grp;
2219 else
2220 enctype = peer->sec_type;
2221 } else {
2222 enctype = HAL_ENCRYPT_TYPE_OPEN;
2223 }
2224 spin_unlock_bh(&ar->ab->base_lock);
2225
2226 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
2227 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2228 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc);
2229
2230 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2231 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2232 RX_FLAG_MMIC_ERROR |
2233 RX_FLAG_DECRYPTED |
2234 RX_FLAG_IV_STRIPPED |
2235 RX_FLAG_MMIC_STRIPPED);
2236
2237 if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
2238 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2239 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC)
2240 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2241
2242 if (is_decrypted) {
2243 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2244
2245 if (fill_crypto_hdr)
2246 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2247 RX_FLAG_ICV_STRIPPED;
2248 else
2249 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2250 RX_FLAG_PN_VALIDATED;
2251 }
2252
2253 ath12k_dp_rx_h_csum_offload(ar, msdu);
2254 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
2255 enctype, rx_status, is_decrypted);
2256
2257 if (!is_decrypted || fill_crypto_hdr)
2258 return;
2259
2260 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) !=
2261 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2262 hdr = (void *)msdu->data;
2263 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2264 }
2265 }
2266
ath12k_dp_rx_h_rate(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2267 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2268 struct ieee80211_rx_status *rx_status)
2269 {
2270 struct ath12k_base *ab = ar->ab;
2271 struct ieee80211_supported_band *sband;
2272 enum rx_msdu_start_pkt_type pkt_type;
2273 u8 bw;
2274 u8 rate_mcs, nss;
2275 u8 sgi;
2276 bool is_cck;
2277
2278 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc);
2279 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc);
2280 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc);
2281 nss = ath12k_dp_rx_h_nss(ab, rx_desc);
2282 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc);
2283
2284 switch (pkt_type) {
2285 case RX_MSDU_START_PKT_TYPE_11A:
2286 case RX_MSDU_START_PKT_TYPE_11B:
2287 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2288 sband = &ar->mac.sbands[rx_status->band];
2289 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs,
2290 is_cck);
2291 break;
2292 case RX_MSDU_START_PKT_TYPE_11N:
2293 rx_status->encoding = RX_ENC_HT;
2294 if (rate_mcs > ATH12K_HT_MCS_MAX) {
2295 ath12k_warn(ar->ab,
2296 "Received with invalid mcs in HT mode %d\n",
2297 rate_mcs);
2298 break;
2299 }
2300 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2301 if (sgi)
2302 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2303 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2304 break;
2305 case RX_MSDU_START_PKT_TYPE_11AC:
2306 rx_status->encoding = RX_ENC_VHT;
2307 rx_status->rate_idx = rate_mcs;
2308 if (rate_mcs > ATH12K_VHT_MCS_MAX) {
2309 ath12k_warn(ar->ab,
2310 "Received with invalid mcs in VHT mode %d\n",
2311 rate_mcs);
2312 break;
2313 }
2314 rx_status->nss = nss;
2315 if (sgi)
2316 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2317 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2318 break;
2319 case RX_MSDU_START_PKT_TYPE_11AX:
2320 rx_status->rate_idx = rate_mcs;
2321 if (rate_mcs > ATH12K_HE_MCS_MAX) {
2322 ath12k_warn(ar->ab,
2323 "Received with invalid mcs in HE mode %d\n",
2324 rate_mcs);
2325 break;
2326 }
2327 rx_status->encoding = RX_ENC_HE;
2328 rx_status->nss = nss;
2329 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
2330 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2331 break;
2332 }
2333 }
2334
ath12k_dp_rx_h_ppdu(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2335 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2336 struct ieee80211_rx_status *rx_status)
2337 {
2338 struct ath12k_base *ab = ar->ab;
2339 u8 channel_num;
2340 u32 center_freq, meta_data;
2341 struct ieee80211_channel *channel;
2342
2343 rx_status->freq = 0;
2344 rx_status->rate_idx = 0;
2345 rx_status->nss = 0;
2346 rx_status->encoding = RX_ENC_LEGACY;
2347 rx_status->bw = RATE_INFO_BW_20;
2348 rx_status->enc_flags = 0;
2349
2350 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2351
2352 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc);
2353 channel_num = meta_data;
2354 center_freq = meta_data >> 16;
2355
2356 if (center_freq >= ATH12K_MIN_6G_FREQ &&
2357 center_freq <= ATH12K_MAX_6G_FREQ) {
2358 rx_status->band = NL80211_BAND_6GHZ;
2359 rx_status->freq = center_freq;
2360 } else if (channel_num >= 1 && channel_num <= 14) {
2361 rx_status->band = NL80211_BAND_2GHZ;
2362 } else if (channel_num >= 36 && channel_num <= 173) {
2363 rx_status->band = NL80211_BAND_5GHZ;
2364 } else {
2365 spin_lock_bh(&ar->data_lock);
2366 channel = ar->rx_channel;
2367 if (channel) {
2368 rx_status->band = channel->band;
2369 channel_num =
2370 ieee80211_frequency_to_channel(channel->center_freq);
2371 }
2372 spin_unlock_bh(&ar->data_lock);
2373 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ",
2374 rx_desc, sizeof(*rx_desc));
2375 }
2376
2377 if (rx_status->band != NL80211_BAND_6GHZ)
2378 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2379 rx_status->band);
2380
2381 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status);
2382 }
2383
ath12k_dp_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2384 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
2385 struct sk_buff *msdu,
2386 struct ieee80211_rx_status *status)
2387 {
2388 struct ath12k_base *ab = ar->ab;
2389 static const struct ieee80211_radiotap_he known = {
2390 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2391 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2392 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2393 };
2394 struct ieee80211_radiotap_he *he;
2395 struct ieee80211_rx_status *rx_status;
2396 struct ieee80211_sta *pubsta;
2397 struct ath12k_peer *peer;
2398 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2399 u8 decap = DP_RX_DECAP_TYPE_RAW;
2400 bool is_mcbc = rxcb->is_mcbc;
2401 bool is_eapol = rxcb->is_eapol;
2402
2403 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2404 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2405 he = skb_push(msdu, sizeof(known));
2406 memcpy(he, &known, sizeof(known));
2407 status->flag |= RX_FLAG_RADIOTAP_HE;
2408 }
2409
2410 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2411 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc);
2412
2413 spin_lock_bh(&ab->base_lock);
2414 peer = ath12k_dp_rx_h_find_peer(ab, msdu);
2415
2416 pubsta = peer ? peer->sta : NULL;
2417
2418 spin_unlock_bh(&ab->base_lock);
2419
2420 ath12k_dbg(ab, ATH12K_DBG_DATA,
2421 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2422 msdu,
2423 msdu->len,
2424 peer ? peer->addr : NULL,
2425 rxcb->tid,
2426 is_mcbc ? "mcast" : "ucast",
2427 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc),
2428 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2429 (status->encoding == RX_ENC_HT) ? "ht" : "",
2430 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2431 (status->encoding == RX_ENC_HE) ? "he" : "",
2432 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2433 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2434 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2435 (status->bw == RATE_INFO_BW_320) ? "320" : "",
2436 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2437 status->rate_idx,
2438 status->nss,
2439 status->freq,
2440 status->band, status->flag,
2441 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2442 !!(status->flag & RX_FLAG_MMIC_ERROR),
2443 !!(status->flag & RX_FLAG_AMSDU_MORE));
2444
2445 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
2446 msdu->data, msdu->len);
2447
2448 rx_status = IEEE80211_SKB_RXCB(msdu);
2449 *rx_status = *status;
2450
2451 /* TODO: trace rx packet */
2452
2453 /* PN for multicast packets are not validate in HW,
2454 * so skip 802.3 rx path
2455 * Also, fast_rx expects the STA to be authorized, hence
2456 * eapol packets are sent in slow path.
2457 */
2458 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2459 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2460 rx_status->flag |= RX_FLAG_8023;
2461
2462 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
2463 }
2464
ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base * ab,struct hal_rx_desc * rx_desc,struct sk_buff * msdu)2465 static bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base *ab,
2466 struct hal_rx_desc *rx_desc,
2467 struct sk_buff *msdu)
2468 {
2469 struct ieee80211_hdr *hdr;
2470 u8 decap_type;
2471 u32 hdr_len;
2472
2473 decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2474 if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI)
2475 return true;
2476
2477 hdr = (struct ieee80211_hdr *)msdu->data;
2478 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2479
2480 if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN)))
2481 return true;
2482
2483 ab->soc_stats.invalid_rbm++;
2484 WARN_ON_ONCE(1);
2485 return false;
2486 }
2487
ath12k_dp_rx_process_msdu(struct ath12k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2488 static int ath12k_dp_rx_process_msdu(struct ath12k *ar,
2489 struct sk_buff *msdu,
2490 struct sk_buff_head *msdu_list,
2491 struct ieee80211_rx_status *rx_status)
2492 {
2493 struct ath12k_base *ab = ar->ab;
2494 struct hal_rx_desc *rx_desc, *lrx_desc;
2495 struct ath12k_skb_rxcb *rxcb;
2496 struct sk_buff *last_buf;
2497 u8 l3_pad_bytes;
2498 u16 msdu_len;
2499 int ret;
2500 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2501
2502 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2503 if (!last_buf) {
2504 ath12k_warn(ab,
2505 "No valid Rx buffer to access MSDU_END tlv\n");
2506 ret = -EIO;
2507 goto free_out;
2508 }
2509
2510 rx_desc = (struct hal_rx_desc *)msdu->data;
2511 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2512 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) {
2513 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n");
2514 ret = -EIO;
2515 goto free_out;
2516 }
2517
2518 rxcb = ATH12K_SKB_RXCB(msdu);
2519 rxcb->rx_desc = rx_desc;
2520 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc);
2521 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc);
2522
2523 if (rxcb->is_frag) {
2524 skb_pull(msdu, hal_rx_desc_sz);
2525 } else if (!rxcb->is_continuation) {
2526 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2527 ret = -EINVAL;
2528 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len);
2529 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
2530 sizeof(*rx_desc));
2531 goto free_out;
2532 }
2533 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2534 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2535 } else {
2536 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list,
2537 msdu, last_buf,
2538 l3_pad_bytes, msdu_len);
2539 if (ret) {
2540 ath12k_warn(ab,
2541 "failed to coalesce msdu rx buffer%d\n", ret);
2542 goto free_out;
2543 }
2544 }
2545
2546 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) {
2547 ret = -EINVAL;
2548 goto free_out;
2549 }
2550
2551 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2552 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2553
2554 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2555
2556 return 0;
2557
2558 free_out:
2559 return ret;
2560 }
2561
ath12k_dp_rx_process_received_packets(struct ath12k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int ring_id)2562 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab,
2563 struct napi_struct *napi,
2564 struct sk_buff_head *msdu_list,
2565 int ring_id)
2566 {
2567 struct ieee80211_rx_status rx_status = {0};
2568 struct ath12k_skb_rxcb *rxcb;
2569 struct sk_buff *msdu;
2570 struct ath12k *ar;
2571 u8 mac_id, pdev_id;
2572 int ret;
2573
2574 if (skb_queue_empty(msdu_list))
2575 return;
2576
2577 rcu_read_lock();
2578
2579 while ((msdu = __skb_dequeue(msdu_list))) {
2580 rxcb = ATH12K_SKB_RXCB(msdu);
2581 mac_id = rxcb->mac_id;
2582 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
2583 ar = ab->pdevs[pdev_id].ar;
2584 if (!rcu_dereference(ab->pdevs_active[pdev_id])) {
2585 dev_kfree_skb_any(msdu);
2586 continue;
2587 }
2588
2589 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
2590 dev_kfree_skb_any(msdu);
2591 continue;
2592 }
2593
2594 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2595 if (ret) {
2596 ath12k_dbg(ab, ATH12K_DBG_DATA,
2597 "Unable to process msdu %d", ret);
2598 dev_kfree_skb_any(msdu);
2599 continue;
2600 }
2601
2602 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2603 }
2604
2605 rcu_read_unlock();
2606 }
2607
ath12k_dp_rx_get_peer_id(struct ath12k_base * ab,enum ath12k_peer_metadata_version ver,__le32 peer_metadata)2608 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab,
2609 enum ath12k_peer_metadata_version ver,
2610 __le32 peer_metadata)
2611 {
2612 switch (ver) {
2613 default:
2614 ath12k_warn(ab, "Unknown peer metadata version: %d", ver);
2615 fallthrough;
2616 case ATH12K_PEER_METADATA_V0:
2617 return le32_get_bits(peer_metadata,
2618 RX_MPDU_DESC_META_DATA_V0_PEER_ID);
2619 case ATH12K_PEER_METADATA_V1:
2620 return le32_get_bits(peer_metadata,
2621 RX_MPDU_DESC_META_DATA_V1_PEER_ID);
2622 case ATH12K_PEER_METADATA_V1A:
2623 return le32_get_bits(peer_metadata,
2624 RX_MPDU_DESC_META_DATA_V1A_PEER_ID);
2625 case ATH12K_PEER_METADATA_V1B:
2626 return le32_get_bits(peer_metadata,
2627 RX_MPDU_DESC_META_DATA_V1B_PEER_ID);
2628 }
2629 }
2630
ath12k_dp_rx_process(struct ath12k_base * ab,int ring_id,struct napi_struct * napi,int budget)2631 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id,
2632 struct napi_struct *napi, int budget)
2633 {
2634 LIST_HEAD(rx_desc_used_list);
2635 struct ath12k_rx_desc_info *desc_info;
2636 struct ath12k_dp *dp = &ab->dp;
2637 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
2638 struct hal_reo_dest_ring *desc;
2639 int num_buffs_reaped = 0;
2640 struct sk_buff_head msdu_list;
2641 struct ath12k_skb_rxcb *rxcb;
2642 int total_msdu_reaped = 0;
2643 struct hal_srng *srng;
2644 struct sk_buff *msdu;
2645 bool done = false;
2646 int mac_id;
2647 u64 desc_va;
2648
2649 __skb_queue_head_init(&msdu_list);
2650
2651 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2652
2653 spin_lock_bh(&srng->lock);
2654
2655 try_again:
2656 ath12k_hal_srng_access_begin(ab, srng);
2657
2658 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
2659 struct rx_mpdu_desc *mpdu_info;
2660 struct rx_msdu_desc *msdu_info;
2661 enum hal_reo_dest_ring_push_reason push_reason;
2662 u32 cookie;
2663
2664 cookie = le32_get_bits(desc->buf_addr_info.info1,
2665 BUFFER_ADDR_INFO1_SW_COOKIE);
2666
2667 mac_id = le32_get_bits(desc->info0,
2668 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
2669
2670 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
2671 le32_to_cpu(desc->buf_va_lo));
2672 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
2673
2674 /* retry manual desc retrieval */
2675 if (!desc_info) {
2676 desc_info = ath12k_dp_get_rx_desc(ab, cookie);
2677 if (!desc_info) {
2678 ath12k_warn(ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n",
2679 cookie);
2680 continue;
2681 }
2682 }
2683
2684 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
2685 ath12k_warn(ab, "Check HW CC implementation");
2686
2687 msdu = desc_info->skb;
2688 desc_info->skb = NULL;
2689
2690 list_add_tail(&desc_info->list, &rx_desc_used_list);
2691
2692 rxcb = ATH12K_SKB_RXCB(msdu);
2693 dma_unmap_single(ab->dev, rxcb->paddr,
2694 msdu->len + skb_tailroom(msdu),
2695 DMA_FROM_DEVICE);
2696
2697 num_buffs_reaped++;
2698
2699 push_reason = le32_get_bits(desc->info0,
2700 HAL_REO_DEST_RING_INFO0_PUSH_REASON);
2701 if (push_reason !=
2702 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2703 dev_kfree_skb_any(msdu);
2704 ab->soc_stats.hal_reo_error[ring_id]++;
2705 continue;
2706 }
2707
2708 msdu_info = &desc->rx_msdu_info;
2709 mpdu_info = &desc->rx_mpdu_info;
2710
2711 rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) &
2712 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2713 rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) &
2714 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2715 rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) &
2716 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2717 rxcb->mac_id = mac_id;
2718 rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver,
2719 mpdu_info->peer_meta_data);
2720 rxcb->tid = le32_get_bits(mpdu_info->info0,
2721 RX_MPDU_DESC_INFO0_TID);
2722
2723 __skb_queue_tail(&msdu_list, msdu);
2724
2725 if (!rxcb->is_continuation) {
2726 total_msdu_reaped++;
2727 done = true;
2728 } else {
2729 done = false;
2730 }
2731
2732 if (total_msdu_reaped >= budget)
2733 break;
2734 }
2735
2736 /* Hw might have updated the head pointer after we cached it.
2737 * In this case, even though there are entries in the ring we'll
2738 * get rx_desc NULL. Give the read another try with updated cached
2739 * head pointer so that we can reap complete MPDU in the current
2740 * rx processing.
2741 */
2742 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) {
2743 ath12k_hal_srng_access_end(ab, srng);
2744 goto try_again;
2745 }
2746
2747 ath12k_hal_srng_access_end(ab, srng);
2748
2749 spin_unlock_bh(&srng->lock);
2750
2751 if (!total_msdu_reaped)
2752 goto exit;
2753
2754 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
2755 num_buffs_reaped);
2756
2757 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2758 ring_id);
2759
2760 exit:
2761 return total_msdu_reaped;
2762 }
2763
ath12k_dp_rx_frag_timer(struct timer_list * timer)2764 static void ath12k_dp_rx_frag_timer(struct timer_list *timer)
2765 {
2766 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2767
2768 spin_lock_bh(&rx_tid->ab->base_lock);
2769 if (rx_tid->last_frag_no &&
2770 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
2771 spin_unlock_bh(&rx_tid->ab->base_lock);
2772 return;
2773 }
2774 ath12k_dp_rx_frags_cleanup(rx_tid, true);
2775 spin_unlock_bh(&rx_tid->ab->base_lock);
2776 }
2777
ath12k_dp_rx_peer_frag_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id)2778 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id)
2779 {
2780 struct ath12k_base *ab = ar->ab;
2781 struct crypto_shash *tfm;
2782 struct ath12k_peer *peer;
2783 struct ath12k_dp_rx_tid *rx_tid;
2784 int i;
2785
2786 tfm = crypto_alloc_shash("michael_mic", 0, 0);
2787 if (IS_ERR(tfm))
2788 return PTR_ERR(tfm);
2789
2790 spin_lock_bh(&ab->base_lock);
2791
2792 peer = ath12k_peer_find(ab, vdev_id, peer_mac);
2793 if (!peer) {
2794 spin_unlock_bh(&ab->base_lock);
2795 crypto_free_shash(tfm);
2796 ath12k_warn(ab, "failed to find the peer to set up fragment info\n");
2797 return -ENOENT;
2798 }
2799
2800 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
2801 rx_tid = &peer->rx_tid[i];
2802 rx_tid->ab = ab;
2803 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0);
2804 skb_queue_head_init(&rx_tid->rx_frags);
2805 }
2806
2807 peer->tfm_mmic = tfm;
2808 peer->dp_setup_done = true;
2809 spin_unlock_bh(&ab->base_lock);
2810
2811 return 0;
2812 }
2813
ath12k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)2814 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
2815 struct ieee80211_hdr *hdr, u8 *data,
2816 size_t data_len, u8 *mic)
2817 {
2818 SHASH_DESC_ON_STACK(desc, tfm);
2819 u8 mic_hdr[16] = {0};
2820 u8 tid = 0;
2821 int ret;
2822
2823 if (!tfm)
2824 return -EINVAL;
2825
2826 desc->tfm = tfm;
2827
2828 ret = crypto_shash_setkey(tfm, key, 8);
2829 if (ret)
2830 goto out;
2831
2832 ret = crypto_shash_init(desc);
2833 if (ret)
2834 goto out;
2835
2836 /* TKIP MIC header */
2837 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
2838 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
2839 if (ieee80211_is_data_qos(hdr->frame_control))
2840 tid = ieee80211_get_tid(hdr);
2841 mic_hdr[12] = tid;
2842
2843 ret = crypto_shash_update(desc, mic_hdr, 16);
2844 if (ret)
2845 goto out;
2846 ret = crypto_shash_update(desc, data, data_len);
2847 if (ret)
2848 goto out;
2849 ret = crypto_shash_final(desc, mic);
2850 out:
2851 shash_desc_zero(desc);
2852 return ret;
2853 }
2854
ath12k_dp_rx_h_verify_tkip_mic(struct ath12k * ar,struct ath12k_peer * peer,struct sk_buff * msdu)2855 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer,
2856 struct sk_buff *msdu)
2857 {
2858 struct ath12k_base *ab = ar->ab;
2859 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
2860 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
2861 struct ieee80211_key_conf *key_conf;
2862 struct ieee80211_hdr *hdr;
2863 u8 mic[IEEE80211_CCMP_MIC_LEN];
2864 int head_len, tail_len, ret;
2865 size_t data_len;
2866 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2867 u8 *key, *data;
2868 u8 key_idx;
2869
2870 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
2871 return 0;
2872
2873 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
2874 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2875 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
2876 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
2877
2878 if (!is_multicast_ether_addr(hdr->addr1))
2879 key_idx = peer->ucast_keyidx;
2880 else
2881 key_idx = peer->mcast_keyidx;
2882
2883 key_conf = peer->keys[key_idx];
2884
2885 data = msdu->data + head_len;
2886 data_len = msdu->len - head_len - tail_len;
2887 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
2888
2889 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
2890 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
2891 goto mic_fail;
2892
2893 return 0;
2894
2895 mic_fail:
2896 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true;
2897 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true;
2898
2899 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
2900 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
2901 skb_pull(msdu, hal_rx_desc_sz);
2902
2903 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu)))
2904 return -EINVAL;
2905
2906 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
2907 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
2908 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
2909 ieee80211_rx(ath12k_ar_to_hw(ar), msdu);
2910 return -EINVAL;
2911 }
2912
ath12k_dp_rx_h_undecap_frag(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)2913 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu,
2914 enum hal_encrypt_type enctype, u32 flags)
2915 {
2916 struct ieee80211_hdr *hdr;
2917 size_t hdr_len;
2918 size_t crypto_len;
2919 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2920
2921 if (!flags)
2922 return;
2923
2924 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
2925
2926 if (flags & RX_FLAG_MIC_STRIPPED)
2927 skb_trim(msdu, msdu->len -
2928 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2929
2930 if (flags & RX_FLAG_ICV_STRIPPED)
2931 skb_trim(msdu, msdu->len -
2932 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2933
2934 if (flags & RX_FLAG_IV_STRIPPED) {
2935 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2936 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2937
2938 memmove(msdu->data + hal_rx_desc_sz + crypto_len,
2939 msdu->data + hal_rx_desc_sz, hdr_len);
2940 skb_pull(msdu, crypto_len);
2941 }
2942 }
2943
ath12k_dp_rx_h_defrag(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)2944 static int ath12k_dp_rx_h_defrag(struct ath12k *ar,
2945 struct ath12k_peer *peer,
2946 struct ath12k_dp_rx_tid *rx_tid,
2947 struct sk_buff **defrag_skb)
2948 {
2949 struct ath12k_base *ab = ar->ab;
2950 struct hal_rx_desc *rx_desc;
2951 struct sk_buff *skb, *first_frag, *last_frag;
2952 struct ieee80211_hdr *hdr;
2953 enum hal_encrypt_type enctype;
2954 bool is_decrypted = false;
2955 int msdu_len = 0;
2956 int extra_space;
2957 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2958
2959 first_frag = skb_peek(&rx_tid->rx_frags);
2960 last_frag = skb_peek_tail(&rx_tid->rx_frags);
2961
2962 skb_queue_walk(&rx_tid->rx_frags, skb) {
2963 flags = 0;
2964 rx_desc = (struct hal_rx_desc *)skb->data;
2965 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
2966
2967 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc);
2968 if (enctype != HAL_ENCRYPT_TYPE_OPEN)
2969 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab,
2970 rx_desc);
2971
2972 if (is_decrypted) {
2973 if (skb != first_frag)
2974 flags |= RX_FLAG_IV_STRIPPED;
2975 if (skb != last_frag)
2976 flags |= RX_FLAG_ICV_STRIPPED |
2977 RX_FLAG_MIC_STRIPPED;
2978 }
2979
2980 /* RX fragments are always raw packets */
2981 if (skb != last_frag)
2982 skb_trim(skb, skb->len - FCS_LEN);
2983 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
2984
2985 if (skb != first_frag)
2986 skb_pull(skb, hal_rx_desc_sz +
2987 ieee80211_hdrlen(hdr->frame_control));
2988 msdu_len += skb->len;
2989 }
2990
2991 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
2992 if (extra_space > 0 &&
2993 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
2994 return -ENOMEM;
2995
2996 __skb_unlink(first_frag, &rx_tid->rx_frags);
2997 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
2998 skb_put_data(first_frag, skb->data, skb->len);
2999 dev_kfree_skb_any(skb);
3000 }
3001
3002 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3003 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3004 ATH12K_SKB_RXCB(first_frag)->is_frag = 1;
3005
3006 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3007 first_frag = NULL;
3008
3009 *defrag_skb = first_frag;
3010 return 0;
3011 }
3012
ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3013 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
3014 struct ath12k_dp_rx_tid *rx_tid,
3015 struct sk_buff *defrag_skb)
3016 {
3017 struct ath12k_base *ab = ar->ab;
3018 struct ath12k_dp *dp = &ab->dp;
3019 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3020 struct hal_reo_entrance_ring *reo_ent_ring;
3021 struct hal_reo_dest_ring *reo_dest_ring;
3022 struct dp_link_desc_bank *link_desc_banks;
3023 struct hal_rx_msdu_link *msdu_link;
3024 struct hal_rx_msdu_details *msdu0;
3025 struct hal_srng *srng;
3026 dma_addr_t link_paddr, buf_paddr;
3027 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info;
3028 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi;
3029 int ret;
3030 struct ath12k_rx_desc_info *desc_info;
3031 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm;
3032 u8 dst_ind;
3033
3034 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3035 link_desc_banks = dp->link_desc_banks;
3036 reo_dest_ring = rx_tid->dst_ring_desc;
3037
3038 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info,
3039 &link_paddr, &cookie);
3040 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK);
3041
3042 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3043 (link_paddr - link_desc_banks[desc_bank].paddr));
3044 msdu0 = &msdu_link->msdu_link[0];
3045 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0);
3046 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND);
3047
3048 memset(msdu0, 0, sizeof(*msdu0));
3049
3050 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) |
3051 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) |
3052 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) |
3053 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz,
3054 RX_MSDU_DESC_INFO0_MSDU_LENGTH) |
3055 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) |
3056 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA);
3057 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info);
3058 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info);
3059
3060 /* change msdu len in hal rx desc */
3061 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3062
3063 buf_paddr = dma_map_single(ab->dev, defrag_skb->data,
3064 defrag_skb->len + skb_tailroom(defrag_skb),
3065 DMA_TO_DEVICE);
3066 if (dma_mapping_error(ab->dev, buf_paddr))
3067 return -ENOMEM;
3068
3069 spin_lock_bh(&dp->rx_desc_lock);
3070 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list,
3071 struct ath12k_rx_desc_info,
3072 list);
3073 if (!desc_info) {
3074 spin_unlock_bh(&dp->rx_desc_lock);
3075 ath12k_warn(ab, "failed to find rx desc for reinject\n");
3076 ret = -ENOMEM;
3077 goto err_unmap_dma;
3078 }
3079
3080 desc_info->skb = defrag_skb;
3081 desc_info->in_use = true;
3082
3083 list_del(&desc_info->list);
3084 spin_unlock_bh(&dp->rx_desc_lock);
3085
3086 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr;
3087
3088 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr,
3089 desc_info->cookie,
3090 HAL_RX_BUF_RBM_SW3_BM);
3091
3092 /* Fill mpdu details into reo entrance ring */
3093 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id];
3094
3095 spin_lock_bh(&srng->lock);
3096 ath12k_hal_srng_access_begin(ab, srng);
3097
3098 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng);
3099 if (!reo_ent_ring) {
3100 ath12k_hal_srng_access_end(ab, srng);
3101 spin_unlock_bh(&srng->lock);
3102 ret = -ENOSPC;
3103 goto err_free_desc;
3104 }
3105 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3106
3107 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr,
3108 cookie,
3109 idle_link_rbm);
3110
3111 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) |
3112 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) |
3113 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) |
3114 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) |
3115 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID);
3116
3117 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info);
3118 reo_ent_ring->rx_mpdu_info.peer_meta_data =
3119 reo_dest_ring->rx_mpdu_info.peer_meta_data;
3120
3121 reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr));
3122 queue_addr_hi = upper_32_bits(rx_tid->paddr);
3123 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi,
3124 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) |
3125 le32_encode_bits(dst_ind,
3126 HAL_REO_ENTR_RING_INFO0_DEST_IND);
3127
3128 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn,
3129 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM);
3130 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0,
3131 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3132 reo_ent_ring->info2 =
3133 cpu_to_le32(u32_get_bits(dest_ring_info0,
3134 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID));
3135
3136 ath12k_hal_srng_access_end(ab, srng);
3137 spin_unlock_bh(&srng->lock);
3138
3139 return 0;
3140
3141 err_free_desc:
3142 spin_lock_bh(&dp->rx_desc_lock);
3143 desc_info->in_use = false;
3144 desc_info->skb = NULL;
3145 list_add_tail(&desc_info->list, &dp->rx_desc_free_list);
3146 spin_unlock_bh(&dp->rx_desc_lock);
3147 err_unmap_dma:
3148 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3149 DMA_TO_DEVICE);
3150 return ret;
3151 }
3152
ath12k_dp_rx_h_cmp_frags(struct ath12k_base * ab,struct sk_buff * a,struct sk_buff * b)3153 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab,
3154 struct sk_buff *a, struct sk_buff *b)
3155 {
3156 int frag1, frag2;
3157
3158 frag1 = ath12k_dp_rx_h_frag_no(ab, a);
3159 frag2 = ath12k_dp_rx_h_frag_no(ab, b);
3160
3161 return frag1 - frag2;
3162 }
3163
ath12k_dp_rx_h_sort_frags(struct ath12k_base * ab,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3164 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab,
3165 struct sk_buff_head *frag_list,
3166 struct sk_buff *cur_frag)
3167 {
3168 struct sk_buff *skb;
3169 int cmp;
3170
3171 skb_queue_walk(frag_list, skb) {
3172 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag);
3173 if (cmp < 0)
3174 continue;
3175 __skb_queue_before(frag_list, skb, cur_frag);
3176 return;
3177 }
3178 __skb_queue_tail(frag_list, cur_frag);
3179 }
3180
ath12k_dp_rx_h_get_pn(struct ath12k * ar,struct sk_buff * skb)3181 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb)
3182 {
3183 struct ieee80211_hdr *hdr;
3184 u64 pn = 0;
3185 u8 *ehdr;
3186 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3187
3188 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3189 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3190
3191 pn = ehdr[0];
3192 pn |= (u64)ehdr[1] << 8;
3193 pn |= (u64)ehdr[4] << 16;
3194 pn |= (u64)ehdr[5] << 24;
3195 pn |= (u64)ehdr[6] << 32;
3196 pn |= (u64)ehdr[7] << 40;
3197
3198 return pn;
3199 }
3200
3201 static bool
ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid)3202 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid)
3203 {
3204 struct ath12k_base *ab = ar->ab;
3205 enum hal_encrypt_type encrypt_type;
3206 struct sk_buff *first_frag, *skb;
3207 struct hal_rx_desc *desc;
3208 u64 last_pn;
3209 u64 cur_pn;
3210
3211 first_frag = skb_peek(&rx_tid->rx_frags);
3212 desc = (struct hal_rx_desc *)first_frag->data;
3213
3214 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc);
3215 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3216 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3217 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3218 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3219 return true;
3220
3221 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag);
3222 skb_queue_walk(&rx_tid->rx_frags, skb) {
3223 if (skb == first_frag)
3224 continue;
3225
3226 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb);
3227 if (cur_pn != last_pn + 1)
3228 return false;
3229 last_pn = cur_pn;
3230 }
3231 return true;
3232 }
3233
ath12k_dp_rx_frag_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_reo_dest_ring * ring_desc)3234 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar,
3235 struct sk_buff *msdu,
3236 struct hal_reo_dest_ring *ring_desc)
3237 {
3238 struct ath12k_base *ab = ar->ab;
3239 struct hal_rx_desc *rx_desc;
3240 struct ath12k_peer *peer;
3241 struct ath12k_dp_rx_tid *rx_tid;
3242 struct sk_buff *defrag_skb = NULL;
3243 u32 peer_id;
3244 u16 seqno, frag_no;
3245 u8 tid;
3246 int ret = 0;
3247 bool more_frags;
3248
3249 rx_desc = (struct hal_rx_desc *)msdu->data;
3250 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc);
3251 tid = ath12k_dp_rx_h_tid(ab, rx_desc);
3252 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc);
3253 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu);
3254 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu);
3255
3256 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) ||
3257 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) ||
3258 tid > IEEE80211_NUM_TIDS)
3259 return -EINVAL;
3260
3261 /* received unfragmented packet in reo
3262 * exception ring, this shouldn't happen
3263 * as these packets typically come from
3264 * reo2sw srngs.
3265 */
3266 if (WARN_ON_ONCE(!frag_no && !more_frags))
3267 return -EINVAL;
3268
3269 spin_lock_bh(&ab->base_lock);
3270 peer = ath12k_peer_find_by_id(ab, peer_id);
3271 if (!peer) {
3272 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3273 peer_id);
3274 ret = -ENOENT;
3275 goto out_unlock;
3276 }
3277
3278 if (!peer->dp_setup_done) {
3279 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3280 peer->addr, peer_id);
3281 ret = -ENOENT;
3282 goto out_unlock;
3283 }
3284
3285 rx_tid = &peer->rx_tid[tid];
3286
3287 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3288 skb_queue_empty(&rx_tid->rx_frags)) {
3289 /* Flush stored fragments and start a new sequence */
3290 ath12k_dp_rx_frags_cleanup(rx_tid, true);
3291 rx_tid->cur_sn = seqno;
3292 }
3293
3294 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3295 /* Fragment already present */
3296 ret = -EINVAL;
3297 goto out_unlock;
3298 }
3299
3300 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap)))
3301 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3302 else
3303 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu);
3304
3305 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3306 if (!more_frags)
3307 rx_tid->last_frag_no = frag_no;
3308
3309 if (frag_no == 0) {
3310 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3311 sizeof(*rx_tid->dst_ring_desc),
3312 GFP_ATOMIC);
3313 if (!rx_tid->dst_ring_desc) {
3314 ret = -ENOMEM;
3315 goto out_unlock;
3316 }
3317 } else {
3318 ath12k_dp_rx_link_desc_return(ab, ring_desc,
3319 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3320 }
3321
3322 if (!rx_tid->last_frag_no ||
3323 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3324 mod_timer(&rx_tid->frag_timer, jiffies +
3325 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS);
3326 goto out_unlock;
3327 }
3328
3329 spin_unlock_bh(&ab->base_lock);
3330 del_timer_sync(&rx_tid->frag_timer);
3331 spin_lock_bh(&ab->base_lock);
3332
3333 peer = ath12k_peer_find_by_id(ab, peer_id);
3334 if (!peer)
3335 goto err_frags_cleanup;
3336
3337 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3338 goto err_frags_cleanup;
3339
3340 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3341 goto err_frags_cleanup;
3342
3343 if (!defrag_skb)
3344 goto err_frags_cleanup;
3345
3346 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3347 goto err_frags_cleanup;
3348
3349 ath12k_dp_rx_frags_cleanup(rx_tid, false);
3350 goto out_unlock;
3351
3352 err_frags_cleanup:
3353 dev_kfree_skb_any(defrag_skb);
3354 ath12k_dp_rx_frags_cleanup(rx_tid, true);
3355 out_unlock:
3356 spin_unlock_bh(&ab->base_lock);
3357 return ret;
3358 }
3359
3360 static int
ath12k_dp_process_rx_err_buf(struct ath12k * ar,struct hal_reo_dest_ring * desc,struct list_head * used_list,bool drop,u32 cookie)3361 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc,
3362 struct list_head *used_list,
3363 bool drop, u32 cookie)
3364 {
3365 struct ath12k_base *ab = ar->ab;
3366 struct sk_buff *msdu;
3367 struct ath12k_skb_rxcb *rxcb;
3368 struct hal_rx_desc *rx_desc;
3369 u16 msdu_len;
3370 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3371 struct ath12k_rx_desc_info *desc_info;
3372 u64 desc_va;
3373
3374 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
3375 le32_to_cpu(desc->buf_va_lo));
3376 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
3377
3378 /* retry manual desc retrieval */
3379 if (!desc_info) {
3380 desc_info = ath12k_dp_get_rx_desc(ab, cookie);
3381 if (!desc_info) {
3382 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n",
3383 cookie);
3384 return -EINVAL;
3385 }
3386 }
3387
3388 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3389 ath12k_warn(ab, " RX Exception, Check HW CC implementation");
3390
3391 msdu = desc_info->skb;
3392 desc_info->skb = NULL;
3393
3394 list_add_tail(&desc_info->list, used_list);
3395
3396 rxcb = ATH12K_SKB_RXCB(msdu);
3397 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3398 msdu->len + skb_tailroom(msdu),
3399 DMA_FROM_DEVICE);
3400
3401 if (drop) {
3402 dev_kfree_skb_any(msdu);
3403 return 0;
3404 }
3405
3406 rcu_read_lock();
3407 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3408 dev_kfree_skb_any(msdu);
3409 goto exit;
3410 }
3411
3412 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
3413 dev_kfree_skb_any(msdu);
3414 goto exit;
3415 }
3416
3417 rx_desc = (struct hal_rx_desc *)msdu->data;
3418 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc);
3419 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3420 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3421 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
3422 sizeof(*rx_desc));
3423 dev_kfree_skb_any(msdu);
3424 goto exit;
3425 }
3426
3427 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3428
3429 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) {
3430 dev_kfree_skb_any(msdu);
3431 ath12k_dp_rx_link_desc_return(ar->ab, desc,
3432 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3433 }
3434 exit:
3435 rcu_read_unlock();
3436 return 0;
3437 }
3438
ath12k_dp_rx_process_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3439 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,
3440 int budget)
3441 {
3442 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3443 struct dp_link_desc_bank *link_desc_banks;
3444 enum hal_rx_buf_return_buf_manager rbm;
3445 struct hal_rx_msdu_link *link_desc_va;
3446 int tot_n_bufs_reaped, quota, ret, i;
3447 struct hal_reo_dest_ring *reo_desc;
3448 struct dp_rxdma_ring *rx_ring;
3449 struct dp_srng *reo_except;
3450 LIST_HEAD(rx_desc_used_list);
3451 u32 desc_bank, num_msdus;
3452 struct hal_srng *srng;
3453 struct ath12k_dp *dp;
3454 int mac_id;
3455 struct ath12k *ar;
3456 dma_addr_t paddr;
3457 bool is_frag;
3458 bool drop;
3459 int pdev_id;
3460
3461 tot_n_bufs_reaped = 0;
3462 quota = budget;
3463
3464 dp = &ab->dp;
3465 reo_except = &dp->reo_except_ring;
3466 link_desc_banks = dp->link_desc_banks;
3467
3468 srng = &ab->hal.srng_list[reo_except->ring_id];
3469
3470 spin_lock_bh(&srng->lock);
3471
3472 ath12k_hal_srng_access_begin(ab, srng);
3473
3474 while (budget &&
3475 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
3476 drop = false;
3477 ab->soc_stats.err_ring_pkts++;
3478
3479 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr,
3480 &desc_bank);
3481 if (ret) {
3482 ath12k_warn(ab, "failed to parse error reo desc %d\n",
3483 ret);
3484 continue;
3485 }
3486 link_desc_va = link_desc_banks[desc_bank].vaddr +
3487 (paddr - link_desc_banks[desc_bank].paddr);
3488 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3489 &rbm);
3490 if (rbm != dp->idle_link_rbm &&
3491 rbm != HAL_RX_BUF_RBM_SW3_BM &&
3492 rbm != ab->hw_params->hal_params->rx_buf_rbm) {
3493 ab->soc_stats.invalid_rbm++;
3494 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm);
3495 ath12k_dp_rx_link_desc_return(ab, reo_desc,
3496 HAL_WBM_REL_BM_ACT_REL_MSDU);
3497 continue;
3498 }
3499
3500 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) &
3501 RX_MPDU_DESC_INFO0_FRAG_FLAG);
3502
3503 /* Process only rx fragments with one msdu per link desc below, and drop
3504 * msdu's indicated due to error reasons.
3505 */
3506 if (!is_frag || num_msdus > 1) {
3507 drop = true;
3508 /* Return the link desc back to wbm idle list */
3509 ath12k_dp_rx_link_desc_return(ab, reo_desc,
3510 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3511 }
3512
3513 for (i = 0; i < num_msdus; i++) {
3514 mac_id = le32_get_bits(reo_desc->info0,
3515 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3516
3517 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
3518 ar = ab->pdevs[pdev_id].ar;
3519
3520 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc,
3521 &rx_desc_used_list,
3522 drop,
3523 msdu_cookies[i]))
3524 tot_n_bufs_reaped++;
3525 }
3526
3527 if (tot_n_bufs_reaped >= quota) {
3528 tot_n_bufs_reaped = quota;
3529 goto exit;
3530 }
3531
3532 budget = quota - tot_n_bufs_reaped;
3533 }
3534
3535 exit:
3536 ath12k_hal_srng_access_end(ab, srng);
3537
3538 spin_unlock_bh(&srng->lock);
3539
3540 rx_ring = &dp->rx_refill_buf_ring;
3541
3542 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
3543 tot_n_bufs_reaped);
3544
3545 return tot_n_bufs_reaped;
3546 }
3547
ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k * ar,int msdu_len,struct sk_buff_head * msdu_list)3548 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar,
3549 int msdu_len,
3550 struct sk_buff_head *msdu_list)
3551 {
3552 struct sk_buff *skb, *tmp;
3553 struct ath12k_skb_rxcb *rxcb;
3554 int n_buffs;
3555
3556 n_buffs = DIV_ROUND_UP(msdu_len,
3557 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz));
3558
3559 skb_queue_walk_safe(msdu_list, skb, tmp) {
3560 rxcb = ATH12K_SKB_RXCB(skb);
3561 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3562 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3563 if (!n_buffs)
3564 break;
3565 __skb_unlink(skb, msdu_list);
3566 dev_kfree_skb_any(skb);
3567 n_buffs--;
3568 }
3569 }
3570 }
3571
ath12k_dp_rx_h_null_q_desc(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3572 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu,
3573 struct ieee80211_rx_status *status,
3574 struct sk_buff_head *msdu_list)
3575 {
3576 struct ath12k_base *ab = ar->ab;
3577 u16 msdu_len;
3578 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3579 u8 l3pad_bytes;
3580 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3581 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3582
3583 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3584
3585 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3586 /* First buffer will be freed by the caller, so deduct it's length */
3587 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3588 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3589 return -EINVAL;
3590 }
3591
3592 /* Even after cleaning up the sg buffers in the msdu list with above check
3593 * any msdu received with continuation flag needs to be dropped as invalid.
3594 * This protects against some random err frame with continuation flag.
3595 */
3596 if (rxcb->is_continuation)
3597 return -EINVAL;
3598
3599 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) {
3600 ath12k_warn(ar->ab,
3601 "msdu_done bit not set in null_q_des processing\n");
3602 __skb_queue_purge(msdu_list);
3603 return -EIO;
3604 }
3605
3606 /* Handle NULL queue descriptor violations arising out a missing
3607 * REO queue for a given peer or a given TID. This typically
3608 * may happen if a packet is received on a QOS enabled TID before the
3609 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3610 * it may also happen for MC/BC frames if they are not routed to the
3611 * non-QOS TID queue, in the absence of any other default TID queue.
3612 * This error can show up both in a REO destination or WBM release ring.
3613 */
3614
3615 if (rxcb->is_frag) {
3616 skb_pull(msdu, hal_rx_desc_sz);
3617 } else {
3618 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3619
3620 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3621 return -EINVAL;
3622
3623 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3624 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3625 }
3626 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
3627 return -EINVAL;
3628
3629 ath12k_dp_rx_h_ppdu(ar, desc, status);
3630
3631 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status);
3632
3633 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc);
3634
3635 /* Please note that caller will having the access to msdu and completing
3636 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3637 */
3638
3639 return 0;
3640 }
3641
ath12k_dp_rx_h_reo_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3642 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu,
3643 struct ieee80211_rx_status *status,
3644 struct sk_buff_head *msdu_list)
3645 {
3646 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3647 bool drop = false;
3648
3649 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3650
3651 switch (rxcb->err_code) {
3652 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3653 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3654 drop = true;
3655 break;
3656 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3657 /* TODO: Do not drop PN failed packets in the driver;
3658 * instead, it is good to drop such packets in mac80211
3659 * after incrementing the replay counters.
3660 */
3661 fallthrough;
3662 default:
3663 /* TODO: Review other errors and process them to mac80211
3664 * as appropriate.
3665 */
3666 drop = true;
3667 break;
3668 }
3669
3670 return drop;
3671 }
3672
ath12k_dp_rx_h_tkip_mic_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3673 static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu,
3674 struct ieee80211_rx_status *status)
3675 {
3676 struct ath12k_base *ab = ar->ab;
3677 u16 msdu_len;
3678 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3679 u8 l3pad_bytes;
3680 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3681 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3682
3683 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc);
3684 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc);
3685
3686 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3687 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3688
3689 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) {
3690 ath12k_dbg(ab, ATH12K_DBG_DATA,
3691 "invalid msdu len in tkip mic err %u\n", msdu_len);
3692 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", desc,
3693 sizeof(*desc));
3694 return true;
3695 }
3696
3697 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3698 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3699
3700 if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
3701 return true;
3702
3703 ath12k_dp_rx_h_ppdu(ar, desc, status);
3704
3705 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3706 RX_FLAG_DECRYPTED);
3707
3708 ath12k_dp_rx_h_undecap(ar, msdu, desc,
3709 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3710 return false;
3711 }
3712
ath12k_dp_rx_h_rxdma_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3713 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu,
3714 struct ieee80211_rx_status *status)
3715 {
3716 struct ath12k_base *ab = ar->ab;
3717 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3718 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3719 bool drop = false;
3720 u32 err_bitmap;
3721
3722 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3723
3724 switch (rxcb->err_code) {
3725 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR:
3726 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3727 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
3728 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) {
3729 drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3730 break;
3731 }
3732 fallthrough;
3733 default:
3734 /* TODO: Review other rxdma error code to check if anything is
3735 * worth reporting to mac80211
3736 */
3737 drop = true;
3738 break;
3739 }
3740
3741 return drop;
3742 }
3743
ath12k_dp_rx_wbm_err(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3744 static void ath12k_dp_rx_wbm_err(struct ath12k *ar,
3745 struct napi_struct *napi,
3746 struct sk_buff *msdu,
3747 struct sk_buff_head *msdu_list)
3748 {
3749 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3750 struct ieee80211_rx_status rxs = {0};
3751 bool drop = true;
3752
3753 switch (rxcb->err_rel_src) {
3754 case HAL_WBM_REL_SRC_MODULE_REO:
3755 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3756 break;
3757 case HAL_WBM_REL_SRC_MODULE_RXDMA:
3758 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3759 break;
3760 default:
3761 /* msdu will get freed */
3762 break;
3763 }
3764
3765 if (drop) {
3766 dev_kfree_skb_any(msdu);
3767 return;
3768 }
3769
3770 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
3771 }
3772
ath12k_dp_rx_process_wbm_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3773 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
3774 struct napi_struct *napi, int budget)
3775 {
3776 LIST_HEAD(rx_desc_used_list);
3777 struct ath12k *ar;
3778 struct ath12k_dp *dp = &ab->dp;
3779 struct dp_rxdma_ring *rx_ring;
3780 struct hal_rx_wbm_rel_info err_info;
3781 struct hal_srng *srng;
3782 struct sk_buff *msdu;
3783 struct sk_buff_head msdu_list, scatter_msdu_list;
3784 struct ath12k_skb_rxcb *rxcb;
3785 void *rx_desc;
3786 u8 mac_id;
3787 int num_buffs_reaped = 0;
3788 struct ath12k_rx_desc_info *desc_info;
3789 int ret, pdev_id;
3790 struct hal_rx_desc *msdu_data;
3791
3792 __skb_queue_head_init(&msdu_list);
3793 __skb_queue_head_init(&scatter_msdu_list);
3794
3795 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3796 rx_ring = &dp->rx_refill_buf_ring;
3797 spin_lock_bh(&srng->lock);
3798
3799 ath12k_hal_srng_access_begin(ab, srng);
3800
3801 while (budget) {
3802 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
3803 if (!rx_desc)
3804 break;
3805
3806 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3807 if (ret) {
3808 ath12k_warn(ab,
3809 "failed to parse rx error in wbm_rel ring desc %d\n",
3810 ret);
3811 continue;
3812 }
3813
3814 desc_info = err_info.rx_desc;
3815
3816 /* retry manual desc retrieval if hw cc is not done */
3817 if (!desc_info) {
3818 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie);
3819 if (!desc_info) {
3820 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n",
3821 err_info.cookie);
3822 continue;
3823 }
3824 }
3825
3826 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3827 ath12k_warn(ab, "WBM RX err, Check HW CC implementation");
3828
3829 msdu = desc_info->skb;
3830 desc_info->skb = NULL;
3831
3832 list_add_tail(&desc_info->list, &rx_desc_used_list);
3833
3834 rxcb = ATH12K_SKB_RXCB(msdu);
3835 dma_unmap_single(ab->dev, rxcb->paddr,
3836 msdu->len + skb_tailroom(msdu),
3837 DMA_FROM_DEVICE);
3838
3839 num_buffs_reaped++;
3840
3841 if (!err_info.continuation)
3842 budget--;
3843
3844 if (err_info.push_reason !=
3845 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
3846 dev_kfree_skb_any(msdu);
3847 continue;
3848 }
3849
3850 msdu_data = (struct hal_rx_desc *)msdu->data;
3851 rxcb->err_rel_src = err_info.err_rel_src;
3852 rxcb->err_code = err_info.err_code;
3853 rxcb->is_first_msdu = err_info.first_msdu;
3854 rxcb->is_last_msdu = err_info.last_msdu;
3855 rxcb->is_continuation = err_info.continuation;
3856 rxcb->rx_desc = msdu_data;
3857
3858 if (err_info.continuation) {
3859 __skb_queue_tail(&scatter_msdu_list, msdu);
3860 continue;
3861 }
3862
3863 mac_id = ath12k_dp_rx_get_msdu_src_link(ab,
3864 msdu_data);
3865 if (mac_id >= MAX_RADIOS) {
3866 dev_kfree_skb_any(msdu);
3867
3868 /* In any case continuation bit is set
3869 * in the previous record, cleanup scatter_msdu_list
3870 */
3871 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
3872 continue;
3873 }
3874
3875 if (!skb_queue_empty(&scatter_msdu_list)) {
3876 struct sk_buff *msdu;
3877
3878 skb_queue_walk(&scatter_msdu_list, msdu) {
3879 rxcb = ATH12K_SKB_RXCB(msdu);
3880 rxcb->mac_id = mac_id;
3881 }
3882
3883 skb_queue_splice_tail_init(&scatter_msdu_list,
3884 &msdu_list);
3885 }
3886
3887 rxcb = ATH12K_SKB_RXCB(msdu);
3888 rxcb->mac_id = mac_id;
3889 __skb_queue_tail(&msdu_list, msdu);
3890 }
3891
3892 /* In any case continuation bit is set in the
3893 * last record, cleanup scatter_msdu_list
3894 */
3895 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
3896
3897 ath12k_hal_srng_access_end(ab, srng);
3898
3899 spin_unlock_bh(&srng->lock);
3900
3901 if (!num_buffs_reaped)
3902 goto done;
3903
3904 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
3905 num_buffs_reaped);
3906
3907 rcu_read_lock();
3908 while ((msdu = __skb_dequeue(&msdu_list))) {
3909 rxcb = ATH12K_SKB_RXCB(msdu);
3910 mac_id = rxcb->mac_id;
3911
3912 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
3913 ar = ab->pdevs[pdev_id].ar;
3914
3915 if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) {
3916 dev_kfree_skb_any(msdu);
3917 continue;
3918 }
3919
3920 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
3921 dev_kfree_skb_any(msdu);
3922 continue;
3923 }
3924 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list);
3925 }
3926 rcu_read_unlock();
3927 done:
3928 return num_buffs_reaped;
3929 }
3930
ath12k_dp_rx_process_reo_status(struct ath12k_base * ab)3931 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab)
3932 {
3933 struct ath12k_dp *dp = &ab->dp;
3934 struct hal_tlv_64_hdr *hdr;
3935 struct hal_srng *srng;
3936 struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
3937 bool found = false;
3938 u16 tag;
3939 struct hal_reo_status reo_status;
3940
3941 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
3942
3943 memset(&reo_status, 0, sizeof(reo_status));
3944
3945 spin_lock_bh(&srng->lock);
3946
3947 ath12k_hal_srng_access_begin(ab, srng);
3948
3949 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
3950 tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG);
3951
3952 switch (tag) {
3953 case HAL_REO_GET_QUEUE_STATS_STATUS:
3954 ath12k_hal_reo_status_queue_stats(ab, hdr,
3955 &reo_status);
3956 break;
3957 case HAL_REO_FLUSH_QUEUE_STATUS:
3958 ath12k_hal_reo_flush_queue_status(ab, hdr,
3959 &reo_status);
3960 break;
3961 case HAL_REO_FLUSH_CACHE_STATUS:
3962 ath12k_hal_reo_flush_cache_status(ab, hdr,
3963 &reo_status);
3964 break;
3965 case HAL_REO_UNBLOCK_CACHE_STATUS:
3966 ath12k_hal_reo_unblk_cache_status(ab, hdr,
3967 &reo_status);
3968 break;
3969 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
3970 ath12k_hal_reo_flush_timeout_list_status(ab, hdr,
3971 &reo_status);
3972 break;
3973 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
3974 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr,
3975 &reo_status);
3976 break;
3977 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
3978 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr,
3979 &reo_status);
3980 break;
3981 default:
3982 ath12k_warn(ab, "Unknown reo status type %d\n", tag);
3983 continue;
3984 }
3985
3986 spin_lock_bh(&dp->reo_cmd_lock);
3987 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
3988 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
3989 found = true;
3990 list_del(&cmd->list);
3991 break;
3992 }
3993 }
3994 spin_unlock_bh(&dp->reo_cmd_lock);
3995
3996 if (found) {
3997 cmd->handler(dp, (void *)&cmd->data,
3998 reo_status.uniform_hdr.cmd_status);
3999 kfree(cmd);
4000 }
4001
4002 found = false;
4003 }
4004
4005 ath12k_hal_srng_access_end(ab, srng);
4006
4007 spin_unlock_bh(&srng->lock);
4008 }
4009
ath12k_dp_rx_free(struct ath12k_base * ab)4010 void ath12k_dp_rx_free(struct ath12k_base *ab)
4011 {
4012 struct ath12k_dp *dp = &ab->dp;
4013 int i;
4014
4015 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
4016
4017 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4018 if (ab->hw_params->rx_mac_buf_ring)
4019 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
4020 }
4021
4022 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++)
4023 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
4024
4025 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
4026
4027 ath12k_dp_rxdma_buf_free(ab);
4028 }
4029
ath12k_dp_rx_pdev_free(struct ath12k_base * ab,int mac_id)4030 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id)
4031 {
4032 struct ath12k *ar = ab->pdevs[mac_id].ar;
4033
4034 ath12k_dp_rx_pdev_srng_free(ar);
4035 }
4036
ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base * ab)4037 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
4038 {
4039 struct ath12k_dp *dp = &ab->dp;
4040 struct htt_rx_ring_tlv_filter tlv_filter = {0};
4041 u32 ring_id;
4042 int ret;
4043 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4044
4045 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4046
4047 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4048 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4049 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4050 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4051 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4052 tlv_filter.offset_valid = true;
4053 tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4054
4055 tlv_filter.rx_mpdu_start_offset =
4056 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4057 tlv_filter.rx_msdu_end_offset =
4058 ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4059
4060 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
4061 tlv_filter.rx_mpdu_start_wmask =
4062 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
4063 tlv_filter.rx_msdu_end_wmask =
4064 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
4065 ath12k_dbg(ab, ATH12K_DBG_DATA,
4066 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
4067 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
4068 }
4069
4070 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
4071 HAL_RXDMA_BUF,
4072 DP_RXDMA_REFILL_RING_SIZE,
4073 &tlv_filter);
4074
4075 return ret;
4076 }
4077
ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base * ab)4078 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
4079 {
4080 struct ath12k_dp *dp = &ab->dp;
4081 struct htt_rx_ring_tlv_filter tlv_filter = {0};
4082 u32 ring_id;
4083 int ret = 0;
4084 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4085 int i;
4086
4087 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4088
4089 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4090 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4091 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4092 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4093 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4094 tlv_filter.offset_valid = true;
4095 tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4096
4097 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
4098
4099 tlv_filter.rx_mpdu_start_offset =
4100 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4101 tlv_filter.rx_msdu_end_offset =
4102 ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4103
4104 /* TODO: Selectively subscribe to required qwords within msdu_end
4105 * and mpdu_start and setup the mask in below msg
4106 * and modify the rx_desc struct
4107 */
4108
4109 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4110 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4111 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
4112 HAL_RXDMA_BUF,
4113 DP_RXDMA_REFILL_RING_SIZE,
4114 &tlv_filter);
4115 }
4116
4117 return ret;
4118 }
4119
ath12k_dp_rx_htt_setup(struct ath12k_base * ab)4120 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab)
4121 {
4122 struct ath12k_dp *dp = &ab->dp;
4123 u32 ring_id;
4124 int i, ret;
4125
4126 /* TODO: Need to verify the HTT setup for QCN9224 */
4127 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4128 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF);
4129 if (ret) {
4130 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4131 ret);
4132 return ret;
4133 }
4134
4135 if (ab->hw_params->rx_mac_buf_ring) {
4136 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4137 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4138 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4139 i, HAL_RXDMA_BUF);
4140 if (ret) {
4141 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4142 i, ret);
4143 return ret;
4144 }
4145 }
4146 }
4147
4148 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4149 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4150 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4151 i, HAL_RXDMA_DST);
4152 if (ret) {
4153 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4154 i, ret);
4155 return ret;
4156 }
4157 }
4158
4159 if (ab->hw_params->rxdma1_enable) {
4160 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4161 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4162 0, HAL_RXDMA_MONITOR_BUF);
4163 if (ret) {
4164 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4165 ret);
4166 return ret;
4167 }
4168 }
4169
4170 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab);
4171 if (ret) {
4172 ath12k_warn(ab, "failed to setup rxdma ring selection config\n");
4173 return ret;
4174 }
4175
4176 return 0;
4177 }
4178
ath12k_dp_rx_alloc(struct ath12k_base * ab)4179 int ath12k_dp_rx_alloc(struct ath12k_base *ab)
4180 {
4181 struct ath12k_dp *dp = &ab->dp;
4182 int i, ret;
4183
4184 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr);
4185 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock);
4186
4187 ret = ath12k_dp_srng_setup(ab,
4188 &dp->rx_refill_buf_ring.refill_buf_ring,
4189 HAL_RXDMA_BUF, 0, 0,
4190 DP_RXDMA_BUF_RING_SIZE);
4191 if (ret) {
4192 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n");
4193 return ret;
4194 }
4195
4196 if (ab->hw_params->rx_mac_buf_ring) {
4197 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4198 ret = ath12k_dp_srng_setup(ab,
4199 &dp->rx_mac_buf_ring[i],
4200 HAL_RXDMA_BUF, 1,
4201 i, DP_RX_MAC_BUF_RING_SIZE);
4202 if (ret) {
4203 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n",
4204 i);
4205 return ret;
4206 }
4207 }
4208 }
4209
4210 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4211 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i],
4212 HAL_RXDMA_DST, 0, i,
4213 DP_RXDMA_ERR_DST_RING_SIZE);
4214 if (ret) {
4215 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i);
4216 return ret;
4217 }
4218 }
4219
4220 if (ab->hw_params->rxdma1_enable) {
4221 ret = ath12k_dp_srng_setup(ab,
4222 &dp->rxdma_mon_buf_ring.refill_buf_ring,
4223 HAL_RXDMA_MONITOR_BUF, 0, 0,
4224 DP_RXDMA_MONITOR_BUF_RING_SIZE);
4225 if (ret) {
4226 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n");
4227 return ret;
4228 }
4229 }
4230
4231 ret = ath12k_dp_rxdma_buf_setup(ab);
4232 if (ret) {
4233 ath12k_warn(ab, "failed to setup rxdma ring\n");
4234 return ret;
4235 }
4236
4237 return 0;
4238 }
4239
ath12k_dp_rx_pdev_alloc(struct ath12k_base * ab,int mac_id)4240 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id)
4241 {
4242 struct ath12k *ar = ab->pdevs[mac_id].ar;
4243 struct ath12k_pdev_dp *dp = &ar->dp;
4244 u32 ring_id;
4245 int i;
4246 int ret;
4247
4248 if (!ab->hw_params->rxdma1_enable)
4249 goto out;
4250
4251 ret = ath12k_dp_rx_pdev_srng_alloc(ar);
4252 if (ret) {
4253 ath12k_warn(ab, "failed to setup rx srngs\n");
4254 return ret;
4255 }
4256
4257 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4258 ring_id = dp->rxdma_mon_dst_ring[i].ring_id;
4259 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4260 mac_id + i,
4261 HAL_RXDMA_MONITOR_DST);
4262 if (ret) {
4263 ath12k_warn(ab,
4264 "failed to configure rxdma_mon_dst_ring %d %d\n",
4265 i, ret);
4266 return ret;
4267 }
4268 }
4269 out:
4270 return 0;
4271 }
4272
ath12k_dp_rx_pdev_mon_status_attach(struct ath12k * ar)4273 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar)
4274 {
4275 struct ath12k_pdev_dp *dp = &ar->dp;
4276 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data;
4277
4278 skb_queue_head_init(&pmon->rx_status_q);
4279
4280 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4281
4282 memset(&pmon->rx_mon_stats, 0,
4283 sizeof(pmon->rx_mon_stats));
4284 return 0;
4285 }
4286
ath12k_dp_rx_pdev_mon_attach(struct ath12k * ar)4287 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar)
4288 {
4289 struct ath12k_pdev_dp *dp = &ar->dp;
4290 struct ath12k_mon_data *pmon = &dp->mon_data;
4291 int ret = 0;
4292
4293 ret = ath12k_dp_rx_pdev_mon_status_attach(ar);
4294 if (ret) {
4295 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed");
4296 return ret;
4297 }
4298
4299 /* if rxdma1_enable is false, no need to setup
4300 * rxdma_mon_desc_ring.
4301 */
4302 if (!ar->ab->hw_params->rxdma1_enable)
4303 return 0;
4304
4305 pmon->mon_last_linkdesc_paddr = 0;
4306 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
4307 spin_lock_init(&pmon->mon_lock);
4308
4309 return 0;
4310 }
4311