1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_HAL_H 8 #define ATH12K_HAL_H 9 10 #include "hal_desc.h" 11 #include "rx_desc.h" 12 13 struct ath12k_base; 14 15 #define HAL_LINK_DESC_SIZE (32 << 2) 16 #define HAL_LINK_DESC_ALIGN 128 17 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 18 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 19 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 20 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 21 #define HAL_MAX_AVAIL_BLK_RES 3 22 23 #define HAL_RING_BASE_ALIGN 8 24 25 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 26 /* TODO: Check with hw team on the supported scatter buf size */ 27 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 29 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 30 31 /* TODO: 16 entries per radio times MAX_VAPS_SUPPORTED */ 32 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 32 33 #define HAL_DSCP_TID_TBL_SIZE 24 34 35 /* calculate the register address from bar0 of shadow register x */ 36 #define HAL_SHADOW_BASE_ADDR 0x000008fc 37 #define HAL_SHADOW_NUM_REGS 40 38 #define HAL_HP_OFFSET_IN_REG_START 1 39 #define HAL_OFFSET_FROM_HP_TO_TP 4 40 41 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) 42 43 /* WCSS Relative address */ 44 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 45 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 46 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 47 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) \ 48 ((ab)->hw_params->regs->hal_umac_ce0_src_reg_base) 49 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) \ 50 ((ab)->hw_params->regs->hal_umac_ce0_dest_reg_base) 51 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) \ 52 ((ab)->hw_params->regs->hal_umac_ce1_src_reg_base) 53 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) \ 54 ((ab)->hw_params->regs->hal_umac_ce1_dest_reg_base) 55 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 56 57 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 58 59 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c 60 61 /* SW2TCL(x) R0 ring configuration address */ 62 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020 63 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240 64 #define HAL_TCL1_RING_BASE_LSB(ab) \ 65 ((ab)->hw_params->regs->hal_tcl1_ring_base_lsb) 66 #define HAL_TCL1_RING_BASE_MSB(ab) \ 67 ((ab)->hw_params->regs->hal_tcl1_ring_base_msb) 68 #define HAL_TCL1_RING_ID(ab) ((ab)->hw_params->regs->hal_tcl1_ring_id) 69 #define HAL_TCL1_RING_MISC(ab) \ 70 ((ab)->hw_params->regs->hal_tcl1_ring_misc) 71 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \ 72 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_lsb) 73 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \ 74 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_msb) 75 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \ 76 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix0) 77 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \ 78 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix1) 79 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \ 80 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_lsb) 81 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \ 82 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb) 83 #define HAL_TCL1_RING_MSI1_DATA(ab) \ 84 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_data) 85 #define HAL_TCL2_RING_BASE_LSB(ab) \ 86 ((ab)->hw_params->regs->hal_tcl2_ring_base_lsb) 87 #define HAL_TCL_RING_BASE_LSB(ab) \ 88 ((ab)->hw_params->regs->hal_tcl_ring_base_lsb) 89 90 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 91 (HAL_TCL1_RING_MSI1_BASE_LSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 92 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 93 (HAL_TCL1_RING_MSI1_BASE_MSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 94 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 95 (HAL_TCL1_RING_MSI1_DATA(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 96 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 97 (HAL_TCL1_RING_BASE_MSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 98 #define HAL_TCL1_RING_ID_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 99 (HAL_TCL1_RING_ID(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 100 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 101 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 102 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 103 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 104 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 105 (HAL_TCL1_RING_TP_ADDR_LSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 106 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 107 (HAL_TCL1_RING_TP_ADDR_MSB(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 108 #define HAL_TCL1_RING_MISC_OFFSET(ab) ({ typeof(ab) _ab = (ab); \ 109 (HAL_TCL1_RING_MISC(_ab) - HAL_TCL1_RING_BASE_LSB(_ab)); }) 110 111 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 112 #define HAL_TCL1_RING_HP 0x00002000 113 #define HAL_TCL1_RING_TP 0x00002004 114 #define HAL_TCL2_RING_HP 0x00002008 115 #define HAL_TCL_RING_HP 0x00002028 116 117 #define HAL_TCL1_RING_TP_OFFSET \ 118 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 119 120 /* TCL STATUS ring address */ 121 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ 122 ((ab)->hw_params->regs->hal_tcl_status_ring_base_lsb) 123 #define HAL_TCL_STATUS_RING_HP 0x00002048 124 125 /* PPE2TCL1 Ring address */ 126 #define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48 127 #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038 128 129 /* WBM PPE Release Ring address */ 130 #define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab) \ 131 ((ab)->hw_params->regs->hal_ppe_rel_ring_base) 132 #define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020 133 134 /* REO2SW(x) R0 ring configuration address */ 135 #define HAL_REO1_GEN_ENABLE 0x00000000 136 #define HAL_REO1_MISC_CTRL_ADDR(ab) \ 137 ((ab)->hw_params->regs->hal_reo1_misc_ctrl_addr) 138 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 139 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 140 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 141 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 142 #define HAL_REO1_SW_COOKIE_CFG0(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg0) 143 #define HAL_REO1_SW_COOKIE_CFG1(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg1) 144 #define HAL_REO1_QDESC_LUT_BASE0(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base0) 145 #define HAL_REO1_QDESC_LUT_BASE1(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base1) 146 #define HAL_REO1_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_lsb) 147 #define HAL_REO1_RING_BASE_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_msb) 148 #define HAL_REO1_RING_ID(ab) ((ab)->hw_params->regs->hal_reo1_ring_id) 149 #define HAL_REO1_RING_MISC(ab) ((ab)->hw_params->regs->hal_reo1_ring_misc) 150 #define HAL_REO1_RING_HP_ADDR_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_lsb) 151 #define HAL_REO1_RING_HP_ADDR_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_msb) 152 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \ 153 ((ab)->hw_params->regs->hal_reo1_ring_producer_int_setup) 154 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \ 155 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_lsb) 156 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \ 157 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_msb) 158 #define HAL_REO1_RING_MSI1_DATA(ab) ((ab)->hw_params->regs->hal_reo1_ring_msi1_data) 159 #define HAL_REO2_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo2_ring_base) 160 #define HAL_REO1_AGING_THRESH_IX_0(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix0) 161 #define HAL_REO1_AGING_THRESH_IX_1(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix1) 162 #define HAL_REO1_AGING_THRESH_IX_2(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix2) 163 #define HAL_REO1_AGING_THRESH_IX_3(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix3) 164 165 /* REO2SW(x) R2 ring pointers (head/tail) address */ 166 #define HAL_REO1_RING_HP 0x00003048 167 #define HAL_REO1_RING_TP 0x0000304c 168 #define HAL_REO2_RING_HP 0x00003050 169 170 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) 171 172 /* REO2SW0 ring configuration address */ 173 #define HAL_REO_SW0_RING_BASE_LSB(ab) \ 174 ((ab)->hw_params->regs->hal_reo2_sw0_ring_base) 175 176 /* REO2SW0 R2 ring pointer (head/tail) address */ 177 #define HAL_REO_SW0_RING_HP 0x00003088 178 179 /* REO CMD R0 address */ 180 #define HAL_REO_CMD_RING_BASE_LSB(ab) \ 181 ((ab)->hw_params->regs->hal_reo_cmd_ring_base) 182 183 /* REO CMD R2 address */ 184 #define HAL_REO_CMD_HP 0x00003020 185 186 /* SW2REO R0 address */ 187 #define HAL_SW2REO_RING_BASE_LSB(ab) \ 188 ((ab)->hw_params->regs->hal_sw2reo_ring_base) 189 #define HAL_SW2REO1_RING_BASE_LSB(ab) \ 190 ((ab)->hw_params->regs->hal_sw2reo1_ring_base) 191 192 /* SW2REO R2 address */ 193 #define HAL_SW2REO_RING_HP 0x00003028 194 #define HAL_SW2REO1_RING_HP 0x00003030 195 196 /* CE ring R0 address */ 197 #define HAL_CE_SRC_RING_BASE_LSB 0x00000000 198 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 199 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 200 #define HAL_CE_DST_RING_CTRL 0x000000b0 201 202 /* CE ring R2 address */ 203 #define HAL_CE_DST_RING_HP 0x00000400 204 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 205 206 /* REO status address */ 207 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \ 208 ((ab)->hw_params->regs->hal_reo_status_ring_base) 209 #define HAL_REO_STATUS_HP 0x000030a8 210 211 /* WBM Idle R0 address */ 212 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab) \ 213 ((ab)->hw_params->regs->hal_wbm_idle_ring_base_lsb) 214 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab) \ 215 ((ab)->hw_params->regs->hal_wbm_idle_ring_misc_addr) 216 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(ab) \ 217 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_cntl_addr) 218 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(ab) \ 219 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_size_addr) 220 #define HAL_WBM_SCATTERED_RING_BASE_LSB(ab) \ 221 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_lsb) 222 #define HAL_WBM_SCATTERED_RING_BASE_MSB(ab) \ 223 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_msb) 224 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(ab) \ 225 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix0) 226 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(ab) \ 227 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix1) 228 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(ab) \ 229 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix0) 230 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(ab) \ 231 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix1) 232 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(ab) \ 233 ((ab)->hw_params->regs->hal_wbm_scattered_desc_ptr_hp_addr) 234 235 /* WBM Idle R2 address */ 236 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b8 237 238 /* SW2WBM R0 release address */ 239 #define HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab) \ 240 ((ab)->hw_params->regs->hal_wbm_sw_release_ring_base_lsb) 241 #define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) \ 242 ((ab)->hw_params->regs->hal_wbm_sw1_release_ring_base_lsb) 243 244 /* SW2WBM R2 release address */ 245 #define HAL_WBM_SW_RELEASE_RING_HP 0x00003010 246 #define HAL_WBM_SW1_RELEASE_RING_HP 0x00003018 247 248 /* WBM2SW R0 release address */ 249 #define HAL_WBM0_RELEASE_RING_BASE_LSB(ab) \ 250 ((ab)->hw_params->regs->hal_wbm0_release_ring_base_lsb) 251 252 #define HAL_WBM1_RELEASE_RING_BASE_LSB(ab) \ 253 ((ab)->hw_params->regs->hal_wbm1_release_ring_base_lsb) 254 255 /* WBM2SW R2 release address */ 256 #define HAL_WBM0_RELEASE_RING_HP 0x000030c8 257 #define HAL_WBM1_RELEASE_RING_HP 0x000030d0 258 259 /* WBM cookie config address and mask */ 260 #define HAL_WBM_SW_COOKIE_CFG0 0x00000040 261 #define HAL_WBM_SW_COOKIE_CFG1 0x00000044 262 #define HAL_WBM_SW_COOKIE_CFG2 0x00000090 263 #define HAL_WBM_SW_COOKIE_CONVERT_CFG 0x00000094 264 265 #define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 266 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 267 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 268 #define HAL_WBM_SW_COOKIE_CFG_ALIGN BIT(18) 269 #define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0) 270 #define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN BIT(1) 271 #define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3) 272 273 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1) 274 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2) 275 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3) 276 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4) 277 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5) 278 #define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8) 279 280 /* TCL ring field mask and offset */ 281 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 282 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 283 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 284 #define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0) 285 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 286 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 287 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 288 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 289 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 290 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 291 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 292 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 293 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 294 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 295 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(23) 296 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 297 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 298 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 299 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 300 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 301 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 302 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 303 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 304 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 305 306 /* REO ring field mask and offset */ 307 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 308 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 309 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 310 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 311 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 312 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 313 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 314 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 315 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 316 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 317 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 318 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 319 #define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17) 320 #define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21) 321 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 322 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 323 #define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 324 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 325 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 326 #define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18) 327 #define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19) 328 #define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20) 329 330 /* CE ring bit field mask and shift */ 331 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 332 333 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 334 335 #define HAL_ADDR_MSB_REG_SHIFT 32 336 337 /* WBM ring bit field mask and shift */ 338 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 339 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 340 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 341 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 342 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 343 344 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 345 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 346 347 #define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE BIT(6) 348 #define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0) 349 350 #define BASE_ADDR_MATCH_TAG_VAL 0x5 351 352 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 353 #define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE 0x000fffff 354 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 355 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 356 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 357 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 358 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 359 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 360 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 361 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 362 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 363 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x000fffff 364 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 365 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 366 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 367 #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff 368 #define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 369 370 #define HAL_WBM2SW_REL_ERR_RING_NUM 3 371 /* Add any other errors here and return them in 372 * ath12k_hal_rx_desc_get_err(). 373 */ 374 375 enum hal_srng_ring_id { 376 HAL_SRNG_RING_ID_REO2SW0 = 0, 377 HAL_SRNG_RING_ID_REO2SW1, 378 HAL_SRNG_RING_ID_REO2SW2, 379 HAL_SRNG_RING_ID_REO2SW3, 380 HAL_SRNG_RING_ID_REO2SW4, 381 HAL_SRNG_RING_ID_REO2SW5, 382 HAL_SRNG_RING_ID_REO2SW6, 383 HAL_SRNG_RING_ID_REO2SW7, 384 HAL_SRNG_RING_ID_REO2SW8, 385 HAL_SRNG_RING_ID_REO2TCL, 386 HAL_SRNG_RING_ID_REO2PPE, 387 388 HAL_SRNG_RING_ID_SW2REO = 16, 389 HAL_SRNG_RING_ID_SW2REO1, 390 HAL_SRNG_RING_ID_SW2REO2, 391 HAL_SRNG_RING_ID_SW2REO3, 392 393 HAL_SRNG_RING_ID_REO_CMD, 394 HAL_SRNG_RING_ID_REO_STATUS, 395 396 HAL_SRNG_RING_ID_SW2TCL1 = 24, 397 HAL_SRNG_RING_ID_SW2TCL2, 398 HAL_SRNG_RING_ID_SW2TCL3, 399 HAL_SRNG_RING_ID_SW2TCL4, 400 HAL_SRNG_RING_ID_SW2TCL5, 401 HAL_SRNG_RING_ID_SW2TCL6, 402 HAL_SRNG_RING_ID_PPE2TCL1 = 30, 403 404 HAL_SRNG_RING_ID_SW2TCL_CMD = 40, 405 HAL_SRNG_RING_ID_SW2TCL1_CMD, 406 HAL_SRNG_RING_ID_TCL_STATUS, 407 408 HAL_SRNG_RING_ID_CE0_SRC = 64, 409 HAL_SRNG_RING_ID_CE1_SRC, 410 HAL_SRNG_RING_ID_CE2_SRC, 411 HAL_SRNG_RING_ID_CE3_SRC, 412 HAL_SRNG_RING_ID_CE4_SRC, 413 HAL_SRNG_RING_ID_CE5_SRC, 414 HAL_SRNG_RING_ID_CE6_SRC, 415 HAL_SRNG_RING_ID_CE7_SRC, 416 HAL_SRNG_RING_ID_CE8_SRC, 417 HAL_SRNG_RING_ID_CE9_SRC, 418 HAL_SRNG_RING_ID_CE10_SRC, 419 HAL_SRNG_RING_ID_CE11_SRC, 420 HAL_SRNG_RING_ID_CE12_SRC, 421 HAL_SRNG_RING_ID_CE13_SRC, 422 HAL_SRNG_RING_ID_CE14_SRC, 423 HAL_SRNG_RING_ID_CE15_SRC, 424 425 HAL_SRNG_RING_ID_CE0_DST = 81, 426 HAL_SRNG_RING_ID_CE1_DST, 427 HAL_SRNG_RING_ID_CE2_DST, 428 HAL_SRNG_RING_ID_CE3_DST, 429 HAL_SRNG_RING_ID_CE4_DST, 430 HAL_SRNG_RING_ID_CE5_DST, 431 HAL_SRNG_RING_ID_CE6_DST, 432 HAL_SRNG_RING_ID_CE7_DST, 433 HAL_SRNG_RING_ID_CE8_DST, 434 HAL_SRNG_RING_ID_CE9_DST, 435 HAL_SRNG_RING_ID_CE10_DST, 436 HAL_SRNG_RING_ID_CE11_DST, 437 HAL_SRNG_RING_ID_CE12_DST, 438 HAL_SRNG_RING_ID_CE13_DST, 439 HAL_SRNG_RING_ID_CE14_DST, 440 HAL_SRNG_RING_ID_CE15_DST, 441 442 HAL_SRNG_RING_ID_CE0_DST_STATUS = 100, 443 HAL_SRNG_RING_ID_CE1_DST_STATUS, 444 HAL_SRNG_RING_ID_CE2_DST_STATUS, 445 HAL_SRNG_RING_ID_CE3_DST_STATUS, 446 HAL_SRNG_RING_ID_CE4_DST_STATUS, 447 HAL_SRNG_RING_ID_CE5_DST_STATUS, 448 HAL_SRNG_RING_ID_CE6_DST_STATUS, 449 HAL_SRNG_RING_ID_CE7_DST_STATUS, 450 HAL_SRNG_RING_ID_CE8_DST_STATUS, 451 HAL_SRNG_RING_ID_CE9_DST_STATUS, 452 HAL_SRNG_RING_ID_CE10_DST_STATUS, 453 HAL_SRNG_RING_ID_CE11_DST_STATUS, 454 HAL_SRNG_RING_ID_CE12_DST_STATUS, 455 HAL_SRNG_RING_ID_CE13_DST_STATUS, 456 HAL_SRNG_RING_ID_CE14_DST_STATUS, 457 HAL_SRNG_RING_ID_CE15_DST_STATUS, 458 459 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120, 460 HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 461 HAL_SRNG_RING_ID_WBM_SW1_RELEASE, 462 HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123, 463 464 HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128, 465 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 466 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 467 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */ 468 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 469 HAL_SRNG_RING_ID_WBM2SW5_RELEASE, 470 HAL_SRNG_RING_ID_WBM2SW6_RELEASE, 471 HAL_SRNG_RING_ID_WBM2SW7_RELEASE, 472 473 HAL_SRNG_RING_ID_UMAC_ID_END = 159, 474 475 /* Common DMAC rings shared by all LMACs */ 476 HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160, 477 HAL_SRNG_SW2RXDMA_BUF0 = HAL_SRNG_RING_ID_DMAC_CMN_ID_START, 478 HAL_SRNG_SW2RXDMA_BUF1 = 161, 479 HAL_SRNG_SW2RXDMA_BUF2 = 162, 480 481 HAL_SRNG_SW2RXMON_BUF0 = 168, 482 483 HAL_SRNG_SW2TXMON_BUF0 = 176, 484 485 HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183, 486 HAL_SRNG_RING_ID_PMAC1_ID_START = 184, 487 488 HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 = HAL_SRNG_RING_ID_PMAC1_ID_START, 489 490 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 491 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 492 HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 493 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 494 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 495 HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, 496 HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, 497 498 HAL_SRNG_RING_ID_PMAC1_ID_END, 499 }; 500 501 /* SRNG registers are split into two groups R0 and R2 */ 502 #define HAL_SRNG_REG_GRP_R0 0 503 #define HAL_SRNG_REG_GRP_R2 1 504 #define HAL_SRNG_NUM_REG_GRP 2 505 506 /* TODO: number of PMACs */ 507 #define HAL_SRNG_NUM_PMACS 3 508 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \ 509 HAL_SRNG_RING_ID_DMAC_CMN_ID_START) 510 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \ 511 HAL_SRNG_RING_ID_PMAC1_ID_START) 512 #define HAL_SRNG_NUM_PMAC_RINGS (HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC) 513 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_DMAC_CMN_ID_END + \ 514 HAL_SRNG_NUM_PMAC_RINGS) 515 516 enum hal_ring_type { 517 HAL_REO_DST, 518 HAL_REO_EXCEPTION, 519 HAL_REO_REINJECT, 520 HAL_REO_CMD, 521 HAL_REO_STATUS, 522 HAL_TCL_DATA, 523 HAL_TCL_CMD, 524 HAL_TCL_STATUS, 525 HAL_CE_SRC, 526 HAL_CE_DST, 527 HAL_CE_DST_STATUS, 528 HAL_WBM_IDLE_LINK, 529 HAL_SW2WBM_RELEASE, 530 HAL_WBM2SW_RELEASE, 531 HAL_RXDMA_BUF, 532 HAL_RXDMA_DST, 533 HAL_RXDMA_MONITOR_BUF, 534 HAL_RXDMA_MONITOR_STATUS, 535 HAL_RXDMA_MONITOR_DST, 536 HAL_RXDMA_MONITOR_DESC, 537 HAL_RXDMA_DIR_BUF, 538 HAL_PPE2TCL, 539 HAL_PPE_RELEASE, 540 HAL_TX_MONITOR_BUF, 541 HAL_TX_MONITOR_DST, 542 HAL_MAX_RING_TYPES, 543 }; 544 545 #define HAL_RX_MAX_BA_WINDOW 256 546 547 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000) 548 #define HAL_DEFAULT_VO_REO_TIMEOUT_USEC (40 * 1000) 549 550 /** 551 * enum hal_reo_cmd_type: Enum for REO command type 552 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 553 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 554 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 555 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 556 * earlier with a 'REO_FLUSH_CACHE' command 557 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 558 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 559 */ 560 enum hal_reo_cmd_type { 561 HAL_REO_CMD_GET_QUEUE_STATS = 0, 562 HAL_REO_CMD_FLUSH_QUEUE = 1, 563 HAL_REO_CMD_FLUSH_CACHE = 2, 564 HAL_REO_CMD_UNBLOCK_CACHE = 3, 565 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 566 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 567 }; 568 569 /** 570 * enum hal_reo_cmd_status: Enum for execution status of REO command 571 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 572 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 573 * or cache was blocked 574 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 575 * invalid queue desc 576 * @HAL_REO_CMD_RESOURCE_BLOCKED: 577 * @HAL_REO_CMD_DRAIN: 578 */ 579 enum hal_reo_cmd_status { 580 HAL_REO_CMD_SUCCESS = 0, 581 HAL_REO_CMD_BLOCKED = 1, 582 HAL_REO_CMD_FAILED = 2, 583 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 584 HAL_REO_CMD_DRAIN = 0xff, 585 }; 586 587 struct hal_wbm_idle_scatter_list { 588 dma_addr_t paddr; 589 struct hal_wbm_link_desc *vaddr; 590 }; 591 592 struct hal_srng_params { 593 dma_addr_t ring_base_paddr; 594 u32 *ring_base_vaddr; 595 int num_entries; 596 u32 intr_batch_cntr_thres_entries; 597 u32 intr_timer_thres_us; 598 u32 flags; 599 u32 max_buffer_len; 600 u32 low_threshold; 601 u32 high_threshold; 602 dma_addr_t msi_addr; 603 dma_addr_t msi2_addr; 604 u32 msi_data; 605 u32 msi2_data; 606 607 /* Add more params as needed */ 608 }; 609 610 enum hal_srng_dir { 611 HAL_SRNG_DIR_SRC, 612 HAL_SRNG_DIR_DST 613 }; 614 615 /* srng flags */ 616 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 617 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 618 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 619 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 620 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 621 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000 622 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 623 624 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 625 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 626 627 /* Common SRNG ring structure for source and destination rings */ 628 struct hal_srng { 629 /* Unique SRNG ring ID */ 630 u8 ring_id; 631 632 /* Ring initialization done */ 633 u8 initialized; 634 635 /* Interrupt/MSI value assigned to this ring */ 636 int irq; 637 638 /* Physical base address of the ring */ 639 dma_addr_t ring_base_paddr; 640 641 /* Virtual base address of the ring */ 642 u32 *ring_base_vaddr; 643 644 /* Number of entries in ring */ 645 u32 num_entries; 646 647 /* Ring size */ 648 u32 ring_size; 649 650 /* Ring size mask */ 651 u32 ring_size_mask; 652 653 /* Size of ring entry */ 654 u32 entry_size; 655 656 /* Interrupt timer threshold - in micro seconds */ 657 u32 intr_timer_thres_us; 658 659 /* Interrupt batch counter threshold - in number of ring entries */ 660 u32 intr_batch_cntr_thres_entries; 661 662 /* MSI Address */ 663 dma_addr_t msi_addr; 664 665 /* MSI data */ 666 u32 msi_data; 667 668 /* MSI2 Address */ 669 dma_addr_t msi2_addr; 670 671 /* MSI2 data */ 672 u32 msi2_data; 673 674 /* Misc flags */ 675 u32 flags; 676 677 /* Lock for serializing ring index updates */ 678 spinlock_t lock; 679 680 struct lock_class_key lock_key; 681 682 /* Start offset of SRNG register groups for this ring 683 * TBD: See if this is required - register address can be derived 684 * from ring ID 685 */ 686 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 687 688 u64 timestamp; 689 690 /* Source or Destination ring */ 691 enum hal_srng_dir ring_dir; 692 693 union { 694 struct { 695 /* SW tail pointer */ 696 u32 tp; 697 698 /* Shadow head pointer location to be updated by HW */ 699 volatile u32 *hp_addr; 700 701 /* Cached head pointer */ 702 u32 cached_hp; 703 704 /* Tail pointer location to be updated by SW - This 705 * will be a register address and need not be 706 * accessed through SW structure 707 */ 708 u32 *tp_addr; 709 710 /* Current SW loop cnt */ 711 u32 loop_cnt; 712 713 /* max transfer size */ 714 u16 max_buffer_length; 715 716 /* head pointer at access end */ 717 u32 last_hp; 718 } dst_ring; 719 720 struct { 721 /* SW head pointer */ 722 u32 hp; 723 724 /* SW reap head pointer */ 725 u32 reap_hp; 726 727 /* Shadow tail pointer location to be updated by HW */ 728 u32 *tp_addr; 729 730 /* Cached tail pointer */ 731 u32 cached_tp; 732 733 /* Head pointer location to be updated by SW - This 734 * will be a register address and need not be accessed 735 * through SW structure 736 */ 737 u32 *hp_addr; 738 739 /* Low threshold - in number of ring entries */ 740 u32 low_threshold; 741 742 /* tail pointer at access end */ 743 u32 last_tp; 744 } src_ring; 745 } u; 746 }; 747 748 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 749 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 750 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 751 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 752 753 /* Interrupt mitigation - timer threshold in us */ 754 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 755 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 756 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 757 758 enum hal_srng_mac_type { 759 ATH12K_HAL_SRNG_UMAC, 760 ATH12K_HAL_SRNG_DMAC, 761 ATH12K_HAL_SRNG_PMAC 762 }; 763 764 /* HW SRNG configuration table */ 765 struct hal_srng_config { 766 int start_ring_id; 767 u16 max_rings; 768 u16 entry_size; 769 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 770 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 771 enum hal_srng_mac_type mac_type; 772 enum hal_srng_dir ring_dir; 773 u32 max_size; 774 }; 775 776 /** 777 * enum hal_rx_buf_return_buf_manager - manager for returned rx buffers 778 * 779 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 780 * @HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST: Descriptor returned to WBM idle 781 * descriptor list, where the device 0 WBM is chosen in case of a multi-device config 782 * @HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST: Descriptor returned to WBM idle 783 * descriptor list, where the device 1 WBM is chosen in case of a multi-device config 784 * @HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST: Descriptor returned to WBM idle 785 * descriptor list, where the device 2 WBM is chosen in case of a multi-device config 786 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 787 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host 788 * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host 789 * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host 790 * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host 791 * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host 792 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host 793 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host 794 */ 795 796 enum hal_rx_buf_return_buf_manager { 797 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 798 HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST, 799 HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST, 800 HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST, 801 HAL_RX_BUF_RBM_FW_BM, 802 HAL_RX_BUF_RBM_SW0_BM, 803 HAL_RX_BUF_RBM_SW1_BM, 804 HAL_RX_BUF_RBM_SW2_BM, 805 HAL_RX_BUF_RBM_SW3_BM, 806 HAL_RX_BUF_RBM_SW4_BM, 807 HAL_RX_BUF_RBM_SW5_BM, 808 HAL_RX_BUF_RBM_SW6_BM, 809 }; 810 811 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 812 813 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 814 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 815 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 816 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 817 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 818 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 819 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 820 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 821 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 822 823 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */ 824 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 825 #define HAL_REO_CMD_UPD0_VLD BIT(9) 826 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 827 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 828 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 829 #define HAL_REO_CMD_UPD0_AC BIT(13) 830 #define HAL_REO_CMD_UPD0_BAR BIT(14) 831 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 832 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 833 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 834 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 835 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 836 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 837 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 838 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 839 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 840 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 841 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 842 #define HAL_REO_CMD_UPD0_SSN BIT(26) 843 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 844 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 845 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 846 #define HAL_REO_CMD_UPD0_PN BIT(30) 847 848 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */ 849 #define HAL_REO_CMD_UPD1_VLD BIT(16) 850 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 851 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 852 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 853 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 854 #define HAL_REO_CMD_UPD1_BAR BIT(23) 855 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 856 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 857 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 858 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 859 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 860 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 861 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 862 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 863 864 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */ 865 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 866 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 867 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 868 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 869 870 struct ath12k_hal_reo_cmd { 871 u32 addr_lo; 872 u32 flag; 873 u32 upd0; 874 u32 upd1; 875 u32 upd2; 876 u32 pn[4]; 877 u16 rx_queue_num; 878 u16 min_rel; 879 u16 min_fwd; 880 u8 addr_hi; 881 u8 ac_list; 882 u8 blocking_idx; 883 u16 ba_window_size; 884 u8 pn_size; 885 }; 886 887 enum hal_pn_type { 888 HAL_PN_TYPE_NONE, 889 HAL_PN_TYPE_WPA, 890 HAL_PN_TYPE_WAPI_EVEN, 891 HAL_PN_TYPE_WAPI_UNEVEN, 892 }; 893 894 enum hal_ce_desc { 895 HAL_CE_DESC_SRC, 896 HAL_CE_DESC_DST, 897 HAL_CE_DESC_DST_STATUS, 898 }; 899 900 #define HAL_HASH_ROUTING_RING_TCL 0 901 #define HAL_HASH_ROUTING_RING_SW1 1 902 #define HAL_HASH_ROUTING_RING_SW2 2 903 #define HAL_HASH_ROUTING_RING_SW3 3 904 #define HAL_HASH_ROUTING_RING_SW4 4 905 #define HAL_HASH_ROUTING_RING_REL 5 906 #define HAL_HASH_ROUTING_RING_FW 6 907 908 struct hal_reo_status_header { 909 u16 cmd_num; 910 enum hal_reo_cmd_status cmd_status; 911 u16 cmd_exe_time; 912 u32 timestamp; 913 }; 914 915 struct hal_reo_status_queue_stats { 916 u16 ssn; 917 u16 curr_idx; 918 u32 pn[4]; 919 u32 last_rx_queue_ts; 920 u32 last_rx_dequeue_ts; 921 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 922 u32 curr_mpdu_cnt; 923 u32 curr_msdu_cnt; 924 u16 fwd_due_to_bar_cnt; 925 u16 dup_cnt; 926 u32 frames_in_order_cnt; 927 u32 num_mpdu_processed_cnt; 928 u32 num_msdu_processed_cnt; 929 u32 total_num_processed_byte_cnt; 930 u32 late_rx_mpdu_cnt; 931 u32 reorder_hole_cnt; 932 u8 timeout_cnt; 933 u8 bar_rx_cnt; 934 u8 num_window_2k_jump_cnt; 935 }; 936 937 struct hal_reo_status_flush_queue { 938 bool err_detected; 939 }; 940 941 enum hal_reo_status_flush_cache_err_code { 942 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 943 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 944 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 945 }; 946 947 struct hal_reo_status_flush_cache { 948 bool err_detected; 949 enum hal_reo_status_flush_cache_err_code err_code; 950 bool cache_controller_flush_status_hit; 951 u8 cache_controller_flush_status_desc_type; 952 u8 cache_controller_flush_status_client_id; 953 u8 cache_controller_flush_status_err; 954 u8 cache_controller_flush_status_cnt; 955 }; 956 957 enum hal_reo_status_unblock_cache_type { 958 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 959 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 960 }; 961 962 struct hal_reo_status_unblock_cache { 963 bool err_detected; 964 enum hal_reo_status_unblock_cache_type unblock_type; 965 }; 966 967 struct hal_reo_status_flush_timeout_list { 968 bool err_detected; 969 bool list_empty; 970 u16 release_desc_cnt; 971 u16 fwd_buf_cnt; 972 }; 973 974 enum hal_reo_threshold_idx { 975 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 976 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 977 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 978 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 979 }; 980 981 struct hal_reo_status_desc_thresh_reached { 982 enum hal_reo_threshold_idx threshold_idx; 983 u32 link_desc_counter0; 984 u32 link_desc_counter1; 985 u32 link_desc_counter2; 986 u32 link_desc_counter_sum; 987 }; 988 989 struct hal_reo_status { 990 struct hal_reo_status_header uniform_hdr; 991 u8 loop_cnt; 992 union { 993 struct hal_reo_status_queue_stats queue_stats; 994 struct hal_reo_status_flush_queue flush_queue; 995 struct hal_reo_status_flush_cache flush_cache; 996 struct hal_reo_status_unblock_cache unblock_cache; 997 struct hal_reo_status_flush_timeout_list timeout_list; 998 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 999 } u; 1000 }; 1001 1002 /* HAL context to be used to access SRNG APIs (currently used by data path 1003 * and transport (CE) modules) 1004 */ 1005 struct ath12k_hal { 1006 /* HAL internal state for all SRNG rings. 1007 */ 1008 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 1009 1010 /* SRNG configuration table */ 1011 struct hal_srng_config *srng_config; 1012 1013 /* Remote pointer memory for HW/FW updates */ 1014 struct { 1015 u32 *vaddr; 1016 dma_addr_t paddr; 1017 } rdp; 1018 1019 /* Shared memory for ring pointer updates from host to FW */ 1020 struct { 1021 u32 *vaddr; 1022 dma_addr_t paddr; 1023 } wrp; 1024 1025 /* Available REO blocking resources bitmap */ 1026 u8 avail_blk_resource; 1027 1028 u8 current_blk_index; 1029 1030 /* shadow register configuration */ 1031 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS]; 1032 int num_shadow_reg_configured; 1033 1034 u32 hal_desc_sz; 1035 }; 1036 1037 /* Maps WBM ring number and Return Buffer Manager Id per TCL ring */ 1038 struct ath12k_hal_tcl_to_wbm_rbm_map { 1039 u8 wbm_ring_num; 1040 u8 rbm_id; 1041 }; 1042 1043 struct hal_rx_ops { 1044 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc); 1045 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc); 1046 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc); 1047 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc); 1048 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc); 1049 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc); 1050 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc); 1051 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc); 1052 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc); 1053 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc); 1054 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc); 1055 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc); 1056 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc); 1057 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc); 1058 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc); 1059 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc); 1060 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc); 1061 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc); 1062 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc); 1063 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc); 1064 void (*rx_desc_copy_end_tlv)(struct hal_rx_desc *fdesc, 1065 struct hal_rx_desc *ldesc); 1066 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc); 1067 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc); 1068 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len); 1069 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc); 1070 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); 1071 u32 (*rx_desc_get_mpdu_start_offset)(void); 1072 u32 (*rx_desc_get_msdu_end_offset)(void); 1073 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc); 1074 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc); 1075 bool (*rx_desc_is_da_mcbc)(struct hal_rx_desc *desc); 1076 void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc, 1077 struct ieee80211_hdr *hdr); 1078 void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc, 1079 u8 *crypto_hdr, 1080 enum hal_encrypt_type enctype); 1081 bool (*dp_rx_h_msdu_done)(struct hal_rx_desc *desc); 1082 bool (*dp_rx_h_l4_cksum_fail)(struct hal_rx_desc *desc); 1083 bool (*dp_rx_h_ip_cksum_fail)(struct hal_rx_desc *desc); 1084 bool (*dp_rx_h_is_decrypted)(struct hal_rx_desc *desc); 1085 u32 (*dp_rx_h_mpdu_err)(struct hal_rx_desc *desc); 1086 u32 (*rx_desc_get_desc_size)(void); 1087 u8 (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc); 1088 }; 1089 1090 struct hal_ops { 1091 int (*create_srng_config)(struct ath12k_base *ab); 1092 u16 (*rxdma_ring_wmask_rx_mpdu_start)(void); 1093 u32 (*rxdma_ring_wmask_rx_msdu_end)(void); 1094 const struct hal_rx_ops *(*get_hal_rx_compact_ops)(void); 1095 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; 1096 }; 1097 1098 extern const struct hal_ops hal_qcn9274_ops; 1099 extern const struct hal_ops hal_wcn7850_ops; 1100 1101 extern const struct hal_rx_ops hal_rx_qcn9274_ops; 1102 extern const struct hal_rx_ops hal_rx_qcn9274_compact_ops; 1103 extern const struct hal_rx_ops hal_rx_wcn7850_ops; 1104 1105 u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 1106 void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, 1107 int tid, u32 ba_window_size, 1108 u32 start_seq, enum hal_pn_type type); 1109 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, 1110 struct hal_srng *srng); 1111 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map); 1112 void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab, 1113 struct hal_wbm_idle_scatter_list *sbuf, 1114 u32 nsbufs, u32 tot_link_desc, 1115 u32 end_offset); 1116 1117 dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab, 1118 struct hal_srng *srng); 1119 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab, 1120 struct hal_srng *srng); 1121 void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 1122 dma_addr_t paddr, 1123 enum hal_rx_buf_return_buf_manager rbm); 1124 u32 ath12k_hal_ce_get_desc_size(enum hal_ce_desc type); 1125 void ath12k_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, dma_addr_t paddr, 1126 u32 len, u32 id, u8 byte_swap_data); 1127 void ath12k_hal_ce_dst_set_desc(struct hal_ce_srng_dest_desc *desc, dma_addr_t paddr); 1128 u32 ath12k_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc); 1129 int ath12k_hal_srng_get_entrysize(struct ath12k_base *ab, u32 ring_type); 1130 int ath12k_hal_srng_get_max_entries(struct ath12k_base *ab, u32 ring_type); 1131 void ath12k_hal_srng_get_params(struct ath12k_base *ab, struct hal_srng *srng, 1132 struct hal_srng_params *params); 1133 void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab, 1134 struct hal_srng *srng); 1135 void *ath12k_hal_srng_dst_peek(struct ath12k_base *ab, struct hal_srng *srng); 1136 int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1137 bool sync_hw_ptr); 1138 void *ath12k_hal_srng_src_get_next_reaped(struct ath12k_base *ab, 1139 struct hal_srng *srng); 1140 void *ath12k_hal_srng_src_reap_next(struct ath12k_base *ab, 1141 struct hal_srng *srng); 1142 void *ath12k_hal_srng_src_get_next_entry(struct ath12k_base *ab, 1143 struct hal_srng *srng); 1144 int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng, 1145 bool sync_hw_ptr); 1146 void ath12k_hal_srng_access_begin(struct ath12k_base *ab, 1147 struct hal_srng *srng); 1148 void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng); 1149 int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type, 1150 int ring_num, int mac_id, 1151 struct hal_srng_params *params); 1152 int ath12k_hal_srng_init(struct ath12k_base *ath12k); 1153 void ath12k_hal_srng_deinit(struct ath12k_base *ath12k); 1154 void ath12k_hal_dump_srng_stats(struct ath12k_base *ab); 1155 void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab, 1156 u32 **cfg, u32 *len); 1157 int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab, 1158 enum hal_ring_type ring_type, 1159 int ring_num); 1160 void ath12k_hal_srng_shadow_config(struct ath12k_base *ab); 1161 void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, 1162 struct hal_srng *srng); 1163 #endif 1164