1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HAL_RX_H
8 #define ATH12K_HAL_RX_H
9
10 struct hal_rx_wbm_rel_info {
11 u32 cookie;
12 enum hal_wbm_rel_src_module err_rel_src;
13 enum hal_reo_dest_ring_push_reason push_reason;
14 u32 err_code;
15 bool first_msdu;
16 bool last_msdu;
17 bool continuation;
18 void *rx_desc;
19 bool hw_cc_done;
20 };
21
22 #define HAL_INVALID_PEERID 0xffff
23 #define VHT_SIG_SU_NSS_MASK 0x7
24
25 #define HAL_RX_MAX_MCS 12
26 #define HAL_RX_MAX_NSS 8
27
28 #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
29 le32_get_bits((__val), GENMASK(7, 0))
30
31 #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
32 le32_get_bits((__val), GENMASK(15, 8))
33
34 #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
35 le32_get_bits((__val), GENMASK(23, 16))
36
37 #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
38 le32_get_bits((__val), GENMASK(31, 24))
39
40 struct hal_rx_mon_status_tlv_hdr {
41 u32 hdr;
42 u8 value[];
43 };
44
45 enum hal_rx_su_mu_coding {
46 HAL_RX_SU_MU_CODING_BCC,
47 HAL_RX_SU_MU_CODING_LDPC,
48 HAL_RX_SU_MU_CODING_MAX,
49 };
50
51 enum hal_rx_gi {
52 HAL_RX_GI_0_8_US,
53 HAL_RX_GI_0_4_US,
54 HAL_RX_GI_1_6_US,
55 HAL_RX_GI_3_2_US,
56 HAL_RX_GI_MAX,
57 };
58
59 enum hal_rx_bw {
60 HAL_RX_BW_20MHZ,
61 HAL_RX_BW_40MHZ,
62 HAL_RX_BW_80MHZ,
63 HAL_RX_BW_160MHZ,
64 HAL_RX_BW_320MHZ,
65 HAL_RX_BW_MAX,
66 };
67
68 enum hal_rx_preamble {
69 HAL_RX_PREAMBLE_11A,
70 HAL_RX_PREAMBLE_11B,
71 HAL_RX_PREAMBLE_11N,
72 HAL_RX_PREAMBLE_11AC,
73 HAL_RX_PREAMBLE_11AX,
74 HAL_RX_PREAMBLE_MAX,
75 };
76
77 enum hal_rx_reception_type {
78 HAL_RX_RECEPTION_TYPE_SU,
79 HAL_RX_RECEPTION_TYPE_MU_MIMO,
80 HAL_RX_RECEPTION_TYPE_MU_OFDMA,
81 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
82 HAL_RX_RECEPTION_TYPE_MAX,
83 };
84
85 enum hal_rx_legacy_rate {
86 HAL_RX_LEGACY_RATE_1_MBPS,
87 HAL_RX_LEGACY_RATE_2_MBPS,
88 HAL_RX_LEGACY_RATE_5_5_MBPS,
89 HAL_RX_LEGACY_RATE_6_MBPS,
90 HAL_RX_LEGACY_RATE_9_MBPS,
91 HAL_RX_LEGACY_RATE_11_MBPS,
92 HAL_RX_LEGACY_RATE_12_MBPS,
93 HAL_RX_LEGACY_RATE_18_MBPS,
94 HAL_RX_LEGACY_RATE_24_MBPS,
95 HAL_RX_LEGACY_RATE_36_MBPS,
96 HAL_RX_LEGACY_RATE_48_MBPS,
97 HAL_RX_LEGACY_RATE_54_MBPS,
98 HAL_RX_LEGACY_RATE_INVALID,
99 };
100
101 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
102 #define HAL_TLV_STATUS_PPDU_DONE 1
103 #define HAL_TLV_STATUS_BUF_DONE 2
104 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
105 #define HAL_RX_FCS_LEN 4
106
107 enum hal_rx_mon_status {
108 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
109 HAL_RX_MON_STATUS_PPDU_DONE,
110 HAL_RX_MON_STATUS_BUF_DONE,
111 };
112
113 #define HAL_RX_MAX_MPDU 256
114 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5)
115
116 struct hal_rx_user_status {
117 u32 mcs:4,
118 nss:3,
119 ofdma_info_valid:1,
120 ul_ofdma_ru_start_index:7,
121 ul_ofdma_ru_width:7,
122 ul_ofdma_ru_size:8;
123 u32 ul_ofdma_user_v0_word0;
124 u32 ul_ofdma_user_v0_word1;
125 u32 ast_index;
126 u32 tid;
127 u16 tcp_msdu_count;
128 u16 tcp_ack_msdu_count;
129 u16 udp_msdu_count;
130 u16 other_msdu_count;
131 u16 frame_control;
132 u8 frame_control_info_valid;
133 u8 data_sequence_control_info_valid;
134 u16 first_data_seq_ctrl;
135 u32 preamble_type;
136 u16 ht_flags;
137 u16 vht_flags;
138 u16 he_flags;
139 u8 rs_flags;
140 u8 ldpc;
141 u32 mpdu_cnt_fcs_ok;
142 u32 mpdu_cnt_fcs_err;
143 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
144 u32 mpdu_ok_byte_count;
145 u32 mpdu_err_byte_count;
146 bool ampdu_present;
147 u16 ampdu_id;
148 };
149
150 #define HAL_MAX_UL_MU_USERS 37
151
152 struct hal_rx_mon_ppdu_info {
153 u32 ppdu_id;
154 u32 last_ppdu_id;
155 u64 ppdu_ts;
156 u32 num_mpdu_fcs_ok;
157 u32 num_mpdu_fcs_err;
158 u32 preamble_type;
159 u32 mpdu_len;
160 u16 chan_num;
161 u16 tcp_msdu_count;
162 u16 tcp_ack_msdu_count;
163 u16 udp_msdu_count;
164 u16 other_msdu_count;
165 u16 peer_id;
166 u8 rate;
167 u8 mcs;
168 u8 nss;
169 u8 bw;
170 u8 vht_flag_values1;
171 u8 vht_flag_values2;
172 u8 vht_flag_values3[4];
173 u8 vht_flag_values4;
174 u8 vht_flag_values5;
175 u16 vht_flag_values6;
176 u8 is_stbc;
177 u8 gi;
178 u8 sgi;
179 u8 ldpc;
180 u8 beamformed;
181 u8 rssi_comb;
182 u16 tid;
183 u8 fc_valid;
184 u16 ht_flags;
185 u16 vht_flags;
186 u16 he_flags;
187 u16 he_mu_flags;
188 u8 dcm;
189 u8 ru_alloc;
190 u8 reception_type;
191 u64 tsft;
192 u64 rx_duration;
193 u16 frame_control;
194 u32 ast_index;
195 u8 rs_fcs_err;
196 u8 rs_flags;
197 u8 cck_flag;
198 u8 ofdm_flag;
199 u8 ulofdma_flag;
200 u8 frame_control_info_valid;
201 u16 he_per_user_1;
202 u16 he_per_user_2;
203 u8 he_per_user_position;
204 u8 he_per_user_known;
205 u16 he_flags1;
206 u16 he_flags2;
207 u8 he_RU[4];
208 u16 he_data1;
209 u16 he_data2;
210 u16 he_data3;
211 u16 he_data4;
212 u16 he_data5;
213 u16 he_data6;
214 u32 ppdu_len;
215 u32 prev_ppdu_id;
216 u32 device_id;
217 u16 first_data_seq_ctrl;
218 u8 monitor_direct_used;
219 u8 data_sequence_control_info_valid;
220 u8 ltf_size;
221 u8 rxpcu_filter_pass;
222 s8 rssi_chain[8][8];
223 u32 num_users;
224 u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
225 u8 addr1[ETH_ALEN];
226 u8 addr2[ETH_ALEN];
227 u8 addr3[ETH_ALEN];
228 u8 addr4[ETH_ALEN];
229 struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
230 u8 userid;
231 bool first_msdu_in_mpdu;
232 bool is_ampdu;
233 u8 medium_prot_type;
234 };
235
236 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
237
238 struct hal_rx_ppdu_start {
239 __le32 info0;
240 __le32 chan_num;
241 __le32 ppdu_start_ts;
242 } __packed;
243
244 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)
245
246 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)
247 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
248 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
249 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
250 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)
251
252 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
253 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
254
255 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
256
257 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
258 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
259
260 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
261 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
262
263 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
264 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
265
266 #define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT GENMASK(24, 0)
267 #define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT GENMASK(24, 0)
268
269 struct hal_rx_ppdu_end_user_stats {
270 __le32 rsvd0[2];
271 __le32 info0;
272 __le32 info1;
273 __le32 info2;
274 __le32 info3;
275 __le32 ht_ctrl;
276 __le32 rsvd1[2];
277 __le32 info4;
278 __le32 info5;
279 __le32 usr_resp_ref;
280 __le32 info6;
281 __le32 rsvd3[4];
282 __le32 mpdu_ok_cnt;
283 __le32 rsvd4;
284 __le32 mpdu_err_cnt;
285 __le32 rsvd5[2];
286 __le32 usr_resp_ref_ext;
287 __le32 rsvd6;
288 } __packed;
289
290 struct hal_rx_ppdu_end_user_stats_ext {
291 __le32 info0;
292 __le32 info1;
293 __le32 info2;
294 __le32 info3;
295 __le32 info4;
296 __le32 info5;
297 __le32 info6;
298 } __packed;
299
300 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
301 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
302
303 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
304 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
305 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
306
307 struct hal_rx_ht_sig_info {
308 __le32 info0;
309 __le32 info1;
310 } __packed;
311
312 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
313 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
314
315 struct hal_rx_lsig_b_info {
316 __le32 info0;
317 } __packed;
318
319 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
320 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
321 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
322
323 struct hal_rx_lsig_a_info {
324 __le32 info0;
325 } __packed;
326
327 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
328 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
329 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
330 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
331
332 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
333 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
334 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
335 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
336
337 struct hal_rx_vht_sig_a_info {
338 __le32 info0;
339 __le32 info1;
340 } __packed;
341
342 enum hal_rx_vht_sig_a_gi_setting {
343 HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
344 HAL_RX_VHT_SIG_A_SHORT_GI = 1,
345 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
346 };
347
348 #define HE_GI_0_8 0
349 #define HE_GI_0_4 1
350 #define HE_GI_1_6 2
351 #define HE_GI_3_2 3
352
353 #define HE_LTF_1_X 0
354 #define HE_LTF_2_X 1
355 #define HE_LTF_4_X 2
356
357 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
358 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
359 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
360 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
361 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
362 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
363 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
364 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
365 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
366 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
367
368 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
369 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
370 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
371 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
372 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
373 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
374 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
375 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
376
377 struct hal_rx_he_sig_a_su_info {
378 __le32 info0;
379 __le32 info1;
380 } __packed;
381
382 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1)
383 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1)
384 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4)
385 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)
386 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11)
387 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15)
388 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
389 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22)
390 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23)
391 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25)
392
393 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0)
394 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING BIT(7)
395 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
396 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11)
397 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12)
398 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF BIT(10)
399 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
400 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15)
401
402 struct hal_rx_he_sig_a_mu_dl_info {
403 __le32 info0;
404 __le32 info1;
405 } __packed;
406
407 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
408
409 struct hal_rx_he_sig_b1_mu_info {
410 __le32 info0;
411 } __packed;
412
413 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
414 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
415 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
416 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
417
418 struct hal_rx_he_sig_b2_mu_info {
419 __le32 info0;
420 } __packed;
421
422 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
423 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
424 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19)
425 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
426 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
427 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
428
429 struct hal_rx_he_sig_b2_ofdma_info {
430 __le32 info0;
431 } __packed;
432
433 enum hal_rx_ul_reception_type {
434 HAL_RECEPTION_TYPE_ULOFMDA,
435 HAL_RECEPTION_TYPE_ULMIMO,
436 HAL_RECEPTION_TYPE_OTHER,
437 HAL_RECEPTION_TYPE_FRAMELESS
438 };
439
440 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB GENMASK(15, 8)
441 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION GENMASK(3, 0)
442
443 struct hal_rx_phyrx_rssi_legacy_info {
444 __le32 rsvd[35];
445 __le32 info0;
446 } __packed;
447
448 #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16)
449 #define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(31, 16)
450 #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0)
451 struct hal_rx_mpdu_start {
452 __le32 info0;
453 __le32 info1;
454 __le32 rsvd1[11];
455 __le32 info2;
456 __le32 rsvd2[9];
457 } __packed;
458
459 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
460 struct hal_rx_ppdu_end_duration {
461 __le32 rsvd0[9];
462 __le32 info0;
463 __le32 rsvd1[4];
464 } __packed;
465
466 struct hal_rx_rxpcu_classification_overview {
467 u32 rsvd0;
468 } __packed;
469
470 struct hal_rx_msdu_desc_info {
471 u32 msdu_flags;
472 u16 msdu_len; /* 14 bits for length */
473 };
474
475 #define HAL_RX_NUM_MSDU_DESC 6
476 struct hal_rx_msdu_list {
477 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
478 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
479 u8 rbm[HAL_RX_NUM_MSDU_DESC];
480 };
481
482 #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0)
483 #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0)
484 #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16)
485 #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0)
486
487 struct hal_rx_frame_bitmap_ack {
488 __le32 reserved;
489 __le32 info0;
490 __le32 info1;
491 __le32 info2;
492 __le32 reserved1[10];
493 } __packed;
494
495 #define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0)
496 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16)
497 #define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0)
498 #define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21)
499 #define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25)
500 #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27)
501 #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28)
502 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29)
503 #define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0)
504 #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0)
505 #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0)
506 #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16)
507 #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0)
508
509 struct hal_rx_resp_req_info {
510 __le32 info0;
511 __le32 reserved[1];
512 __le32 info1;
513 __le32 info2;
514 __le32 reserved1[2];
515 __le32 info3;
516 __le32 info4;
517 __le32 info5;
518 __le32 reserved2[5];
519 } __packed;
520
521 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
522 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
523 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
524 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
525
526 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30)
527 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31)
528 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0)
529 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3)
530 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7)
531 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8)
532 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9)
533 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16)
534
535 /* HE Radiotap data1 Mask */
536 #define HE_SU_FORMAT_TYPE 0x0000
537 #define HE_EXT_SU_FORMAT_TYPE 0x0001
538 #define HE_MU_FORMAT_TYPE 0x0002
539 #define HE_TRIG_FORMAT_TYPE 0x0003
540 #define HE_BEAM_CHANGE_KNOWN 0x0008
541 #define HE_DL_UL_KNOWN 0x0010
542 #define HE_MCS_KNOWN 0x0020
543 #define HE_DCM_KNOWN 0x0040
544 #define HE_CODING_KNOWN 0x0080
545 #define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
546 #define HE_STBC_KNOWN 0x0200
547 #define HE_DATA_BW_RU_KNOWN 0x4000
548 #define HE_DOPPLER_KNOWN 0x8000
549 #define HE_BSS_COLOR_KNOWN 0x0004
550
551 /* HE Radiotap data2 Mask */
552 #define HE_GI_KNOWN 0x0002
553 #define HE_TXBF_KNOWN 0x0010
554 #define HE_PE_DISAMBIGUITY_KNOWN 0x0020
555 #define HE_TXOP_KNOWN 0x0040
556 #define HE_LTF_SYMBOLS_KNOWN 0x0004
557 #define HE_PRE_FEC_PADDING_KNOWN 0x0008
558 #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
559
560 /* HE radiotap data3 shift values */
561 #define HE_BEAM_CHANGE_SHIFT 6
562 #define HE_DL_UL_SHIFT 7
563 #define HE_TRANSMIT_MCS_SHIFT 8
564 #define HE_DCM_SHIFT 12
565 #define HE_CODING_SHIFT 13
566 #define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
567 #define HE_STBC_SHIFT 15
568
569 /* HE radiotap data4 shift values */
570 #define HE_STA_ID_SHIFT 4
571
572 /* HE radiotap data5 */
573 #define HE_GI_SHIFT 4
574 #define HE_LTF_SIZE_SHIFT 6
575 #define HE_LTF_SYM_SHIFT 8
576 #define HE_TXBF_SHIFT 14
577 #define HE_PE_DISAMBIGUITY_SHIFT 15
578 #define HE_PRE_FEC_PAD_SHIFT 12
579
580 /* HE radiotap data6 */
581 #define HE_DOPPLER_SHIFT 4
582 #define HE_TXOP_SHIFT 8
583
584 /* HE radiotap HE-MU flags1 */
585 #define HE_SIG_B_MCS_KNOWN 0x0010
586 #define HE_SIG_B_DCM_KNOWN 0x0040
587 #define HE_SIG_B_SYM_NUM_KNOWN 0x8000
588 #define HE_RU_0_KNOWN 0x0100
589 #define HE_RU_1_KNOWN 0x0200
590 #define HE_RU_2_KNOWN 0x0400
591 #define HE_RU_3_KNOWN 0x0800
592 #define HE_DCM_FLAG_1_SHIFT 5
593 #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
594 #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
595
596 /* HE radiotap HE-MU flags2 */
597 #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
598 #define HE_BW_KNOWN 0x0004
599 #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
600 #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
601 #define HE_NUM_SIG_B_FLAG_2_SHIFT 9
602 #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
603 #define HE_LTF_KNOWN 0x8000
604
605 /* HE radiotap per_user_1 */
606 #define HE_STA_SPATIAL_SHIFT 11
607 #define HE_TXBF_SHIFT 14
608 #define HE_RESERVED_SET_TO_1_SHIFT 19
609 #define HE_STA_CODING_SHIFT 20
610
611 /* HE radiotap per_user_2 */
612 #define HE_STA_MCS_SHIFT 4
613 #define HE_STA_DCM_SHIFT 5
614
615 /* HE radiotap per user known */
616 #define HE_USER_FIELD_POSITION_KNOWN 0x01
617 #define HE_STA_ID_PER_USER_KNOWN 0x02
618 #define HE_STA_NSTS_KNOWN 0x04
619 #define HE_STA_TX_BF_KNOWN 0x08
620 #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
621 #define HE_STA_MCS_KNOWN 0x20
622 #define HE_STA_DCM_KNOWN 0x40
623 #define HE_STA_CODING_KNOWN 0x80
624
625 #define HAL_RX_MPDU_ERR_FCS BIT(0)
626 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
627 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
628 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
629 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
630 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
631 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
632 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
633
634 static inline
ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)635 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
636 {
637 enum nl80211_he_ru_alloc ret;
638
639 switch (ru_tones) {
640 case RU_52:
641 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
642 break;
643 case RU_106:
644 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
645 break;
646 case RU_242:
647 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
648 break;
649 case RU_484:
650 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
651 break;
652 case RU_996:
653 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
654 break;
655 case RU_26:
656 fallthrough;
657 default:
658 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
659 break;
660 }
661 return ret;
662 }
663
664 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
665 struct hal_tlv_64_hdr *tlv,
666 struct hal_reo_status *status);
667 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
668 struct hal_tlv_64_hdr *tlv,
669 struct hal_reo_status *status);
670 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
671 struct hal_tlv_64_hdr *tlv,
672 struct hal_reo_status *status);
673 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
674 struct hal_tlv_64_hdr *tlv,
675 struct hal_reo_status *status);
676 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
677 struct hal_tlv_64_hdr *tlv,
678 struct hal_reo_status *status);
679 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
680 struct hal_tlv_64_hdr *tlv,
681 struct hal_reo_status *status);
682 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
683 struct hal_tlv_64_hdr *tlv,
684 struct hal_reo_status *status);
685 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
686 u32 *msdu_cookies,
687 enum hal_rx_buf_return_buf_manager *rbm);
688 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
689 struct hal_wbm_release_ring *dst_desc,
690 struct hal_wbm_release_ring *src_desc,
691 enum hal_wbm_rel_bm_act action);
692 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
693 dma_addr_t paddr, u32 cookie, u8 manager);
694 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
695 dma_addr_t *paddr,
696 u32 *cookie, u8 *rbm);
697 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
698 struct hal_reo_dest_ring *desc,
699 dma_addr_t *paddr, u32 *desc_bank);
700 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
701 struct hal_rx_wbm_rel_info *rel_info);
702 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
703 struct ath12k_buffer_addr *buff_addr,
704 dma_addr_t *paddr, u32 *cookie);
705
706 #endif
707