1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/etherdevice.h>
7 #include <linux/of.h>
8 #include <linux/hwmon.h>
9 #include <linux/hwmon-sysfs.h>
10 #include <linux/thermal.h>
11 #include "mt7996.h"
12 #include "mac.h"
13 #include "mcu.h"
14 #include "coredump.h"
15 #include "eeprom.h"
16
17 static const struct ieee80211_iface_limit if_limits[] = {
18 {
19 .max = 16,
20 .types = BIT(NL80211_IFTYPE_AP)
21 #ifdef CONFIG_MAC80211_MESH
22 | BIT(NL80211_IFTYPE_MESH_POINT)
23 #endif
24 }, {
25 .max = MT7996_MAX_INTERFACES,
26 .types = BIT(NL80211_IFTYPE_STATION)
27 }
28 };
29
30 static const struct ieee80211_iface_combination if_comb[] = {
31 {
32 .limits = if_limits,
33 .n_limits = ARRAY_SIZE(if_limits),
34 .max_interfaces = MT7996_MAX_INTERFACES,
35 .num_different_channels = 1,
36 .beacon_int_infra_match = true,
37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
38 BIT(NL80211_CHAN_WIDTH_20) |
39 BIT(NL80211_CHAN_WIDTH_40) |
40 BIT(NL80211_CHAN_WIDTH_80) |
41 BIT(NL80211_CHAN_WIDTH_160),
42 .beacon_int_min_gcd = 100,
43 }
44 };
45
mt7996_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)46 static ssize_t mt7996_thermal_temp_show(struct device *dev,
47 struct device_attribute *attr,
48 char *buf)
49 {
50 struct mt7996_phy *phy = dev_get_drvdata(dev);
51 int i = to_sensor_dev_attr(attr)->index;
52 int temperature;
53
54 switch (i) {
55 case 0:
56 temperature = mt7996_mcu_get_temperature(phy);
57 if (temperature < 0)
58 return temperature;
59 /* display in millidegree celcius */
60 return sprintf(buf, "%u\n", temperature * 1000);
61 case 1:
62 case 2:
63 return sprintf(buf, "%u\n",
64 phy->throttle_temp[i - 1] * 1000);
65 case 3:
66 return sprintf(buf, "%hhu\n", phy->throttle_state);
67 default:
68 return -EINVAL;
69 }
70 }
71
mt7996_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)72 static ssize_t mt7996_thermal_temp_store(struct device *dev,
73 struct device_attribute *attr,
74 const char *buf, size_t count)
75 {
76 struct mt7996_phy *phy = dev_get_drvdata(dev);
77 int ret, i = to_sensor_dev_attr(attr)->index;
78 long val;
79
80 ret = kstrtol(buf, 10, &val);
81 if (ret < 0)
82 return ret;
83
84 mutex_lock(&phy->dev->mt76.mutex);
85 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000);
86
87 /* add a safety margin ~10 */
88 if ((i - 1 == MT7996_CRIT_TEMP_IDX &&
89 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) ||
90 (i - 1 == MT7996_MAX_TEMP_IDX &&
91 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) {
92 dev_err(phy->dev->mt76.dev,
93 "temp1_max shall be 10 degrees higher than temp1_crit.");
94 mutex_unlock(&phy->dev->mt76.mutex);
95 return -EINVAL;
96 }
97
98 phy->throttle_temp[i - 1] = val;
99 mutex_unlock(&phy->dev->mt76.mutex);
100
101 ret = mt7996_mcu_set_thermal_protect(phy, true);
102 if (ret)
103 return ret;
104
105 return count;
106 }
107
108 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0);
109 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1);
110 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2);
111 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3);
112
113 static struct attribute *mt7996_hwmon_attrs[] = {
114 &sensor_dev_attr_temp1_input.dev_attr.attr,
115 &sensor_dev_attr_temp1_crit.dev_attr.attr,
116 &sensor_dev_attr_temp1_max.dev_attr.attr,
117 &sensor_dev_attr_throttle1.dev_attr.attr,
118 NULL,
119 };
120 ATTRIBUTE_GROUPS(mt7996_hwmon);
121
122 static int
mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)123 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
124 unsigned long *state)
125 {
126 *state = MT7996_CDEV_THROTTLE_MAX;
127
128 return 0;
129 }
130
131 static int
mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)132 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
133 unsigned long *state)
134 {
135 struct mt7996_phy *phy = cdev->devdata;
136
137 *state = phy->cdev_state;
138
139 return 0;
140 }
141
142 static int
mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)143 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
144 unsigned long state)
145 {
146 struct mt7996_phy *phy = cdev->devdata;
147 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state;
148 int ret;
149
150 if (state > MT7996_CDEV_THROTTLE_MAX) {
151 dev_err(phy->dev->mt76.dev,
152 "please specify a valid throttling state\n");
153 return -EINVAL;
154 }
155
156 if (state == phy->cdev_state)
157 return 0;
158
159 /* cooling_device convention: 0 = no cooling, more = more cooling
160 * mcu convention: 1 = max cooling, more = less cooling
161 */
162 ret = mt7996_mcu_set_thermal_throttling(phy, throttling);
163 if (ret)
164 return ret;
165
166 phy->cdev_state = state;
167
168 return 0;
169 }
170
171 static const struct thermal_cooling_device_ops mt7996_thermal_ops = {
172 .get_max_state = mt7996_thermal_get_max_throttle_state,
173 .get_cur_state = mt7996_thermal_get_cur_throttle_state,
174 .set_cur_state = mt7996_thermal_set_cur_throttle_state,
175 };
176
mt7996_unregister_thermal(struct mt7996_phy * phy)177 static void mt7996_unregister_thermal(struct mt7996_phy *phy)
178 {
179 struct wiphy *wiphy = phy->mt76->hw->wiphy;
180
181 if (!phy->cdev)
182 return;
183
184 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
185 thermal_cooling_device_unregister(phy->cdev);
186 }
187
mt7996_thermal_init(struct mt7996_phy * phy)188 static int mt7996_thermal_init(struct mt7996_phy *phy)
189 {
190 struct wiphy *wiphy = phy->mt76->hw->wiphy;
191 struct thermal_cooling_device *cdev;
192 struct device *hwmon;
193 const char *name;
194
195 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s",
196 wiphy_name(wiphy));
197
198 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops);
199 if (!IS_ERR(cdev)) {
200 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
201 "cooling_device") < 0)
202 thermal_cooling_device_unregister(cdev);
203 else
204 phy->cdev = cdev;
205 }
206
207 /* initialize critical/maximum high temperature */
208 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP;
209 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP;
210
211 if (!IS_REACHABLE(CONFIG_HWMON))
212 return 0;
213
214 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
215 mt7996_hwmon_groups);
216
217 if (IS_ERR(hwmon))
218 return PTR_ERR(hwmon);
219
220 return 0;
221 }
222
mt7996_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)223 static void mt7996_led_set_config(struct led_classdev *led_cdev,
224 u8 delay_on, u8 delay_off)
225 {
226 struct mt7996_dev *dev;
227 struct mt76_phy *mphy;
228 u32 val;
229
230 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
231 dev = container_of(mphy->dev, struct mt7996_dev, mt76);
232
233 /* select TX blink mode, 2: only data frames */
234 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2);
235
236 /* enable LED */
237 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
238
239 /* set LED Tx blink on/off time */
240 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
241 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
242 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val);
243
244 /* turn LED off */
245 if (delay_off == 0xff && delay_on == 0x0) {
246 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK;
247 } else {
248 /* control LED */
249 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
250 if (mphy->band_idx == MT_BAND1)
251 val |= MT_LED_CTRL_BLINK_BAND_SEL;
252 }
253
254 if (mphy->leds.al)
255 val |= MT_LED_CTRL_POLARITY;
256
257 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
258 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
259 }
260
mt7996_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)261 static int mt7996_led_set_blink(struct led_classdev *led_cdev,
262 unsigned long *delay_on,
263 unsigned long *delay_off)
264 {
265 u16 delta_on = 0, delta_off = 0;
266
267 #define HW_TICK 10
268 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
269
270 if (*delay_on)
271 delta_on = TO_HW_TICK(*delay_on);
272 if (*delay_off)
273 delta_off = TO_HW_TICK(*delay_off);
274
275 mt7996_led_set_config(led_cdev, delta_on, delta_off);
276
277 return 0;
278 }
279
mt7996_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)280 static void mt7996_led_set_brightness(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282 {
283 if (!brightness)
284 mt7996_led_set_config(led_cdev, 0, 0xff);
285 else
286 mt7996_led_set_config(led_cdev, 0xff, 0);
287 }
288
__mt7996_init_txpower(struct mt7996_phy * phy,struct ieee80211_supported_band * sband)289 static void __mt7996_init_txpower(struct mt7996_phy *phy,
290 struct ieee80211_supported_band *sband)
291 {
292 struct mt7996_dev *dev = phy->dev;
293 int i, nss = hweight16(phy->mt76->chainmask);
294 int nss_delta = mt76_tx_power_nss_delta(nss);
295 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band);
296 struct mt76_power_limits limits;
297
298 for (i = 0; i < sband->n_channels; i++) {
299 struct ieee80211_channel *chan = &sband->channels[i];
300 int target_power = mt7996_eeprom_get_target_power(dev, chan);
301
302 target_power += pwr_delta;
303 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
304 &limits,
305 target_power);
306 target_power += nss_delta;
307 target_power = DIV_ROUND_UP(target_power, 2);
308 chan->max_power = min_t(int, chan->max_reg_power,
309 target_power);
310 chan->orig_mpwr = target_power;
311 }
312 }
313
mt7996_init_txpower(struct mt7996_phy * phy)314 void mt7996_init_txpower(struct mt7996_phy *phy)
315 {
316 if (!phy)
317 return;
318
319 if (phy->mt76->cap.has_2ghz)
320 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband);
321 if (phy->mt76->cap.has_5ghz)
322 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband);
323 if (phy->mt76->cap.has_6ghz)
324 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband);
325 }
326
327 static void
mt7996_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)328 mt7996_regd_notifier(struct wiphy *wiphy,
329 struct regulatory_request *request)
330 {
331 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
332 struct mt7996_dev *dev = mt7996_hw_dev(hw);
333 struct mt7996_phy *phy = mt7996_hw_phy(hw);
334
335 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
336 dev->mt76.region = request->dfs_region;
337
338 if (dev->mt76.region == NL80211_DFS_UNSET)
339 mt7996_mcu_rdd_background_enable(phy, NULL);
340
341 mt7996_init_txpower(phy);
342
343 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
344 mt7996_dfs_init_radar_detector(phy);
345 }
346
347 static void
mt7996_init_wiphy(struct ieee80211_hw * hw,struct mtk_wed_device * wed)348 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed)
349 {
350 struct mt7996_phy *phy = mt7996_hw_phy(hw);
351 struct mt76_dev *mdev = &phy->dev->mt76;
352 struct wiphy *wiphy = hw->wiphy;
353 u16 max_subframes = phy->dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT :
354 IEEE80211_MAX_AMPDU_BUF_HE;
355
356 hw->queues = 4;
357 hw->max_rx_aggregation_subframes = max_subframes;
358 hw->max_tx_aggregation_subframes = max_subframes;
359 hw->netdev_features = NETIF_F_RXCSUM;
360 if (mtk_wed_device_active(wed))
361 hw->netdev_features |= NETIF_F_HW_TC;
362
363 hw->radiotap_timestamp.units_pos =
364 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
365
366 phy->slottime = 9;
367 phy->beacon_rate = -1;
368
369 hw->sta_data_size = sizeof(struct mt7996_sta);
370 hw->vif_data_size = sizeof(struct mt7996_vif);
371
372 wiphy->iface_combinations = if_comb;
373 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
374 wiphy->reg_notifier = mt7996_regd_notifier;
375 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
376 wiphy->mbssid_max_interfaces = 16;
377
378 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
379 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
380 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
381 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
382 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
383 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
384 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
385 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
386 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
387 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER);
389
390 if (!mdev->dev->of_node ||
391 !of_property_read_bool(mdev->dev->of_node,
392 "mediatek,disable-radar-background"))
393 wiphy_ext_feature_set(wiphy,
394 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
395
396 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
397 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
398 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
399 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
400 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
401
402 hw->max_tx_fragments = 4;
403
404 if (phy->mt76->cap.has_2ghz) {
405 phy->mt76->sband_2g.sband.ht_cap.cap |=
406 IEEE80211_HT_CAP_LDPC_CODING |
407 IEEE80211_HT_CAP_MAX_AMSDU;
408 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
409 IEEE80211_HT_MPDU_DENSITY_2;
410 }
411
412 if (phy->mt76->cap.has_5ghz) {
413 phy->mt76->sband_5g.sband.ht_cap.cap |=
414 IEEE80211_HT_CAP_LDPC_CODING |
415 IEEE80211_HT_CAP_MAX_AMSDU;
416
417 phy->mt76->sband_5g.sband.vht_cap.cap |=
418 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
419 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
420 IEEE80211_VHT_CAP_SHORT_GI_160 |
421 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
422 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
423 IEEE80211_HT_MPDU_DENSITY_1;
424
425 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
426 }
427
428 /* init led callbacks */
429 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
430 phy->mt76->leds.cdev.brightness_set = mt7996_led_set_brightness;
431 phy->mt76->leds.cdev.blink_set = mt7996_led_set_blink;
432 }
433
434 mt76_set_stream_caps(phy->mt76, true);
435 mt7996_set_stream_vht_txbf_caps(phy);
436 mt7996_set_stream_he_eht_caps(phy);
437 mt7996_init_txpower(phy);
438
439 wiphy->available_antennas_rx = phy->mt76->antenna_mask;
440 wiphy->available_antennas_tx = phy->mt76->antenna_mask;
441 }
442
443 static void
mt7996_mac_init_band(struct mt7996_dev * dev,u8 band)444 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band)
445 {
446 u32 mask, set;
447
448 /* clear estimated value of EIFS for Rx duration & OBSS time */
449 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
450
451 /* clear backoff time for Rx duration */
452 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
453 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
454 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
455 MT_WF_RMAC_MIB_QOS01_BACKOFF);
456 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
457 MT_WF_RMAC_MIB_QOS23_BACKOFF);
458
459 /* clear backoff time and set software compensation for OBSS time */
460 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
461 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
462 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
463 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
464
465 /* filter out non-resp frames and get instanstaeous signal reporting */
466 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM;
467 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) |
468 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3);
469 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set);
470
471 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
472 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
473 */
474 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
475 }
476
mt7996_mac_init_basic_rates(struct mt7996_dev * dev)477 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev)
478 {
479 int i;
480
481 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) {
482 u16 rate = mt76_rates[i].hw_value;
483 /* odd index for driver, even index for firmware */
484 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i;
485
486 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) |
487 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));
488 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false);
489 }
490 }
491
mt7996_mac_init(struct mt7996_dev * dev)492 void mt7996_mac_init(struct mt7996_dev *dev)
493 {
494 #define HIF_TXD_V2_1 0x21
495 int i;
496
497 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
498
499 for (i = 0; i < mt7996_wtbl_size(dev); i++)
500 mt7996_mac_wtbl_update(dev, i,
501 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
502
503 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
504 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
505 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
506 }
507
508 /* rro module init */
509 if (is_mt7996(&dev->mt76))
510 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
511 else
512 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
513 dev->hif2 ? 7 : 0);
514
515 if (dev->has_rro) {
516 u16 timeout;
517
518 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128;
519 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout);
520 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1);
521 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0);
522 } else {
523 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3);
524 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1);
525 }
526
527 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
528 MCU_WA_PARAM_HW_PATH_HIF_VER,
529 HIF_TXD_V2_1, 0);
530
531 for (i = MT_BAND0; i <= MT_BAND2; i++)
532 mt7996_mac_init_band(dev, i);
533
534 mt7996_mac_init_basic_rates(dev);
535 }
536
mt7996_txbf_init(struct mt7996_dev * dev)537 int mt7996_txbf_init(struct mt7996_dev *dev)
538 {
539 int ret;
540
541 if (mt7996_band_valid(dev, MT_BAND1) ||
542 mt7996_band_valid(dev, MT_BAND2)) {
543 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL);
544 if (ret)
545 return ret;
546 }
547
548 /* trigger sounding packets */
549 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON);
550 if (ret)
551 return ret;
552
553 /* enable eBF */
554 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);
555 }
556
mt7996_register_phy(struct mt7996_dev * dev,struct mt7996_phy * phy,enum mt76_band_id band)557 static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
558 enum mt76_band_id band)
559 {
560 struct mt76_phy *mphy;
561 u32 mac_ofs, hif1_ofs = 0;
562 int ret;
563 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
564
565 if (!mt7996_band_valid(dev, band) || band == MT_BAND0)
566 return 0;
567
568 if (phy)
569 return 0;
570
571 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) {
572 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
573 wed = &dev->mt76.mmio.wed_hif2;
574 }
575
576 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band);
577 if (!mphy)
578 return -ENOMEM;
579
580 phy = mphy->priv;
581 phy->dev = dev;
582 phy->mt76 = mphy;
583 mphy->dev->phys[band] = mphy;
584
585 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work);
586
587 ret = mt7996_eeprom_parse_hw_cap(dev, phy);
588 if (ret)
589 goto error;
590
591 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2;
592 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
593 /* Make the extra PHY MAC address local without overlapping with
594 * the usual MAC address allocation scheme on multiple virtual interfaces
595 */
596 if (!is_valid_ether_addr(mphy->macaddr)) {
597 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
598 ETH_ALEN);
599 mphy->macaddr[0] |= 2;
600 mphy->macaddr[0] ^= BIT(7);
601 if (band == MT_BAND2)
602 mphy->macaddr[0] ^= BIT(6);
603 }
604 mt76_eeprom_override(mphy);
605
606 /* init wiphy according to mphy and phy */
607 mt7996_init_wiphy(mphy->hw, wed);
608 ret = mt7996_init_tx_queues(mphy->priv,
609 MT_TXQ_ID(band),
610 MT7996_TX_RING_SIZE,
611 MT_TXQ_RING_BASE(band) + hif1_ofs,
612 wed);
613 if (ret)
614 goto error;
615
616 ret = mt76_register_phy(mphy, true, mt76_rates,
617 ARRAY_SIZE(mt76_rates));
618 if (ret)
619 goto error;
620
621 ret = mt7996_thermal_init(phy);
622 if (ret)
623 goto error;
624
625 ret = mt7996_init_debugfs(phy);
626 if (ret)
627 goto error;
628
629 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
630 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2;
631
632 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask);
633 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask);
634 }
635
636 return 0;
637
638 error:
639 mphy->dev->phys[band] = NULL;
640 ieee80211_free_hw(mphy->hw);
641 return ret;
642 }
643
644 static void
mt7996_unregister_phy(struct mt7996_phy * phy,enum mt76_band_id band)645 mt7996_unregister_phy(struct mt7996_phy *phy, enum mt76_band_id band)
646 {
647 struct mt76_phy *mphy;
648
649 if (!phy)
650 return;
651
652 mt7996_unregister_thermal(phy);
653
654 mphy = phy->dev->mt76.phys[band];
655 mt76_unregister_phy(mphy);
656 ieee80211_free_hw(mphy->hw);
657 phy->dev->mt76.phys[band] = NULL;
658 }
659
mt7996_init_work(struct work_struct * work)660 static void mt7996_init_work(struct work_struct *work)
661 {
662 struct mt7996_dev *dev = container_of(work, struct mt7996_dev,
663 init_work);
664
665 mt7996_mcu_set_eeprom(dev);
666 mt7996_mac_init(dev);
667 mt7996_txbf_init(dev);
668 }
669
mt7996_wfsys_reset(struct mt7996_dev * dev)670 void mt7996_wfsys_reset(struct mt7996_dev *dev)
671 {
672 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
673 msleep(20);
674
675 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
676 msleep(20);
677 }
678
mt7996_wed_rro_init(struct mt7996_dev * dev)679 static int mt7996_wed_rro_init(struct mt7996_dev *dev)
680 {
681 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
682 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
683 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0;
684 struct mt7996_wed_rro_addr *addr;
685 void *ptr;
686 int i;
687
688 if (!dev->has_rro)
689 return 0;
690
691 if (!mtk_wed_device_active(wed))
692 return 0;
693
694 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
695 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
696 MT7996_RRO_BA_BITMAP_CR_SIZE,
697 &dev->wed_rro.ba_bitmap[i].phy_addr,
698 GFP_KERNEL);
699 if (!ptr)
700 return -ENOMEM;
701
702 dev->wed_rro.ba_bitmap[i].ptr = ptr;
703 }
704
705 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
706 int j;
707
708 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
709 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr),
710 &dev->wed_rro.addr_elem[i].phy_addr,
711 GFP_KERNEL);
712 if (!ptr)
713 return -ENOMEM;
714
715 dev->wed_rro.addr_elem[i].ptr = ptr;
716 memset(dev->wed_rro.addr_elem[i].ptr, 0,
717 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr));
718
719 addr = dev->wed_rro.addr_elem[i].ptr;
720 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) {
721 addr->signature = 0xff;
722 addr++;
723 }
724
725 wed->wlan.ind_cmd.addr_elem_phys[i] =
726 dev->wed_rro.addr_elem[i].phy_addr;
727 }
728
729 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
730 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr),
731 &dev->wed_rro.session.phy_addr,
732 GFP_KERNEL);
733 if (!ptr)
734 return -ENOMEM;
735
736 dev->wed_rro.session.ptr = ptr;
737 addr = dev->wed_rro.session.ptr;
738 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
739 addr->signature = 0xff;
740 addr++;
741 }
742
743 /* rro hw init */
744 /* TODO: remove line after WM has set */
745 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK);
746
747 /* setup BA bitmap cache address */
748 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0,
749 dev->wed_rro.ba_bitmap[0].phy_addr);
750 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0);
751 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0,
752 dev->wed_rro.ba_bitmap[1].phy_addr);
753 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0);
754
755 /* setup Address element address */
756 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
757 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4);
758 reg += 4;
759 }
760
761 /* setup Address element address - separate address segment mode */
762 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1,
763 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE);
764
765 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6;
766 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION;
767 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr;
768 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN;
769 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL;
770
771 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00);
772 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1,
773 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN);
774
775 /* particular session configure */
776 /* use max session idx + 1 as particular session id */
777 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr);
778 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1,
779 MT_RRO_PARTICULAR_CONFG_EN |
780 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION));
781
782 /* interrupt enable */
783 mt76_wr(dev, MT_RRO_HOST_INT_ENA,
784 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA);
785
786 /* rro ind cmd queue init */
787 return mt7996_dma_rro_init(dev);
788 #else
789 return 0;
790 #endif
791 }
792
mt7996_wed_rro_free(struct mt7996_dev * dev)793 static void mt7996_wed_rro_free(struct mt7996_dev *dev)
794 {
795 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
796 int i;
797
798 if (!dev->has_rro)
799 return;
800
801 if (!mtk_wed_device_active(&dev->mt76.mmio.wed))
802 return;
803
804 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
805 if (!dev->wed_rro.ba_bitmap[i].ptr)
806 continue;
807
808 dmam_free_coherent(dev->mt76.dma_dev,
809 MT7996_RRO_BA_BITMAP_CR_SIZE,
810 dev->wed_rro.ba_bitmap[i].ptr,
811 dev->wed_rro.ba_bitmap[i].phy_addr);
812 }
813
814 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
815 if (!dev->wed_rro.addr_elem[i].ptr)
816 continue;
817
818 dmam_free_coherent(dev->mt76.dma_dev,
819 MT7996_RRO_WINDOW_MAX_SIZE *
820 sizeof(struct mt7996_wed_rro_addr),
821 dev->wed_rro.addr_elem[i].ptr,
822 dev->wed_rro.addr_elem[i].phy_addr);
823 }
824
825 if (!dev->wed_rro.session.ptr)
826 return;
827
828 dmam_free_coherent(dev->mt76.dma_dev,
829 MT7996_RRO_WINDOW_MAX_LEN *
830 sizeof(struct mt7996_wed_rro_addr),
831 dev->wed_rro.session.ptr,
832 dev->wed_rro.session.phy_addr);
833 #endif
834 }
835
mt7996_wed_rro_work(struct work_struct * work)836 static void mt7996_wed_rro_work(struct work_struct *work)
837 {
838 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
839 struct mt7996_dev *dev;
840 LIST_HEAD(list);
841
842 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev,
843 wed_rro.work);
844
845 spin_lock_bh(&dev->wed_rro.lock);
846 list_splice_init(&dev->wed_rro.poll_list, &list);
847 spin_unlock_bh(&dev->wed_rro.lock);
848
849 while (!list_empty(&list)) {
850 struct mt7996_wed_rro_session_id *e;
851 int i;
852
853 e = list_first_entry(&list, struct mt7996_wed_rro_session_id,
854 list);
855 list_del_init(&e->list);
856
857 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
858 void *ptr = dev->wed_rro.session.ptr;
859 struct mt7996_wed_rro_addr *elem;
860 u32 idx, elem_id = i;
861
862 if (e->id == MT7996_RRO_MAX_SESSION)
863 goto reset;
864
865 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE;
866 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem))
867 goto out;
868
869 ptr = dev->wed_rro.addr_elem[idx].ptr;
870 elem_id +=
871 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) *
872 MT7996_RRO_WINDOW_MAX_LEN;
873 reset:
874 elem = ptr + elem_id * sizeof(*elem);
875 elem->signature = 0xff;
876 }
877 mt7996_mcu_wed_rro_reset_sessions(dev, e->id);
878 out:
879 kfree(e);
880 }
881 #endif
882 }
883
mt7996_init_hardware(struct mt7996_dev * dev)884 static int mt7996_init_hardware(struct mt7996_dev *dev)
885 {
886 int ret, idx;
887
888 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
889 if (is_mt7992(&dev->mt76)) {
890 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
891 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
892 }
893
894 INIT_WORK(&dev->init_work, mt7996_init_work);
895 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work);
896 INIT_LIST_HEAD(&dev->wed_rro.poll_list);
897 spin_lock_init(&dev->wed_rro.lock);
898
899 ret = mt7996_dma_init(dev);
900 if (ret)
901 return ret;
902
903 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
904
905 ret = mt7996_mcu_init(dev);
906 if (ret)
907 return ret;
908
909 ret = mt7996_wed_rro_init(dev);
910 if (ret)
911 return ret;
912
913 ret = mt7996_eeprom_init(dev);
914 if (ret < 0)
915 return ret;
916
917 /* Beacon and mgmt frames should occupy wcid 0 */
918 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA);
919 if (idx)
920 return -ENOSPC;
921
922 dev->mt76.global_wcid.idx = idx;
923 dev->mt76.global_wcid.hw_key_idx = -1;
924 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
925 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
926
927 return 0;
928 }
929
mt7996_set_stream_vht_txbf_caps(struct mt7996_phy * phy)930 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy)
931 {
932 int sts;
933 u32 *cap;
934
935 if (!phy->mt76->cap.has_5ghz)
936 return;
937
938 sts = hweight16(phy->mt76->chainmask);
939 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
940
941 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
942 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
943
944 if (is_mt7996(phy->mt76->dev))
945 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3);
946 else
947 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4);
948
949 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
950 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
951 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
952
953 if (sts < 2)
954 return;
955
956 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
957 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
958 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1);
959 }
960
961 static void
mt7996_set_stream_he_txbf_caps(struct mt7996_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif)962 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
963 struct ieee80211_sta_he_cap *he_cap, int vif)
964 {
965 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
966 int sts = hweight16(phy->mt76->chainmask);
967 u8 c;
968
969 #ifdef CONFIG_MAC80211_MESH
970 if (vif == NL80211_IFTYPE_MESH_POINT)
971 return;
972 #endif
973
974 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
975 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
976
977 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
978 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
979 elem->phy_cap_info[5] &= ~c;
980
981 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
982 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
983 elem->phy_cap_info[6] &= ~c;
984
985 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
986
987 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
988 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
989 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
990 elem->phy_cap_info[2] |= c;
991
992 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
993
994 if (is_mt7996(phy->mt76->dev))
995 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
996 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
997 else
998 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 |
999 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5;
1000
1001 elem->phy_cap_info[4] |= c;
1002
1003 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
1004 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
1005 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
1006
1007 if (vif == NL80211_IFTYPE_STATION)
1008 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
1009
1010 elem->phy_cap_info[6] |= c;
1011
1012 if (sts < 2)
1013 return;
1014
1015 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
1016 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
1017
1018 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION))
1019 return;
1020
1021 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1022
1023 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1024 sts - 1) |
1025 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1026 sts - 1);
1027 elem->phy_cap_info[5] |= c;
1028
1029 if (vif != NL80211_IFTYPE_AP)
1030 return;
1031
1032 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1033
1034 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1035 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1036 elem->phy_cap_info[6] |= c;
1037
1038 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1039 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1040 elem->phy_cap_info[7] |= c;
1041 }
1042
1043 static void
mt7996_init_he_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1044 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band,
1045 struct ieee80211_sband_iftype_data *data,
1046 enum nl80211_iftype iftype)
1047 {
1048 struct ieee80211_sta_he_cap *he_cap = &data->he_cap;
1049 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem;
1050 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp;
1051 int i, nss = hweight8(phy->mt76->antenna_mask);
1052 u16 mcs_map = 0;
1053
1054 for (i = 0; i < 8; i++) {
1055 if (i < nss)
1056 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1057 else
1058 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1059 }
1060
1061 he_cap->has_he = true;
1062
1063 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
1064 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1065 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1066 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1067
1068 if (band == NL80211_BAND_2GHZ)
1069 he_cap_elem->phy_cap_info[0] =
1070 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1071 else
1072 he_cap_elem->phy_cap_info[0] =
1073 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1074 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1075
1076 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1077 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1078 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1079
1080 he_cap_elem->phy_cap_info[7] =
1081 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1082
1083 switch (iftype) {
1084 case NL80211_IFTYPE_AP:
1085 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES;
1086 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR;
1087 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR;
1088 he_cap_elem->mac_cap_info[5] |=
1089 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1090 he_cap_elem->phy_cap_info[3] |=
1091 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1092 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1093 he_cap_elem->phy_cap_info[6] |=
1094 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1095 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1096 he_cap_elem->phy_cap_info[9] |=
1097 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1098 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1099 break;
1100 case NL80211_IFTYPE_STATION:
1101 he_cap_elem->mac_cap_info[1] |=
1102 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1103
1104 if (band == NL80211_BAND_2GHZ)
1105 he_cap_elem->phy_cap_info[0] |=
1106 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1107 else
1108 he_cap_elem->phy_cap_info[0] |=
1109 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1110
1111 he_cap_elem->phy_cap_info[1] |=
1112 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1113 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1114 he_cap_elem->phy_cap_info[3] |=
1115 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1116 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1117 he_cap_elem->phy_cap_info[6] |=
1118 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1119 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1120 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1121 he_cap_elem->phy_cap_info[7] |=
1122 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP;
1123 he_cap_elem->phy_cap_info[8] |=
1124 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1125 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1126 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
1127 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1128 he_cap_elem->phy_cap_info[9] |=
1129 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1130 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1131 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1132 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1133 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1134 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1135 break;
1136 default:
1137 break;
1138 }
1139
1140 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1141 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1142 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map);
1143 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map);
1144
1145 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype);
1146
1147 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1148 if (he_cap_elem->phy_cap_info[6] &
1149 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1150 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss);
1151 } else {
1152 he_cap_elem->phy_cap_info[9] |=
1153 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1154 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1155 }
1156
1157 if (band == NL80211_BAND_6GHZ) {
1158 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1159 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1160
1161 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5,
1162 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1163 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1164 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1165 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1166 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1167
1168 data->he_6ghz_capa.capa = cpu_to_le16(cap);
1169 }
1170 }
1171
1172 static void
mt7996_init_eht_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1173 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
1174 struct ieee80211_sband_iftype_data *data,
1175 enum nl80211_iftype iftype)
1176 {
1177 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap;
1178 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem;
1179 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp;
1180 enum nl80211_chan_width width = phy->mt76->chandef.width;
1181 int nss = hweight8(phy->mt76->antenna_mask);
1182 int sts = hweight16(phy->mt76->chainmask);
1183 u8 val;
1184
1185 if (!phy->dev->has_eht)
1186 return;
1187
1188 eht_cap->has_eht = true;
1189
1190 eht_cap_elem->mac_cap_info[0] =
1191 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS |
1192 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
1193 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
1194 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
1195
1196 eht_cap_elem->mac_cap_info[1] |=
1197 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK;
1198
1199 eht_cap_elem->phy_cap_info[0] =
1200 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
1201 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
1202 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
1203
1204 /* Set the maximum capability regardless of the antenna configuration. */
1205 val = is_mt7992(phy->mt76->dev) ? 4 : 3;
1206 eht_cap_elem->phy_cap_info[0] |=
1207 u8_encode_bits(u8_get_bits(val, BIT(0)),
1208 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
1209
1210 eht_cap_elem->phy_cap_info[1] =
1211 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),
1212 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
1213 u8_encode_bits(val,
1214 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
1215
1216 eht_cap_elem->phy_cap_info[2] =
1217 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK) |
1218 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK);
1219
1220 if (band == NL80211_BAND_6GHZ) {
1221 eht_cap_elem->phy_cap_info[0] |=
1222 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
1223
1224 eht_cap_elem->phy_cap_info[1] |=
1225 u8_encode_bits(val,
1226 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
1227
1228 eht_cap_elem->phy_cap_info[2] |=
1229 u8_encode_bits(sts - 1,
1230 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
1231 }
1232
1233 eht_cap_elem->phy_cap_info[3] =
1234 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1235 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1236 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1237 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
1238
1239 eht_cap_elem->phy_cap_info[4] =
1240 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI |
1241 u8_encode_bits(min_t(int, sts - 1, 2),
1242 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
1243
1244 eht_cap_elem->phy_cap_info[5] =
1245 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
1246 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
1247 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),
1248 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK);
1249
1250 val = width == NL80211_CHAN_WIDTH_320 ? 0xf :
1251 width == NL80211_CHAN_WIDTH_160 ? 0x7 :
1252 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1;
1253 eht_cap_elem->phy_cap_info[6] =
1254 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK);
1255
1256 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
1257 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX);
1258 #define SET_EHT_MAX_NSS(_bw, _val) do { \
1259 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \
1260 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \
1261 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \
1262 } while (0)
1263
1264 SET_EHT_MAX_NSS(80, val);
1265 SET_EHT_MAX_NSS(160, val);
1266 if (band == NL80211_BAND_6GHZ)
1267 SET_EHT_MAX_NSS(320, val);
1268 #undef SET_EHT_MAX_NSS
1269
1270 if (iftype != NL80211_IFTYPE_AP)
1271 return;
1272
1273 eht_cap_elem->phy_cap_info[3] |=
1274 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
1275 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
1276
1277 eht_cap_elem->phy_cap_info[7] =
1278 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
1279 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
1280 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ |
1281 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ;
1282
1283 if (band != NL80211_BAND_6GHZ)
1284 return;
1285
1286 eht_cap_elem->phy_cap_info[7] |=
1287 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
1288 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
1289 }
1290
1291 static void
__mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy,struct ieee80211_supported_band * sband,enum nl80211_band band)1292 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy,
1293 struct ieee80211_supported_band *sband,
1294 enum nl80211_band band)
1295 {
1296 struct ieee80211_sband_iftype_data *data = phy->iftype[band];
1297 int i, n = 0;
1298
1299 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1300 switch (i) {
1301 case NL80211_IFTYPE_STATION:
1302 case NL80211_IFTYPE_AP:
1303 #ifdef CONFIG_MAC80211_MESH
1304 case NL80211_IFTYPE_MESH_POINT:
1305 #endif
1306 break;
1307 default:
1308 continue;
1309 }
1310
1311 data[n].types_mask = BIT(i);
1312 mt7996_init_he_caps(phy, band, &data[n], i);
1313 mt7996_init_eht_caps(phy, band, &data[n], i);
1314
1315 n++;
1316 }
1317
1318 _ieee80211_set_sband_iftype_data(sband, data, n);
1319 }
1320
mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy)1321 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy)
1322 {
1323 if (phy->mt76->cap.has_2ghz)
1324 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband,
1325 NL80211_BAND_2GHZ);
1326
1327 if (phy->mt76->cap.has_5ghz)
1328 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband,
1329 NL80211_BAND_5GHZ);
1330
1331 if (phy->mt76->cap.has_6ghz)
1332 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband,
1333 NL80211_BAND_6GHZ);
1334 }
1335
mt7996_register_device(struct mt7996_dev * dev)1336 int mt7996_register_device(struct mt7996_dev *dev)
1337 {
1338 struct ieee80211_hw *hw = mt76_hw(dev);
1339 int ret;
1340
1341 dev->phy.dev = dev;
1342 dev->phy.mt76 = &dev->mt76.phy;
1343 dev->mt76.phy.priv = &dev->phy;
1344 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work);
1345 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work);
1346 INIT_LIST_HEAD(&dev->sta_rc_list);
1347 INIT_LIST_HEAD(&dev->twt_list);
1348
1349 init_waitqueue_head(&dev->reset_wait);
1350 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work);
1351 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work);
1352 mutex_init(&dev->dump_mutex);
1353
1354 ret = mt7996_init_hardware(dev);
1355 if (ret)
1356 return ret;
1357
1358 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed);
1359
1360 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1361 ARRAY_SIZE(mt76_rates));
1362 if (ret)
1363 return ret;
1364
1365 ret = mt7996_thermal_init(&dev->phy);
1366 if (ret)
1367 return ret;
1368
1369 ret = mt7996_register_phy(dev, mt7996_phy2(dev), MT_BAND1);
1370 if (ret)
1371 return ret;
1372
1373 ret = mt7996_register_phy(dev, mt7996_phy3(dev), MT_BAND2);
1374 if (ret)
1375 return ret;
1376
1377 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1378
1379 dev->recovery.hw_init_done = true;
1380
1381 ret = mt7996_init_debugfs(&dev->phy);
1382 if (ret)
1383 goto error;
1384
1385 ret = mt7996_coredump_register(dev);
1386 if (ret)
1387 goto error;
1388
1389 return 0;
1390
1391 error:
1392 cancel_work_sync(&dev->init_work);
1393
1394 return ret;
1395 }
1396
mt7996_unregister_device(struct mt7996_dev * dev)1397 void mt7996_unregister_device(struct mt7996_dev *dev)
1398 {
1399 cancel_work_sync(&dev->wed_rro.work);
1400 mt7996_unregister_phy(mt7996_phy3(dev), MT_BAND2);
1401 mt7996_unregister_phy(mt7996_phy2(dev), MT_BAND1);
1402 mt7996_unregister_thermal(&dev->phy);
1403 mt7996_coredump_unregister(dev);
1404 mt76_unregister_device(&dev->mt76);
1405 mt7996_wed_rro_free(dev);
1406 mt7996_mcu_exit(dev);
1407 mt7996_tx_token_put(dev);
1408 mt7996_dma_cleanup(dev);
1409 tasklet_disable(&dev->mt76.irq_tasklet);
1410
1411 mt76_free_device(&dev->mt76);
1412 }
1413