1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #ifndef __MT7996_H
7 #define __MT7996_H
8
9 #include <linux/interrupt.h>
10 #include <linux/ktime.h>
11 #include "../mt76_connac.h"
12 #include "regs.h"
13
14 #define MT7996_MAX_INTERFACES 19 /* per-band */
15 #define MT7996_MAX_WMM_SETS 4
16 #define MT7996_WTBL_BMC_SIZE (is_mt7992(&dev->mt76) ? 32 : 64)
17 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
18 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
19 mt7996_max_interface_num(dev))
20
21 #define MT7996_WATCHDOG_TIME (HZ / 10)
22 #define MT7996_RESET_TIMEOUT (30 * HZ)
23
24 #define MT7996_TX_RING_SIZE 2048
25 #define MT7996_TX_MCU_RING_SIZE 256
26 #define MT7996_TX_FWDL_RING_SIZE 128
27
28 #define MT7996_RX_RING_SIZE 1536
29 #define MT7996_RX_MCU_RING_SIZE 512
30 #define MT7996_RX_MCU_RING_SIZE_WA 1024
31 /* scatter-gather of mcu event is not supported in connac3 */
32 #define MT7996_RX_MCU_BUF_SIZE (2048 + \
33 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
34
35 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
36 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
37 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"
38 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
39
40 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"
41 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"
42 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"
43 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"
44
45 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
46 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"
47 #define MT7996_EEPROM_SIZE 7680
48 #define MT7996_EEPROM_BLOCK_SIZE 16
49 #define MT7996_TOKEN_SIZE 16384
50 #define MT7996_HW_TOKEN_SIZE 8192
51
52 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
53 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
54
55 #define MT7996_SKU_RATE_NUM 417
56 #define MT7996_SKU_PATH_NUM 494
57
58 #define MT7996_MAX_TWT_AGRT 16
59 #define MT7996_MAX_STA_TWT_AGRT 8
60 #define MT7996_MIN_TWT_DUR 64
61 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
62
63 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */
64 #define MT7996_BASIC_RATES_TBL 31
65 #define MT7996_BEACON_RATES_TBL 25
66
67 #define MT7996_THERMAL_THROTTLE_MAX 100
68 #define MT7996_CDEV_THROTTLE_MAX 99
69 #define MT7996_CRIT_TEMP_IDX 0
70 #define MT7996_MAX_TEMP_IDX 1
71 #define MT7996_CRIT_TEMP 110
72 #define MT7996_MAX_TEMP 120
73
74 #define MT7996_RRO_MAX_SESSION 1024
75 #define MT7996_RRO_WINDOW_MAX_LEN 1024
76 #define MT7996_RRO_ADDR_ELEM_LEN 128
77 #define MT7996_RRO_BA_BITMAP_LEN 2
78 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \
79 MT7996_RRO_BA_BITMAP_LEN)
80 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \
81 MT7996_RRO_ADDR_ELEM_LEN)
82 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \
83 MT7996_RRO_BA_BITMAP_SESSION_SIZE)
84
85 #define MT7996_RX_BUF_SIZE (1800 + \
86 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
87 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \
88 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
89
90 struct mt7996_vif;
91 struct mt7996_sta;
92 struct mt7996_dfs_pulse;
93 struct mt7996_dfs_pattern;
94
95 enum mt7996_ram_type {
96 MT7996_RAM_TYPE_WM,
97 MT7996_RAM_TYPE_WA,
98 MT7996_RAM_TYPE_DSP,
99 };
100
101 enum mt7996_txq_id {
102 MT7996_TXQ_FWDL = 16,
103 MT7996_TXQ_MCU_WM,
104 MT7996_TXQ_BAND0,
105 MT7996_TXQ_BAND1,
106 MT7996_TXQ_MCU_WA,
107 MT7996_TXQ_BAND2,
108 };
109
110 enum mt7996_rxq_id {
111 MT7996_RXQ_MCU_WM = 0,
112 MT7996_RXQ_MCU_WA,
113 MT7996_RXQ_MCU_WA_MAIN = 2,
114 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
115 MT7996_RXQ_MCU_WA_TRI = 3,
116 MT7996_RXQ_BAND0 = 4,
117 MT7996_RXQ_BAND1 = 5, /* for mt7992 */
118 MT7996_RXQ_BAND2 = 5,
119 MT7996_RXQ_RRO_BAND0 = 8,
120 MT7996_RXQ_RRO_BAND1 = 8,/* unused */
121 MT7996_RXQ_RRO_BAND2 = 6,
122 MT7996_RXQ_MSDU_PG_BAND0 = 10,
123 MT7996_RXQ_MSDU_PG_BAND1 = 11,
124 MT7996_RXQ_MSDU_PG_BAND2 = 12,
125 MT7996_RXQ_TXFREE0 = 9,
126 MT7996_RXQ_TXFREE1 = 9,
127 MT7996_RXQ_TXFREE2 = 7,
128 MT7996_RXQ_RRO_IND = 0,
129 };
130
131 struct mt7996_twt_flow {
132 struct list_head list;
133 u64 start_tsf;
134 u64 tsf;
135 u32 duration;
136 u16 wcid;
137 __le16 mantissa;
138 u8 exp;
139 u8 table_id;
140 u8 id;
141 u8 protection:1;
142 u8 flowtype:1;
143 u8 trigger:1;
144 u8 sched:1;
145 };
146
147 DECLARE_EWMA(avg_signal, 10, 8)
148
149 struct mt7996_sta {
150 struct mt76_wcid wcid; /* must be first */
151
152 struct mt7996_vif *vif;
153
154 struct list_head rc_list;
155 u32 airtime_ac[8];
156
157 int ack_signal;
158 struct ewma_avg_signal avg_ack_signal;
159
160 unsigned long changed;
161
162 struct mt76_connac_sta_key_conf bip;
163
164 struct {
165 u8 flowid_mask;
166 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
167 } twt;
168 };
169
170 struct mt7996_vif {
171 struct mt76_vif mt76; /* must be first */
172
173 struct mt7996_sta sta;
174 struct mt7996_phy *phy;
175
176 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
177 struct cfg80211_bitrate_mask bitrate_mask;
178 };
179
180 /* crash-dump */
181 struct mt7996_crash_data {
182 guid_t guid;
183 struct timespec64 timestamp;
184
185 u8 *memdump_buf;
186 size_t memdump_buf_len;
187 };
188
189 struct mt7996_hif {
190 struct list_head list;
191
192 struct device *dev;
193 void __iomem *regs;
194 int irq;
195 };
196
197 struct mt7996_wed_rro_addr {
198 u32 head_low;
199 u32 head_high : 4;
200 u32 count: 11;
201 u32 oor: 1;
202 u32 rsv : 8;
203 u32 signature : 8;
204 };
205
206 struct mt7996_wed_rro_session_id {
207 struct list_head list;
208 u16 id;
209 };
210
211 struct mt7996_phy {
212 struct mt76_phy *mt76;
213 struct mt7996_dev *dev;
214
215 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
216
217 struct ieee80211_vif *monitor_vif;
218
219 struct thermal_cooling_device *cdev;
220 u8 cdev_state;
221 u8 throttle_state;
222 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
223
224 u32 rxfilter;
225 u64 omac_mask;
226
227 u16 noise;
228
229 s16 coverage_class;
230 u8 slottime;
231
232 u8 rdd_state;
233
234 u16 beacon_rate;
235
236 u32 rx_ampdu_ts;
237 u32 ampdu_ref;
238
239 struct mt76_mib_stats mib;
240 struct mt76_channel_state state_ts;
241
242 bool has_aux_rx;
243 };
244
245 struct mt7996_dev {
246 union { /* must be first */
247 struct mt76_dev mt76;
248 struct mt76_phy mphy;
249 };
250
251 struct mt7996_hif *hif2;
252 struct mt7996_reg_desc reg;
253 u8 q_id[MT7996_MAX_QUEUE];
254 u32 q_int_mask[MT7996_MAX_QUEUE];
255 u32 q_wfdma_mask;
256
257 const struct mt76_bus_ops *bus_ops;
258 struct mt7996_phy phy;
259
260 /* monitor rx chain configured channel */
261 struct cfg80211_chan_def rdd2_chandef;
262 struct mt7996_phy *rdd2_phy;
263
264 u16 chainmask;
265 u8 chainshift[__MT_MAX_BAND];
266 u32 hif_idx;
267
268 struct work_struct init_work;
269 struct work_struct rc_work;
270 struct work_struct dump_work;
271 struct work_struct reset_work;
272 wait_queue_head_t reset_wait;
273 struct {
274 u32 state;
275 u32 wa_reset_count;
276 u32 wm_reset_count;
277 bool hw_full_reset:1;
278 bool hw_init_done:1;
279 bool restart:1;
280 } recovery;
281
282 /* protects coredump data */
283 struct mutex dump_mutex;
284 #ifdef CONFIG_DEV_COREDUMP
285 struct {
286 struct mt7996_crash_data *crash_data;
287 } coredump;
288 #endif
289
290 struct list_head sta_rc_list;
291 struct list_head twt_list;
292
293 u32 hw_pattern;
294
295 bool flash_mode:1;
296 bool has_eht:1;
297 bool has_rro:1;
298
299 struct {
300 struct {
301 void *ptr;
302 dma_addr_t phy_addr;
303 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];
304 struct {
305 void *ptr;
306 dma_addr_t phy_addr;
307 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];
308 struct {
309 void *ptr;
310 dma_addr_t phy_addr;
311 } session;
312
313 struct work_struct work;
314 struct list_head poll_list;
315 spinlock_t lock;
316 } wed_rro;
317
318 bool ibf;
319 u8 fw_debug_wm;
320 u8 fw_debug_wa;
321 u8 fw_debug_bin;
322 u16 fw_debug_seq;
323
324 struct dentry *debugfs_dir;
325 struct rchan *relay_fwlog;
326
327 struct {
328 u16 table_mask;
329 u8 n_agrt;
330 } twt;
331
332 spinlock_t reg_lock;
333
334 u8 wtbl_size_group;
335 };
336
337 enum {
338 WFDMA0 = 0x0,
339 WFDMA1,
340 WFDMA_EXT,
341 __MT_WFDMA_MAX,
342 };
343
344 enum {
345 MT_RX_SEL0,
346 MT_RX_SEL1,
347 MT_RX_SEL2, /* monitor chain */
348 };
349
350 enum mt7996_rdd_cmd {
351 RDD_STOP,
352 RDD_START,
353 RDD_DET_MODE,
354 RDD_RADAR_EMULATE,
355 RDD_START_TXQ = 20,
356 RDD_CAC_START = 50,
357 RDD_CAC_END,
358 RDD_NORMAL_START,
359 RDD_DISABLE_DFS_CAL,
360 RDD_PULSE_DBG,
361 RDD_READ_PULSE,
362 RDD_RESUME_BF,
363 RDD_IRQ_OFF,
364 };
365
366 static inline struct mt7996_phy *
mt7996_hw_phy(struct ieee80211_hw * hw)367 mt7996_hw_phy(struct ieee80211_hw *hw)
368 {
369 struct mt76_phy *phy = hw->priv;
370
371 return phy->priv;
372 }
373
374 static inline struct mt7996_dev *
mt7996_hw_dev(struct ieee80211_hw * hw)375 mt7996_hw_dev(struct ieee80211_hw *hw)
376 {
377 struct mt76_phy *phy = hw->priv;
378
379 return container_of(phy->dev, struct mt7996_dev, mt76);
380 }
381
382 static inline struct mt7996_phy *
__mt7996_phy(struct mt7996_dev * dev,enum mt76_band_id band)383 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
384 {
385 struct mt76_phy *phy = dev->mt76.phys[band];
386
387 if (!phy)
388 return NULL;
389
390 return phy->priv;
391 }
392
393 static inline struct mt7996_phy *
mt7996_phy2(struct mt7996_dev * dev)394 mt7996_phy2(struct mt7996_dev *dev)
395 {
396 return __mt7996_phy(dev, MT_BAND1);
397 }
398
399 static inline struct mt7996_phy *
mt7996_phy3(struct mt7996_dev * dev)400 mt7996_phy3(struct mt7996_dev *dev)
401 {
402 return __mt7996_phy(dev, MT_BAND2);
403 }
404
405 static inline bool
mt7996_band_valid(struct mt7996_dev * dev,u8 band)406 mt7996_band_valid(struct mt7996_dev *dev, u8 band)
407 {
408 if (is_mt7992(&dev->mt76))
409 return band <= MT_BAND1;
410
411 /* tri-band support */
412 if (band <= MT_BAND2 &&
413 mt76_get_field(dev, MT_PAD_GPIO, MT_PAD_GPIO_ADIE_COMB) <= 1)
414 return true;
415
416 return band == MT_BAND0 || band == MT_BAND2;
417 }
418
419 extern const struct ieee80211_ops mt7996_ops;
420 extern struct pci_driver mt7996_pci_driver;
421 extern struct pci_driver mt7996_hif_driver;
422
423 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
424 void __iomem *mem_base, u32 device_id);
425 void mt7996_wfsys_reset(struct mt7996_dev *dev);
426 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
427 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif);
428 int mt7996_register_device(struct mt7996_dev *dev);
429 void mt7996_unregister_device(struct mt7996_dev *dev);
430 int mt7996_eeprom_init(struct mt7996_dev *dev);
431 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
432 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
433 struct ieee80211_channel *chan);
434 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
435 int mt7996_dma_init(struct mt7996_dev *dev);
436 void mt7996_dma_reset(struct mt7996_dev *dev, bool force);
437 void mt7996_dma_prefetch(struct mt7996_dev *dev);
438 void mt7996_dma_cleanup(struct mt7996_dev *dev);
439 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);
440 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,
441 int n_desc, int ring_base, struct mtk_wed_device *wed);
442 void mt7996_init_txpower(struct mt7996_phy *phy);
443 int mt7996_txbf_init(struct mt7996_dev *dev);
444 void mt7996_reset(struct mt7996_dev *dev);
445 int mt7996_run(struct ieee80211_hw *hw);
446 int mt7996_mcu_init(struct mt7996_dev *dev);
447 int mt7996_mcu_init_firmware(struct mt7996_dev *dev);
448 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
449 struct mt7996_vif *mvif,
450 struct mt7996_twt_flow *flow,
451 int cmd);
452 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy,
453 struct ieee80211_vif *vif, bool enable);
454 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy,
455 struct ieee80211_vif *vif, int enable);
456 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif,
457 struct ieee80211_sta *sta, bool enable, bool newly);
458 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
459 struct ieee80211_ampdu_params *params,
460 bool add);
461 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
462 struct ieee80211_ampdu_params *params,
463 bool add);
464 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif,
465 struct cfg80211_he_bss_color *he_bss_color);
466 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
467 int enable);
468 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
469 struct ieee80211_vif *vif, u32 changed);
470 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif,
471 struct ieee80211_he_obss_pd *he_obss_pd);
472 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif,
473 struct ieee80211_sta *sta, bool changed);
474 int mt7996_set_channel(struct mt76_phy *mphy);
475 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
476 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif);
477 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
478 void *data, u16 version);
479 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct ieee80211_vif *vif,
480 struct ieee80211_sta *sta, void *data, u32 field);
481 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
482 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset);
483 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);
484 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
485 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
486 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
487 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
488 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
489 const struct mt7996_dfs_pulse *pulse);
490 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
491 const struct mt7996_dfs_pattern *pattern);
492 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
493 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
494 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif);
495 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
496 int mt7996_mcu_get_temperature(struct mt7996_phy *phy);
497 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);
498 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);
499 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);
500 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index,
501 u8 rx_sel, u8 val);
502 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
503 struct cfg80211_chan_def *chandef);
504 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
505 u16 rate_idx, bool beacon);
506 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
507 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
508 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
509 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
510 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
511 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
512 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
513 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
514 void mt7996_mcu_exit(struct mt7996_dev *dev);
515 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);
516 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);
517
mt7996_max_interface_num(struct mt7996_dev * dev)518 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
519 {
520 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +
521 mt7996_band_valid(dev, MT_BAND2)),
522 MT7996_WTBL_BMC_SIZE);
523 }
524
mt7996_wtbl_size(struct mt7996_dev * dev)525 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
526 {
527 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;
528 }
529
530 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
531 u32 clear, u32 set);
532
mt7996_irq_enable(struct mt7996_dev * dev,u32 mask)533 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
534 {
535 if (dev->hif2)
536 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
537 else
538 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
539
540 tasklet_schedule(&dev->mt76.irq_tasklet);
541 }
542
mt7996_irq_disable(struct mt7996_dev * dev,u32 mask)543 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
544 {
545 if (dev->hif2)
546 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
547 else
548 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
549 }
550
551 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
552 size_t len);
553
mt7996_rx_chainmask(struct mt7996_phy * phy)554 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)
555 {
556 int max_nss = hweight8(phy->mt76->hw->wiphy->available_antennas_tx);
557 int cur_nss = hweight8(phy->mt76->antenna_mask);
558 u16 tx_chainmask = phy->mt76->chainmask;
559
560 if (cur_nss != max_nss)
561 return tx_chainmask;
562
563 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);
564 }
565
566 void mt7996_mac_init(struct mt7996_dev *dev);
567 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
568 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
569 void mt7996_mac_reset_counters(struct mt7996_phy *phy);
570 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
571 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
572 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev,
573 struct ieee80211_vif *vif, bool enable);
574 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
575 struct sk_buff *skb, struct mt76_wcid *wcid,
576 struct ieee80211_key_conf *key, int pid,
577 enum mt76_txq_id qid, u32 changed);
578 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
579 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
580 struct ieee80211_sta *sta);
581 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
582 struct ieee80211_sta *sta);
583 void mt7996_mac_work(struct work_struct *work);
584 void mt7996_mac_reset_work(struct work_struct *work);
585 void mt7996_mac_dump_work(struct work_struct *work);
586 void mt7996_mac_sta_rc_work(struct work_struct *work);
587 void mt7996_mac_update_stats(struct mt7996_phy *phy);
588 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
589 struct mt7996_sta *msta,
590 u8 flowid);
591 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
592 struct ieee80211_sta *sta,
593 struct ieee80211_twt_setup *twt);
594 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
595 enum mt76_txq_id qid, struct mt76_wcid *wcid,
596 struct ieee80211_sta *sta,
597 struct mt76_tx_info *tx_info);
598 void mt7996_tx_token_put(struct mt7996_dev *dev);
599 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
600 struct sk_buff *skb, u32 *info);
601 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
602 void mt7996_stats_work(struct work_struct *work);
603 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
604 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
605 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
606 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
607 void mt7996_update_channel(struct mt76_phy *mphy);
608 int mt7996_init_debugfs(struct mt7996_phy *phy);
609 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
610 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
611 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
612 struct ieee80211_key_conf *key, int mcu_cmd,
613 struct mt76_wcid *wcid, enum set_key_cmd cmd);
614 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, struct ieee80211_vif *vif,
615 struct ieee80211_key_conf *key);
616 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
617 struct ieee80211_vif *vif,
618 struct ieee80211_sta *sta);
619 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode);
620 #ifdef CONFIG_MAC80211_DEBUGFS
621 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
622 struct ieee80211_sta *sta, struct dentry *dir);
623 #endif
624 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
625 bool hif2, int *irq);
626 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
627
628 #ifdef CONFIG_MTK_DEBUG
629 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
630 #endif
631
632 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
633 int mt7996_dma_rro_init(struct mt7996_dev *dev);
634 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
635
636 #endif
637