1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4 #include <linux/ip.h>
5 #include <linux/udp.h>
6
7 #include "cam.h"
8 #include "chan.h"
9 #include "coex.h"
10 #include "core.h"
11 #include "efuse.h"
12 #include "fw.h"
13 #include "mac.h"
14 #include "phy.h"
15 #include "ps.h"
16 #include "reg.h"
17 #include "sar.h"
18 #include "ser.h"
19 #include "txrx.h"
20 #include "util.h"
21 #include "wow.h"
22
23 static bool rtw89_disable_ps_mode;
24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
26
27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
37
38 static struct ieee80211_channel rtw89_channels_2ghz[] = {
39 RTW89_DEF_CHAN_2G(2412, 1),
40 RTW89_DEF_CHAN_2G(2417, 2),
41 RTW89_DEF_CHAN_2G(2422, 3),
42 RTW89_DEF_CHAN_2G(2427, 4),
43 RTW89_DEF_CHAN_2G(2432, 5),
44 RTW89_DEF_CHAN_2G(2437, 6),
45 RTW89_DEF_CHAN_2G(2442, 7),
46 RTW89_DEF_CHAN_2G(2447, 8),
47 RTW89_DEF_CHAN_2G(2452, 9),
48 RTW89_DEF_CHAN_2G(2457, 10),
49 RTW89_DEF_CHAN_2G(2462, 11),
50 RTW89_DEF_CHAN_2G(2467, 12),
51 RTW89_DEF_CHAN_2G(2472, 13),
52 RTW89_DEF_CHAN_2G(2484, 14),
53 };
54
55 static struct ieee80211_channel rtw89_channels_5ghz[] = {
56 RTW89_DEF_CHAN_5G(5180, 36),
57 RTW89_DEF_CHAN_5G(5200, 40),
58 RTW89_DEF_CHAN_5G(5220, 44),
59 RTW89_DEF_CHAN_5G(5240, 48),
60 RTW89_DEF_CHAN_5G(5260, 52),
61 RTW89_DEF_CHAN_5G(5280, 56),
62 RTW89_DEF_CHAN_5G(5300, 60),
63 RTW89_DEF_CHAN_5G(5320, 64),
64 RTW89_DEF_CHAN_5G(5500, 100),
65 RTW89_DEF_CHAN_5G(5520, 104),
66 RTW89_DEF_CHAN_5G(5540, 108),
67 RTW89_DEF_CHAN_5G(5560, 112),
68 RTW89_DEF_CHAN_5G(5580, 116),
69 RTW89_DEF_CHAN_5G(5600, 120),
70 RTW89_DEF_CHAN_5G(5620, 124),
71 RTW89_DEF_CHAN_5G(5640, 128),
72 RTW89_DEF_CHAN_5G(5660, 132),
73 RTW89_DEF_CHAN_5G(5680, 136),
74 RTW89_DEF_CHAN_5G(5700, 140),
75 RTW89_DEF_CHAN_5G(5720, 144),
76 RTW89_DEF_CHAN_5G(5745, 149),
77 RTW89_DEF_CHAN_5G(5765, 153),
78 RTW89_DEF_CHAN_5G(5785, 157),
79 RTW89_DEF_CHAN_5G(5805, 161),
80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
81 RTW89_DEF_CHAN_5G(5845, 169),
82 RTW89_DEF_CHAN_5G(5865, 173),
83 RTW89_DEF_CHAN_5G(5885, 177),
84 };
85
86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
87 ARRAY_SIZE(rtw89_channels_5ghz));
88
89 static struct ieee80211_channel rtw89_channels_6ghz[] = {
90 RTW89_DEF_CHAN_6G(5955, 1),
91 RTW89_DEF_CHAN_6G(5975, 5),
92 RTW89_DEF_CHAN_6G(5995, 9),
93 RTW89_DEF_CHAN_6G(6015, 13),
94 RTW89_DEF_CHAN_6G(6035, 17),
95 RTW89_DEF_CHAN_6G(6055, 21),
96 RTW89_DEF_CHAN_6G(6075, 25),
97 RTW89_DEF_CHAN_6G(6095, 29),
98 RTW89_DEF_CHAN_6G(6115, 33),
99 RTW89_DEF_CHAN_6G(6135, 37),
100 RTW89_DEF_CHAN_6G(6155, 41),
101 RTW89_DEF_CHAN_6G(6175, 45),
102 RTW89_DEF_CHAN_6G(6195, 49),
103 RTW89_DEF_CHAN_6G(6215, 53),
104 RTW89_DEF_CHAN_6G(6235, 57),
105 RTW89_DEF_CHAN_6G(6255, 61),
106 RTW89_DEF_CHAN_6G(6275, 65),
107 RTW89_DEF_CHAN_6G(6295, 69),
108 RTW89_DEF_CHAN_6G(6315, 73),
109 RTW89_DEF_CHAN_6G(6335, 77),
110 RTW89_DEF_CHAN_6G(6355, 81),
111 RTW89_DEF_CHAN_6G(6375, 85),
112 RTW89_DEF_CHAN_6G(6395, 89),
113 RTW89_DEF_CHAN_6G(6415, 93),
114 RTW89_DEF_CHAN_6G(6435, 97),
115 RTW89_DEF_CHAN_6G(6455, 101),
116 RTW89_DEF_CHAN_6G(6475, 105),
117 RTW89_DEF_CHAN_6G(6495, 109),
118 RTW89_DEF_CHAN_6G(6515, 113),
119 RTW89_DEF_CHAN_6G(6535, 117),
120 RTW89_DEF_CHAN_6G(6555, 121),
121 RTW89_DEF_CHAN_6G(6575, 125),
122 RTW89_DEF_CHAN_6G(6595, 129),
123 RTW89_DEF_CHAN_6G(6615, 133),
124 RTW89_DEF_CHAN_6G(6635, 137),
125 RTW89_DEF_CHAN_6G(6655, 141),
126 RTW89_DEF_CHAN_6G(6675, 145),
127 RTW89_DEF_CHAN_6G(6695, 149),
128 RTW89_DEF_CHAN_6G(6715, 153),
129 RTW89_DEF_CHAN_6G(6735, 157),
130 RTW89_DEF_CHAN_6G(6755, 161),
131 RTW89_DEF_CHAN_6G(6775, 165),
132 RTW89_DEF_CHAN_6G(6795, 169),
133 RTW89_DEF_CHAN_6G(6815, 173),
134 RTW89_DEF_CHAN_6G(6835, 177),
135 RTW89_DEF_CHAN_6G(6855, 181),
136 RTW89_DEF_CHAN_6G(6875, 185),
137 RTW89_DEF_CHAN_6G(6895, 189),
138 RTW89_DEF_CHAN_6G(6915, 193),
139 RTW89_DEF_CHAN_6G(6935, 197),
140 RTW89_DEF_CHAN_6G(6955, 201),
141 RTW89_DEF_CHAN_6G(6975, 205),
142 RTW89_DEF_CHAN_6G(6995, 209),
143 RTW89_DEF_CHAN_6G(7015, 213),
144 RTW89_DEF_CHAN_6G(7035, 217),
145 RTW89_DEF_CHAN_6G(7055, 221),
146 RTW89_DEF_CHAN_6G(7075, 225),
147 RTW89_DEF_CHAN_6G(7095, 229),
148 RTW89_DEF_CHAN_6G(7115, 233),
149 };
150
151 static struct ieee80211_rate rtw89_bitrates[] = {
152 { .bitrate = 10, .hw_value = 0x00, },
153 { .bitrate = 20, .hw_value = 0x01, },
154 { .bitrate = 55, .hw_value = 0x02, },
155 { .bitrate = 110, .hw_value = 0x03, },
156 { .bitrate = 60, .hw_value = 0x04, },
157 { .bitrate = 90, .hw_value = 0x05, },
158 { .bitrate = 120, .hw_value = 0x06, },
159 { .bitrate = 180, .hw_value = 0x07, },
160 { .bitrate = 240, .hw_value = 0x08, },
161 { .bitrate = 360, .hw_value = 0x09, },
162 { .bitrate = 480, .hw_value = 0x0a, },
163 { .bitrate = 540, .hw_value = 0x0b, },
164 };
165
166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
167 {
168 .max = 1,
169 .types = BIT(NL80211_IFTYPE_STATION),
170 },
171 {
172 .max = 1,
173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
174 BIT(NL80211_IFTYPE_P2P_GO) |
175 BIT(NL80211_IFTYPE_AP),
176 },
177 };
178
179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
180 {
181 .max = 1,
182 .types = BIT(NL80211_IFTYPE_STATION),
183 },
184 {
185 .max = 1,
186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
187 BIT(NL80211_IFTYPE_P2P_GO),
188 },
189 };
190
191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
192 {
193 .limits = rtw89_iface_limits,
194 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
195 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
196 .num_different_channels = 1,
197 },
198 {
199 .limits = rtw89_iface_limits_mcc,
200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
201 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
202 .num_different_channels = 2,
203 },
204 };
205
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)206 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
207 {
208 struct ieee80211_rate rate;
209
210 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
211 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
212 return false;
213 }
214
215 rate = rtw89_bitrates[rpt_rate];
216 *bitrate = rate.bitrate;
217
218 return true;
219 }
220
221 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
222 .band = NL80211_BAND_2GHZ,
223 .channels = rtw89_channels_2ghz,
224 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
225 .bitrates = rtw89_bitrates,
226 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
227 .ht_cap = {0},
228 .vht_cap = {0},
229 };
230
231 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
232 .band = NL80211_BAND_5GHZ,
233 .channels = rtw89_channels_5ghz,
234 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
235
236 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
237 .bitrates = rtw89_bitrates + 4,
238 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
239 .ht_cap = {0},
240 .vht_cap = {0},
241 };
242
243 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
244 .band = NL80211_BAND_6GHZ,
245 .channels = rtw89_channels_6ghz,
246 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
247
248 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
249 .bitrates = rtw89_bitrates + 4,
250 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
251 };
252
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)253 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
254 struct rtw89_traffic_stats *stats,
255 struct sk_buff *skb, bool tx)
256 {
257 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
258
259 if (tx && ieee80211_is_assoc_req(hdr->frame_control))
260 rtw89_wow_parse_akm(rtwdev, skb);
261
262 if (!ieee80211_is_data(hdr->frame_control))
263 return;
264
265 if (is_broadcast_ether_addr(hdr->addr1) ||
266 is_multicast_ether_addr(hdr->addr1))
267 return;
268
269 if (tx) {
270 stats->tx_cnt++;
271 stats->tx_unicast += skb->len;
272 } else {
273 stats->rx_cnt++;
274 stats->rx_unicast += skb->len;
275 }
276 }
277
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)278 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
279 {
280 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
281 NL80211_CHAN_NO_HT);
282 }
283
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)284 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
285 struct rtw89_chan *chan)
286 {
287 struct ieee80211_channel *channel = chandef->chan;
288 enum nl80211_chan_width width = chandef->width;
289 u32 primary_freq, center_freq;
290 u8 center_chan;
291 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
292 u32 offset;
293 u8 band;
294
295 center_chan = channel->hw_value;
296 primary_freq = channel->center_freq;
297 center_freq = chandef->center_freq1;
298
299 switch (width) {
300 case NL80211_CHAN_WIDTH_20_NOHT:
301 case NL80211_CHAN_WIDTH_20:
302 bandwidth = RTW89_CHANNEL_WIDTH_20;
303 break;
304 case NL80211_CHAN_WIDTH_40:
305 bandwidth = RTW89_CHANNEL_WIDTH_40;
306 if (primary_freq > center_freq) {
307 center_chan -= 2;
308 } else {
309 center_chan += 2;
310 }
311 break;
312 case NL80211_CHAN_WIDTH_80:
313 case NL80211_CHAN_WIDTH_160:
314 bandwidth = nl_to_rtw89_bandwidth(width);
315 if (primary_freq > center_freq) {
316 offset = (primary_freq - center_freq - 10) / 20;
317 center_chan -= 2 + offset * 4;
318 } else {
319 offset = (center_freq - primary_freq - 10) / 20;
320 center_chan += 2 + offset * 4;
321 }
322 break;
323 default:
324 center_chan = 0;
325 break;
326 }
327
328 switch (channel->band) {
329 default:
330 case NL80211_BAND_2GHZ:
331 band = RTW89_BAND_2G;
332 break;
333 case NL80211_BAND_5GHZ:
334 band = RTW89_BAND_5G;
335 break;
336 case NL80211_BAND_6GHZ:
337 band = RTW89_BAND_6G;
338 break;
339 }
340
341 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
342 }
343
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)344 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
345 const struct rtw89_chan *chan,
346 enum rtw89_phy_idx phy_idx)
347 {
348 const struct rtw89_chip_info *chip = rtwdev->chip;
349 bool entity_active;
350
351 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
352 if (!entity_active)
353 return;
354
355 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
356 }
357
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)358 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
359 {
360 const struct rtw89_chan *chan;
361
362 chan = rtw89_mgnt_chan_get(rtwdev, 0);
363 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
364
365 if (!rtwdev->support_mlo)
366 return;
367
368 chan = rtw89_mgnt_chan_get(rtwdev, 1);
369 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
370 }
371
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)372 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
373 const struct rtw89_chan *chan,
374 enum rtw89_mac_idx mac_idx,
375 enum rtw89_phy_idx phy_idx)
376 {
377 const struct rtw89_chip_info *chip = rtwdev->chip;
378 const struct rtw89_chan_rcd *chan_rcd;
379 struct rtw89_channel_help_params bak;
380 bool entity_active;
381
382 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
383
384 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
385
386 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
387
388 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
389
390 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
391
392 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
393
394 if (!entity_active || chan_rcd->band_changed) {
395 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
396 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
397 }
398
399 rtw89_set_entity_state(rtwdev, phy_idx, true);
400 }
401
rtw89_set_channel(struct rtw89_dev * rtwdev)402 int rtw89_set_channel(struct rtw89_dev *rtwdev)
403 {
404 const struct rtw89_chan *chan;
405 enum rtw89_entity_mode mode;
406
407 mode = rtw89_entity_recalc(rtwdev);
408 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
409 WARN(1, "Invalid ent mode: %d\n", mode);
410 return -EINVAL;
411 }
412
413 chan = rtw89_mgnt_chan_get(rtwdev, 0);
414 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
415
416 if (!rtwdev->support_mlo)
417 return 0;
418
419 chan = rtw89_mgnt_chan_get(rtwdev, 1);
420 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1);
421
422 return 0;
423 }
424
425 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)426 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
427 struct sk_buff *skb)
428 {
429 struct ieee80211_hdr *hdr = (void *)skb->data;
430 __le16 fc = hdr->frame_control;
431
432 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
433 return RTW89_CORE_TX_TYPE_MGMT;
434
435 return RTW89_CORE_TX_TYPE_DATA;
436 }
437
438 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)439 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
440 struct rtw89_core_tx_request *tx_req,
441 enum btc_pkt_type pkt_type)
442 {
443 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
444 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
445 struct ieee80211_link_sta *link_sta;
446 struct sk_buff *skb = tx_req->skb;
447 struct rtw89_sta *rtwsta;
448 u8 ampdu_num;
449 u8 tid;
450
451 if (pkt_type == PACKET_EAPOL) {
452 desc_info->bk = true;
453 return;
454 }
455
456 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
457 return;
458
459 if (!rtwsta_link) {
460 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
461 return;
462 }
463
464 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
465 rtwsta = rtwsta_link->rtwsta;
466
467 rcu_read_lock();
468
469 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
470 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
471 rtwsta->ampdu_params[tid].agg_num :
472 4 << link_sta->ht_cap.ampdu_factor) - 1);
473
474 desc_info->agg_en = true;
475 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
476 desc_info->ampdu_num = ampdu_num;
477
478 rcu_read_unlock();
479 }
480
481 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)482 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
483 struct rtw89_core_tx_request *tx_req)
484 {
485 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
486 const struct rtw89_chip_info *chip = rtwdev->chip;
487 const struct rtw89_sec_cam_entry *sec_cam;
488 struct ieee80211_tx_info *info;
489 struct ieee80211_key_conf *key;
490 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
491 struct sk_buff *skb = tx_req->skb;
492 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
493 u8 sec_cam_idx;
494 u64 pn64;
495
496 info = IEEE80211_SKB_CB(skb);
497 key = info->control.hw_key;
498 sec_cam_idx = key->hw_key_idx;
499 sec_cam = cam_info->sec_entries[sec_cam_idx];
500 if (!sec_cam) {
501 rtw89_warn(rtwdev, "sec cam entry is empty\n");
502 return;
503 }
504
505 switch (key->cipher) {
506 case WLAN_CIPHER_SUITE_WEP40:
507 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
508 break;
509 case WLAN_CIPHER_SUITE_WEP104:
510 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
511 break;
512 case WLAN_CIPHER_SUITE_TKIP:
513 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
514 break;
515 case WLAN_CIPHER_SUITE_CCMP:
516 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
517 break;
518 case WLAN_CIPHER_SUITE_CCMP_256:
519 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
520 break;
521 case WLAN_CIPHER_SUITE_GCMP:
522 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
523 break;
524 case WLAN_CIPHER_SUITE_GCMP_256:
525 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
526 break;
527 default:
528 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
529 return;
530 }
531
532 desc_info->sec_en = true;
533 desc_info->sec_keyid = key->keyidx;
534 desc_info->sec_type = sec_type;
535 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
536
537 if (!chip->hw_sec_hdr)
538 return;
539
540 pn64 = atomic64_inc_return(&key->tx_pn);
541 desc_info->sec_seq[0] = pn64;
542 desc_info->sec_seq[1] = pn64 >> 8;
543 desc_info->sec_seq[2] = pn64 >> 16;
544 desc_info->sec_seq[3] = pn64 >> 24;
545 desc_info->sec_seq[4] = pn64 >> 32;
546 desc_info->sec_seq[5] = pn64 >> 40;
547 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
548 }
549
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)550 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
551 struct rtw89_core_tx_request *tx_req,
552 const struct rtw89_chan *chan)
553 {
554 struct sk_buff *skb = tx_req->skb;
555 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
556 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
557 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
558 struct ieee80211_vif *vif = tx_info->control.vif;
559 struct ieee80211_bss_conf *bss_conf;
560 u16 lowest_rate;
561 u16 rate;
562
563 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
564 (vif && vif->p2p))
565 lowest_rate = RTW89_HW_RATE_OFDM6;
566 else if (chan->band_type == RTW89_BAND_2G)
567 lowest_rate = RTW89_HW_RATE_CCK1;
568 else
569 lowest_rate = RTW89_HW_RATE_OFDM6;
570
571 if (!rtwvif_link)
572 return lowest_rate;
573
574 rcu_read_lock();
575
576 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
577 if (!bss_conf->basic_rates || !rtwsta_link) {
578 rate = lowest_rate;
579 goto out;
580 }
581
582 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
583
584 out:
585 rcu_read_unlock();
586
587 return rate;
588 }
589
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)590 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
591 struct rtw89_core_tx_request *tx_req)
592 {
593 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
594 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
595
596 if (!rtwsta_link)
597 return rtwvif_link->mac_id;
598
599 return rtwsta_link->mac_id;
600 }
601
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)602 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
603 struct rtw89_tx_desc_info *desc_info,
604 struct sk_buff *skb)
605 {
606 struct ieee80211_hdr *hdr = (void *)skb->data;
607 __le16 fc = hdr->frame_control;
608
609 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
610 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
611 }
612
613 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)614 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
615 struct rtw89_core_tx_request *tx_req)
616 {
617 const struct rtw89_chip_info *chip = rtwdev->chip;
618 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
619 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
620 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
621 rtwvif_link->chanctx_idx);
622 struct sk_buff *skb = tx_req->skb;
623 u8 qsel, ch_dma;
624
625 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
626 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
627
628 desc_info->qsel = qsel;
629 desc_info->ch_dma = ch_dma;
630 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
631 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
632 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
633 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
634
635 /* fixed data rate for mgmt frames */
636 desc_info->en_wd_info = true;
637 desc_info->use_rate = true;
638 desc_info->dis_data_fb = true;
639 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
640
641 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
642 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
643 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
644 }
645
646 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
647 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
648 desc_info->data_rate, chan->channel, chan->band_type,
649 chan->band_width);
650 }
651
652 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)653 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
654 struct rtw89_core_tx_request *tx_req)
655 {
656 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
657
658 desc_info->is_bmc = false;
659 desc_info->wd_page = false;
660 desc_info->ch_dma = RTW89_DMA_H2C;
661 }
662
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)663 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
664 const struct rtw89_chan *chan)
665 {
666 static const u8 rtw89_bandwidth_to_om[] = {
667 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
668 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
669 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
670 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
671 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
672 };
673 const struct rtw89_chip_info *chip = rtwdev->chip;
674 struct rtw89_hal *hal = &rtwdev->hal;
675 u8 om_bandwidth;
676
677 if (!chip->dis_2g_40m_ul_ofdma ||
678 chan->band_type != RTW89_BAND_2G ||
679 chan->band_width != RTW89_CHANNEL_WIDTH_40)
680 return;
681
682 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
683 rtw89_bandwidth_to_om[chan->band_width] : 0;
684 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
685 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
686 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
687 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
688 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
689 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
690 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
691 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
692 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
693 }
694
695 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)696 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
697 struct rtw89_core_tx_request *tx_req,
698 enum btc_pkt_type pkt_type)
699 {
700 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
701 struct sk_buff *skb = tx_req->skb;
702 struct ieee80211_hdr *hdr = (void *)skb->data;
703 struct ieee80211_link_sta *link_sta;
704 __le16 fc = hdr->frame_control;
705
706 /* AP IOT issue with EAPoL, ARP and DHCP */
707 if (pkt_type < PACKET_MAX)
708 return false;
709
710 if (!rtwsta_link)
711 return false;
712
713 rcu_read_lock();
714
715 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
716 if (!link_sta->he_cap.has_he) {
717 rcu_read_unlock();
718 return false;
719 }
720
721 rcu_read_unlock();
722
723 if (!ieee80211_is_data_qos(fc))
724 return false;
725
726 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
727 return false;
728
729 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
730 return false;
731
732 return true;
733 }
734
735 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)736 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
737 struct rtw89_core_tx_request *tx_req)
738 {
739 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
740 struct sk_buff *skb = tx_req->skb;
741 struct ieee80211_hdr *hdr = (void *)skb->data;
742 __le16 fc = hdr->frame_control;
743 void *data;
744 __le32 *htc;
745 u8 *qc;
746 int hdr_len;
747
748 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
749 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
750 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
751
752 hdr = data;
753 htc = data + hdr_len;
754 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
755 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
756 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
757 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
758
759 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
760 qc[0] |= IEEE80211_QOS_CTL_EOSP;
761 }
762
763 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)764 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
765 struct rtw89_core_tx_request *tx_req,
766 enum btc_pkt_type pkt_type)
767 {
768 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
769 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
770
771 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
772 goto desc_bk;
773
774 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
775
776 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
777 desc_info->a_ctrl_bsr = true;
778
779 desc_bk:
780 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
781 return;
782
783 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
784 desc_info->bk = true;
785 }
786
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)787 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
788 struct rtw89_core_tx_request *tx_req)
789 {
790 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
791 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
792 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
793 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
794 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
795 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
796 struct ieee80211_link_sta *link_sta;
797 u16 lowest_rate;
798 u16 rate;
799
800 if (rate_pattern->enable)
801 return rate_pattern->rate;
802
803 if (vif->p2p)
804 lowest_rate = RTW89_HW_RATE_OFDM6;
805 else if (chan->band_type == RTW89_BAND_2G)
806 lowest_rate = RTW89_HW_RATE_CCK1;
807 else
808 lowest_rate = RTW89_HW_RATE_OFDM6;
809
810 if (!rtwsta_link)
811 return lowest_rate;
812
813 rcu_read_lock();
814
815 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
816 if (!link_sta->supp_rates[chan->band_type]) {
817 rate = lowest_rate;
818 goto out;
819 }
820
821 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
822
823 out:
824 rcu_read_unlock();
825
826 return rate;
827 }
828
829 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)830 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
831 struct rtw89_core_tx_request *tx_req)
832 {
833 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
834 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
835 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
836 struct sk_buff *skb = tx_req->skb;
837 u8 tid, tid_indicate;
838 u8 qsel, ch_dma;
839
840 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
841 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
842 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
843 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
844
845 desc_info->ch_dma = ch_dma;
846 desc_info->tid_indicate = tid_indicate;
847 desc_info->qsel = qsel;
848 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
849 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
850 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
851 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
852 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
853
854 /* enable wd_info for AMPDU */
855 desc_info->en_wd_info = true;
856
857 if (IEEE80211_SKB_CB(skb)->control.hw_key)
858 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
859
860 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
861 }
862
863 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)864 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
865 struct rtw89_core_tx_request *tx_req)
866 {
867 struct sk_buff *skb = tx_req->skb;
868 struct udphdr *udphdr;
869
870 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
871 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
872 return PACKET_EAPOL;
873 }
874
875 if (skb->protocol == htons(ETH_P_ARP)) {
876 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
877 return PACKET_ARP;
878 }
879
880 if (skb->protocol == htons(ETH_P_IP) &&
881 ip_hdr(skb)->protocol == IPPROTO_UDP) {
882 udphdr = udp_hdr(skb);
883 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
884 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
885 skb->len > 282) {
886 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
887 return PACKET_DHCP;
888 }
889 }
890
891 if (skb->protocol == htons(ETH_P_IP) &&
892 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
893 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
894 return PACKET_ICMP;
895 }
896
897 return PACKET_MAX;
898 }
899
900 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)901 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
902 struct rtw89_core_tx_request *tx_req)
903 {
904 const struct rtw89_chip_info *chip = rtwdev->chip;
905
906 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
907 return;
908
909 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
910 return;
911
912 if (chip->chip_id != RTL8852C &&
913 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
914 return;
915
916 rtw89_mac_notify_wake(rtwdev);
917 }
918
919 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)920 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
921 struct rtw89_core_tx_request *tx_req)
922 {
923 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
924 struct sk_buff *skb = tx_req->skb;
925 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
926 struct ieee80211_hdr *hdr = (void *)skb->data;
927 enum rtw89_core_tx_type tx_type;
928 enum btc_pkt_type pkt_type;
929 bool is_bmc;
930 u16 seq;
931
932 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
933 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
934 tx_type = rtw89_core_get_tx_type(rtwdev, skb);
935 tx_req->tx_type = tx_type;
936 }
937 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
938 is_multicast_ether_addr(hdr->addr1));
939
940 desc_info->seq = seq;
941 desc_info->pkt_size = skb->len;
942 desc_info->is_bmc = is_bmc;
943 desc_info->wd_page = true;
944 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
945
946 switch (tx_req->tx_type) {
947 case RTW89_CORE_TX_TYPE_MGMT:
948 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
949 break;
950 case RTW89_CORE_TX_TYPE_DATA:
951 rtw89_core_tx_update_data_info(rtwdev, tx_req);
952 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
953 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
954 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
955 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
956 break;
957 case RTW89_CORE_TX_TYPE_FWCMD:
958 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
959 break;
960 }
961 }
962
rtw89_tx_wait_work(struct wiphy * wiphy,struct wiphy_work * work)963 static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work)
964 {
965 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
966 tx_wait_work.work);
967
968 rtw89_tx_wait_list_clear(rtwdev);
969 }
970
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)971 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
972 {
973 u8 ch_dma;
974
975 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
976
977 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
978 }
979
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)980 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
981 int qsel, unsigned int timeout)
982 {
983 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
984 struct rtw89_tx_wait_info *wait;
985 unsigned long time_left;
986 int ret = 0;
987
988 lockdep_assert_wiphy(rtwdev->hw->wiphy);
989
990 wait = kzalloc(sizeof(*wait), GFP_KERNEL);
991 if (!wait) {
992 rtw89_core_tx_kick_off(rtwdev, qsel);
993 return 0;
994 }
995
996 init_completion(&wait->completion);
997 wait->skb = skb;
998 rcu_assign_pointer(skb_data->wait, wait);
999
1000 rtw89_core_tx_kick_off(rtwdev, qsel);
1001 time_left = wait_for_completion_timeout(&wait->completion,
1002 msecs_to_jiffies(timeout));
1003
1004 if (time_left == 0) {
1005 ret = -ETIMEDOUT;
1006 list_add_tail(&wait->list, &rtwdev->tx_waits);
1007 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work,
1008 RTW89_TX_WAIT_WORK_TIMEOUT);
1009 } else {
1010 if (!wait->tx_done)
1011 ret = -EAGAIN;
1012 rtw89_tx_wait_release(wait);
1013 }
1014
1015 return ret;
1016 }
1017
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1018 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1019 struct sk_buff *skb, bool fwdl)
1020 {
1021 struct rtw89_core_tx_request tx_req = {0};
1022 u32 cnt;
1023 int ret;
1024
1025 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1026 rtw89_debug(rtwdev, RTW89_DBG_FW,
1027 "ignore h2c due to power is off with firmware state=%d\n",
1028 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1029 dev_kfree_skb(skb);
1030 return 0;
1031 }
1032
1033 tx_req.skb = skb;
1034 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1035 if (fwdl)
1036 tx_req.desc_info.fw_dl = true;
1037
1038 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1039
1040 if (!fwdl)
1041 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1042
1043 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1044 if (cnt == 0) {
1045 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1046 return -ENOSPC;
1047 }
1048
1049 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1050 if (ret) {
1051 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1052 return ret;
1053 }
1054 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1055
1056 return 0;
1057 }
1058
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1059 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1060 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1061 {
1062 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1063 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1064 struct rtw89_core_tx_request tx_req = {0};
1065 struct rtw89_sta_link *rtwsta_link = NULL;
1066 struct rtw89_vif_link *rtwvif_link;
1067 int ret;
1068
1069 /* By default, driver writes tx via the link on HW-0. And then,
1070 * according to links' status, HW can change tx to another link.
1071 */
1072
1073 if (rtwsta) {
1074 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1075 if (unlikely(!rtwsta_link)) {
1076 rtw89_err(rtwdev, "tx: find no sta link on HW-0\n");
1077 return -ENOLINK;
1078 }
1079 }
1080
1081 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
1082 if (unlikely(!rtwvif_link)) {
1083 rtw89_err(rtwdev, "tx: find no vif link on HW-0\n");
1084 return -ENOLINK;
1085 }
1086
1087 tx_req.skb = skb;
1088 tx_req.rtwvif_link = rtwvif_link;
1089 tx_req.rtwsta_link = rtwsta_link;
1090
1091 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
1092 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
1093 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1094 rtw89_core_tx_wake(rtwdev, &tx_req);
1095
1096 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1097 if (ret) {
1098 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1099 return ret;
1100 }
1101
1102 if (qsel)
1103 *qsel = tx_req.desc_info.qsel;
1104
1105 return 0;
1106 }
1107
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1108 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1109 {
1110 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1111 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1112 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1113 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1114 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1115 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1116 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1117 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1118
1119 return cpu_to_le32(dword);
1120 }
1121
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1122 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1123 {
1124 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1125 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1126 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1127 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1128 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1129 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1130
1131 return cpu_to_le32(dword);
1132 }
1133
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1134 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1135 {
1136 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1137 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1138 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1139
1140 return cpu_to_le32(dword);
1141 }
1142
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1143 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1144 {
1145 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1146 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1147 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1148 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1149
1150 return cpu_to_le32(dword);
1151 }
1152
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1153 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1154 {
1155 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1156 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1157 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1158
1159 return cpu_to_le32(dword);
1160 }
1161
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1162 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1163 {
1164 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1165 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1166
1167 return cpu_to_le32(dword);
1168 }
1169
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1170 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1171 {
1172 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1173 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1174 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1175 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1176
1177 return cpu_to_le32(dword);
1178 }
1179
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1180 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1181 {
1182 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1183 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1184
1185 return cpu_to_le32(dword);
1186 }
1187
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1188 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1189 {
1190 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1191 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1192 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1193 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1194 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1195 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1196
1197 return cpu_to_le32(dword);
1198 }
1199
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1200 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1201 {
1202 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1203 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1204 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1205 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1206 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1207 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1208
1209 return cpu_to_le32(dword);
1210 }
1211
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1212 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1213 {
1214 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1215 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1216 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1217 desc_info->data_retry_lowest_rate);
1218
1219 return cpu_to_le32(dword);
1220 }
1221
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1222 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1223 {
1224 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1225 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1226 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1227 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1228
1229 return cpu_to_le32(dword);
1230 }
1231
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1232 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1233 {
1234 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1235 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1236 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1237
1238 return cpu_to_le32(dword);
1239 }
1240
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1241 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1242 {
1243 bool rts_en = !desc_info->is_bmc;
1244 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1245 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1246
1247 return cpu_to_le32(dword);
1248 }
1249
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1250 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1251 struct rtw89_tx_desc_info *desc_info,
1252 void *txdesc)
1253 {
1254 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1255 struct rtw89_txwd_info *txwd_info;
1256
1257 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1258 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1259 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1260
1261 if (!desc_info->en_wd_info)
1262 return;
1263
1264 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1265 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1266 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1267 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1268 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1269
1270 }
1271 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1272
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1273 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1274 struct rtw89_tx_desc_info *desc_info,
1275 void *txdesc)
1276 {
1277 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1278 struct rtw89_txwd_info *txwd_info;
1279
1280 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1281 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1282 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1283 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1284 if (desc_info->sec_en) {
1285 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1286 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1287 }
1288 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1289
1290 if (!desc_info->en_wd_info)
1291 return;
1292
1293 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1294 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1295 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1296 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1297 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1298 }
1299 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1300
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1301 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1302 {
1303 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1304 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1305 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1306 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1307 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1308
1309 return cpu_to_le32(dword);
1310 }
1311
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1312 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1313 {
1314 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1315 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1316 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1317
1318 return cpu_to_le32(dword);
1319 }
1320
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1321 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1322 {
1323 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1324 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1325 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1326 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1327 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1328 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1329
1330 return cpu_to_le32(dword);
1331 }
1332
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1333 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1334 {
1335 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq);
1336
1337 return cpu_to_le32(dword);
1338 }
1339
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1340 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1341 {
1342 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1343 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1344
1345 return cpu_to_le32(dword);
1346 }
1347
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1348 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1349 {
1350 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1351 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1352 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1353 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1354
1355 return cpu_to_le32(dword);
1356 }
1357
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1358 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1359 {
1360 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1361 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1362 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1363 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1364
1365 return cpu_to_le32(dword);
1366 }
1367
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1368 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1369 {
1370 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1371 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1372 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1373 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port);
1374
1375 return cpu_to_le32(dword);
1376 }
1377
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1378 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1379 {
1380 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1381 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1382 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1383 desc_info->data_retry_lowest_rate);
1384
1385 return cpu_to_le32(dword);
1386 }
1387
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1388 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1389 {
1390 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1391 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1392 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1393
1394 return cpu_to_le32(dword);
1395 }
1396
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1397 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1398 {
1399 bool rts_en = !desc_info->is_bmc;
1400 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1401 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1402
1403 return cpu_to_le32(dword);
1404 }
1405
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1406 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1407 struct rtw89_tx_desc_info *desc_info,
1408 void *txdesc)
1409 {
1410 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1411 struct rtw89_txwd_info_v2 *txwd_info;
1412
1413 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1414 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1415 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1416 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1417 if (desc_info->sec_en) {
1418 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1419 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1420 }
1421 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1422
1423 if (!desc_info->en_wd_info)
1424 return;
1425
1426 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1427 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1428 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1429 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1430 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1431 }
1432 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1433
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1434 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1435 {
1436 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1437 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1438 RTW89_CORE_RX_TYPE_FWDL :
1439 RTW89_CORE_RX_TYPE_H2C);
1440
1441 return cpu_to_le32(dword);
1442 }
1443
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1444 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1445 struct rtw89_tx_desc_info *desc_info,
1446 void *txdesc)
1447 {
1448 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1449
1450 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1451 }
1452 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1453
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1454 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1455 {
1456 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1457 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1458 RTW89_CORE_RX_TYPE_FWDL :
1459 RTW89_CORE_RX_TYPE_H2C);
1460
1461 return cpu_to_le32(dword);
1462 }
1463
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1464 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1465 struct rtw89_tx_desc_info *desc_info,
1466 void *txdesc)
1467 {
1468 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1469
1470 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1471 }
1472 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1473
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1474 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1475 struct sk_buff *skb,
1476 struct rtw89_rx_phy_ppdu *phy_ppdu)
1477 {
1478 const struct rtw89_chip_info *chip = rtwdev->chip;
1479 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1480 const struct rtw89_rxinfo_user *user;
1481 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1482 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1483 bool rx_cnt_valid = false;
1484 bool invalid = false;
1485 u8 plcp_size = 0;
1486 u8 *phy_sts;
1487 u8 usr_num;
1488 int i;
1489
1490 if (chip_gen == RTW89_CHIP_BE) {
1491 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1492 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1493 }
1494
1495 if (invalid)
1496 return -EINVAL;
1497
1498 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1499 if (chip_gen == RTW89_CHIP_BE) {
1500 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1501 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1502 } else {
1503 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1504 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1505 }
1506 if (usr_num > chip->ppdu_max_usr) {
1507 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1508 usr_num);
1509 return -EINVAL;
1510 }
1511
1512 for (i = 0; i < usr_num; i++) {
1513 user = &rxinfo->user[i];
1514 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1515 continue;
1516 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1517 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1518 */
1519 if (chip_gen == RTW89_CHIP_BE)
1520 phy_ppdu->mac_id =
1521 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1522 phy_ppdu->has_data =
1523 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1524 phy_ppdu->has_bcn =
1525 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1526 break;
1527 }
1528
1529 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1530 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1531 /* 8-byte alignment */
1532 if (usr_num & BIT(0))
1533 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1534 if (rx_cnt_valid)
1535 phy_sts += rx_cnt_size;
1536 phy_sts += plcp_size;
1537
1538 if (phy_sts > skb->data + skb->len)
1539 return -EINVAL;
1540
1541 phy_ppdu->buf = phy_sts;
1542 phy_ppdu->len = skb->data + skb->len - phy_sts;
1543
1544 return 0;
1545 }
1546
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)1547 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
1548 {
1549 u8 data_rate_mode;
1550
1551 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1552 switch (data_rate_mode) {
1553 case DATA_RATE_MODE_NON_HT:
1554 return 1;
1555 case DATA_RATE_MODE_HT:
1556 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
1557 case DATA_RATE_MODE_VHT:
1558 case DATA_RATE_MODE_HE:
1559 case DATA_RATE_MODE_EHT:
1560 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
1561 default:
1562 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1563 return 0;
1564 }
1565 }
1566
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1567 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1568 struct ieee80211_sta *sta)
1569 {
1570 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1571 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
1572 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1573 struct rtw89_hal *hal = &rtwdev->hal;
1574 struct rtw89_sta_link *rtwsta_link;
1575 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1576 u8 ant_pos = U8_MAX;
1577 u8 evm_pos = 0;
1578 int i;
1579
1580 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
1581 * enabling multiple active links, we should determine the right link.
1582 */
1583 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
1584 if (unlikely(!rtwsta_link))
1585 return;
1586
1587 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1588 return;
1589
1590 if (hal->ant_diversity && hal->antenna_rx) {
1591 ant_pos = __ffs(hal->antenna_rx);
1592 evm_pos = ant_pos;
1593 }
1594
1595 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
1596
1597 if (ant_pos < ant_num) {
1598 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
1599 } else {
1600 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1601 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
1602 }
1603
1604 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
1605 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
1606 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
1607 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
1608 } else {
1609 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
1610 phy_ppdu->ofdm.evm_min);
1611 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
1612 phy_ppdu->ofdm.evm_max);
1613 }
1614 }
1615 }
1616
1617 #define VAR_LEN 0xff
1618 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1619 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
1620 const struct rtw89_phy_sts_iehdr *iehdr)
1621 {
1622 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
1623 [RTW89_CHIP_AX] = {
1624 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1625 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1626 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1627 },
1628 [RTW89_CHIP_BE] = {
1629 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1630 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1631 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1632 },
1633 };
1634 const u8 *physts_ie_len_tab;
1635 u16 ie_len;
1636 u8 ie;
1637
1638 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
1639
1640 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1641 if (physts_ie_len_tab[ie] != VAR_LEN)
1642 ie_len = physts_ie_len_tab[ie];
1643 else
1644 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
1645
1646 return ie_len;
1647 }
1648
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1649 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
1650 const struct rtw89_phy_sts_iehdr *iehdr,
1651 struct rtw89_rx_phy_ppdu *phy_ppdu)
1652 {
1653 const struct rtw89_phy_sts_ie01_v2 *ie;
1654 u8 *rpl_fd = phy_ppdu->rpl_fd;
1655
1656 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
1657 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
1658 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
1659 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
1660 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
1661
1662 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
1663 }
1664
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1665 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
1666 const struct rtw89_phy_sts_iehdr *iehdr,
1667 struct rtw89_rx_phy_ppdu *phy_ppdu)
1668 {
1669 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
1670 s16 cfo;
1671 u32 t;
1672
1673 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
1674
1675 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
1676 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
1677 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
1678 }
1679
1680 if (!phy_ppdu->hdr_2_en)
1681 phy_ppdu->rx_path_en =
1682 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
1683
1684 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1685 return;
1686
1687 if (!phy_ppdu->to_self)
1688 return;
1689
1690 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
1691 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
1692 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
1693 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
1694 phy_ppdu->ofdm.has = true;
1695
1696 /* sign conversion for S(12,2) */
1697 if (rtwdev->chip->cfo_src_fd) {
1698 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
1699 cfo = sign_extend32(t, 11);
1700 } else {
1701 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
1702 cfo = sign_extend32(t, 11);
1703 }
1704
1705 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1706
1707 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1708 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
1709 }
1710
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1711 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
1712 const struct rtw89_phy_sts_iehdr *iehdr,
1713 struct rtw89_rx_phy_ppdu *phy_ppdu)
1714 {
1715 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
1716 u16 tmp_rpl;
1717
1718 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
1719 phy_ppdu->rpl_avg = tmp_rpl >> 1;
1720 }
1721
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1722 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
1723 const struct rtw89_phy_sts_iehdr *iehdr,
1724 struct rtw89_rx_phy_ppdu *phy_ppdu)
1725 {
1726 const struct rtw89_phy_sts_ie00_v2 *ie;
1727 u8 *rpl_path = phy_ppdu->rpl_path;
1728 u16 tmp_rpl[RF_PATH_MAX];
1729 u8 i;
1730
1731 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
1732 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
1733 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
1734 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
1735 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
1736
1737 for (i = 0; i < RF_PATH_MAX; i++)
1738 rpl_path[i] = tmp_rpl[i] >> 1;
1739 }
1740
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1741 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
1742 const struct rtw89_phy_sts_iehdr *iehdr,
1743 struct rtw89_rx_phy_ppdu *phy_ppdu)
1744 {
1745 u8 ie;
1746
1747 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1748
1749 switch (ie) {
1750 case RTW89_PHYSTS_IE00_CMN_CCK:
1751 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
1752 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1753 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
1754 break;
1755 case RTW89_PHYSTS_IE01_CMN_OFDM:
1756 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
1757 break;
1758 default:
1759 break;
1760 }
1761
1762 return 0;
1763 }
1764
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)1765 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
1766 {
1767 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
1768
1769 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
1770 }
1771
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1772 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1773 {
1774 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1775 u8 *rssi = phy_ppdu->rssi;
1776
1777 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
1778 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
1779 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
1780 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
1781 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
1782 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
1783
1784 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
1785 if (phy_ppdu->hdr_2_en)
1786 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
1787 }
1788
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1789 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1790 struct rtw89_rx_phy_ppdu *phy_ppdu)
1791 {
1792 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1793 u32 len_from_header;
1794 bool physts_valid;
1795
1796 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
1797 if (!physts_valid)
1798 return -EINVAL;
1799
1800 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
1801
1802 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
1803 len_from_header += PHY_STS_HDR_LEN;
1804
1805 if (len_from_header != phy_ppdu->len) {
1806 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1807 return -EINVAL;
1808 }
1809 rtw89_core_update_phy_ppdu(phy_ppdu);
1810
1811 return 0;
1812 }
1813
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1814 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1815 struct rtw89_rx_phy_ppdu *phy_ppdu)
1816 {
1817 u16 ie_len;
1818 void *pos, *end;
1819
1820 /* mark invalid reports and bypass them */
1821 if (phy_ppdu->ie < RTW89_CCK_PKT)
1822 return -EINVAL;
1823
1824 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
1825 end = phy_ppdu->buf + phy_ppdu->len;
1826 while (pos < end) {
1827 const struct rtw89_phy_sts_iehdr *iehdr = pos;
1828
1829 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
1830 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
1831 pos += ie_len;
1832 if (pos > end || ie_len == 0) {
1833 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1834 "phy status parse failed\n");
1835 return -EINVAL;
1836 }
1837 }
1838
1839 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
1840 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
1841
1842 return 0;
1843 }
1844
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1845 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1846 struct rtw89_rx_phy_ppdu *phy_ppdu)
1847 {
1848 int ret;
1849
1850 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1851 if (ret)
1852 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1853 else
1854 phy_ppdu->valid = true;
1855
1856 ieee80211_iterate_stations_atomic(rtwdev->hw,
1857 rtw89_core_rx_process_phy_ppdu_iter,
1858 phy_ppdu);
1859 }
1860
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)1861 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
1862 u8 desc_info_gi,
1863 bool rx_status, bool eht)
1864 {
1865 switch (desc_info_gi) {
1866 case RTW89_GILTF_SGI_4XHE08:
1867 case RTW89_GILTF_2XHE08:
1868 case RTW89_GILTF_1XHE08:
1869 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 :
1870 NL80211_RATE_INFO_HE_GI_0_8;
1871 case RTW89_GILTF_2XHE16:
1872 case RTW89_GILTF_1XHE16:
1873 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 :
1874 NL80211_RATE_INFO_HE_GI_1_6;
1875 case RTW89_GILTF_LGI_4XHE32:
1876 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 :
1877 NL80211_RATE_INFO_HE_GI_3_2;
1878 default:
1879 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
1880 if (rx_status)
1881 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 :
1882 NL80211_RATE_INFO_HE_GI_3_2;
1883 return U8_MAX;
1884 }
1885 }
1886
1887 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)1888 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
1889 bool eht)
1890 {
1891 if (eht)
1892 return status->eht.gi == gi_ltf;
1893
1894 return status->he_gi == gi_ltf;
1895 }
1896
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1897 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
1898 struct rtw89_rx_desc_info *desc_info,
1899 struct ieee80211_rx_status *status)
1900 {
1901 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1902 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
1903 bool eht = false;
1904 u16 data_rate;
1905 bool ret;
1906
1907 data_rate = desc_info->data_rate;
1908 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1909 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1910 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
1911 /* rate_idx is still hardware value here */
1912 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
1913 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
1914 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
1915 data_rate_mode == DATA_RATE_MODE_HE ||
1916 data_rate_mode == DATA_RATE_MODE_EHT) {
1917 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1918 } else {
1919 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1920 }
1921
1922 eht = data_rate_mode == DATA_RATE_MODE_EHT;
1923 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1924 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
1925 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
1926 status->rate_idx == rate_idx &&
1927 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
1928 status->bw == bw;
1929
1930 return ret;
1931 }
1932
1933 struct rtw89_vif_rx_stats_iter_data {
1934 struct rtw89_dev *rtwdev;
1935 struct rtw89_rx_phy_ppdu *phy_ppdu;
1936 struct rtw89_rx_desc_info *desc_info;
1937 struct sk_buff *skb;
1938 const u8 *bssid;
1939 };
1940
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)1941 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
1942 struct rtw89_vif_link *rtwvif_link,
1943 struct ieee80211_bss_conf *bss_conf,
1944 struct sk_buff *skb)
1945 {
1946 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
1947 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1948 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
1949 u8 *pos, *end, type, tf_bw;
1950 u16 aid, tf_rua;
1951
1952 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
1953 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
1954 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
1955 return;
1956
1957 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
1958 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
1959 return;
1960
1961 end = (u8 *)tf + skb->len;
1962 pos = tf->variable;
1963
1964 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
1965 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
1966 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
1967 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
1968 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1969 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
1970 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
1971 tf_rua, tf_bw);
1972
1973 if (aid == RTW89_TF_PAD)
1974 break;
1975
1976 if (aid == vif->cfg.aid) {
1977 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
1978
1979 rtwvif->stats.rx_tf_acc++;
1980 rtwdev->stats.rx_tf_acc++;
1981 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
1982 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
1983 rtwvif_link->pwr_diff_en = true;
1984 break;
1985 }
1986
1987 pos += RTW89_TF_BASIC_USER_INFO_SZ;
1988 }
1989 }
1990
rtw89_cancel_6ghz_probe_work(struct work_struct * work)1991 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
1992 {
1993 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1994 cancel_6ghz_probe_work);
1995 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
1996 struct rtw89_pktofld_info *info;
1997
1998 mutex_lock(&rtwdev->mutex);
1999
2000 if (!rtwdev->scanning)
2001 goto out;
2002
2003 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2004 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2005 continue;
2006
2007 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2008
2009 /* Don't delete/free info from pkt_list at this moment. Let it
2010 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2011 * since if during scanning, pkt_list is accessed in bottom half.
2012 */
2013 }
2014
2015 out:
2016 mutex_unlock(&rtwdev->mutex);
2017 }
2018
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2019 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2020 struct sk_buff *skb)
2021 {
2022 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2023 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2024 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2025 struct rtw89_pktofld_info *info;
2026 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2027 bool queue_work = false;
2028
2029 if (rx_status->band != NL80211_BAND_6GHZ)
2030 return;
2031
2032 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) {
2033 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n");
2034 return;
2035 }
2036
2037 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2038
2039 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2040 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2041 info->cancel = true;
2042 queue_work = true;
2043 continue;
2044 }
2045
2046 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2047 continue;
2048
2049 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2050 info->cancel = true;
2051 queue_work = true;
2052 }
2053 }
2054
2055 if (queue_work)
2056 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
2057 }
2058
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2059 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2060 struct ieee80211_hdr *hdr, size_t len)
2061 {
2062 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2063
2064 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2065 return;
2066
2067 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2068 }
2069
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)2070 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
2071 struct ieee80211_vif *vif)
2072 {
2073 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
2074 struct rtw89_dev *rtwdev = iter_data->rtwdev;
2075 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
2076 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2077 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2078 struct sk_buff *skb = iter_data->skb;
2079 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2080 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
2081 struct ieee80211_bss_conf *bss_conf;
2082 struct rtw89_vif_link *rtwvif_link;
2083 const u8 *bssid = iter_data->bssid;
2084
2085 if (rtwdev->scanning &&
2086 (ieee80211_is_beacon(hdr->frame_control) ||
2087 ieee80211_is_probe_resp(hdr->frame_control)))
2088 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
2089
2090 rcu_read_lock();
2091
2092 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2093 * enabling multiple active links, we should determine the right link.
2094 */
2095 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0);
2096 if (unlikely(!rtwvif_link))
2097 goto out;
2098
2099 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
2100 if (!bss_conf->bssid)
2101 goto out;
2102
2103 if (ieee80211_is_trigger(hdr->frame_control)) {
2104 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
2105 goto out;
2106 }
2107
2108 if (!ether_addr_equal(bss_conf->bssid, bssid))
2109 goto out;
2110
2111 if (ieee80211_is_beacon(hdr->frame_control)) {
2112 if (vif->type == NL80211_IFTYPE_STATION &&
2113 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
2114 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
2115 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
2116 }
2117 pkt_stat->beacon_nr++;
2118 }
2119
2120 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
2121 goto out;
2122
2123 if (desc_info->data_rate < RTW89_HW_RATE_NR)
2124 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
2125
2126 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
2127
2128 out:
2129 rcu_read_unlock();
2130 }
2131
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2132 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
2133 struct rtw89_rx_phy_ppdu *phy_ppdu,
2134 struct rtw89_rx_desc_info *desc_info,
2135 struct sk_buff *skb)
2136 {
2137 struct rtw89_vif_rx_stats_iter_data iter_data;
2138
2139 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
2140
2141 iter_data.rtwdev = rtwdev;
2142 iter_data.phy_ppdu = phy_ppdu;
2143 iter_data.desc_info = desc_info;
2144 iter_data.skb = skb;
2145 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
2146 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
2147 }
2148
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)2149 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
2150 struct ieee80211_rx_status *status)
2151 {
2152 const struct rtw89_chan_rcd *rcd =
2153 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
2154 u16 chan = rcd->prev_primary_channel;
2155 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
2156
2157 if (status->band != NL80211_BAND_2GHZ &&
2158 status->encoding == RX_ENC_LEGACY &&
2159 status->rate_idx < RTW89_HW_RATE_OFDM6) {
2160 status->freq = ieee80211_channel_to_frequency(chan, band);
2161 status->band = band;
2162 }
2163 }
2164
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)2165 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
2166 {
2167 if (rx_status->band == NL80211_BAND_2GHZ ||
2168 rx_status->encoding != RX_ENC_LEGACY)
2169 return;
2170
2171 /* Some control frames' freq(ACKs in this case) are reported wrong due
2172 * to FW notify timing, set to lowest rate to prevent overflow.
2173 */
2174 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
2175 rx_status->rate_idx = 0;
2176 return;
2177 }
2178
2179 /* No 4 CCK rates for non-2G */
2180 rx_status->rate_idx -= 4;
2181 }
2182
2183 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)2184 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
2185 struct ieee80211_rx_status *rx_status,
2186 struct rtw89_rx_phy_ppdu *phy_ppdu)
2187 {
2188 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2189 return;
2190
2191 if (!phy_ppdu)
2192 return;
2193
2194 if (phy_ppdu->ldpc)
2195 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2196 if (phy_ppdu->stbc)
2197 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
2198 }
2199
2200 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
2201 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
2202 [RATE_INFO_BW_5] = U8_MAX,
2203 [RATE_INFO_BW_10] = U8_MAX,
2204 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
2205 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
2206 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
2207 [RATE_INFO_BW_HE_RU] = U8_MAX,
2208 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
2209 [RATE_INFO_BW_EHT_RU] = U8_MAX,
2210 };
2211
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2212 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
2213 struct sk_buff *skb,
2214 struct ieee80211_rx_status *rx_status)
2215 {
2216 struct ieee80211_radiotap_eht_usig *usig;
2217 struct ieee80211_radiotap_eht *eht;
2218 struct ieee80211_radiotap_tlv *tlv;
2219 int eht_len = struct_size(eht, user_info, 1);
2220 int usig_len = sizeof(*usig);
2221 int len;
2222 u8 bw;
2223
2224 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
2225 sizeof(*tlv) + ALIGN(usig_len, 4);
2226
2227 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
2228 skb_reset_mac_header(skb);
2229
2230 /* EHT */
2231 tlv = skb_push(skb, len);
2232 memset(tlv, 0, len);
2233 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
2234 tlv->len = cpu_to_le16(eht_len);
2235
2236 eht = (struct ieee80211_radiotap_eht *)tlv->data;
2237 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
2238 eht->data[0] =
2239 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
2240
2241 eht->user_info[0] =
2242 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
2243 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
2244 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
2245 eht->user_info[0] |=
2246 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
2247 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
2248 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
2249 eht->user_info[0] |=
2250 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
2251
2252 /* U-SIG */
2253 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
2254 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
2255 tlv->len = cpu_to_le16(usig_len);
2256
2257 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
2258 return;
2259
2260 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
2261 if (bw == U8_MAX)
2262 return;
2263
2264 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
2265 usig->common =
2266 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
2267 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
2268 }
2269
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)2270 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
2271 struct sk_buff *skb,
2272 struct ieee80211_rx_status *rx_status)
2273 {
2274 static const struct ieee80211_radiotap_he known_he = {
2275 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2276 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
2277 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
2278 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2279 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2280 };
2281 struct ieee80211_radiotap_he *he;
2282
2283 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
2284 return;
2285
2286 if (rx_status->encoding == RX_ENC_HE) {
2287 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
2288 he = skb_push(skb, sizeof(*he));
2289 *he = known_he;
2290 } else if (rx_status->encoding == RX_ENC_EHT) {
2291 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
2292 }
2293 }
2294
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)2295 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
2296 struct rtw89_rx_phy_ppdu *phy_ppdu,
2297 struct rtw89_rx_desc_info *desc_info,
2298 struct sk_buff *skb_ppdu,
2299 struct ieee80211_rx_status *rx_status)
2300 {
2301 struct napi_struct *napi = &rtwdev->napi;
2302
2303 /* In low power mode, napi isn't scheduled. Receive it to netif. */
2304 if (unlikely(!napi_is_scheduled(napi)))
2305 napi = NULL;
2306
2307 rtw89_core_hw_to_sband_rate(rx_status);
2308 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
2309 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
2310 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
2311 /* In low power mode, it does RX in thread context. */
2312 local_bh_disable();
2313 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
2314 local_bh_enable();
2315 rtwdev->napi_budget_countdown--;
2316 }
2317
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2318 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
2319 struct rtw89_rx_phy_ppdu *phy_ppdu,
2320 struct rtw89_rx_desc_info *desc_info,
2321 struct sk_buff *skb)
2322 {
2323 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2324 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
2325 struct sk_buff *skb_ppdu = NULL, *tmp;
2326 struct ieee80211_rx_status *rx_status;
2327
2328 if (curr > RTW89_MAX_PPDU_CNT)
2329 return;
2330
2331 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
2332 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
2333 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2334 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
2335 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
2336 rtw89_correct_cck_chan(rtwdev, rx_status);
2337 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
2338 }
2339 }
2340
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2341 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
2342 struct rtw89_rx_desc_info *desc_info,
2343 struct sk_buff *skb)
2344 {
2345 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
2346 .len = skb->len,
2347 .to_self = desc_info->addr1_match,
2348 .rate = desc_info->data_rate,
2349 .mac_id = desc_info->mac_id};
2350 int ret;
2351
2352 if (desc_info->mac_info_valid) {
2353 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
2354 if (ret)
2355 goto out;
2356 }
2357
2358 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
2359 if (ret)
2360 goto out;
2361
2362 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
2363
2364 out:
2365 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
2366 dev_kfree_skb_any(skb);
2367 }
2368
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2369 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
2370 struct rtw89_rx_desc_info *desc_info,
2371 struct sk_buff *skb)
2372 {
2373 switch (desc_info->pkt_type) {
2374 case RTW89_CORE_RX_TYPE_C2H:
2375 rtw89_fw_c2h_irqsafe(rtwdev, skb);
2376 break;
2377 case RTW89_CORE_RX_TYPE_PPDU_STAT:
2378 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
2379 break;
2380 default:
2381 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
2382 desc_info->pkt_type);
2383 dev_kfree_skb_any(skb);
2384 break;
2385 }
2386 }
2387
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2388 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
2389 struct rtw89_rx_desc_info *desc_info,
2390 u8 *data, u32 data_offset)
2391 {
2392 const struct rtw89_chip_info *chip = rtwdev->chip;
2393 struct rtw89_rxdesc_short *rxd_s;
2394 struct rtw89_rxdesc_long *rxd_l;
2395 u8 shift_len, drv_info_len;
2396
2397 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
2398 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
2399 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
2400 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
2401 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
2402 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
2403 if (chip->chip_id == RTL8852C)
2404 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
2405 else
2406 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
2407 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
2408 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
2409 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
2410 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
2411 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
2412 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
2413 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
2414 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
2415 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
2416 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
2417 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
2418 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
2419
2420 shift_len = desc_info->shift << 1; /* 2-byte unit */
2421 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2422 desc_info->offset = data_offset + shift_len + drv_info_len;
2423 if (desc_info->long_rxdesc)
2424 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
2425 else
2426 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
2427 desc_info->ready = true;
2428
2429 if (!desc_info->long_rxdesc)
2430 return;
2431
2432 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
2433 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
2434 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
2435 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
2436 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
2437 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
2438 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
2439 }
2440 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
2441
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)2442 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
2443 struct rtw89_rx_desc_info *desc_info,
2444 u8 *data, u32 data_offset)
2445 {
2446 struct rtw89_rxdesc_short_v2 *rxd_s;
2447 struct rtw89_rxdesc_long_v2 *rxd_l;
2448 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
2449
2450 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
2451
2452 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
2453 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
2454 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
2455 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
2456 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
2457 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
2458 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
2459 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
2460 desc_info->mac_info_valid = true;
2461
2462 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
2463 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
2464 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
2465
2466 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
2467 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
2468 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
2469 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
2470 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
2471
2472 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
2473 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
2474 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
2475 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
2476 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
2477
2478 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
2479
2480 shift_len = desc_info->shift << 1; /* 2-byte unit */
2481 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
2482 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
2483 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
2484 desc_info->offset = data_offset + shift_len + drv_info_len +
2485 phy_rtp_len + hdr_cnv_len;
2486
2487 if (desc_info->long_rxdesc)
2488 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
2489 else
2490 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
2491 desc_info->ready = true;
2492
2493 if (!desc_info->long_rxdesc)
2494 return;
2495
2496 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
2497
2498 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
2499 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
2500 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
2501 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
2502
2503 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
2504 }
2505 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
2506
2507 struct rtw89_core_iter_rx_status {
2508 struct rtw89_dev *rtwdev;
2509 struct ieee80211_rx_status *rx_status;
2510 struct rtw89_rx_desc_info *desc_info;
2511 u8 mac_id;
2512 };
2513
2514 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)2515 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
2516 {
2517 struct rtw89_core_iter_rx_status *iter_data =
2518 (struct rtw89_core_iter_rx_status *)data;
2519 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
2520 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2521 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2522 struct rtw89_sta_link *rtwsta_link;
2523 u8 mac_id = iter_data->mac_id;
2524
2525 /* FIXME: For single link, taking link on HW-0 here is okay. But, when
2526 * enabling multiple active links, we should determine the right link.
2527 */
2528 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
2529 if (unlikely(!rtwsta_link))
2530 return;
2531
2532 if (mac_id != rtwsta_link->mac_id)
2533 return;
2534
2535 rtwsta_link->rx_status = *rx_status;
2536 rtwsta_link->rx_hw_rate = desc_info->data_rate;
2537 }
2538
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2539 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
2540 struct rtw89_rx_desc_info *desc_info,
2541 struct ieee80211_rx_status *rx_status)
2542 {
2543 struct rtw89_core_iter_rx_status iter_data;
2544
2545 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
2546 return;
2547
2548 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
2549 return;
2550
2551 iter_data.rtwdev = rtwdev;
2552 iter_data.rx_status = rx_status;
2553 iter_data.desc_info = desc_info;
2554 iter_data.mac_id = desc_info->mac_id;
2555 ieee80211_iterate_stations_atomic(rtwdev->hw,
2556 rtw89_core_stats_sta_rx_status_iter,
2557 &iter_data);
2558 }
2559
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2560 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
2561 struct rtw89_rx_desc_info *desc_info,
2562 struct ieee80211_rx_status *rx_status)
2563 {
2564 const struct cfg80211_chan_def *chandef =
2565 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
2566 u16 data_rate;
2567 u8 data_rate_mode;
2568 bool eht = false;
2569 u8 gi;
2570
2571 /* currently using single PHY */
2572 rx_status->freq = chandef->chan->center_freq;
2573 rx_status->band = chandef->chan->band;
2574
2575 if (rtwdev->scanning &&
2576 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
2577 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
2578 u8 chan = cur->primary_channel;
2579 u8 band = cur->band_type;
2580 enum nl80211_band nl_band;
2581
2582 nl_band = rtw89_hw_to_nl80211_band(band);
2583 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
2584 rx_status->band = nl_band;
2585 }
2586
2587 if (desc_info->icv_err || desc_info->crc32_err)
2588 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2589
2590 if (desc_info->hw_dec &&
2591 !(desc_info->sw_dec || desc_info->icv_err))
2592 rx_status->flag |= RX_FLAG_DECRYPTED;
2593
2594 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2595
2596 data_rate = desc_info->data_rate;
2597 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2598 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2599 rx_status->encoding = RX_ENC_LEGACY;
2600 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2601 /* convert rate_idx after we get the correct band */
2602 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2603 rx_status->encoding = RX_ENC_HT;
2604 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2605 if (desc_info->gi_ltf)
2606 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2607 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
2608 rx_status->encoding = RX_ENC_VHT;
2609 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2610 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2611 if (desc_info->gi_ltf)
2612 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2613 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
2614 rx_status->encoding = RX_ENC_HE;
2615 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2616 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2617 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
2618 rx_status->encoding = RX_ENC_EHT;
2619 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2620 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
2621 eht = true;
2622 } else {
2623 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2624 }
2625
2626 /* he_gi is used to match ppdu, so we always fill it. */
2627 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
2628 if (eht)
2629 rx_status->eht.gi = gi;
2630 else
2631 rx_status->he_gi = gi;
2632 rx_status->flag |= RX_FLAG_MACTIME_START;
2633 rx_status->mactime = desc_info->free_run_cnt;
2634
2635 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
2636 }
2637
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)2638 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
2639 {
2640 const struct rtw89_chip_info *chip = rtwdev->chip;
2641
2642 /* FIXME: Fix __rtw89_enter_ps_mode() to consider MLO cases. */
2643 if (rtwdev->support_mlo)
2644 return RTW89_PS_MODE_NONE;
2645
2646 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
2647 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
2648 return RTW89_PS_MODE_NONE;
2649
2650 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
2651 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
2652 return RTW89_PS_MODE_PWR_GATED;
2653
2654 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
2655 return RTW89_PS_MODE_CLK_GATED;
2656
2657 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
2658 return RTW89_PS_MODE_RFOFF;
2659
2660 return RTW89_PS_MODE_NONE;
2661 }
2662
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2663 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
2664 struct rtw89_rx_desc_info *desc_info)
2665 {
2666 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2667 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2668 struct ieee80211_rx_status *rx_status;
2669 struct sk_buff *skb_ppdu, *tmp;
2670
2671 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
2672 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
2673 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2674 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
2675 }
2676 }
2677
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2678 void rtw89_core_rx(struct rtw89_dev *rtwdev,
2679 struct rtw89_rx_desc_info *desc_info,
2680 struct sk_buff *skb)
2681 {
2682 struct ieee80211_rx_status *rx_status;
2683 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2684 u8 ppdu_cnt = desc_info->ppdu_cnt;
2685 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2686
2687 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
2688 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
2689 return;
2690 }
2691
2692 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
2693 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
2694 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
2695 }
2696
2697 rx_status = IEEE80211_SKB_RXCB(skb);
2698 memset(rx_status, 0, sizeof(*rx_status));
2699 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
2700 if (desc_info->long_rxdesc &&
2701 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
2702 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
2703 else
2704 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
2705 }
2706 EXPORT_SYMBOL(rtw89_core_rx);
2707
rtw89_core_napi_start(struct rtw89_dev * rtwdev)2708 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
2709 {
2710 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2711 return;
2712
2713 napi_enable(&rtwdev->napi);
2714 }
2715 EXPORT_SYMBOL(rtw89_core_napi_start);
2716
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2717 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
2718 {
2719 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2720 return;
2721
2722 napi_synchronize(&rtwdev->napi);
2723 napi_disable(&rtwdev->napi);
2724 }
2725 EXPORT_SYMBOL(rtw89_core_napi_stop);
2726
rtw89_core_napi_init(struct rtw89_dev * rtwdev)2727 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
2728 {
2729 rtwdev->netdev = alloc_netdev_dummy(0);
2730 if (!rtwdev->netdev)
2731 return -ENOMEM;
2732
2733 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
2734 rtwdev->hci.ops->napi_poll);
2735 return 0;
2736 }
2737 EXPORT_SYMBOL(rtw89_core_napi_init);
2738
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2739 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
2740 {
2741 rtw89_core_napi_stop(rtwdev);
2742 netif_napi_del(&rtwdev->napi);
2743 free_netdev(rtwdev->netdev);
2744 }
2745 EXPORT_SYMBOL(rtw89_core_napi_deinit);
2746
rtw89_core_ba_work(struct work_struct * work)2747 static void rtw89_core_ba_work(struct work_struct *work)
2748 {
2749 struct rtw89_dev *rtwdev =
2750 container_of(work, struct rtw89_dev, ba_work);
2751 struct rtw89_txq *rtwtxq, *tmp;
2752 int ret;
2753
2754 spin_lock_bh(&rtwdev->ba_lock);
2755 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2756 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2757 struct ieee80211_sta *sta = txq->sta;
2758 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2759 u8 tid = txq->tid;
2760
2761 if (!sta) {
2762 rtw89_warn(rtwdev, "cannot start BA without sta\n");
2763 goto skip_ba_work;
2764 }
2765
2766 if (rtwsta->disassoc) {
2767 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2768 "cannot start BA with disassoc sta\n");
2769 goto skip_ba_work;
2770 }
2771
2772 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
2773 if (ret) {
2774 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2775 "failed to setup BA session for %pM:%2d: %d\n",
2776 sta->addr, tid, ret);
2777 if (ret == -EINVAL)
2778 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
2779 }
2780 skip_ba_work:
2781 list_del_init(&rtwtxq->list);
2782 }
2783 spin_unlock_bh(&rtwdev->ba_lock);
2784 }
2785
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2786 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
2787 struct ieee80211_sta *sta)
2788 {
2789 struct rtw89_txq *rtwtxq, *tmp;
2790
2791 spin_lock_bh(&rtwdev->ba_lock);
2792 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2793 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2794
2795 if (sta == txq->sta)
2796 list_del_init(&rtwtxq->list);
2797 }
2798 spin_unlock_bh(&rtwdev->ba_lock);
2799 }
2800
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2801 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
2802 struct ieee80211_sta *sta)
2803 {
2804 struct rtw89_txq *rtwtxq, *tmp;
2805
2806 spin_lock_bh(&rtwdev->ba_lock);
2807 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2808 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2809
2810 if (sta == txq->sta) {
2811 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2812 list_del_init(&rtwtxq->list);
2813 }
2814 }
2815 spin_unlock_bh(&rtwdev->ba_lock);
2816 }
2817
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2818 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
2819 struct ieee80211_sta *sta)
2820 {
2821 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2822 struct sk_buff *skb, *tmp;
2823
2824 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2825 skb_unlink(skb, &rtwsta->roc_queue);
2826 dev_kfree_skb_any(skb);
2827 }
2828 }
2829
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)2830 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
2831 struct rtw89_txq *rtwtxq)
2832 {
2833 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2834 struct ieee80211_sta *sta = txq->sta;
2835 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2836
2837 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
2838 return;
2839
2840 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
2841 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2842 return;
2843
2844 spin_lock_bh(&rtwdev->ba_lock);
2845 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2846 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
2847 spin_unlock_bh(&rtwdev->ba_lock);
2848
2849 ieee80211_stop_tx_ba_session(sta, txq->tid);
2850 cancel_delayed_work(&rtwdev->forbid_ba_work);
2851 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
2852 RTW89_FORBID_BA_TIMER);
2853 }
2854
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)2855 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
2856 struct rtw89_txq *rtwtxq,
2857 struct sk_buff *skb)
2858 {
2859 struct ieee80211_hw *hw = rtwdev->hw;
2860 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2861 struct ieee80211_sta *sta = txq->sta;
2862 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2863
2864 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2865 return;
2866
2867 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
2868 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
2869 return;
2870 }
2871
2872 if (unlikely(!sta))
2873 return;
2874
2875 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
2876 return;
2877
2878 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
2879 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
2880 return;
2881 }
2882
2883 spin_lock_bh(&rtwdev->ba_lock);
2884 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
2885 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
2886 ieee80211_queue_work(hw, &rtwdev->ba_work);
2887 }
2888 spin_unlock_bh(&rtwdev->ba_lock);
2889 }
2890
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)2891 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
2892 struct rtw89_txq *rtwtxq,
2893 unsigned long frame_cnt,
2894 unsigned long byte_cnt)
2895 {
2896 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2897 struct ieee80211_vif *vif = txq->vif;
2898 struct ieee80211_sta *sta = txq->sta;
2899 struct sk_buff *skb;
2900 unsigned long i;
2901 int ret;
2902
2903 rcu_read_lock();
2904 for (i = 0; i < frame_cnt; i++) {
2905 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
2906 if (!skb) {
2907 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
2908 goto out;
2909 }
2910 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
2911 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
2912 if (ret) {
2913 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
2914 ieee80211_free_txskb(rtwdev->hw, skb);
2915 break;
2916 }
2917 }
2918 out:
2919 rcu_read_unlock();
2920 }
2921
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)2922 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
2923 {
2924 u8 qsel, ch_dma;
2925
2926 qsel = rtw89_core_get_qsel(rtwdev, tid);
2927 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
2928
2929 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
2930 }
2931
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)2932 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
2933 struct ieee80211_txq *txq,
2934 unsigned long *frame_cnt,
2935 bool *sched_txq, bool *reinvoke)
2936 {
2937 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2938 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
2939 struct rtw89_sta_link *rtwsta_link;
2940
2941 if (!rtwsta)
2942 return false;
2943
2944 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0);
2945 if (unlikely(!rtwsta_link)) {
2946 rtw89_err(rtwdev, "agg wait: find no link on HW-0\n");
2947 return false;
2948 }
2949
2950 if (rtwsta_link->max_agg_wait <= 0)
2951 return false;
2952
2953 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
2954 return false;
2955
2956 if (*frame_cnt > 1) {
2957 *frame_cnt -= 1;
2958 *sched_txq = true;
2959 *reinvoke = true;
2960 rtwtxq->wait_cnt = 1;
2961 return false;
2962 }
2963
2964 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
2965 *reinvoke = true;
2966 rtwtxq->wait_cnt++;
2967 return true;
2968 }
2969
2970 rtwtxq->wait_cnt = 0;
2971 return false;
2972 }
2973
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)2974 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
2975 {
2976 struct ieee80211_hw *hw = rtwdev->hw;
2977 struct ieee80211_txq *txq;
2978 struct rtw89_vif *rtwvif;
2979 struct rtw89_txq *rtwtxq;
2980 unsigned long frame_cnt;
2981 unsigned long byte_cnt;
2982 u32 tx_resource;
2983 bool sched_txq;
2984
2985 ieee80211_txq_schedule_start(hw, ac);
2986 while ((txq = ieee80211_next_txq(hw, ac))) {
2987 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2988 rtwvif = vif_to_rtwvif(txq->vif);
2989
2990 if (rtwvif->offchan) {
2991 ieee80211_return_txq(hw, txq, true);
2992 continue;
2993 }
2994 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
2995 sched_txq = false;
2996
2997 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
2998 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
2999 ieee80211_return_txq(hw, txq, true);
3000 continue;
3001 }
3002 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
3003 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
3004 ieee80211_return_txq(hw, txq, sched_txq);
3005 if (frame_cnt != 0)
3006 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
3007
3008 /* bound of tx_resource could get stuck due to burst traffic */
3009 if (frame_cnt == tx_resource)
3010 *reinvoke = true;
3011 }
3012 ieee80211_txq_schedule_end(hw, ac);
3013 }
3014
rtw89_ips_work(struct work_struct * work)3015 static void rtw89_ips_work(struct work_struct *work)
3016 {
3017 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3018 ips_work);
3019 mutex_lock(&rtwdev->mutex);
3020 rtw89_enter_ips_by_hwflags(rtwdev);
3021 mutex_unlock(&rtwdev->mutex);
3022 }
3023
rtw89_core_txq_work(struct work_struct * w)3024 static void rtw89_core_txq_work(struct work_struct *w)
3025 {
3026 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
3027 bool reinvoke = false;
3028 u8 ac;
3029
3030 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3031 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
3032
3033 if (reinvoke) {
3034 /* reinvoke to process the last frame */
3035 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
3036 }
3037 }
3038
rtw89_core_txq_reinvoke_work(struct work_struct * w)3039 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
3040 {
3041 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3042 txq_reinvoke_work.work);
3043
3044 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3045 }
3046
rtw89_forbid_ba_work(struct work_struct * w)3047 static void rtw89_forbid_ba_work(struct work_struct *w)
3048 {
3049 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
3050 forbid_ba_work.work);
3051 struct rtw89_txq *rtwtxq, *tmp;
3052
3053 spin_lock_bh(&rtwdev->ba_lock);
3054 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
3055 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3056 list_del_init(&rtwtxq->list);
3057 }
3058 spin_unlock_bh(&rtwdev->ba_lock);
3059 }
3060
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)3061 static void rtw89_core_sta_pending_tx_iter(void *data,
3062 struct ieee80211_sta *sta)
3063 {
3064 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3065 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3066 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
3067 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3068 struct rtw89_vif_link *target = data;
3069 struct rtw89_vif_link *rtwvif_link;
3070 struct sk_buff *skb, *tmp;
3071 unsigned int link_id;
3072 int qsel, ret;
3073
3074 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3075 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
3076 goto bottom;
3077
3078 return;
3079
3080 bottom:
3081 if (skb_queue_len(&rtwsta->roc_queue) == 0)
3082 return;
3083
3084 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
3085 skb_unlink(skb, &rtwsta->roc_queue);
3086
3087 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3088 if (ret) {
3089 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
3090 dev_kfree_skb_any(skb);
3091 } else {
3092 rtw89_core_tx_kick_off(rtwdev, qsel);
3093 }
3094 }
3095 }
3096
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)3097 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
3098 struct rtw89_vif_link *rtwvif_link)
3099 {
3100 ieee80211_iterate_stations_atomic(rtwdev->hw,
3101 rtw89_core_sta_pending_tx_iter,
3102 rtwvif_link);
3103 }
3104
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps)3105 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev,
3106 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps)
3107 {
3108 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3109 struct ieee80211_sta *sta;
3110 struct ieee80211_hdr *hdr;
3111 struct sk_buff *skb;
3112 int ret, qsel;
3113
3114 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
3115 return 0;
3116
3117 rcu_read_lock();
3118 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
3119 if (!sta) {
3120 ret = -EINVAL;
3121 goto out;
3122 }
3123
3124 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos);
3125 if (!skb) {
3126 ret = -ENOMEM;
3127 goto out;
3128 }
3129
3130 hdr = (struct ieee80211_hdr *)skb->data;
3131 if (ps)
3132 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
3133
3134 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
3135 if (ret) {
3136 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
3137 dev_kfree_skb_any(skb);
3138 goto out;
3139 }
3140
3141 rcu_read_unlock();
3142
3143 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel,
3144 RTW89_ROC_TX_TIMEOUT);
3145 out:
3146 rcu_read_unlock();
3147
3148 return ret;
3149 }
3150
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3151 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3152 {
3153 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3154 struct ieee80211_hw *hw = rtwdev->hw;
3155 struct rtw89_roc *roc = &rtwvif->roc;
3156 struct rtw89_vif_link *rtwvif_link;
3157 struct cfg80211_chan_def roc_chan;
3158 struct rtw89_vif *tmp_vif;
3159 int ret;
3160
3161 lockdep_assert_held(&rtwdev->mutex);
3162
3163 rtw89_leave_ips_by_hwflags(rtwdev);
3164 rtw89_leave_lps(rtwdev);
3165
3166 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3167 if (unlikely(!rtwvif_link)) {
3168 rtw89_err(rtwdev, "roc start: find no link on HW-%u\n",
3169 RTW89_ROC_BY_LINK_INDEX);
3170 return;
3171 }
3172
3173 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC);
3174
3175 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true);
3176 if (ret)
3177 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3178 "roc send null-1 failed: %d\n", ret);
3179
3180 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
3181 struct rtw89_vif_link *tmp_link;
3182 unsigned int link_id;
3183
3184 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
3185 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
3186 tmp_vif->offchan = true;
3187 break;
3188 }
3189 }
3190 }
3191
3192 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
3193 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, &roc_chan);
3194 rtw89_set_channel(rtwdev);
3195 rtw89_write32_clr(rtwdev,
3196 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
3197 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
3198
3199 ieee80211_ready_on_channel(hw);
3200 cancel_delayed_work(&rtwvif->roc.roc_work);
3201 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work,
3202 msecs_to_jiffies(rtwvif->roc.duration));
3203 }
3204
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3205 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3206 {
3207 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3208 struct ieee80211_hw *hw = rtwdev->hw;
3209 struct rtw89_roc *roc = &rtwvif->roc;
3210 struct rtw89_vif_link *rtwvif_link;
3211 struct rtw89_vif *tmp_vif;
3212 int ret;
3213
3214 lockdep_assert_held(&rtwdev->mutex);
3215
3216 ieee80211_remain_on_channel_expired(hw);
3217
3218 rtw89_leave_ips_by_hwflags(rtwdev);
3219 rtw89_leave_lps(rtwdev);
3220
3221 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX);
3222 if (unlikely(!rtwvif_link)) {
3223 rtw89_err(rtwdev, "roc end: find no link on HW-%u\n",
3224 RTW89_ROC_BY_LINK_INDEX);
3225 return;
3226 }
3227
3228 rtw89_write32_mask(rtwdev,
3229 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
3230 B_AX_RX_FLTR_CFG_MASK,
3231 rtwdev->hal.rx_fltr);
3232
3233 roc->state = RTW89_ROC_IDLE;
3234 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, NULL);
3235 rtw89_chanctx_proceed(rtwdev, NULL);
3236 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false);
3237 if (ret)
3238 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3239 "roc send null-0 failed: %d\n", ret);
3240
3241 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
3242 tmp_vif->offchan = false;
3243
3244 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
3245 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
3246
3247 if (hw->conf.flags & IEEE80211_CONF_IDLE)
3248 ieee80211_queue_delayed_work(hw, &roc->roc_work,
3249 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
3250 }
3251
rtw89_roc_work(struct work_struct * work)3252 void rtw89_roc_work(struct work_struct *work)
3253 {
3254 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
3255 roc.roc_work.work);
3256 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3257 struct rtw89_roc *roc = &rtwvif->roc;
3258
3259 mutex_lock(&rtwdev->mutex);
3260
3261 switch (roc->state) {
3262 case RTW89_ROC_IDLE:
3263 rtw89_enter_ips_by_hwflags(rtwdev);
3264 break;
3265 case RTW89_ROC_MGMT:
3266 case RTW89_ROC_NORMAL:
3267 rtw89_roc_end(rtwdev, rtwvif);
3268 break;
3269 default:
3270 break;
3271 }
3272
3273 mutex_unlock(&rtwdev->mutex);
3274 }
3275
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)3276 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
3277 u32 throughput, u64 cnt)
3278 {
3279 if (cnt < 100)
3280 return RTW89_TFC_IDLE;
3281 if (throughput > 50)
3282 return RTW89_TFC_HIGH;
3283 if (throughput > 10)
3284 return RTW89_TFC_MID;
3285 if (throughput > 2)
3286 return RTW89_TFC_LOW;
3287 return RTW89_TFC_ULTRA_LOW;
3288 }
3289
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3290 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
3291 struct rtw89_traffic_stats *stats)
3292 {
3293 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
3294 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
3295
3296 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
3297 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
3298
3299 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
3300 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
3301
3302 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
3303 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
3304 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
3305 stats->tx_cnt);
3306 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
3307 stats->rx_cnt);
3308 stats->tx_avg_len = stats->tx_cnt ?
3309 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
3310 stats->rx_avg_len = stats->rx_cnt ?
3311 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
3312
3313 stats->tx_unicast = 0;
3314 stats->rx_unicast = 0;
3315 stats->tx_cnt = 0;
3316 stats->rx_cnt = 0;
3317 stats->rx_tf_periodic = stats->rx_tf_acc;
3318 stats->rx_tf_acc = 0;
3319
3320 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
3321 return true;
3322
3323 return false;
3324 }
3325
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)3326 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
3327 {
3328 struct rtw89_vif_link *rtwvif_link;
3329 struct rtw89_vif *rtwvif;
3330 unsigned int link_id;
3331 bool tfc_changed;
3332
3333 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
3334
3335 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3336 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
3337
3338 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3339 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
3340 }
3341
3342 return tfc_changed;
3343 }
3344
rtw89_vif_enter_lps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)3345 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev,
3346 struct rtw89_vif_link *rtwvif_link)
3347 {
3348 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION &&
3349 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT)
3350 return;
3351
3352 rtw89_enter_lps(rtwdev, rtwvif_link, true);
3353 }
3354
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)3355 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
3356 {
3357 struct rtw89_vif_link *rtwvif_link;
3358 struct rtw89_vif *rtwvif;
3359 unsigned int link_id;
3360
3361 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
3362 if (rtwvif->tdls_peer)
3363 continue;
3364 if (rtwvif->offchan)
3365 continue;
3366
3367 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE ||
3368 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE)
3369 continue;
3370
3371 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
3372 rtw89_vif_enter_lps(rtwdev, rtwvif_link);
3373 }
3374 }
3375
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)3376 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
3377 {
3378 enum rtw89_entity_mode mode;
3379
3380 mode = rtw89_get_entity_mode(rtwdev);
3381 if (mode == RTW89_ENTITY_MODE_MCC)
3382 return;
3383
3384 rtw89_chip_rfk_track(rtwdev);
3385 }
3386
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)3387 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
3388 struct rtw89_vif_link *rtwvif_link,
3389 struct ieee80211_bss_conf *bss_conf)
3390 {
3391 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
3392
3393 if (mode == RTW89_ENTITY_MODE_MCC)
3394 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
3395 else
3396 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
3397 }
3398
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)3399 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3400 struct rtw89_traffic_stats *stats)
3401 {
3402 stats->tx_unicast = 0;
3403 stats->rx_unicast = 0;
3404 stats->tx_cnt = 0;
3405 stats->rx_cnt = 0;
3406 ewma_tp_init(&stats->tx_ewma_tp);
3407 ewma_tp_init(&stats->rx_ewma_tp);
3408 }
3409
rtw89_track_work(struct work_struct * work)3410 static void rtw89_track_work(struct work_struct *work)
3411 {
3412 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
3413 track_work.work);
3414 bool tfc_changed;
3415
3416 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
3417 return;
3418
3419 mutex_lock(&rtwdev->mutex);
3420
3421 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
3422 goto out;
3423
3424 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
3425 RTW89_TRACK_WORK_PERIOD);
3426
3427 tfc_changed = rtw89_traffic_stats_track(rtwdev);
3428 if (rtwdev->scanning)
3429 goto out;
3430
3431 rtw89_leave_lps(rtwdev);
3432
3433 if (tfc_changed) {
3434 rtw89_hci_recalc_int_mit(rtwdev);
3435 rtw89_btc_ntfy_wl_sta(rtwdev);
3436 }
3437 rtw89_mac_bf_monitor_track(rtwdev);
3438 rtw89_phy_stat_track(rtwdev);
3439 rtw89_phy_env_monitor_track(rtwdev);
3440 rtw89_phy_dig(rtwdev);
3441 rtw89_core_rfk_track(rtwdev);
3442 rtw89_phy_ra_update(rtwdev);
3443 rtw89_phy_cfo_track(rtwdev);
3444 rtw89_phy_tx_path_div_track(rtwdev);
3445 rtw89_phy_antdiv_track(rtwdev);
3446 rtw89_phy_ul_tb_ctrl_track(rtwdev);
3447 rtw89_phy_edcca_track(rtwdev);
3448 rtw89_tas_track(rtwdev);
3449 rtw89_chanctx_track(rtwdev);
3450 rtw89_core_rfkill_poll(rtwdev, false);
3451
3452 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
3453 rtw89_enter_lps_track(rtwdev);
3454
3455 out:
3456 mutex_unlock(&rtwdev->mutex);
3457 }
3458
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)3459 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
3460 {
3461 unsigned long bit;
3462
3463 bit = find_first_zero_bit(addr, size);
3464 if (bit < size)
3465 set_bit(bit, addr);
3466
3467 return bit;
3468 }
3469
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)3470 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
3471 {
3472 clear_bit(bit, addr);
3473 }
3474
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)3475 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
3476 {
3477 bitmap_zero(addr, nbits);
3478 }
3479
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3480 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
3481 struct rtw89_sta_link *rtwsta_link, u8 tid,
3482 u8 *cam_idx)
3483 {
3484 const struct rtw89_chip_info *chip = rtwdev->chip;
3485 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3486 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3487 u8 idx;
3488 int i;
3489
3490 lockdep_assert_held(&rtwdev->mutex);
3491
3492 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
3493 if (idx == chip->bacam_num) {
3494 /* allocate a static BA CAM to tid=0/5, so replace the existing
3495 * one if BA CAM is full. Hardware will process the original tid
3496 * automatically.
3497 */
3498 if (tid != 0 && tid != 5)
3499 return -ENOSPC;
3500
3501 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
3502 tmp = &cam_info->ba_cam_entry[i];
3503 if (tmp->tid == 0 || tmp->tid == 5)
3504 continue;
3505
3506 idx = i;
3507 entry = tmp;
3508 list_del(&entry->list);
3509 break;
3510 }
3511
3512 if (!entry)
3513 return -ENOSPC;
3514 } else {
3515 entry = &cam_info->ba_cam_entry[idx];
3516 }
3517
3518 entry->tid = tid;
3519 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
3520
3521 *cam_idx = idx;
3522
3523 return 0;
3524 }
3525
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)3526 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
3527 struct rtw89_sta_link *rtwsta_link, u8 tid,
3528 u8 *cam_idx)
3529 {
3530 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3531 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
3532 u8 idx;
3533
3534 lockdep_assert_held(&rtwdev->mutex);
3535
3536 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
3537 if (entry->tid != tid)
3538 continue;
3539
3540 idx = entry - cam_info->ba_cam_entry;
3541 list_del(&entry->list);
3542
3543 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
3544 *cam_idx = idx;
3545 return 0;
3546 }
3547
3548 return -ENOENT;
3549 }
3550
3551 #define RTW89_TYPE_MAPPING(_type) \
3552 case NL80211_IFTYPE_ ## _type: \
3553 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
3554 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)3555 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
3556 {
3557 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3558 const struct ieee80211_bss_conf *bss_conf;
3559
3560 switch (vif->type) {
3561 case NL80211_IFTYPE_STATION:
3562 if (vif->p2p)
3563 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
3564 else
3565 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
3566 break;
3567 case NL80211_IFTYPE_AP:
3568 if (vif->p2p)
3569 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
3570 else
3571 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
3572 break;
3573 RTW89_TYPE_MAPPING(ADHOC);
3574 RTW89_TYPE_MAPPING(MONITOR);
3575 RTW89_TYPE_MAPPING(MESH_POINT);
3576 default:
3577 WARN_ON(1);
3578 break;
3579 }
3580
3581 switch (vif->type) {
3582 case NL80211_IFTYPE_AP:
3583 case NL80211_IFTYPE_MESH_POINT:
3584 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
3585 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
3586 break;
3587 case NL80211_IFTYPE_ADHOC:
3588 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
3589 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3590 break;
3591 case NL80211_IFTYPE_STATION:
3592 if (assoc) {
3593 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
3594
3595 rcu_read_lock();
3596 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
3597 rtwvif_link->trigger = bss_conf->he_support;
3598 rcu_read_unlock();
3599 } else {
3600 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
3601 rtwvif_link->trigger = false;
3602 }
3603 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
3604 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
3605 break;
3606 case NL80211_IFTYPE_MONITOR:
3607 break;
3608 default:
3609 WARN_ON(1);
3610 break;
3611 }
3612 }
3613
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3614 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
3615 struct rtw89_vif_link *rtwvif_link,
3616 struct rtw89_sta_link *rtwsta_link)
3617 {
3618 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3619 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3620 struct rtw89_hal *hal = &rtwdev->hal;
3621 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3622 int i;
3623 int ret;
3624
3625 rtwsta_link->prev_rssi = 0;
3626 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
3627 ewma_rssi_init(&rtwsta_link->avg_rssi);
3628 ewma_snr_init(&rtwsta_link->avg_snr);
3629 ewma_evm_init(&rtwsta_link->evm_1ss);
3630 for (i = 0; i < ant_num; i++) {
3631 ewma_rssi_init(&rtwsta_link->rssi[i]);
3632 ewma_evm_init(&rtwsta_link->evm_min[i]);
3633 ewma_evm_init(&rtwsta_link->evm_max[i]);
3634 }
3635
3636 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3637 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
3638 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
3639 if (ret)
3640 return ret;
3641
3642 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3643 BTC_ROLE_MSTS_STA_CONN_START);
3644 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
3645 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3646 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
3647 if (ret) {
3648 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
3649 return ret;
3650 }
3651
3652 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3653 RTW89_ROLE_CREATE);
3654 if (ret) {
3655 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3656 return ret;
3657 }
3658
3659 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3660 if (ret)
3661 return ret;
3662
3663 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3664 if (ret)
3665 return ret;
3666 }
3667
3668 return 0;
3669 }
3670
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3671 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
3672 struct rtw89_vif_link *rtwvif_link,
3673 struct rtw89_sta_link *rtwsta_link)
3674 {
3675 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3676
3677 if (vif->type == NL80211_IFTYPE_STATION)
3678 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
3679
3680 return 0;
3681 }
3682
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3683 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
3684 struct rtw89_vif_link *rtwvif_link,
3685 struct rtw89_sta_link *rtwsta_link)
3686 {
3687 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3688 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3689 int ret;
3690
3691 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
3692 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
3693
3694 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
3695 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
3696 if (sta->tdls)
3697 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
3698
3699 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3700 rtw89_vif_type_mapping(rtwvif_link, false);
3701 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
3702 }
3703
3704 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3705 if (ret) {
3706 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3707 return ret;
3708 }
3709
3710 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
3711 if (ret) {
3712 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3713 return ret;
3714 }
3715
3716 /* update cam aid mac_id net_type */
3717 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3718 if (ret) {
3719 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3720 return ret;
3721 }
3722
3723 return ret;
3724 }
3725
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3726 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
3727 struct rtw89_vif_link *rtwvif_link,
3728 struct rtw89_sta_link *rtwsta_link)
3729 {
3730 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3731 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3732 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
3733 rtwsta_link);
3734 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
3735 rtwvif_link->chanctx_idx);
3736 int ret;
3737
3738 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3739 if (sta->tdls) {
3740 struct ieee80211_link_sta *link_sta;
3741
3742 rcu_read_lock();
3743
3744 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3745 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
3746 link_sta->addr);
3747 if (ret) {
3748 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
3749 rcu_read_unlock();
3750 return ret;
3751 }
3752
3753 rcu_read_unlock();
3754 }
3755
3756 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
3757 if (ret) {
3758 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
3759 return ret;
3760 }
3761 }
3762
3763 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
3764 if (ret) {
3765 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3766 return ret;
3767 }
3768
3769 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
3770 if (ret) {
3771 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3772 return ret;
3773 }
3774
3775 /* update cam aid mac_id net_type */
3776 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL);
3777 if (ret) {
3778 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3779 return ret;
3780 }
3781
3782 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
3783 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
3784 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
3785
3786 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3787 struct ieee80211_bss_conf *bss_conf;
3788
3789 rcu_read_lock();
3790
3791 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
3792 if (bss_conf->he_support &&
3793 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE))
3794 rtwsta_link->er_cap = true;
3795
3796 rcu_read_unlock();
3797
3798 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3799 BTC_ROLE_MSTS_STA_CONN_END);
3800 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
3801 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
3802
3803 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
3804 if (ret) {
3805 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
3806 return ret;
3807 }
3808
3809 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
3810 }
3811
3812 return ret;
3813 }
3814
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)3815 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
3816 struct rtw89_vif_link *rtwvif_link,
3817 struct rtw89_sta_link *rtwsta_link)
3818 {
3819 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3820 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
3821 int ret;
3822
3823 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3824 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
3825 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
3826 BTC_ROLE_MSTS_STA_DIS_CONN);
3827 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3828 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
3829 RTW89_ROLE_REMOVE);
3830 if (ret) {
3831 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3832 return ret;
3833 }
3834 }
3835
3836 return 0;
3837 }
3838
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)3839 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3840 struct ieee80211_sta *sta,
3841 struct cfg80211_tid_cfg *tid_conf)
3842 {
3843 struct ieee80211_txq *txq;
3844 struct rtw89_txq *rtwtxq;
3845 u32 mask = tid_conf->mask;
3846 u8 tids = tid_conf->tids;
3847 int tids_nbit = BITS_PER_BYTE;
3848 int i;
3849
3850 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
3851 if (!tids)
3852 break;
3853
3854 if (!(tids & BIT(0)))
3855 continue;
3856
3857 txq = sta->txq[i];
3858 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3859
3860 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
3861 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
3862 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3863 } else {
3864 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
3865 ieee80211_stop_tx_ba_session(sta, txq->tid);
3866 spin_lock_bh(&rtwdev->ba_lock);
3867 list_del_init(&rtwtxq->list);
3868 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3869 spin_unlock_bh(&rtwdev->ba_lock);
3870 }
3871 }
3872
3873 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
3874 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
3875 sta->max_amsdu_subframes = 0;
3876 else
3877 sta->max_amsdu_subframes = 1;
3878 }
3879 }
3880 }
3881
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)3882 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3883 struct ieee80211_sta *sta,
3884 struct cfg80211_tid_config *tid_config)
3885 {
3886 int i;
3887
3888 for (i = 0; i < tid_config->n_tid_conf; i++)
3889 _rtw89_core_set_tid_config(rtwdev, sta,
3890 &tid_config->tid_conf[i]);
3891 }
3892
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)3893 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
3894 struct ieee80211_sta_ht_cap *ht_cap)
3895 {
3896 static const __le16 highest[RF_PATH_MAX] = {
3897 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
3898 };
3899 struct rtw89_hal *hal = &rtwdev->hal;
3900 u8 nss = hal->rx_nss;
3901 int i;
3902
3903 ht_cap->ht_supported = true;
3904 ht_cap->cap = 0;
3905 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
3906 IEEE80211_HT_CAP_MAX_AMSDU |
3907 IEEE80211_HT_CAP_TX_STBC |
3908 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
3909 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
3910 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3911 IEEE80211_HT_CAP_DSSSCCK40 |
3912 IEEE80211_HT_CAP_SGI_40;
3913 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
3914 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
3915 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3916 for (i = 0; i < nss; i++)
3917 ht_cap->mcs.rx_mask[i] = 0xFF;
3918 ht_cap->mcs.rx_mask[4] = 0x01;
3919 ht_cap->mcs.rx_highest = highest[nss - 1];
3920 }
3921
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)3922 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
3923 struct ieee80211_sta_vht_cap *vht_cap)
3924 {
3925 static const __le16 highest_bw80[RF_PATH_MAX] = {
3926 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
3927 };
3928 static const __le16 highest_bw160[RF_PATH_MAX] = {
3929 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
3930 };
3931 const struct rtw89_chip_info *chip = rtwdev->chip;
3932 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
3933 highest_bw160 : highest_bw80;
3934 struct rtw89_hal *hal = &rtwdev->hal;
3935 u16 tx_mcs_map = 0, rx_mcs_map = 0;
3936 u8 sts_cap = 3;
3937 int i;
3938
3939 for (i = 0; i < 8; i++) {
3940 if (i < hal->tx_nss)
3941 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3942 else
3943 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3944 if (i < hal->rx_nss)
3945 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3946 else
3947 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3948 }
3949
3950 vht_cap->vht_supported = true;
3951 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
3952 IEEE80211_VHT_CAP_SHORT_GI_80 |
3953 IEEE80211_VHT_CAP_RXSTBC_1 |
3954 IEEE80211_VHT_CAP_HTC_VHT |
3955 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
3956 0;
3957 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
3958 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
3959 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
3960 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
3961 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
3962 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
3963 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
3964 IEEE80211_VHT_CAP_SHORT_GI_160;
3965 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
3966 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
3967 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
3968 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
3969
3970 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
3971 vht_cap->vht_mcs.tx_highest |=
3972 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
3973 }
3974
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)3975 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
3976 enum nl80211_band band,
3977 enum nl80211_iftype iftype,
3978 struct ieee80211_sband_iftype_data *iftype_data)
3979 {
3980 const struct rtw89_chip_info *chip = rtwdev->chip;
3981 struct rtw89_hal *hal = &rtwdev->hal;
3982 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
3983 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
3984 struct ieee80211_sta_he_cap *he_cap;
3985 int nss = hal->rx_nss;
3986 u8 *mac_cap_info;
3987 u8 *phy_cap_info;
3988 u16 mcs_map = 0;
3989 int i;
3990
3991 for (i = 0; i < 8; i++) {
3992 if (i < nss)
3993 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
3994 else
3995 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
3996 }
3997
3998 he_cap = &iftype_data->he_cap;
3999 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
4000 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
4001
4002 he_cap->has_he = true;
4003 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
4004 if (iftype == NL80211_IFTYPE_STATION)
4005 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
4006 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
4007 IEEE80211_HE_MAC_CAP2_BSR;
4008 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
4009 if (iftype == NL80211_IFTYPE_AP)
4010 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
4011 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
4012 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
4013 if (iftype == NL80211_IFTYPE_STATION)
4014 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
4015 if (band == NL80211_BAND_2GHZ) {
4016 phy_cap_info[0] =
4017 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
4018 } else {
4019 phy_cap_info[0] =
4020 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
4021 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4022 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
4023 }
4024 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
4025 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
4026 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
4027 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
4028 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
4029 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
4030 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
4031 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
4032 if (iftype == NL80211_IFTYPE_STATION)
4033 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
4034 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
4035 if (iftype == NL80211_IFTYPE_AP)
4036 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
4037 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
4038 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
4039 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4040 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
4041 phy_cap_info[5] = no_ng16 ? 0 :
4042 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
4043 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
4044 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
4045 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
4046 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
4047 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
4048 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
4049 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
4050 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
4051 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
4052 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
4053 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
4054 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
4055 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
4056 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
4057 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
4058 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
4059 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
4060 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
4061 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
4062 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
4063 if (iftype == NL80211_IFTYPE_STATION)
4064 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
4065 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
4066 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
4067 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
4068 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
4069 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
4070 }
4071
4072 if (band == NL80211_BAND_6GHZ) {
4073 __le16 capa;
4074
4075 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
4076 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
4077 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
4078 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
4079 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
4080 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
4081 iftype_data->he_6ghz_capa.capa = capa;
4082 }
4083 }
4084
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)4085 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
4086 enum nl80211_band band,
4087 enum nl80211_iftype iftype,
4088 struct ieee80211_sband_iftype_data *iftype_data)
4089 {
4090 const struct rtw89_chip_info *chip = rtwdev->chip;
4091 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
4092 struct ieee80211_eht_mcs_nss_supp *eht_nss;
4093 struct ieee80211_sta_eht_cap *eht_cap;
4094 struct rtw89_hal *hal = &rtwdev->hal;
4095 bool support_320mhz = false;
4096 int sts = 8;
4097 u8 val;
4098
4099 if (chip->chip_gen == RTW89_CHIP_AX)
4100 return;
4101
4102 if (band == NL80211_BAND_6GHZ &&
4103 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
4104 support_320mhz = true;
4105
4106 eht_cap = &iftype_data->eht_cap;
4107 eht_cap_elem = &eht_cap->eht_cap_elem;
4108 eht_nss = &eht_cap->eht_mcs_nss_supp;
4109
4110 eht_cap->has_eht = true;
4111
4112 eht_cap_elem->mac_cap_info[0] =
4113 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
4114 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
4115 eht_cap_elem->mac_cap_info[1] = 0;
4116
4117 eht_cap_elem->phy_cap_info[0] =
4118 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
4119 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
4120 if (support_320mhz)
4121 eht_cap_elem->phy_cap_info[0] |=
4122 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
4123
4124 eht_cap_elem->phy_cap_info[0] |=
4125 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
4126 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
4127 eht_cap_elem->phy_cap_info[1] =
4128 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
4129 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
4130 u8_encode_bits(sts - 1,
4131 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
4132 if (support_320mhz)
4133 eht_cap_elem->phy_cap_info[1] |=
4134 u8_encode_bits(sts - 1,
4135 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
4136
4137 eht_cap_elem->phy_cap_info[2] = 0;
4138
4139 eht_cap_elem->phy_cap_info[3] =
4140 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
4141 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
4142 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
4143 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
4144
4145 eht_cap_elem->phy_cap_info[4] =
4146 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
4147 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
4148
4149 eht_cap_elem->phy_cap_info[5] =
4150 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
4151 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
4152
4153 eht_cap_elem->phy_cap_info[6] = 0;
4154 eht_cap_elem->phy_cap_info[7] = 0;
4155 eht_cap_elem->phy_cap_info[8] = 0;
4156
4157 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
4158 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
4159 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
4160 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
4161 eht_nss->bw._80.rx_tx_mcs13_max_nss = val;
4162 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
4163 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
4164 eht_nss->bw._160.rx_tx_mcs13_max_nss = val;
4165 if (support_320mhz) {
4166 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
4167 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
4168 eht_nss->bw._320.rx_tx_mcs13_max_nss = val;
4169 }
4170 }
4171
4172 #define RTW89_SBAND_IFTYPES_NR 2
4173
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)4174 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
4175 enum nl80211_band band,
4176 struct ieee80211_supported_band *sband)
4177 {
4178 struct ieee80211_sband_iftype_data *iftype_data;
4179 enum nl80211_iftype iftype;
4180 int idx = 0;
4181
4182 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
4183 if (!iftype_data)
4184 return;
4185
4186 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
4187 switch (iftype) {
4188 case NL80211_IFTYPE_STATION:
4189 case NL80211_IFTYPE_AP:
4190 break;
4191 default:
4192 continue;
4193 }
4194
4195 if (idx >= RTW89_SBAND_IFTYPES_NR) {
4196 rtw89_warn(rtwdev, "run out of iftype_data\n");
4197 break;
4198 }
4199
4200 iftype_data[idx].types_mask = BIT(iftype);
4201
4202 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
4203 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
4204
4205 idx++;
4206 }
4207
4208 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
4209 }
4210
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)4211 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
4212 {
4213 struct ieee80211_hw *hw = rtwdev->hw;
4214 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
4215 struct ieee80211_supported_band *sband_6ghz = NULL;
4216 u32 size = sizeof(struct ieee80211_supported_band);
4217 u8 support_bands = rtwdev->chip->support_bands;
4218
4219 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
4220 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
4221 if (!sband_2ghz)
4222 goto err;
4223 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
4224 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
4225 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
4226 }
4227
4228 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
4229 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
4230 if (!sband_5ghz)
4231 goto err;
4232 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
4233 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
4234 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
4235 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
4236 }
4237
4238 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
4239 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
4240 if (!sband_6ghz)
4241 goto err;
4242 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
4243 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
4244 }
4245
4246 return 0;
4247
4248 err:
4249 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4250 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4251 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4252 if (sband_2ghz)
4253 kfree((__force void *)sband_2ghz->iftype_data);
4254 if (sband_5ghz)
4255 kfree((__force void *)sband_5ghz->iftype_data);
4256 if (sband_6ghz)
4257 kfree((__force void *)sband_6ghz->iftype_data);
4258 kfree(sband_2ghz);
4259 kfree(sband_5ghz);
4260 kfree(sband_6ghz);
4261 return -ENOMEM;
4262 }
4263
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)4264 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
4265 {
4266 struct ieee80211_hw *hw = rtwdev->hw;
4267
4268 if (hw->wiphy->bands[NL80211_BAND_2GHZ])
4269 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
4270 if (hw->wiphy->bands[NL80211_BAND_5GHZ])
4271 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
4272 if (hw->wiphy->bands[NL80211_BAND_6GHZ])
4273 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
4274 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
4275 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
4276 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
4277 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
4278 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
4279 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
4280 }
4281
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)4282 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
4283 {
4284 int i;
4285
4286 for (i = 0; i < RTW89_PHY_MAX; i++)
4287 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
4288 for (i = 0; i < RTW89_PHY_MAX; i++)
4289 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
4290 }
4291
rtw89_core_update_beacon_work(struct work_struct * work)4292 void rtw89_core_update_beacon_work(struct work_struct *work)
4293 {
4294 struct rtw89_dev *rtwdev;
4295 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
4296 update_beacon_work);
4297
4298 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
4299 return;
4300
4301 rtwdev = rtwvif_link->rtwvif->rtwdev;
4302
4303 mutex_lock(&rtwdev->mutex);
4304 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
4305 mutex_unlock(&rtwdev->mutex);
4306 }
4307
rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)4308 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
4309 {
4310 struct completion *cmpl = &wait->completion;
4311 unsigned long time_left;
4312 unsigned int cur;
4313
4314 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
4315 if (cur != RTW89_WAIT_COND_IDLE)
4316 return -EBUSY;
4317
4318 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
4319 if (time_left == 0) {
4320 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4321 return -ETIMEDOUT;
4322 }
4323
4324 if (wait->data.err)
4325 return -EFAULT;
4326
4327 return 0;
4328 }
4329
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)4330 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
4331 const struct rtw89_completion_data *data)
4332 {
4333 unsigned int cur;
4334
4335 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
4336 if (cur != cond)
4337 return;
4338
4339 wait->data = *data;
4340 complete(&wait->completion);
4341 }
4342
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)4343 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
4344 {
4345 u16 bt_req_len;
4346
4347 switch (event) {
4348 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
4349 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
4350 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4351 "coex updates BT req len to %d TU\n", bt_req_len);
4352 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
4353 break;
4354 default:
4355 if (event < NUM_OF_RTW89_BTC_HMSG)
4356 rtw89_debug(rtwdev, RTW89_DBG_BTC,
4357 "unhandled BTC HMSG event: %d\n", event);
4358 else
4359 rtw89_warn(rtwdev,
4360 "unrecognized BTC HMSG event: %d\n", event);
4361 break;
4362 }
4363 }
4364
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)4365 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
4366 {
4367 const struct dmi_system_id *match;
4368 enum rtw89_quirks quirk;
4369
4370 if (!quirks)
4371 return;
4372
4373 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
4374 quirk = (uintptr_t)match->driver_data;
4375 if (quirk >= NUM_OF_RTW89_QUIRKS)
4376 continue;
4377
4378 set_bit(quirk, rtwdev->quirks);
4379 }
4380 }
4381 EXPORT_SYMBOL(rtw89_check_quirks);
4382
rtw89_core_start(struct rtw89_dev * rtwdev)4383 int rtw89_core_start(struct rtw89_dev *rtwdev)
4384 {
4385 int ret;
4386
4387 ret = rtw89_mac_init(rtwdev);
4388 if (ret) {
4389 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
4390 return ret;
4391 }
4392
4393 rtw89_btc_ntfy_poweron(rtwdev);
4394
4395 /* efuse process */
4396
4397 /* pre-config BB/RF, BB reset/RFC reset */
4398 ret = rtw89_chip_reset_bb_rf(rtwdev);
4399 if (ret)
4400 return ret;
4401
4402 rtw89_phy_init_bb_reg(rtwdev);
4403 rtw89_chip_bb_postinit(rtwdev);
4404 rtw89_phy_init_rf_reg(rtwdev, false);
4405
4406 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
4407
4408 rtw89_phy_dm_init(rtwdev);
4409
4410 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
4411 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0);
4412
4413 rtw89_tas_reset(rtwdev);
4414
4415 ret = rtw89_hci_start(rtwdev);
4416 if (ret) {
4417 rtw89_err(rtwdev, "failed to start hci\n");
4418 return ret;
4419 }
4420
4421 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
4422 RTW89_TRACK_WORK_PERIOD);
4423
4424 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4425
4426 rtw89_chip_rfk_init_late(rtwdev);
4427 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
4428 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
4429 rtw89_fw_h2c_init_ba_cam(rtwdev);
4430
4431 return 0;
4432 }
4433
rtw89_core_stop(struct rtw89_dev * rtwdev)4434 void rtw89_core_stop(struct rtw89_dev *rtwdev)
4435 {
4436 struct rtw89_btc *btc = &rtwdev->btc;
4437 struct wiphy *wiphy = rtwdev->hw->wiphy;
4438
4439 /* Prvent to stop twice; enter_ips and ops_stop */
4440 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4441 return;
4442
4443 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
4444
4445 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
4446
4447 mutex_unlock(&rtwdev->mutex);
4448
4449 cancel_work_sync(&rtwdev->c2h_work);
4450 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
4451 cancel_work_sync(&btc->eapol_notify_work);
4452 cancel_work_sync(&btc->arp_notify_work);
4453 cancel_work_sync(&btc->dhcp_notify_work);
4454 cancel_work_sync(&btc->icmp_notify_work);
4455 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
4456 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work);
4457 cancel_delayed_work_sync(&rtwdev->track_work);
4458 cancel_delayed_work_sync(&rtwdev->chanctx_work);
4459 cancel_delayed_work_sync(&rtwdev->coex_act1_work);
4460 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
4461 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
4462 cancel_delayed_work_sync(&rtwdev->cfo_track_work);
4463 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
4464 cancel_delayed_work_sync(&rtwdev->antdiv_work);
4465
4466 mutex_lock(&rtwdev->mutex);
4467
4468 rtw89_btc_ntfy_poweroff(rtwdev);
4469 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4470 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
4471 rtw89_hci_stop(rtwdev);
4472 rtw89_hci_deinit(rtwdev);
4473 rtw89_mac_pwr_off(rtwdev);
4474 rtw89_hci_reset(rtwdev);
4475 }
4476
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)4477 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
4478 {
4479 const struct rtw89_chip_info *chip = rtwdev->chip;
4480 u8 mac_id_num;
4481 u8 mac_id;
4482
4483 if (rtwdev->support_mlo)
4484 mac_id_num = chip->support_macid_num / chip->support_link_num;
4485 else
4486 mac_id_num = chip->support_macid_num;
4487
4488 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
4489 if (mac_id == mac_id_num)
4490 return RTW89_MAX_MAC_ID_NUM;
4491
4492 set_bit(mac_id, rtwdev->mac_id_map);
4493 return mac_id;
4494 }
4495
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)4496 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
4497 {
4498 clear_bit(mac_id, rtwdev->mac_id_map);
4499 }
4500
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)4501 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4502 u8 mac_id, u8 port)
4503 {
4504 const struct rtw89_chip_info *chip = rtwdev->chip;
4505 u8 support_link_num = chip->support_link_num;
4506 u8 support_mld_num = 0;
4507 unsigned int link_id;
4508 u8 index;
4509
4510 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4511 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4512 rtwvif->links[link_id] = NULL;
4513
4514 rtwvif->rtwdev = rtwdev;
4515
4516 if (rtwdev->support_mlo) {
4517 rtwvif->links_inst_valid_num = support_link_num;
4518 support_mld_num = chip->support_macid_num / support_link_num;
4519 } else {
4520 rtwvif->links_inst_valid_num = 1;
4521 }
4522
4523 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
4524 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
4525
4526 inst->rtwvif = rtwvif;
4527 inst->mac_id = mac_id + index * support_mld_num;
4528 inst->mac_idx = RTW89_MAC_0 + index;
4529 inst->phy_idx = RTW89_PHY_0 + index;
4530
4531 /* multi-link use the same port id on different HW bands */
4532 inst->port = port;
4533 }
4534 }
4535
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)4536 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4537 struct rtw89_sta *rtwsta, u8 mac_id)
4538 {
4539 const struct rtw89_chip_info *chip = rtwdev->chip;
4540 u8 support_link_num = chip->support_link_num;
4541 u8 support_mld_num = 0;
4542 unsigned int link_id;
4543 u8 index;
4544
4545 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
4546 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
4547 rtwsta->links[link_id] = NULL;
4548
4549 rtwsta->rtwdev = rtwdev;
4550 rtwsta->rtwvif = rtwvif;
4551
4552 if (rtwdev->support_mlo) {
4553 rtwsta->links_inst_valid_num = support_link_num;
4554 support_mld_num = chip->support_macid_num / support_link_num;
4555 } else {
4556 rtwsta->links_inst_valid_num = 1;
4557 }
4558
4559 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
4560 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
4561
4562 inst->rtwvif_link = &rtwvif->links_inst[index];
4563
4564 inst->rtwsta = rtwsta;
4565 inst->mac_id = mac_id + index * support_mld_num;
4566 }
4567 }
4568
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)4569 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
4570 unsigned int link_id)
4571 {
4572 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4573 u8 index;
4574 int ret;
4575
4576 if (rtwvif_link)
4577 return rtwvif_link;
4578
4579 index = find_first_zero_bit(rtwvif->links_inst_map,
4580 rtwvif->links_inst_valid_num);
4581 if (index == rtwvif->links_inst_valid_num) {
4582 ret = -EBUSY;
4583 goto err;
4584 }
4585
4586 rtwvif_link = &rtwvif->links_inst[index];
4587 rtwvif_link->link_id = link_id;
4588
4589 set_bit(index, rtwvif->links_inst_map);
4590 rtwvif->links[link_id] = rtwvif_link;
4591 return rtwvif_link;
4592
4593 err:
4594 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
4595 link_id, ret);
4596 return NULL;
4597 }
4598
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)4599 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
4600 {
4601 struct rtw89_vif_link **container = &rtwvif->links[link_id];
4602 struct rtw89_vif_link *link = *container;
4603 u8 index;
4604
4605 if (!link)
4606 return;
4607
4608 index = rtw89_vif_link_inst_get_index(link);
4609 clear_bit(index, rtwvif->links_inst_map);
4610 *container = NULL;
4611 }
4612
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)4613 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
4614 unsigned int link_id)
4615 {
4616 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4617 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
4618 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
4619 u8 index;
4620 int ret;
4621
4622 if (rtwsta_link)
4623 return rtwsta_link;
4624
4625 if (!rtwvif_link) {
4626 ret = -ENOLINK;
4627 goto err;
4628 }
4629
4630 index = rtw89_vif_link_inst_get_index(rtwvif_link);
4631 if (test_bit(index, rtwsta->links_inst_map)) {
4632 ret = -EBUSY;
4633 goto err;
4634 }
4635
4636 rtwsta_link = &rtwsta->links_inst[index];
4637 rtwsta_link->link_id = link_id;
4638
4639 set_bit(index, rtwsta->links_inst_map);
4640 rtwsta->links[link_id] = rtwsta_link;
4641 return rtwsta_link;
4642
4643 err:
4644 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
4645 link_id, ret);
4646 return NULL;
4647 }
4648
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)4649 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
4650 {
4651 struct rtw89_sta_link **container = &rtwsta->links[link_id];
4652 struct rtw89_sta_link *link = *container;
4653 u8 index;
4654
4655 if (!link)
4656 return;
4657
4658 index = rtw89_sta_link_inst_get_index(link);
4659 clear_bit(index, rtwsta->links_inst_map);
4660 *container = NULL;
4661 }
4662
rtw89_core_init(struct rtw89_dev * rtwdev)4663 int rtw89_core_init(struct rtw89_dev *rtwdev)
4664 {
4665 struct rtw89_btc *btc = &rtwdev->btc;
4666 u8 band;
4667
4668 INIT_LIST_HEAD(&rtwdev->ba_list);
4669 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
4670 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
4671 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
4672 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
4673 if (!(rtwdev->chip->support_bands & BIT(band)))
4674 continue;
4675 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
4676 }
4677 INIT_LIST_HEAD(&rtwdev->tx_waits);
4678 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
4679 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
4680 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
4681 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
4682 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work);
4683 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
4684 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
4685 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
4686 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
4687 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work);
4688 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
4689 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
4690 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
4691 if (!rtwdev->txq_wq)
4692 return -ENOMEM;
4693 spin_lock_init(&rtwdev->ba_lock);
4694 spin_lock_init(&rtwdev->rpwm_lock);
4695 mutex_init(&rtwdev->mutex);
4696 mutex_init(&rtwdev->rf_mutex);
4697 rtwdev->total_sta_assoc = 0;
4698
4699 rtw89_init_wait(&rtwdev->mcc.wait);
4700 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
4701 rtw89_init_wait(&rtwdev->wow.wait);
4702 rtw89_init_wait(&rtwdev->mac.ps_wait);
4703
4704 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
4705 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
4706 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
4707 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
4708
4709 skb_queue_head_init(&rtwdev->c2h_queue);
4710 rtw89_core_ppdu_sts_init(rtwdev);
4711 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
4712
4713 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
4714 rtwdev->dbcc_en = false;
4715 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
4716 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
4717
4718 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4719 rtwdev->dbcc_en = true;
4720 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
4721 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF;
4722 }
4723
4724 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
4725 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
4726 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
4727 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
4728
4729 init_completion(&rtwdev->fw.req.completion);
4730 init_completion(&rtwdev->rfk_wait.completion);
4731
4732 schedule_work(&rtwdev->load_firmware_work);
4733
4734 rtw89_ser_init(rtwdev);
4735 rtw89_entity_init(rtwdev);
4736 rtw89_tas_init(rtwdev);
4737
4738 return 0;
4739 }
4740 EXPORT_SYMBOL(rtw89_core_init);
4741
rtw89_core_deinit(struct rtw89_dev * rtwdev)4742 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
4743 {
4744 rtw89_ser_deinit(rtwdev);
4745 rtw89_unload_firmware(rtwdev);
4746 rtw89_fw_free_all_early_h2c(rtwdev);
4747
4748 destroy_workqueue(rtwdev->txq_wq);
4749 mutex_destroy(&rtwdev->rf_mutex);
4750 mutex_destroy(&rtwdev->mutex);
4751 }
4752 EXPORT_SYMBOL(rtw89_core_deinit);
4753
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)4754 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4755 const u8 *mac_addr, bool hw_scan)
4756 {
4757 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4758 rtwvif_link->chanctx_idx);
4759
4760 rtwdev->scanning = true;
4761 rtw89_leave_lps(rtwdev);
4762 if (hw_scan)
4763 rtw89_leave_ips_by_hwflags(rtwdev);
4764
4765 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
4766 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type);
4767 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
4768 rtw89_hci_recalc_int_mit(rtwdev);
4769 rtw89_phy_config_edcca(rtwdev, true);
4770
4771 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr);
4772 }
4773
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)4774 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
4775 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
4776 {
4777 struct ieee80211_bss_conf *bss_conf;
4778
4779 if (!rtwvif_link)
4780 return;
4781
4782 rcu_read_lock();
4783
4784 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
4785 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
4786
4787 rcu_read_unlock();
4788
4789 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4790
4791 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
4792 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0);
4793 rtw89_phy_config_edcca(rtwdev, false);
4794
4795 rtwdev->scanning = false;
4796 rtwdev->dig.bypass_dig = true;
4797 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
4798 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
4799 }
4800
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)4801 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
4802 {
4803 const struct rtw89_chip_info *chip = rtwdev->chip;
4804 int ret;
4805 u8 val;
4806 u8 cv;
4807
4808 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
4809 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
4810 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
4811 cv = CHIP_CAV;
4812 else
4813 cv = CHIP_CBV;
4814 }
4815
4816 rtwdev->hal.cv = cv;
4817
4818 if (rtw89_is_rtl885xb(rtwdev)) {
4819 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
4820 if (ret)
4821 return;
4822
4823 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
4824 }
4825 }
4826
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)4827 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
4828 {
4829 rtwdev->hal.support_cckpd =
4830 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
4831 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
4832 rtwdev->hal.support_igi =
4833 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
4834 }
4835
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)4836 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
4837 {
4838 const struct rtw89_chip_info *chip = rtwdev->chip;
4839 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
4840 struct rtw89_efuse *efuse = &rtwdev->efuse;
4841 const struct rtw89_rfe_parms *sel;
4842 u8 rfe_type = efuse->rfe_type;
4843
4844 if (!conf) {
4845 sel = chip->dflt_parms;
4846 goto out;
4847 }
4848
4849 while (conf->rfe_parms) {
4850 if (rfe_type == conf->rfe_type) {
4851 sel = conf->rfe_parms;
4852 goto out;
4853 }
4854 conf++;
4855 }
4856
4857 sel = chip->dflt_parms;
4858
4859 out:
4860 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
4861 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
4862 }
4863
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)4864 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
4865 {
4866 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4867 int ret;
4868
4869 ret = rtw89_mac_partial_init(rtwdev, false);
4870 if (ret)
4871 return ret;
4872
4873 ret = mac->parse_efuse_map(rtwdev);
4874 if (ret)
4875 return ret;
4876
4877 ret = mac->parse_phycap_map(rtwdev);
4878 if (ret)
4879 return ret;
4880
4881 ret = rtw89_mac_setup_phycap(rtwdev);
4882 if (ret)
4883 return ret;
4884
4885 rtw89_core_setup_phycap(rtwdev);
4886
4887 rtw89_hci_mac_pre_deinit(rtwdev);
4888
4889 return 0;
4890 }
4891
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)4892 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
4893 {
4894 rtw89_chip_fem_setup(rtwdev);
4895
4896 return 0;
4897 }
4898
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)4899 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
4900 {
4901 return !!rtwdev->chip->rfkill_init;
4902 }
4903
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)4904 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
4905 {
4906 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
4907
4908 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
4909 regs->pinmux.mask, regs->pinmux.data);
4910 rtw89_write16_mask(rtwdev, regs->mode.addr,
4911 regs->mode.mask, regs->mode.data);
4912 }
4913
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)4914 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
4915 {
4916 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
4917
4918 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
4919 }
4920
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)4921 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
4922 {
4923 if (!rtw89_chip_has_rfkill(rtwdev))
4924 return;
4925
4926 rtw89_core_rfkill_init(rtwdev);
4927 rtw89_core_rfkill_poll(rtwdev, true);
4928 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
4929 }
4930
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)4931 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
4932 {
4933 if (!rtw89_chip_has_rfkill(rtwdev))
4934 return;
4935
4936 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
4937 }
4938
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)4939 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
4940 {
4941 bool prev, blocked;
4942
4943 if (!rtw89_chip_has_rfkill(rtwdev))
4944 return;
4945
4946 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
4947 blocked = rtw89_core_rfkill_get(rtwdev);
4948
4949 if (!force && prev == blocked)
4950 return;
4951
4952 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
4953 blocked ? "disable" : "enable");
4954
4955 if (blocked)
4956 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
4957 else
4958 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
4959
4960 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
4961 }
4962
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)4963 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
4964 {
4965 int ret;
4966
4967 rtw89_read_chip_ver(rtwdev);
4968
4969 ret = rtw89_mac_pwr_on(rtwdev);
4970 if (ret) {
4971 rtw89_err(rtwdev, "failed to power on\n");
4972 return ret;
4973 }
4974
4975 ret = rtw89_wait_firmware_completion(rtwdev);
4976 if (ret) {
4977 rtw89_err(rtwdev, "failed to wait firmware completion\n");
4978 goto out;
4979 }
4980
4981 ret = rtw89_fw_recognize(rtwdev);
4982 if (ret) {
4983 rtw89_err(rtwdev, "failed to recognize firmware\n");
4984 goto out;
4985 }
4986
4987 ret = rtw89_chip_efuse_info_setup(rtwdev);
4988 if (ret)
4989 goto out;
4990
4991 ret = rtw89_fw_recognize_elements(rtwdev);
4992 if (ret) {
4993 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
4994 goto out;
4995 }
4996
4997 ret = rtw89_chip_board_info_setup(rtwdev);
4998 if (ret)
4999 goto out;
5000
5001 rtw89_core_setup_rfe_parms(rtwdev);
5002 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
5003
5004 out:
5005 rtw89_mac_pwr_off(rtwdev);
5006
5007 return ret;
5008 }
5009 EXPORT_SYMBOL(rtw89_chip_info_setup);
5010
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5011 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5012 struct rtw89_vif_link *rtwvif_link)
5013 {
5014 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5015 const struct rtw89_chip_info *chip = rtwdev->chip;
5016 struct ieee80211_bss_conf *bss_conf;
5017
5018 rcu_read_lock();
5019
5020 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
5021 if (!bss_conf->he_support || !vif->cfg.assoc) {
5022 rcu_read_unlock();
5023 return;
5024 }
5025
5026 rcu_read_unlock();
5027
5028 if (chip->ops->set_txpwr_ul_tb_offset)
5029 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
5030 }
5031
rtw89_core_register_hw(struct rtw89_dev * rtwdev)5032 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
5033 {
5034 const struct rtw89_chip_info *chip = rtwdev->chip;
5035 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
5036 struct ieee80211_hw *hw = rtwdev->hw;
5037 struct rtw89_efuse *efuse = &rtwdev->efuse;
5038 struct rtw89_hal *hal = &rtwdev->hal;
5039 int ret;
5040 int tx_headroom = IEEE80211_HT_CTL_LEN;
5041
5042 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
5043 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
5044 hw->txq_data_size = sizeof(struct rtw89_txq);
5045 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
5046
5047 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
5048
5049 hw->extra_tx_headroom = tx_headroom;
5050 hw->queues = IEEE80211_NUM_ACS;
5051 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
5052 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
5053 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
5054
5055 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
5056 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
5057 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
5058
5059 ieee80211_hw_set(hw, SIGNAL_DBM);
5060 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5061 ieee80211_hw_set(hw, MFP_CAPABLE);
5062 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
5063 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5064 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
5065 ieee80211_hw_set(hw, TX_AMSDU);
5066 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
5067 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
5068 ieee80211_hw_set(hw, SUPPORTS_PS);
5069 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
5070 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
5071 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
5072 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
5073
5074 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5075 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
5076
5077 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
5078 ieee80211_hw_set(hw, CONNECTION_MONITOR);
5079
5080 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
5081 BIT(NL80211_IFTYPE_AP) |
5082 BIT(NL80211_IFTYPE_P2P_CLIENT) |
5083 BIT(NL80211_IFTYPE_P2P_GO);
5084
5085 if (hal->ant_diversity) {
5086 hw->wiphy->available_antennas_tx = 0x3;
5087 hw->wiphy->available_antennas_rx = 0x3;
5088 } else {
5089 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
5090 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
5091 }
5092
5093 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
5094 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
5095 WIPHY_FLAG_AP_UAPSD |
5096 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
5097
5098 if (!chip->support_rnr)
5099 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
5100
5101 if (chip->chip_gen == RTW89_CHIP_BE)
5102 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
5103
5104 if (rtwdev->support_mlo)
5105 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
5106
5107 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
5108
5109 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5110 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
5111
5112 #ifdef CONFIG_PM
5113 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
5114 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
5115 #endif
5116
5117 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5118 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
5119 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5120 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
5121 hw->wiphy->max_remain_on_channel_duration = 1000;
5122
5123 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
5124 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
5125 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
5126
5127 ret = rtw89_core_set_supported_band(rtwdev);
5128 if (ret) {
5129 rtw89_err(rtwdev, "failed to set supported band\n");
5130 return ret;
5131 }
5132
5133 ret = rtw89_regd_setup(rtwdev);
5134 if (ret) {
5135 rtw89_err(rtwdev, "failed to set up regd\n");
5136 goto err_free_supported_band;
5137 }
5138
5139 hw->wiphy->sar_capa = &rtw89_sar_capa;
5140
5141 ret = ieee80211_register_hw(hw);
5142 if (ret) {
5143 rtw89_err(rtwdev, "failed to register hw\n");
5144 goto err_free_supported_band;
5145 }
5146
5147 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
5148 if (ret) {
5149 rtw89_err(rtwdev, "failed to init regd\n");
5150 goto err_unregister_hw;
5151 }
5152
5153 rtw89_rfkill_polling_init(rtwdev);
5154
5155 return 0;
5156
5157 err_unregister_hw:
5158 ieee80211_unregister_hw(hw);
5159 err_free_supported_band:
5160 rtw89_core_clr_supported_band(rtwdev);
5161
5162 return ret;
5163 }
5164
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)5165 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
5166 {
5167 struct ieee80211_hw *hw = rtwdev->hw;
5168
5169 rtw89_rfkill_polling_deinit(rtwdev);
5170 ieee80211_unregister_hw(hw);
5171 rtw89_core_clr_supported_band(rtwdev);
5172 }
5173
rtw89_core_register(struct rtw89_dev * rtwdev)5174 int rtw89_core_register(struct rtw89_dev *rtwdev)
5175 {
5176 int ret;
5177
5178 ret = rtw89_core_register_hw(rtwdev);
5179 if (ret) {
5180 rtw89_err(rtwdev, "failed to register core hw\n");
5181 return ret;
5182 }
5183
5184 rtw89_debugfs_init(rtwdev);
5185
5186 return 0;
5187 }
5188 EXPORT_SYMBOL(rtw89_core_register);
5189
rtw89_core_unregister(struct rtw89_dev * rtwdev)5190 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
5191 {
5192 rtw89_core_unregister_hw(rtwdev);
5193
5194 rtw89_debugfs_deinit(rtwdev);
5195 }
5196 EXPORT_SYMBOL(rtw89_core_unregister);
5197
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip)5198 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5199 u32 bus_data_size,
5200 const struct rtw89_chip_info *chip)
5201 {
5202 struct rtw89_fw_info early_fw = {};
5203 const struct firmware *firmware;
5204 struct ieee80211_hw *hw;
5205 struct rtw89_dev *rtwdev;
5206 struct ieee80211_ops *ops;
5207 u32 driver_data_size;
5208 int fw_format = -1;
5209 bool support_mlo;
5210 bool no_chanctx;
5211
5212 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
5213
5214 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
5215 if (!ops)
5216 goto err;
5217
5218 no_chanctx = chip->support_chanctx_num == 0 ||
5219 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
5220 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
5221
5222 if (no_chanctx) {
5223 ops->add_chanctx = ieee80211_emulate_add_chanctx;
5224 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
5225 ops->change_chanctx = ieee80211_emulate_change_chanctx;
5226 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
5227 ops->assign_vif_chanctx = NULL;
5228 ops->unassign_vif_chanctx = NULL;
5229 ops->remain_on_channel = NULL;
5230 ops->cancel_remain_on_channel = NULL;
5231 }
5232
5233 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
5234 hw = ieee80211_alloc_hw(driver_data_size, ops);
5235 if (!hw)
5236 goto err;
5237
5238 /* TODO: When driver MLO arch. is done, determine whether to support MLO
5239 * according to the following conditions.
5240 * 1. run with chanctx_ops
5241 * 2. chip->support_link_num != 0
5242 * 3. FW feature supports AP_LINK_PS
5243 */
5244 support_mlo = false;
5245
5246 hw->wiphy->iface_combinations = rtw89_iface_combs;
5247
5248 if (no_chanctx || chip->support_chanctx_num == 1)
5249 hw->wiphy->n_iface_combinations = 1;
5250 else
5251 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
5252
5253 rtwdev = hw->priv;
5254 rtwdev->hw = hw;
5255 rtwdev->dev = device;
5256 rtwdev->ops = ops;
5257 rtwdev->chip = chip;
5258 rtwdev->fw.req.firmware = firmware;
5259 rtwdev->fw.fw_format = fw_format;
5260 rtwdev->support_mlo = support_mlo;
5261
5262 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
5263 no_chanctx ? "without" : "with");
5264 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
5265 support_mlo ? "with" : "without");
5266
5267 return rtwdev;
5268
5269 err:
5270 kfree(ops);
5271 release_firmware(firmware);
5272 return NULL;
5273 }
5274 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
5275
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)5276 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
5277 {
5278 kfree(rtwdev->ops);
5279 kfree(rtwdev->rfe_data);
5280 release_firmware(rtwdev->fw.req.firmware);
5281 ieee80211_free_hw(rtwdev->hw);
5282 }
5283 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
5284
5285 MODULE_AUTHOR("Realtek Corporation");
5286 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
5287 MODULE_LICENSE("Dual BSD/GPL");
5288