1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "chan.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "fw.h"
9 #include "mac.h"
10 #include "phy.h"
11 #include "ps.h"
12 #include "reg.h"
13 #include "sar.h"
14 #include "txrx.h"
15 #include "util.h"
16
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)17 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
18 {
19 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
20
21 return phy->phy0_phy1_offset(rtwdev, addr);
22 }
23
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)24 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
25 const struct rtw89_ra_report *report)
26 {
27 u32 bit_rate = report->bit_rate;
28
29 /* lower than ofdm, do not aggregate */
30 if (bit_rate < 550)
31 return 1;
32
33 /* avoid AMSDU for legacy rate */
34 if (report->might_fallback_legacy)
35 return 1;
36
37 /* lower than 20M vht 2ss mcs8, make it small */
38 if (bit_rate < 1800)
39 return 1200;
40
41 /* lower than 40M vht 2ss mcs9, make it medium */
42 if (bit_rate < 4000)
43 return 2600;
44
45 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
46 if (bit_rate < 7000)
47 return 3500;
48
49 return rtwdev->chip->max_amsdu_limit;
50 }
51
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)52 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
53 {
54 u64 ra_mask = 0;
55 u8 mcs_cap;
56 int i, nss;
57
58 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
59 mcs_cap = mcs_map & 0x3;
60 switch (mcs_cap) {
61 case 2:
62 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
63 break;
64 case 1:
65 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
66 break;
67 case 0:
68 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
69 break;
70 default:
71 break;
72 }
73 }
74
75 return ra_mask;
76 }
77
get_he_ra_mask(struct ieee80211_link_sta * link_sta)78 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta)
79 {
80 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
81 u16 mcs_map;
82
83 switch (link_sta->bandwidth) {
84 case IEEE80211_STA_RX_BW_160:
85 if (cap.he_cap_elem.phy_cap_info[0] &
86 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
87 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
88 else
89 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
90 break;
91 default:
92 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
93 }
94
95 /* MCS11, MCS9, MCS7 */
96 return get_mcs_ra_mask(mcs_map, 11, 2);
97 }
98
get_eht_mcs_ra_mask(u8 * max_nss,u8 start_mcs,u8 n_nss)99 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)
100 {
101 u64 nss_mcs_shift;
102 u64 nss_mcs_val;
103 u64 mask = 0;
104 int i, j;
105 u8 nss;
106
107 for (i = 0; i < n_nss; i++) {
108 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);
109 if (!nss)
110 continue;
111
112 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);
113
114 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)
115 mask |= nss_mcs_val << nss_mcs_shift;
116 }
117
118 return mask;
119 }
120
get_eht_ra_mask(struct ieee80211_link_sta * link_sta)121 static u64 get_eht_ra_mask(struct ieee80211_link_sta *link_sta)
122 {
123 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
124 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;
125 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;
126 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
127
128 switch (link_sta->bandwidth) {
129 case IEEE80211_STA_RX_BW_320:
130 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
131 /* MCS 9, 11, 13 */
132 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
133 case IEEE80211_STA_RX_BW_160:
134 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
135 /* MCS 9, 11, 13 */
136 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
137 case IEEE80211_STA_RX_BW_20:
138 if (!(he_phy_cap[0] &
139 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
140 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
141 /* MCS 7, 9, 11, 13 */
142 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
143 }
144 fallthrough;
145 case IEEE80211_STA_RX_BW_80:
146 default:
147 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
148 /* MCS 9, 11, 13 */
149 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
150 }
151 }
152
153 #define RA_FLOOR_TABLE_SIZE 7
154 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)155 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
156 u8 ratr_state)
157 {
158 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
159 u8 rssi_lv = 0;
160 u8 i;
161
162 rssi >>= 1;
163 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
164 if (i >= ratr_state)
165 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
166 if (rssi < rssi_lv_t[i]) {
167 rssi_lv = i;
168 break;
169 }
170 }
171 if (rssi_lv == 0)
172 return 0xffffffffffffffffULL;
173 else if (rssi_lv == 1)
174 return 0xfffffffffffffff0ULL;
175 else if (rssi_lv == 2)
176 return 0xffffffffffffefe0ULL;
177 else if (rssi_lv == 3)
178 return 0xffffffffffffcfc0ULL;
179 else if (rssi_lv == 4)
180 return 0xffffffffffff8f80ULL;
181 else if (rssi_lv >= 5)
182 return 0xffffffffffff0f00ULL;
183
184 return 0xffffffffffffffffULL;
185 }
186
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)187 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
188 {
189 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
190 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
191
192 if (ra_mask == 0)
193 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
194
195 return ra_mask;
196 }
197
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan)198 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev,
199 struct rtw89_sta_link *rtwsta_link,
200 struct ieee80211_link_sta *link_sta,
201 const struct rtw89_chan *chan)
202 {
203 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
204 enum nl80211_band band;
205 u64 cfg_mask;
206
207 if (!rtwsta_link->use_cfg_mask)
208 return -1;
209
210 switch (chan->band_type) {
211 case RTW89_BAND_2G:
212 band = NL80211_BAND_2GHZ;
213 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
214 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
215 break;
216 case RTW89_BAND_5G:
217 band = NL80211_BAND_5GHZ;
218 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
219 RA_MASK_OFDM_RATES);
220 break;
221 case RTW89_BAND_6G:
222 band = NL80211_BAND_6GHZ;
223 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
224 RA_MASK_OFDM_RATES);
225 break;
226 default:
227 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
228 return -1;
229 }
230
231 if (link_sta->he_cap.has_he) {
232 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
233 RA_MASK_HE_1SS_RATES);
234 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
235 RA_MASK_HE_2SS_RATES);
236 } else if (link_sta->vht_cap.vht_supported) {
237 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
238 RA_MASK_VHT_1SS_RATES);
239 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
240 RA_MASK_VHT_2SS_RATES);
241 } else if (link_sta->ht_cap.ht_supported) {
242 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
243 RA_MASK_HT_1SS_RATES);
244 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
245 RA_MASK_HT_2SS_RATES);
246 }
247
248 return cfg_mask;
249 }
250
251 static const u64
252 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
253 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
254 static const u64
255 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
256 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
257 static const u64
258 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
259 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
260 static const u64
261 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,
262 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};
263
rtw89_phy_ra_gi_ltf(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,const struct rtw89_chan * chan,bool * fix_giltf_en,u8 * fix_giltf)264 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
265 struct rtw89_sta_link *rtwsta_link,
266 const struct rtw89_chan *chan,
267 bool *fix_giltf_en, u8 *fix_giltf)
268 {
269 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
270 u8 band = chan->band_type;
271 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
272 u8 he_gi = mask->control[nl_band].he_gi;
273 u8 he_ltf = mask->control[nl_band].he_ltf;
274
275 if (!rtwsta_link->use_cfg_mask)
276 return;
277
278 if (he_ltf == 2 && he_gi == 2) {
279 *fix_giltf = RTW89_GILTF_LGI_4XHE32;
280 } else if (he_ltf == 2 && he_gi == 0) {
281 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
282 } else if (he_ltf == 1 && he_gi == 1) {
283 *fix_giltf = RTW89_GILTF_2XHE16;
284 } else if (he_ltf == 1 && he_gi == 0) {
285 *fix_giltf = RTW89_GILTF_2XHE08;
286 } else if (he_ltf == 0 && he_gi == 1) {
287 *fix_giltf = RTW89_GILTF_1XHE16;
288 } else if (he_ltf == 0 && he_gi == 0) {
289 *fix_giltf = RTW89_GILTF_1XHE08;
290 } else {
291 *fix_giltf_en = false;
292 return;
293 }
294
295 *fix_giltf_en = true;
296 }
297
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,bool p2p,bool csi)298 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
299 struct rtw89_vif_link *rtwvif_link,
300 struct rtw89_sta_link *rtwsta_link,
301 struct ieee80211_link_sta *link_sta,
302 bool p2p, bool csi)
303 {
304 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
305 struct rtw89_ra_info *ra = &rtwsta_link->ra;
306 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
307 rtwvif_link->chanctx_idx);
308 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
309 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
310 u64 ra_mask = 0;
311 u64 ra_mask_bak;
312 u8 mode = 0;
313 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
314 u8 bw_mode = 0;
315 u8 stbc_en = 0;
316 u8 ldpc_en = 0;
317 u8 fix_giltf = 0;
318 u8 i;
319 bool sgi = false;
320 bool fix_giltf_en = false;
321
322 memset(ra, 0, sizeof(*ra));
323 /* Set the ra mask from sta's capability */
324 if (link_sta->eht_cap.has_eht) {
325 mode |= RTW89_RA_MODE_EHT;
326 ra_mask |= get_eht_ra_mask(link_sta);
327 high_rate_masks = rtw89_ra_mask_eht_rates;
328 } else if (link_sta->he_cap.has_he) {
329 mode |= RTW89_RA_MODE_HE;
330 csi_mode = RTW89_RA_RPT_MODE_HE;
331 ra_mask |= get_he_ra_mask(link_sta);
332 high_rate_masks = rtw89_ra_mask_he_rates;
333 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
334 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
335 stbc_en = 1;
336 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
337 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
338 ldpc_en = 1;
339 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, chan, &fix_giltf_en, &fix_giltf);
340 } else if (link_sta->vht_cap.vht_supported) {
341 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
342
343 mode |= RTW89_RA_MODE_VHT;
344 csi_mode = RTW89_RA_RPT_MODE_VHT;
345 /* MCS9 (non-20MHz), MCS8, MCS7 */
346 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
347 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1);
348 else
349 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
350 high_rate_masks = rtw89_ra_mask_vht_rates;
351 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
352 stbc_en = 1;
353 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
354 ldpc_en = 1;
355 } else if (link_sta->ht_cap.ht_supported) {
356 mode |= RTW89_RA_MODE_HT;
357 csi_mode = RTW89_RA_RPT_MODE_HT;
358 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
359 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
360 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
361 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
362 high_rate_masks = rtw89_ra_mask_ht_rates;
363 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
364 stbc_en = 1;
365 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
366 ldpc_en = 1;
367 }
368
369 switch (chan->band_type) {
370 case RTW89_BAND_2G:
371 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
372 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
373 mode |= RTW89_RA_MODE_CCK;
374 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
375 mode |= RTW89_RA_MODE_OFDM;
376 break;
377 case RTW89_BAND_5G:
378 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
379 mode |= RTW89_RA_MODE_OFDM;
380 break;
381 case RTW89_BAND_6G:
382 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
383 mode |= RTW89_RA_MODE_OFDM;
384 break;
385 default:
386 rtw89_err(rtwdev, "Unknown band type\n");
387 break;
388 }
389
390 ra_mask_bak = ra_mask;
391
392 if (mode >= RTW89_RA_MODE_HT) {
393 u64 mask = 0;
394 for (i = 0; i < rtwdev->hal.tx_nss; i++)
395 mask |= high_rate_masks[i];
396 if (mode & RTW89_RA_MODE_OFDM)
397 mask |= RA_MASK_SUBOFDM_RATES;
398 if (mode & RTW89_RA_MODE_CCK)
399 mask |= RA_MASK_SUBCCK_RATES;
400 ra_mask &= mask;
401 } else if (mode & RTW89_RA_MODE_OFDM) {
402 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
403 }
404
405 if (mode != RTW89_RA_MODE_CCK)
406 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
407
408 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
409 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
410
411 switch (link_sta->bandwidth) {
412 case IEEE80211_STA_RX_BW_160:
413 bw_mode = RTW89_CHANNEL_WIDTH_160;
414 sgi = link_sta->vht_cap.vht_supported &&
415 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
416 break;
417 case IEEE80211_STA_RX_BW_80:
418 bw_mode = RTW89_CHANNEL_WIDTH_80;
419 sgi = link_sta->vht_cap.vht_supported &&
420 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
421 break;
422 case IEEE80211_STA_RX_BW_40:
423 bw_mode = RTW89_CHANNEL_WIDTH_40;
424 sgi = link_sta->ht_cap.ht_supported &&
425 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
426 break;
427 default:
428 bw_mode = RTW89_CHANNEL_WIDTH_20;
429 sgi = link_sta->ht_cap.ht_supported &&
430 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
431 break;
432 }
433
434 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
435 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
436 ra->dcm_cap = 1;
437
438 if (rate_pattern->enable && !p2p) {
439 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
440 ra_mask &= rate_pattern->ra_mask;
441 mode = rate_pattern->ra_mode;
442 }
443
444 ra->bw_cap = bw_mode;
445 ra->er_cap = rtwsta_link->er_cap;
446 ra->mode_ctrl = mode;
447 ra->macid = rtwsta_link->mac_id;
448 ra->stbc_cap = stbc_en;
449 ra->ldpc_cap = ldpc_en;
450 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
451 ra->en_sgi = sgi;
452 ra->ra_mask = ra_mask;
453 ra->fix_giltf_en = fix_giltf_en;
454 ra->fix_giltf = fix_giltf;
455
456 if (!csi)
457 return;
458
459 ra->fixed_csi_rate_en = false;
460 ra->ra_csi_rate_en = true;
461 ra->cr_tbl_sel = false;
462 ra->band_num = rtwvif_link->phy_idx;
463 ra->csi_bw = bw_mode;
464 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
465 ra->csi_mcs_ss_idx = 5;
466 ra->csi_mode = csi_mode;
467 }
468
__rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,u32 changed)469 static void __rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev,
470 struct rtw89_vif_link *rtwvif_link,
471 struct rtw89_sta_link *rtwsta_link,
472 u32 changed)
473 {
474 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
475 struct rtw89_ra_info *ra = &rtwsta_link->ra;
476 struct ieee80211_link_sta *link_sta;
477
478 rcu_read_lock();
479
480 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
481 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
482 link_sta, vif->p2p, false);
483
484 rcu_read_unlock();
485
486 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
487 ra->upd_mask = 1;
488 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
489 ra->upd_bw_nss_mask = 1;
490
491 rtw89_debug(rtwdev, RTW89_DBG_RA,
492 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
493 ra->macid,
494 ra->bw_cap,
495 ra->ss_num,
496 ra->en_sgi,
497 ra->giltf);
498
499 rtw89_fw_h2c_ra(rtwdev, ra, false);
500 }
501
rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)502 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
503 u32 changed)
504 {
505 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
506 struct rtw89_vif_link *rtwvif_link;
507 struct rtw89_sta_link *rtwsta_link;
508 unsigned int link_id;
509
510 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
511 rtwvif_link = rtwsta_link->rtwvif_link;
512 __rtw89_phy_ra_update_sta(rtwdev, rtwvif_link, rtwsta_link, changed);
513 }
514 }
515
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)516 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
517 u16 rate_base, u64 ra_mask, u8 ra_mode,
518 u32 rate_ctrl, u32 ctrl_skip, bool force)
519 {
520 u8 n, c;
521
522 if (rate_ctrl == ctrl_skip)
523 return true;
524
525 n = hweight32(rate_ctrl);
526 if (n == 0)
527 return true;
528
529 if (force && n != 1)
530 return false;
531
532 if (next->enable)
533 return false;
534
535 c = __fls(rate_ctrl);
536 next->rate = rate_base + c;
537 next->ra_mode = ra_mode;
538 next->ra_mask = ra_mask;
539 next->enable = true;
540
541 return true;
542 }
543
544 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
545 { \
546 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
547 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \
548 }
549
550 static
__rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const struct cfg80211_bitrate_mask * mask)551 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
552 struct rtw89_vif_link *rtwvif_link,
553 const struct cfg80211_bitrate_mask *mask)
554 {
555 struct ieee80211_supported_band *sband;
556 struct rtw89_phy_rate_pattern next_pattern = {0};
557 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
558 rtwvif_link->chanctx_idx);
559 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
560 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
561 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
562 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0),
563 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0),
564 };
565 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = {
566 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0),
567 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0),
568 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0),
569 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0),
570 };
571 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = {
572 RTW89_HW_RATE_BY_CHIP_GEN(MCS0),
573 RTW89_HW_RATE_BY_CHIP_GEN(MCS8),
574 RTW89_HW_RATE_BY_CHIP_GEN(MCS16),
575 RTW89_HW_RATE_BY_CHIP_GEN(MCS24),
576 };
577 u8 band = chan->band_type;
578 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
579 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
580 u8 tx_nss = rtwdev->hal.tx_nss;
581 u8 i;
582
583 for (i = 0; i < tx_nss; i++)
584 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
585 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
586 mask->control[nl_band].he_mcs[i],
587 0, true))
588 goto out;
589
590 for (i = 0; i < tx_nss; i++)
591 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen],
592 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
593 mask->control[nl_band].vht_mcs[i],
594 0, true))
595 goto out;
596
597 for (i = 0; i < tx_nss; i++)
598 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen],
599 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
600 mask->control[nl_band].ht_mcs[i],
601 0, true))
602 goto out;
603
604 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
605 * require at least one basic rate for ieee80211_set_bitrate_mask,
606 * so the decision just depends on if all bitrates are set or not.
607 */
608 sband = rtwdev->hw->wiphy->bands[nl_band];
609 if (band == RTW89_BAND_2G) {
610 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
611 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
612 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
613 mask->control[nl_band].legacy,
614 BIT(sband->n_bitrates) - 1, false))
615 goto out;
616 } else {
617 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
618 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
619 mask->control[nl_band].legacy,
620 BIT(sband->n_bitrates) - 1, false))
621 goto out;
622 }
623
624 if (!next_pattern.enable)
625 goto out;
626
627 rtwvif_link->rate_pattern = next_pattern;
628 rtw89_debug(rtwdev, RTW89_DBG_RA,
629 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
630 next_pattern.rate,
631 next_pattern.ra_mask,
632 next_pattern.ra_mode);
633 return;
634
635 out:
636 rtwvif_link->rate_pattern.enable = false;
637 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
638 }
639
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)640 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
641 struct ieee80211_vif *vif,
642 const struct cfg80211_bitrate_mask *mask)
643 {
644 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
645 struct rtw89_vif_link *rtwvif_link;
646 unsigned int link_id;
647
648 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
649 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask);
650 }
651
rtw89_phy_ra_update_sta_iter(void * data,struct ieee80211_sta * sta)652 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta)
653 {
654 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
655
656 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
657 }
658
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)659 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
660 {
661 ieee80211_iterate_stations_atomic(rtwdev->hw,
662 rtw89_phy_ra_update_sta_iter,
663 rtwdev);
664 }
665
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)666 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link)
667 {
668 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
669 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
670 struct rtw89_ra_info *ra = &rtwsta_link->ra;
671 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
672 struct ieee80211_link_sta *link_sta;
673 bool csi;
674
675 rcu_read_lock();
676
677 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
678 csi = rtw89_sta_has_beamformer_cap(link_sta);
679
680 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
681 link_sta, vif->p2p, csi);
682
683 rcu_read_unlock();
684
685 if (rssi > 40)
686 ra->init_rate_lv = 1;
687 else if (rssi > 20)
688 ra->init_rate_lv = 2;
689 else if (rssi > 1)
690 ra->init_rate_lv = 3;
691 else
692 ra->init_rate_lv = 0;
693 ra->upd_all = 1;
694 rtw89_debug(rtwdev, RTW89_DBG_RA,
695 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
696 ra->macid,
697 ra->mode_ctrl,
698 ra->bw_cap,
699 ra->ss_num,
700 ra->init_rate_lv);
701 rtw89_debug(rtwdev, RTW89_DBG_RA,
702 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
703 ra->dcm_cap,
704 ra->er_cap,
705 ra->ldpc_cap,
706 ra->stbc_cap,
707 ra->en_sgi,
708 ra->giltf);
709
710 rtw89_fw_h2c_ra(rtwdev, ra, csi);
711 }
712
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)713 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
714 const struct rtw89_chan *chan,
715 enum rtw89_bandwidth dbw)
716 {
717 enum rtw89_bandwidth cbw = chan->band_width;
718 u8 pri_ch = chan->primary_channel;
719 u8 central_ch = chan->channel;
720 u8 txsc_idx = 0;
721 u8 tmp = 0;
722
723 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
724 return txsc_idx;
725
726 switch (cbw) {
727 case RTW89_CHANNEL_WIDTH_40:
728 txsc_idx = pri_ch > central_ch ? 1 : 2;
729 break;
730 case RTW89_CHANNEL_WIDTH_80:
731 if (dbw == RTW89_CHANNEL_WIDTH_20) {
732 if (pri_ch > central_ch)
733 txsc_idx = (pri_ch - central_ch) >> 1;
734 else
735 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
736 } else {
737 txsc_idx = pri_ch > central_ch ? 9 : 10;
738 }
739 break;
740 case RTW89_CHANNEL_WIDTH_160:
741 if (pri_ch > central_ch)
742 tmp = (pri_ch - central_ch) >> 1;
743 else
744 tmp = ((central_ch - pri_ch) >> 1) + 1;
745
746 if (dbw == RTW89_CHANNEL_WIDTH_20) {
747 txsc_idx = tmp;
748 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
749 if (tmp == 1 || tmp == 3)
750 txsc_idx = 9;
751 else if (tmp == 5 || tmp == 7)
752 txsc_idx = 11;
753 else if (tmp == 2 || tmp == 4)
754 txsc_idx = 10;
755 else if (tmp == 6 || tmp == 8)
756 txsc_idx = 12;
757 else
758 return 0xff;
759 } else {
760 txsc_idx = pri_ch > central_ch ? 13 : 14;
761 }
762 break;
763 case RTW89_CHANNEL_WIDTH_80_80:
764 if (dbw == RTW89_CHANNEL_WIDTH_20) {
765 if (pri_ch > central_ch)
766 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
767 else
768 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
769 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
770 txsc_idx = pri_ch > central_ch ? 10 : 12;
771 } else {
772 txsc_idx = 14;
773 }
774 break;
775 default:
776 break;
777 }
778
779 return txsc_idx;
780 }
781 EXPORT_SYMBOL(rtw89_phy_get_txsc);
782
rtw89_phy_get_txsb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)783 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
784 enum rtw89_bandwidth dbw)
785 {
786 enum rtw89_bandwidth cbw = chan->band_width;
787 u8 pri_ch = chan->primary_channel;
788 u8 central_ch = chan->channel;
789 u8 txsb_idx = 0;
790
791 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
792 return txsb_idx;
793
794 switch (cbw) {
795 case RTW89_CHANNEL_WIDTH_40:
796 txsb_idx = pri_ch > central_ch ? 1 : 0;
797 break;
798 case RTW89_CHANNEL_WIDTH_80:
799 if (dbw == RTW89_CHANNEL_WIDTH_20)
800 txsb_idx = (pri_ch - central_ch + 6) / 4;
801 else
802 txsb_idx = pri_ch > central_ch ? 1 : 0;
803 break;
804 case RTW89_CHANNEL_WIDTH_160:
805 if (dbw == RTW89_CHANNEL_WIDTH_20)
806 txsb_idx = (pri_ch - central_ch + 14) / 4;
807 else if (dbw == RTW89_CHANNEL_WIDTH_40)
808 txsb_idx = (pri_ch - central_ch + 12) / 8;
809 else
810 txsb_idx = pri_ch > central_ch ? 1 : 0;
811 break;
812 case RTW89_CHANNEL_WIDTH_320:
813 if (dbw == RTW89_CHANNEL_WIDTH_20)
814 txsb_idx = (pri_ch - central_ch + 30) / 4;
815 else if (dbw == RTW89_CHANNEL_WIDTH_40)
816 txsb_idx = (pri_ch - central_ch + 28) / 8;
817 else if (dbw == RTW89_CHANNEL_WIDTH_80)
818 txsb_idx = (pri_ch - central_ch + 24) / 16;
819 else
820 txsb_idx = pri_ch > central_ch ? 1 : 0;
821 break;
822 default:
823 break;
824 }
825
826 return txsb_idx;
827 }
828 EXPORT_SYMBOL(rtw89_phy_get_txsb);
829
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)830 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
831 {
832 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
833 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
834 }
835
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)836 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
837 u32 addr, u32 mask)
838 {
839 const struct rtw89_chip_info *chip = rtwdev->chip;
840 const u32 *base_addr = chip->rf_base_addr;
841 u32 val, direct_addr;
842
843 if (rf_path >= rtwdev->chip->rf_path_num) {
844 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
845 return INV_RF_DATA;
846 }
847
848 addr &= 0xff;
849 direct_addr = base_addr[rf_path] + (addr << 2);
850 mask &= RFREG_MASK;
851
852 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
853
854 return val;
855 }
856 EXPORT_SYMBOL(rtw89_phy_read_rf);
857
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)858 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
859 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
860 {
861 bool busy;
862 bool done;
863 u32 val;
864 int ret;
865
866 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
867 1, 30, false, rtwdev);
868 if (ret) {
869 rtw89_err(rtwdev, "read rf busy swsi\n");
870 return INV_RF_DATA;
871 }
872
873 mask &= RFREG_MASK;
874
875 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
876 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
877 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
878 udelay(2);
879
880 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
881 30, false, rtwdev, R_SWSI_V1,
882 B_SWSI_R_DATA_DONE_V1);
883 if (ret) {
884 rtw89_err(rtwdev, "read swsi busy\n");
885 return INV_RF_DATA;
886 }
887
888 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
889 }
890
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)891 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
892 u32 addr, u32 mask)
893 {
894 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
895
896 if (rf_path >= rtwdev->chip->rf_path_num) {
897 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
898 return INV_RF_DATA;
899 }
900
901 if (ad_sel)
902 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
903 else
904 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
905 }
906 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
907
rtw89_phy_read_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)908 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
909 enum rtw89_rf_path rf_path, u32 addr)
910 {
911 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24};
912 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC};
913 bool busy, done;
914 int ret;
915 u32 val;
916
917 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
918 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
919 1, 3800, false,
920 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
921 if (ret) {
922 rtw89_warn(rtwdev, "poll HWSI is busy\n");
923 return INV_RF_DATA;
924 }
925
926 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
927 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
928 udelay(2);
929
930 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
931 1, 3800, false,
932 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
933 if (ret) {
934 rtw89_warn(rtwdev, "read HWSI is busy\n");
935 val = INV_RF_DATA;
936 goto out;
937 }
938
939 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
940 out:
941 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
942
943 return val;
944 }
945
rtw89_phy_read_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)946 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
947 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
948 {
949 u32 val;
950
951 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
952
953 return (val & mask) >> __ffs(mask);
954 }
955
rtw89_phy_read_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)956 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
957 u32 addr, u32 mask)
958 {
959 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
960
961 if (rf_path >= rtwdev->chip->rf_path_num) {
962 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
963 return INV_RF_DATA;
964 }
965
966 if (ad_sel)
967 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
968 else
969 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
970 }
971 EXPORT_SYMBOL(rtw89_phy_read_rf_v2);
972
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)973 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
974 u32 addr, u32 mask, u32 data)
975 {
976 const struct rtw89_chip_info *chip = rtwdev->chip;
977 const u32 *base_addr = chip->rf_base_addr;
978 u32 direct_addr;
979
980 if (rf_path >= rtwdev->chip->rf_path_num) {
981 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
982 return false;
983 }
984
985 addr &= 0xff;
986 direct_addr = base_addr[rf_path] + (addr << 2);
987 mask &= RFREG_MASK;
988
989 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
990
991 /* delay to ensure writing properly */
992 udelay(1);
993
994 return true;
995 }
996 EXPORT_SYMBOL(rtw89_phy_write_rf);
997
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)998 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
999 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
1000 u32 data)
1001 {
1002 u8 bit_shift;
1003 u32 val;
1004 bool busy, b_msk_en = false;
1005 int ret;
1006
1007 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
1008 1, 30, false, rtwdev);
1009 if (ret) {
1010 rtw89_err(rtwdev, "write rf busy swsi\n");
1011 return false;
1012 }
1013
1014 data &= RFREG_MASK;
1015 mask &= RFREG_MASK;
1016
1017 if (mask != RFREG_MASK) {
1018 b_msk_en = true;
1019 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
1020 mask);
1021 bit_shift = __ffs(mask);
1022 data = (data << bit_shift) & RFREG_MASK;
1023 }
1024
1025 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
1026 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
1027 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
1028 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
1029
1030 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
1031
1032 return true;
1033 }
1034
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1035 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1036 u32 addr, u32 mask, u32 data)
1037 {
1038 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
1039
1040 if (rf_path >= rtwdev->chip->rf_path_num) {
1041 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1042 return false;
1043 }
1044
1045 if (ad_sel)
1046 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1047 else
1048 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1049 }
1050 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
1051
1052 static
rtw89_phy_write_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1053 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1054 u32 addr, u32 data)
1055 {
1056 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24};
1057 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0};
1058 bool busy;
1059 u32 val;
1060 int ret;
1061
1062 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1063 1, 3800, false,
1064 rtwdev, addr_is_idle[rf_path], BIT(29));
1065 if (ret) {
1066 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1067 return false;
1068 }
1069
1070 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) |
1071 u32_encode_bits(data, B_HWSI_DATA_VAL);
1072
1073 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1074
1075 return true;
1076 }
1077
1078 static
rtw89_phy_write_rf_a_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1079 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1080 u32 addr, u32 mask, u32 data)
1081 {
1082 u32 val;
1083
1084 if (mask == RFREG_MASK) {
1085 val = data;
1086 } else {
1087 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1088 val &= ~mask;
1089 val |= (data << __ffs(mask)) & mask;
1090 }
1091
1092 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1093 }
1094
rtw89_phy_write_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1095 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1096 u32 addr, u32 mask, u32 data)
1097 {
1098 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1099
1100 if (rf_path >= rtwdev->chip->rf_path_num) {
1101 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1102 return INV_RF_DATA;
1103 }
1104
1105 if (ad_sel)
1106 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1107 else
1108 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1109 }
1110 EXPORT_SYMBOL(rtw89_phy_write_rf_v2);
1111
rtw89_chip_rf_v1(struct rtw89_dev * rtwdev)1112 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1113 {
1114 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1115 }
1116
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1117 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1118 enum rtw89_phy_idx phy_idx)
1119 {
1120 const struct rtw89_chip_info *chip = rtwdev->chip;
1121
1122 chip->ops->bb_reset(rtwdev, phy_idx);
1123 }
1124
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1125 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1126 const struct rtw89_reg2_def *reg,
1127 enum rtw89_rf_path rf_path,
1128 void *extra_data)
1129 {
1130 u32 addr;
1131
1132 if (reg->addr == 0xfe) {
1133 mdelay(50);
1134 } else if (reg->addr == 0xfd) {
1135 mdelay(5);
1136 } else if (reg->addr == 0xfc) {
1137 mdelay(1);
1138 } else if (reg->addr == 0xfb) {
1139 udelay(50);
1140 } else if (reg->addr == 0xfa) {
1141 udelay(5);
1142 } else if (reg->addr == 0xf9) {
1143 udelay(1);
1144 } else if (reg->data == BYPASS_CR_DATA) {
1145 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1146 } else {
1147 addr = reg->addr;
1148
1149 if ((uintptr_t)extra_data == RTW89_PHY_1)
1150 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1151
1152 rtw89_phy_write32(rtwdev, addr, reg->data);
1153 }
1154 }
1155
1156 union rtw89_phy_bb_gain_arg {
1157 u32 addr;
1158 struct {
1159 union {
1160 u8 type;
1161 struct {
1162 u8 rxsc_start:4;
1163 u8 bw:4;
1164 };
1165 };
1166 u8 path;
1167 u8 gain_band;
1168 u8 cfg_type;
1169 };
1170 } __packed;
1171
1172 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1173 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1174 union rtw89_phy_bb_gain_arg arg, u32 data)
1175 {
1176 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1177 u8 type = arg.type;
1178 u8 path = arg.path;
1179 u8 gband = arg.gain_band;
1180 int i;
1181
1182 switch (type) {
1183 case 0:
1184 for (i = 0; i < 4; i++, data >>= 8)
1185 gain->lna_gain[gband][path][i] = data & 0xff;
1186 break;
1187 case 1:
1188 for (i = 4; i < 7; i++, data >>= 8)
1189 gain->lna_gain[gband][path][i] = data & 0xff;
1190 break;
1191 case 2:
1192 for (i = 0; i < 2; i++, data >>= 8)
1193 gain->tia_gain[gband][path][i] = data & 0xff;
1194 break;
1195 default:
1196 rtw89_warn(rtwdev,
1197 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
1198 arg.addr, data, type);
1199 break;
1200 }
1201 }
1202
1203 enum rtw89_phy_bb_rxsc_start_idx {
1204 RTW89_BB_RXSC_START_IDX_FULL = 0,
1205 RTW89_BB_RXSC_START_IDX_20 = 1,
1206 RTW89_BB_RXSC_START_IDX_20_1 = 5,
1207 RTW89_BB_RXSC_START_IDX_40 = 9,
1208 RTW89_BB_RXSC_START_IDX_80 = 13,
1209 };
1210
1211 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1212 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1213 union rtw89_phy_bb_gain_arg arg, u32 data)
1214 {
1215 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1216 u8 rxsc_start = arg.rxsc_start;
1217 u8 bw = arg.bw;
1218 u8 path = arg.path;
1219 u8 gband = arg.gain_band;
1220 u8 rxsc;
1221 s8 ofst;
1222 int i;
1223
1224 switch (bw) {
1225 case RTW89_CHANNEL_WIDTH_20:
1226 gain->rpl_ofst_20[gband][path] = (s8)data;
1227 break;
1228 case RTW89_CHANNEL_WIDTH_40:
1229 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1230 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1231 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1232 for (i = 0; i < 2; i++, data >>= 8) {
1233 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1234 ofst = (s8)(data & 0xff);
1235 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1236 }
1237 }
1238 break;
1239 case RTW89_CHANNEL_WIDTH_80:
1240 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1241 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1242 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1243 for (i = 0; i < 4; i++, data >>= 8) {
1244 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1245 ofst = (s8)(data & 0xff);
1246 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1247 }
1248 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1249 for (i = 0; i < 2; i++, data >>= 8) {
1250 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1251 ofst = (s8)(data & 0xff);
1252 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1253 }
1254 }
1255 break;
1256 case RTW89_CHANNEL_WIDTH_160:
1257 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1258 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1259 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1260 for (i = 0; i < 4; i++, data >>= 8) {
1261 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1262 ofst = (s8)(data & 0xff);
1263 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1264 }
1265 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
1266 for (i = 0; i < 4; i++, data >>= 8) {
1267 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
1268 ofst = (s8)(data & 0xff);
1269 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1270 }
1271 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1272 for (i = 0; i < 4; i++, data >>= 8) {
1273 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1274 ofst = (s8)(data & 0xff);
1275 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1276 }
1277 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
1278 for (i = 0; i < 2; i++, data >>= 8) {
1279 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
1280 ofst = (s8)(data & 0xff);
1281 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1282 }
1283 }
1284 break;
1285 default:
1286 rtw89_warn(rtwdev,
1287 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1288 arg.addr, data, bw);
1289 break;
1290 }
1291 }
1292
1293 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1294 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1295 union rtw89_phy_bb_gain_arg arg, u32 data)
1296 {
1297 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1298 u8 type = arg.type;
1299 u8 path = arg.path;
1300 u8 gband = arg.gain_band;
1301 int i;
1302
1303 switch (type) {
1304 case 0:
1305 for (i = 0; i < 4; i++, data >>= 8)
1306 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1307 break;
1308 case 1:
1309 for (i = 4; i < 7; i++, data >>= 8)
1310 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1311 break;
1312 default:
1313 rtw89_warn(rtwdev,
1314 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
1315 arg.addr, data, type);
1316 break;
1317 }
1318 }
1319
1320 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1321 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1322 union rtw89_phy_bb_gain_arg arg, u32 data)
1323 {
1324 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1325 u8 type = arg.type;
1326 u8 path = arg.path;
1327 u8 gband = arg.gain_band;
1328 int i;
1329
1330 switch (type) {
1331 case 0:
1332 for (i = 0; i < 4; i++, data >>= 8)
1333 gain->lna_op1db[gband][path][i] = data & 0xff;
1334 break;
1335 case 1:
1336 for (i = 4; i < 7; i++, data >>= 8)
1337 gain->lna_op1db[gband][path][i] = data & 0xff;
1338 break;
1339 case 2:
1340 for (i = 0; i < 4; i++, data >>= 8)
1341 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1342 break;
1343 case 3:
1344 for (i = 4; i < 8; i++, data >>= 8)
1345 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1346 break;
1347 default:
1348 rtw89_warn(rtwdev,
1349 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
1350 arg.addr, data, type);
1351 break;
1352 }
1353 }
1354
rtw89_phy_config_bb_gain_ax(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1355 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1356 const struct rtw89_reg2_def *reg,
1357 enum rtw89_rf_path rf_path,
1358 void *extra_data)
1359 {
1360 const struct rtw89_chip_info *chip = rtwdev->chip;
1361 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1362 struct rtw89_efuse *efuse = &rtwdev->efuse;
1363
1364 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1365 return;
1366
1367 if (arg.path >= chip->rf_path_num)
1368 return;
1369
1370 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1371 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1372 return;
1373 }
1374
1375 switch (arg.cfg_type) {
1376 case 0:
1377 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1378 break;
1379 case 1:
1380 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1381 break;
1382 case 2:
1383 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1384 break;
1385 case 3:
1386 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1387 break;
1388 case 4:
1389 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
1390 if (efuse->rfe_type < 50)
1391 break;
1392 fallthrough;
1393 default:
1394 rtw89_warn(rtwdev,
1395 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1396 arg.addr, reg->data, arg.cfg_type);
1397 break;
1398 }
1399 }
1400
1401 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1402 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1403 const struct rtw89_reg2_def *reg,
1404 enum rtw89_rf_path rf_path,
1405 struct rtw89_fw_h2c_rf_reg_info *info)
1406 {
1407 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1408 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1409
1410 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1411 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1412 rf_path, info->curr_idx);
1413 return;
1414 }
1415
1416 info->rtw89_phy_config_rf_h2c[page][idx] =
1417 cpu_to_le32((reg->addr << 20) | reg->data);
1418 info->curr_idx++;
1419 }
1420
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1421 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1422 struct rtw89_fw_h2c_rf_reg_info *info)
1423 {
1424 u16 remain = info->curr_idx;
1425 u16 len = 0;
1426 u8 i;
1427 int ret = 0;
1428
1429 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1430 rtw89_warn(rtwdev,
1431 "rf reg h2c total len %d larger than %d\n",
1432 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1433 ret = -EINVAL;
1434 goto out;
1435 }
1436
1437 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1438 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1439 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1440 if (ret)
1441 goto out;
1442 }
1443 out:
1444 info->curr_idx = 0;
1445
1446 return ret;
1447 }
1448
rtw89_phy_config_rf_reg_noio(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1449 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1450 const struct rtw89_reg2_def *reg,
1451 enum rtw89_rf_path rf_path,
1452 void *extra_data)
1453 {
1454 u32 addr = reg->addr;
1455
1456 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1457 addr == 0xfa || addr == 0xf9)
1458 return;
1459
1460 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1461 return;
1462
1463 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1464 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1465 }
1466
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1467 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1468 const struct rtw89_reg2_def *reg,
1469 enum rtw89_rf_path rf_path,
1470 void *extra_data)
1471 {
1472 if (reg->addr == 0xfe) {
1473 mdelay(50);
1474 } else if (reg->addr == 0xfd) {
1475 mdelay(5);
1476 } else if (reg->addr == 0xfc) {
1477 mdelay(1);
1478 } else if (reg->addr == 0xfb) {
1479 udelay(50);
1480 } else if (reg->addr == 0xfa) {
1481 udelay(5);
1482 } else if (reg->addr == 0xf9) {
1483 udelay(1);
1484 } else {
1485 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1486 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1487 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1488 }
1489 }
1490
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1491 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1492 const struct rtw89_reg2_def *reg,
1493 enum rtw89_rf_path rf_path,
1494 void *extra_data)
1495 {
1496 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1497
1498 if (reg->addr < 0x100)
1499 return;
1500
1501 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1502 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1503 }
1504 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1505
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1506 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1507 const struct rtw89_phy_table *table,
1508 u32 *headline_size, u32 *headline_idx,
1509 u8 rfe, u8 cv)
1510 {
1511 const struct rtw89_reg2_def *reg;
1512 u32 headline;
1513 u32 compare, target;
1514 u8 rfe_para, cv_para;
1515 u8 cv_max = 0;
1516 bool case_matched = false;
1517 u32 i;
1518
1519 for (i = 0; i < table->n_regs; i++) {
1520 reg = &table->regs[i];
1521 headline = get_phy_headline(reg->addr);
1522 if (headline != PHY_HEADLINE_VALID)
1523 break;
1524 }
1525 *headline_size = i;
1526 if (*headline_size == 0)
1527 return 0;
1528
1529 /* case 1: RFE match, CV match */
1530 compare = get_phy_compare(rfe, cv);
1531 for (i = 0; i < *headline_size; i++) {
1532 reg = &table->regs[i];
1533 target = get_phy_target(reg->addr);
1534 if (target == compare) {
1535 *headline_idx = i;
1536 return 0;
1537 }
1538 }
1539
1540 /* case 2: RFE match, CV don't care */
1541 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1542 for (i = 0; i < *headline_size; i++) {
1543 reg = &table->regs[i];
1544 target = get_phy_target(reg->addr);
1545 if (target == compare) {
1546 *headline_idx = i;
1547 return 0;
1548 }
1549 }
1550
1551 /* case 3: RFE match, CV max in table */
1552 for (i = 0; i < *headline_size; i++) {
1553 reg = &table->regs[i];
1554 rfe_para = get_phy_cond_rfe(reg->addr);
1555 cv_para = get_phy_cond_cv(reg->addr);
1556 if (rfe_para == rfe) {
1557 if (cv_para >= cv_max) {
1558 cv_max = cv_para;
1559 *headline_idx = i;
1560 case_matched = true;
1561 }
1562 }
1563 }
1564
1565 if (case_matched)
1566 return 0;
1567
1568 /* case 4: RFE don't care, CV max in table */
1569 for (i = 0; i < *headline_size; i++) {
1570 reg = &table->regs[i];
1571 rfe_para = get_phy_cond_rfe(reg->addr);
1572 cv_para = get_phy_cond_cv(reg->addr);
1573 if (rfe_para == PHY_COND_DONT_CARE) {
1574 if (cv_para >= cv_max) {
1575 cv_max = cv_para;
1576 *headline_idx = i;
1577 case_matched = true;
1578 }
1579 }
1580 }
1581
1582 if (case_matched)
1583 return 0;
1584
1585 return -EINVAL;
1586 }
1587
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1588 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1589 const struct rtw89_phy_table *table,
1590 void (*config)(struct rtw89_dev *rtwdev,
1591 const struct rtw89_reg2_def *reg,
1592 enum rtw89_rf_path rf_path,
1593 void *data),
1594 void *extra_data)
1595 {
1596 const struct rtw89_reg2_def *reg;
1597 enum rtw89_rf_path rf_path = table->rf_path;
1598 u8 rfe = rtwdev->efuse.rfe_type;
1599 u8 cv = rtwdev->hal.cv;
1600 u32 i;
1601 u32 headline_size = 0, headline_idx = 0;
1602 u32 target = 0, cfg_target;
1603 u8 cond;
1604 bool is_matched = true;
1605 bool target_found = false;
1606 int ret;
1607
1608 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1609 &headline_idx, rfe, cv);
1610 if (ret) {
1611 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1612 return;
1613 }
1614
1615 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1616 for (i = headline_size; i < table->n_regs; i++) {
1617 reg = &table->regs[i];
1618 cond = get_phy_cond(reg->addr);
1619 switch (cond) {
1620 case PHY_COND_BRANCH_IF:
1621 case PHY_COND_BRANCH_ELIF:
1622 target = get_phy_target(reg->addr);
1623 break;
1624 case PHY_COND_BRANCH_ELSE:
1625 is_matched = false;
1626 if (!target_found) {
1627 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1628 reg->addr, reg->data);
1629 return;
1630 }
1631 break;
1632 case PHY_COND_BRANCH_END:
1633 is_matched = true;
1634 target_found = false;
1635 break;
1636 case PHY_COND_CHECK:
1637 if (target_found) {
1638 is_matched = false;
1639 break;
1640 }
1641
1642 if (target == cfg_target) {
1643 is_matched = true;
1644 target_found = true;
1645 } else {
1646 is_matched = false;
1647 target_found = false;
1648 }
1649 break;
1650 default:
1651 if (is_matched)
1652 config(rtwdev, reg, rf_path, extra_data);
1653 break;
1654 }
1655 }
1656 }
1657
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1658 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1659 {
1660 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1661 const struct rtw89_chip_info *chip = rtwdev->chip;
1662 const struct rtw89_phy_table *bb_table;
1663 const struct rtw89_phy_table *bb_gain_table;
1664
1665 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1666 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1667 if (rtwdev->dbcc_en)
1668 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1669 (void *)RTW89_PHY_1);
1670 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
1671
1672 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1673 if (bb_gain_table)
1674 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1675 chip->phy_def->config_bb_gain, NULL);
1676 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1677 }
1678
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1679 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1680 {
1681 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1682 udelay(1);
1683 return rtw89_phy_read32(rtwdev, 0x8080);
1684 }
1685
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev,bool noio)1686 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1687 {
1688 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1689 enum rtw89_rf_path rf_path, void *data);
1690 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1691 const struct rtw89_chip_info *chip = rtwdev->chip;
1692 const struct rtw89_phy_table *rf_table;
1693 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1694 u8 path;
1695
1696 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1697 if (!rf_reg_info)
1698 return;
1699
1700 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1701 rf_table = elm_info->rf_radio[path] ?
1702 elm_info->rf_radio[path] : chip->rf_table[path];
1703 rf_reg_info->rf_path = rf_table->rf_path;
1704 if (noio)
1705 config = rtw89_phy_config_rf_reg_noio;
1706 else
1707 config = rf_table->config ? rf_table->config :
1708 rtw89_phy_config_rf_reg;
1709 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1710 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1711 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1712 rf_reg_info->rf_path);
1713 }
1714 kfree(rf_reg_info);
1715 }
1716
rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev * rtwdev)1717 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
1718 {
1719 const struct rtw89_chip_info *chip = rtwdev->chip;
1720 u32 val;
1721 int ret;
1722
1723 /* IQK/DPK clock & reset */
1724 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
1725 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
1726 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
1727 if (chip->chip_id != RTL8851B)
1728 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
1729 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
1730 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
1731
1732 /* check 0x8080 */
1733 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
1734
1735 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1736 1000, false, rtwdev);
1737 if (ret)
1738 rtw89_err(rtwdev, "failed to poll nctl block\n");
1739 }
1740
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1741 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1742 {
1743 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1744 const struct rtw89_chip_info *chip = rtwdev->chip;
1745 const struct rtw89_phy_table *nctl_table;
1746
1747 rtw89_phy_preinit_rf_nctl(rtwdev);
1748
1749 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
1750 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1751
1752 if (chip->nctl_post_table)
1753 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1754 }
1755
rtw89_phy0_phy1_offset_ax(struct rtw89_dev * rtwdev,u32 addr)1756 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
1757 {
1758 u32 phy_page = addr >> 8;
1759 u32 ofst = 0;
1760
1761 switch (phy_page) {
1762 case 0x6:
1763 case 0x7:
1764 case 0x8:
1765 case 0x9:
1766 case 0xa:
1767 case 0xb:
1768 case 0xc:
1769 case 0xd:
1770 case 0x19:
1771 case 0x1a:
1772 case 0x1b:
1773 ofst = 0x2000;
1774 break;
1775 default:
1776 /* warning case */
1777 ofst = 0;
1778 break;
1779 }
1780
1781 if (phy_page >= 0x40 && phy_page <= 0x4f)
1782 ofst = 0x2000;
1783
1784 return ofst;
1785 }
1786
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1787 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1788 u32 data, enum rtw89_phy_idx phy_idx)
1789 {
1790 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1791 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1792 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1793 }
1794 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1795
rtw89_phy_read32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,enum rtw89_phy_idx phy_idx)1796 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1797 enum rtw89_phy_idx phy_idx)
1798 {
1799 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1800 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1801 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1802 }
1803 EXPORT_SYMBOL(rtw89_phy_read32_idx);
1804
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1805 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1806 u32 val)
1807 {
1808 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1809
1810 if (!rtwdev->dbcc_en)
1811 return;
1812
1813 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1814 }
1815 EXPORT_SYMBOL(rtw89_phy_set_phy_regs);
1816
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1817 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1818 const struct rtw89_phy_reg3_tbl *tbl)
1819 {
1820 const struct rtw89_reg3_def *reg3;
1821 int i;
1822
1823 for (i = 0; i < tbl->size; i++) {
1824 reg3 = &tbl->reg3[i];
1825 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1826 }
1827 }
1828 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1829
1830 static const u8 rtw89_rs_idx_num_ax[] = {
1831 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
1832 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
1833 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
1834 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
1835 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
1836 };
1837
1838 static const u8 rtw89_rs_nss_num_ax[] = {
1839 [RTW89_RS_CCK] = 1,
1840 [RTW89_RS_OFDM] = 1,
1841 [RTW89_RS_MCS] = RTW89_NSS_NUM,
1842 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
1843 [RTW89_RS_OFFSET] = 1,
1844 };
1845
rtw89_phy_raw_byr_seek(struct rtw89_dev * rtwdev,struct rtw89_txpwr_byrate * head,const struct rtw89_rate_desc * desc)1846 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
1847 struct rtw89_txpwr_byrate *head,
1848 const struct rtw89_rate_desc *desc)
1849 {
1850 switch (desc->rs) {
1851 case RTW89_RS_CCK:
1852 return &head->cck[desc->idx];
1853 case RTW89_RS_OFDM:
1854 return &head->ofdm[desc->idx];
1855 case RTW89_RS_MCS:
1856 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
1857 case RTW89_RS_HEDCM:
1858 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
1859 case RTW89_RS_OFFSET:
1860 return &head->offset[desc->idx];
1861 default:
1862 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
1863 return &head->trap;
1864 }
1865 }
1866
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)1867 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
1868 const struct rtw89_txpwr_table *tbl)
1869 {
1870 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
1871 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
1872 struct rtw89_txpwr_byrate *byr_head;
1873 struct rtw89_rate_desc desc = {};
1874 s8 *byr;
1875 u32 data;
1876 u8 i;
1877
1878 for (; cfg < end; cfg++) {
1879 byr_head = &rtwdev->byr[cfg->band][0];
1880 desc.rs = cfg->rs;
1881 desc.nss = cfg->nss;
1882 data = cfg->data;
1883
1884 for (i = 0; i < cfg->len; i++, data >>= 8) {
1885 desc.idx = cfg->shf + i;
1886 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
1887 *byr = data & 0xff;
1888 }
1889 }
1890 }
1891 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
1892
rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev * rtwdev,s8 txpwr_rf)1893 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
1894 {
1895 const struct rtw89_chip_info *chip = rtwdev->chip;
1896
1897 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
1898 }
1899
rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev * rtwdev,s8 dbm)1900 static s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm)
1901 {
1902 const struct rtw89_chip_info *chip = rtwdev->chip;
1903
1904 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63);
1905 }
1906
rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)1907 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
1908 {
1909 const u8 tssi_deviation_point = 0;
1910 const u8 tssi_max_deviation = 2;
1911
1912 if (dbm <= tssi_deviation_point)
1913 dbm -= tssi_max_deviation;
1914
1915 return dbm;
1916 }
1917
rtw89_phy_get_tpe_constraint(struct rtw89_dev * rtwdev,u8 band)1918 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
1919 {
1920 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
1921 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
1922 s8 cstr = S8_MAX;
1923
1924 if (band == RTW89_BAND_6G && tpe->valid)
1925 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
1926
1927 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
1928 }
1929
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,u8 bw,const struct rtw89_rate_desc * rate_desc)1930 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
1931 const struct rtw89_rate_desc *rate_desc)
1932 {
1933 struct rtw89_txpwr_byrate *byr_head;
1934 s8 *byr;
1935
1936 if (rate_desc->rs == RTW89_RS_CCK)
1937 band = RTW89_BAND_2G;
1938
1939 byr_head = &rtwdev->byr[band][bw];
1940 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
1941
1942 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
1943 }
1944
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)1945 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
1946 {
1947 switch (channel_6g) {
1948 case 1 ... 29:
1949 return (channel_6g - 1) / 2;
1950 case 33 ... 61:
1951 return (channel_6g - 3) / 2;
1952 case 65 ... 93:
1953 return (channel_6g - 5) / 2;
1954 case 97 ... 125:
1955 return (channel_6g - 7) / 2;
1956 case 129 ... 157:
1957 return (channel_6g - 9) / 2;
1958 case 161 ... 189:
1959 return (channel_6g - 11) / 2;
1960 case 193 ... 221:
1961 return (channel_6g - 13) / 2;
1962 case 225 ... 253:
1963 return (channel_6g - 15) / 2;
1964 default:
1965 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
1966 return 0;
1967 }
1968 }
1969
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)1970 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
1971 {
1972 if (band == RTW89_BAND_6G)
1973 return rtw89_channel_6g_to_idx(rtwdev, channel);
1974
1975 switch (channel) {
1976 case 1 ... 14:
1977 return channel - 1;
1978 case 36 ... 64:
1979 return (channel - 36) / 2;
1980 case 100 ... 144:
1981 return ((channel - 100) / 2) + 15;
1982 case 149 ... 177:
1983 return ((channel - 149) / 2) + 38;
1984 default:
1985 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
1986 return 0;
1987 }
1988 }
1989
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)1990 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
1991 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
1992 {
1993 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1994 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
1995 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
1996 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
1997 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
1998 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
1999 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2000 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2001 u8 regd = rtw89_regd_get(rtwdev, band);
2002 u8 reg6 = regulatory->reg_6ghz_power;
2003 s8 lmt = 0, sar;
2004 s8 cstr;
2005
2006 switch (band) {
2007 case RTW89_BAND_2G:
2008 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2009 if (lmt)
2010 break;
2011
2012 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2013 break;
2014 case RTW89_BAND_5G:
2015 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2016 if (lmt)
2017 break;
2018
2019 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2020 break;
2021 case RTW89_BAND_6G:
2022 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2023 if (lmt)
2024 break;
2025
2026 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2027 [RTW89_REG_6GHZ_POWER_DFLT]
2028 [ch_idx];
2029 break;
2030 default:
2031 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2032 return 0;
2033 }
2034
2035 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt);
2036 sar = rtw89_query_sar(rtwdev, freq);
2037 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2038
2039 return min3(lmt, sar, cstr);
2040 }
2041 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
2042
2043 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2044 do { \
2045 u8 __i; \
2046 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
2047 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2048 band, \
2049 bw, ntx, \
2050 rs, __i, \
2051 (ch)); \
2052 } while (0)
2053
rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch)2054 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2055 struct rtw89_txpwr_limit_ax *lmt,
2056 u8 band, u8 ntx, u8 ch)
2057 {
2058 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2059 ntx, RTW89_RS_CCK, ch);
2060 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2061 ntx, RTW89_RS_CCK, ch);
2062 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2063 ntx, RTW89_RS_OFDM, ch);
2064 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2065 RTW89_CHANNEL_WIDTH_20,
2066 ntx, RTW89_RS_MCS, ch);
2067 }
2068
rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2069 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2070 struct rtw89_txpwr_limit_ax *lmt,
2071 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2072 {
2073 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2074 ntx, RTW89_RS_CCK, ch - 2);
2075 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2076 ntx, RTW89_RS_CCK, ch);
2077 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2078 ntx, RTW89_RS_OFDM, pri_ch);
2079 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2080 RTW89_CHANNEL_WIDTH_20,
2081 ntx, RTW89_RS_MCS, ch - 2);
2082 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2083 RTW89_CHANNEL_WIDTH_20,
2084 ntx, RTW89_RS_MCS, ch + 2);
2085 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2086 RTW89_CHANNEL_WIDTH_40,
2087 ntx, RTW89_RS_MCS, ch);
2088 }
2089
rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2090 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2091 struct rtw89_txpwr_limit_ax *lmt,
2092 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2093 {
2094 s8 val_0p5_n[RTW89_BF_NUM];
2095 s8 val_0p5_p[RTW89_BF_NUM];
2096 u8 i;
2097
2098 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2099 ntx, RTW89_RS_OFDM, pri_ch);
2100 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2101 RTW89_CHANNEL_WIDTH_20,
2102 ntx, RTW89_RS_MCS, ch - 6);
2103 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2104 RTW89_CHANNEL_WIDTH_20,
2105 ntx, RTW89_RS_MCS, ch - 2);
2106 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2107 RTW89_CHANNEL_WIDTH_20,
2108 ntx, RTW89_RS_MCS, ch + 2);
2109 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2110 RTW89_CHANNEL_WIDTH_20,
2111 ntx, RTW89_RS_MCS, ch + 6);
2112 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2113 RTW89_CHANNEL_WIDTH_40,
2114 ntx, RTW89_RS_MCS, ch - 4);
2115 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2116 RTW89_CHANNEL_WIDTH_40,
2117 ntx, RTW89_RS_MCS, ch + 4);
2118 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2119 RTW89_CHANNEL_WIDTH_80,
2120 ntx, RTW89_RS_MCS, ch);
2121
2122 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2123 ntx, RTW89_RS_MCS, ch - 4);
2124 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2125 ntx, RTW89_RS_MCS, ch + 4);
2126
2127 for (i = 0; i < RTW89_BF_NUM; i++)
2128 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2129 }
2130
rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2131 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2132 struct rtw89_txpwr_limit_ax *lmt,
2133 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2134 {
2135 s8 val_0p5_n[RTW89_BF_NUM];
2136 s8 val_0p5_p[RTW89_BF_NUM];
2137 s8 val_2p5_n[RTW89_BF_NUM];
2138 s8 val_2p5_p[RTW89_BF_NUM];
2139 u8 i;
2140
2141 /* fill ofdm section */
2142 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2143 ntx, RTW89_RS_OFDM, pri_ch);
2144
2145 /* fill mcs 20m section */
2146 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2147 RTW89_CHANNEL_WIDTH_20,
2148 ntx, RTW89_RS_MCS, ch - 14);
2149 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2150 RTW89_CHANNEL_WIDTH_20,
2151 ntx, RTW89_RS_MCS, ch - 10);
2152 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2153 RTW89_CHANNEL_WIDTH_20,
2154 ntx, RTW89_RS_MCS, ch - 6);
2155 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2156 RTW89_CHANNEL_WIDTH_20,
2157 ntx, RTW89_RS_MCS, ch - 2);
2158 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2159 RTW89_CHANNEL_WIDTH_20,
2160 ntx, RTW89_RS_MCS, ch + 2);
2161 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2162 RTW89_CHANNEL_WIDTH_20,
2163 ntx, RTW89_RS_MCS, ch + 6);
2164 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2165 RTW89_CHANNEL_WIDTH_20,
2166 ntx, RTW89_RS_MCS, ch + 10);
2167 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2168 RTW89_CHANNEL_WIDTH_20,
2169 ntx, RTW89_RS_MCS, ch + 14);
2170
2171 /* fill mcs 40m section */
2172 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2173 RTW89_CHANNEL_WIDTH_40,
2174 ntx, RTW89_RS_MCS, ch - 12);
2175 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2176 RTW89_CHANNEL_WIDTH_40,
2177 ntx, RTW89_RS_MCS, ch - 4);
2178 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2179 RTW89_CHANNEL_WIDTH_40,
2180 ntx, RTW89_RS_MCS, ch + 4);
2181 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2182 RTW89_CHANNEL_WIDTH_40,
2183 ntx, RTW89_RS_MCS, ch + 12);
2184
2185 /* fill mcs 80m section */
2186 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2187 RTW89_CHANNEL_WIDTH_80,
2188 ntx, RTW89_RS_MCS, ch - 8);
2189 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2190 RTW89_CHANNEL_WIDTH_80,
2191 ntx, RTW89_RS_MCS, ch + 8);
2192
2193 /* fill mcs 160m section */
2194 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2195 RTW89_CHANNEL_WIDTH_160,
2196 ntx, RTW89_RS_MCS, ch);
2197
2198 /* fill mcs 40m 0p5 section */
2199 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2200 ntx, RTW89_RS_MCS, ch - 4);
2201 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2202 ntx, RTW89_RS_MCS, ch + 4);
2203
2204 for (i = 0; i < RTW89_BF_NUM; i++)
2205 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2206
2207 /* fill mcs 40m 2p5 section */
2208 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2209 ntx, RTW89_RS_MCS, ch - 8);
2210 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2211 ntx, RTW89_RS_MCS, ch + 8);
2212
2213 for (i = 0; i < RTW89_BF_NUM; i++)
2214 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2215 }
2216
2217 static
rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ax * lmt,u8 ntx)2218 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2219 const struct rtw89_chan *chan,
2220 struct rtw89_txpwr_limit_ax *lmt,
2221 u8 ntx)
2222 {
2223 u8 band = chan->band_type;
2224 u8 pri_ch = chan->primary_channel;
2225 u8 ch = chan->channel;
2226 u8 bw = chan->band_width;
2227
2228 memset(lmt, 0, sizeof(*lmt));
2229
2230 switch (bw) {
2231 case RTW89_CHANNEL_WIDTH_20:
2232 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2233 break;
2234 case RTW89_CHANNEL_WIDTH_40:
2235 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2236 pri_ch);
2237 break;
2238 case RTW89_CHANNEL_WIDTH_80:
2239 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2240 pri_ch);
2241 break;
2242 case RTW89_CHANNEL_WIDTH_160:
2243 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2244 pri_ch);
2245 break;
2246 }
2247 }
2248
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)2249 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2250 u8 ru, u8 ntx, u8 ch)
2251 {
2252 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2253 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2254 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2255 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2256 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2257 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2258 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2259 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2260 u8 regd = rtw89_regd_get(rtwdev, band);
2261 u8 reg6 = regulatory->reg_6ghz_power;
2262 s8 lmt_ru = 0, sar;
2263 s8 cstr;
2264
2265 switch (band) {
2266 case RTW89_BAND_2G:
2267 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2268 if (lmt_ru)
2269 break;
2270
2271 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2272 break;
2273 case RTW89_BAND_5G:
2274 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2275 if (lmt_ru)
2276 break;
2277
2278 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2279 break;
2280 case RTW89_BAND_6G:
2281 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2282 if (lmt_ru)
2283 break;
2284
2285 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2286 [RTW89_REG_6GHZ_POWER_DFLT]
2287 [ch_idx];
2288 break;
2289 default:
2290 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2291 return 0;
2292 }
2293
2294 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru);
2295 sar = rtw89_query_sar(rtwdev, freq);
2296 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2297
2298 return min3(lmt_ru, sar, cstr);
2299 }
2300
2301 static void
rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2302 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2303 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2304 u8 band, u8 ntx, u8 ch)
2305 {
2306 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2307 RTW89_RU26,
2308 ntx, ch);
2309 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2310 RTW89_RU52,
2311 ntx, ch);
2312 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2313 RTW89_RU106,
2314 ntx, ch);
2315 }
2316
2317 static void
rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2318 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2319 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2320 u8 band, u8 ntx, u8 ch)
2321 {
2322 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2323 RTW89_RU26,
2324 ntx, ch - 2);
2325 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2326 RTW89_RU26,
2327 ntx, ch + 2);
2328 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2329 RTW89_RU52,
2330 ntx, ch - 2);
2331 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2332 RTW89_RU52,
2333 ntx, ch + 2);
2334 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2335 RTW89_RU106,
2336 ntx, ch - 2);
2337 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2338 RTW89_RU106,
2339 ntx, ch + 2);
2340 }
2341
2342 static void
rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2343 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2344 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2345 u8 band, u8 ntx, u8 ch)
2346 {
2347 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2348 RTW89_RU26,
2349 ntx, ch - 6);
2350 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2351 RTW89_RU26,
2352 ntx, ch - 2);
2353 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2354 RTW89_RU26,
2355 ntx, ch + 2);
2356 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2357 RTW89_RU26,
2358 ntx, ch + 6);
2359 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2360 RTW89_RU52,
2361 ntx, ch - 6);
2362 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2363 RTW89_RU52,
2364 ntx, ch - 2);
2365 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2366 RTW89_RU52,
2367 ntx, ch + 2);
2368 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2369 RTW89_RU52,
2370 ntx, ch + 6);
2371 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2372 RTW89_RU106,
2373 ntx, ch - 6);
2374 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2375 RTW89_RU106,
2376 ntx, ch - 2);
2377 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2378 RTW89_RU106,
2379 ntx, ch + 2);
2380 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2381 RTW89_RU106,
2382 ntx, ch + 6);
2383 }
2384
2385 static void
rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2386 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2387 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2388 u8 band, u8 ntx, u8 ch)
2389 {
2390 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2391 int i;
2392
2393 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2394 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) {
2395 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2396 RTW89_RU26,
2397 ntx,
2398 ch + ofst[i]);
2399 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2400 RTW89_RU52,
2401 ntx,
2402 ch + ofst[i]);
2403 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2404 RTW89_RU106,
2405 ntx,
2406 ch + ofst[i]);
2407 }
2408 }
2409
2410 static
rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 ntx)2411 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2412 const struct rtw89_chan *chan,
2413 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2414 u8 ntx)
2415 {
2416 u8 band = chan->band_type;
2417 u8 ch = chan->channel;
2418 u8 bw = chan->band_width;
2419
2420 memset(lmt_ru, 0, sizeof(*lmt_ru));
2421
2422 switch (bw) {
2423 case RTW89_CHANNEL_WIDTH_20:
2424 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2425 ch);
2426 break;
2427 case RTW89_CHANNEL_WIDTH_40:
2428 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2429 ch);
2430 break;
2431 case RTW89_CHANNEL_WIDTH_80:
2432 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2433 ch);
2434 break;
2435 case RTW89_CHANNEL_WIDTH_160:
2436 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2437 ch);
2438 break;
2439 }
2440 }
2441
rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2442 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
2443 const struct rtw89_chan *chan,
2444 enum rtw89_phy_idx phy_idx)
2445 {
2446 u8 max_nss_num = rtwdev->chip->rf_path_num;
2447 static const u8 rs[] = {
2448 RTW89_RS_CCK,
2449 RTW89_RS_OFDM,
2450 RTW89_RS_MCS,
2451 RTW89_RS_HEDCM,
2452 };
2453 struct rtw89_rate_desc cur = {};
2454 u8 band = chan->band_type;
2455 u8 ch = chan->channel;
2456 u32 addr, val;
2457 s8 v[4] = {};
2458 u8 i;
2459
2460 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2461 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
2462
2463 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
2464 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
2465 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
2466 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
2467
2468 addr = R_AX_PWR_BY_RATE;
2469 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
2470 for (i = 0; i < ARRAY_SIZE(rs); i++) {
2471 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
2472 continue;
2473
2474 cur.rs = rs[i];
2475 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
2476 cur.idx++) {
2477 v[cur.idx % 4] =
2478 rtw89_phy_read_txpwr_byrate(rtwdev,
2479 band, 0,
2480 &cur);
2481
2482 if ((cur.idx + 1) % 4)
2483 continue;
2484
2485 val = FIELD_PREP(GENMASK(7, 0), v[0]) |
2486 FIELD_PREP(GENMASK(15, 8), v[1]) |
2487 FIELD_PREP(GENMASK(23, 16), v[2]) |
2488 FIELD_PREP(GENMASK(31, 24), v[3]);
2489
2490 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2491 val);
2492 addr += 4;
2493 }
2494 }
2495 }
2496 }
2497
2498 static
rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2499 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
2500 const struct rtw89_chan *chan,
2501 enum rtw89_phy_idx phy_idx)
2502 {
2503 struct rtw89_rate_desc desc = {
2504 .nss = RTW89_NSS_1,
2505 .rs = RTW89_RS_OFFSET,
2506 };
2507 u8 band = chan->band_type;
2508 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
2509 u32 val;
2510
2511 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2512
2513 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++)
2514 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2515
2516 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5);
2517 val = FIELD_PREP(GENMASK(3, 0), v[0]) |
2518 FIELD_PREP(GENMASK(7, 4), v[1]) |
2519 FIELD_PREP(GENMASK(11, 8), v[2]) |
2520 FIELD_PREP(GENMASK(15, 12), v[3]) |
2521 FIELD_PREP(GENMASK(19, 16), v[4]);
2522
2523 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2524 GENMASK(19, 0), val);
2525 }
2526
rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2527 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2528 const struct rtw89_chan *chan,
2529 enum rtw89_phy_idx phy_idx)
2530 {
2531 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2532 struct rtw89_txpwr_limit_ax lmt;
2533 u8 ch = chan->channel;
2534 u8 bw = chan->band_width;
2535 const s8 *ptr;
2536 u32 addr, val;
2537 u8 i, j;
2538
2539 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2540 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
2541
2542 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) !=
2543 RTW89_TXPWR_LMT_PAGE_SIZE_AX);
2544
2545 addr = R_AX_PWR_LMT;
2546 for (i = 0; i < max_ntx_num; i++) {
2547 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
2548
2549 ptr = (s8 *)&lmt;
2550 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX;
2551 j += 4, addr += 4, ptr += 4) {
2552 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2553 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2554 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2555 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2556
2557 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2558 }
2559 }
2560 }
2561
rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2562 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2563 const struct rtw89_chan *chan,
2564 enum rtw89_phy_idx phy_idx)
2565 {
2566 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2567 struct rtw89_txpwr_limit_ru_ax lmt_ru;
2568 u8 ch = chan->channel;
2569 u8 bw = chan->band_width;
2570 const s8 *ptr;
2571 u32 addr, val;
2572 u8 i, j;
2573
2574 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2575 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
2576
2577 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) !=
2578 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX);
2579
2580 addr = R_AX_PWR_RU_LMT;
2581 for (i = 0; i < max_ntx_num; i++) {
2582 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
2583
2584 ptr = (s8 *)&lmt_ru;
2585 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX;
2586 j += 4, addr += 4, ptr += 4) {
2587 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2588 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2589 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2590 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2591
2592 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2593 }
2594 }
2595 }
2596
2597 struct rtw89_phy_iter_ra_data {
2598 struct rtw89_dev *rtwdev;
2599 struct sk_buff *c2h;
2600 };
2601
__rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,struct rtw89_phy_iter_ra_data * ra_data)2602 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
2603 struct ieee80211_link_sta *link_sta,
2604 struct rtw89_phy_iter_ra_data *ra_data)
2605 {
2606 struct rtw89_dev *rtwdev = ra_data->rtwdev;
2607 const struct rtw89_c2h_ra_rpt *c2h =
2608 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
2609 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
2610 const struct rtw89_chip_info *chip = rtwdev->chip;
2611 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
2612 u8 mode, rate, bw, giltf, mac_id;
2613 u16 legacy_bitrate;
2614 bool valid;
2615 u8 mcs = 0;
2616 u8 t;
2617
2618 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
2619 if (mac_id != rtwsta_link->mac_id)
2620 return;
2621
2622 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
2623 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
2624 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
2625 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
2626
2627 if (format_v1) {
2628 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
2629 rate |= u8_encode_bits(t, BIT(7));
2630 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
2631 bw |= u8_encode_bits(t, BIT(2));
2632 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
2633 mode |= u8_encode_bits(t, BIT(2));
2634 }
2635
2636 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
2637 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
2638 if (!valid)
2639 return;
2640 }
2641
2642 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
2643
2644 switch (mode) {
2645 case RTW89_RA_RPT_MODE_LEGACY:
2646 ra_report->txrate.legacy = legacy_bitrate;
2647 break;
2648 case RTW89_RA_RPT_MODE_HT:
2649 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
2650 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2651 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
2652 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
2653 else
2654 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
2655 ra_report->txrate.mcs = rate;
2656 if (giltf)
2657 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2658 mcs = ra_report->txrate.mcs & 0x07;
2659 break;
2660 case RTW89_RA_RPT_MODE_VHT:
2661 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
2662 ra_report->txrate.mcs = format_v1 ?
2663 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2664 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2665 ra_report->txrate.nss = format_v1 ?
2666 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2667 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2668 if (giltf)
2669 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2670 mcs = ra_report->txrate.mcs;
2671 break;
2672 case RTW89_RA_RPT_MODE_HE:
2673 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
2674 ra_report->txrate.mcs = format_v1 ?
2675 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2676 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2677 ra_report->txrate.nss = format_v1 ?
2678 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2679 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2680 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2681 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
2682 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2683 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
2684 else
2685 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
2686 mcs = ra_report->txrate.mcs;
2687 break;
2688 case RTW89_RA_RPT_MODE_EHT:
2689 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
2690 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
2691 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
2692 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2693 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
2694 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2695 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
2696 else
2697 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
2698 mcs = ra_report->txrate.mcs;
2699 break;
2700 }
2701
2702 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
2703 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
2704 ra_report->hw_rate = format_v1 ?
2705 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
2706 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
2707 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
2708 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
2709 ra_report->might_fallback_legacy = mcs <= 2;
2710 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
2711 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
2712 }
2713
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)2714 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
2715 {
2716 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
2717 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2718 struct rtw89_sta_link *rtwsta_link;
2719 struct ieee80211_link_sta *link_sta;
2720 unsigned int link_id;
2721
2722 rcu_read_lock();
2723
2724 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
2725 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
2726 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
2727 }
2728
2729 rcu_read_unlock();
2730 }
2731
2732 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2733 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2734 {
2735 struct rtw89_phy_iter_ra_data ra_data;
2736
2737 ra_data.rtwdev = rtwdev;
2738 ra_data.c2h = c2h;
2739 ieee80211_iterate_stations_atomic(rtwdev->hw,
2740 rtw89_phy_c2h_ra_rpt_iter,
2741 &ra_data);
2742 }
2743
2744 static
2745 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
2746 struct sk_buff *c2h, u32 len) = {
2747 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
2748 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
2749 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
2750 };
2751
rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)2752 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
2753 enum rtw89_phy_c2h_rfk_log_func func,
2754 void *content, u16 len)
2755 {
2756 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk;
2757 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck;
2758 struct rtw89_c2h_rf_dack_rpt_log *dack;
2759 struct rtw89_c2h_rf_dpk_rpt_log *dpk;
2760
2761 switch (func) {
2762 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
2763 if (len != sizeof(*dpk))
2764 goto out;
2765
2766 dpk = content;
2767 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2768 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
2769 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
2770 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2771 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n",
2772 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
2773 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2774 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n",
2775 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
2776 return;
2777 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
2778 if (len != sizeof(*dack))
2779 goto out;
2780
2781 dack = content;
2782
2783 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ver=0x%x 0x%x\n",
2784 dack->fwdack_ver, dack->fwdack_rpt_ver);
2785 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
2786 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
2787 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
2788 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
2789 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
2790 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
2791 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
2792 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
2793
2794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
2795 dack->addck2_d[0][0][0], dack->addck2_d[0][0][1]);
2796 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
2797 dack->addck2_d[0][1][0], dack->addck2_d[0][1][1]);
2798 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
2799 dack->addck2_d[1][0][0], dack->addck2_d[1][0][1]);
2800 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
2801 dack->addck2_d[1][1][0], dack->addck2_d[1][1][1]);
2802
2803 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
2804 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
2805 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
2806 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
2807
2808 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
2809 dack->dadck_d[0][0], dack->dadck_d[0][1]);
2810 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
2811 dack->dadck_d[1][0], dack->dadck_d[1][1]);
2812
2813 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
2814 dack->biask_d[0][0]);
2815 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
2816 dack->biask_d[1][0]);
2817
2818 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic: %*ph\n",
2819 (int)sizeof(dack->msbk_d[0][0]), dack->msbk_d[0][0]);
2820 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc: %*ph\n",
2821 (int)sizeof(dack->msbk_d[0][1]), dack->msbk_d[0][1]);
2822 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic: %*ph\n",
2823 (int)sizeof(dack->msbk_d[1][0]), dack->msbk_d[1][0]);
2824 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc: %*ph\n",
2825 (int)sizeof(dack->msbk_d[1][1]), dack->msbk_d[1][1]);
2826 return;
2827 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
2828 if (len != sizeof(*rxdck))
2829 goto out;
2830
2831 rxdck = content;
2832 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2833 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
2834 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
2835 rxdck->timeout);
2836 return;
2837 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
2838 if (len != sizeof(*txgapk))
2839 goto out;
2840
2841 txgapk = content;
2842 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2843 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n",
2844 le32_to_cpu(txgapk->r0x8010[0]),
2845 le32_to_cpu(txgapk->r0x8010[1]));
2846 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
2847 txgapk->chk_id);
2848 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
2849 le32_to_cpu(txgapk->chk_cnt));
2850 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
2851 txgapk->ver);
2852 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n",
2853 txgapk->rsv1);
2854
2855 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
2856 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
2857 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
2858 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
2859 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
2860 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
2861 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
2862 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
2863 return;
2864 default:
2865 break;
2866 }
2867
2868 out:
2869 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2870 "unexpected RFK func %d report log with length %d\n", func, len);
2871 }
2872
rtw89_phy_c2h_rfk_run_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)2873 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
2874 enum rtw89_phy_c2h_rfk_log_func func,
2875 void *content, u16 len)
2876 {
2877 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
2878 const struct rtw89_c2h_rf_run_log *log = content;
2879 const struct rtw89_fw_element_hdr *elm;
2880 u32 fmt_idx;
2881 u16 offset;
2882
2883 if (sizeof(*log) != len)
2884 return false;
2885
2886 if (!elm_info->rfk_log_fmt)
2887 return false;
2888
2889 elm = elm_info->rfk_log_fmt->elm[func];
2890 fmt_idx = le32_to_cpu(log->fmt_idx);
2891 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
2892 return false;
2893
2894 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
2895 if (offset == 0)
2896 return false;
2897
2898 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
2899 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
2900 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
2901
2902 return true;
2903 }
2904
rtw89_phy_c2h_rfk_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len,enum rtw89_phy_c2h_rfk_log_func func,const char * rfk_name)2905 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
2906 u32 len, enum rtw89_phy_c2h_rfk_log_func func,
2907 const char *rfk_name)
2908 {
2909 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
2910 struct rtw89_c2h_rf_log_hdr *log_hdr;
2911 void *log_ptr = c2h_hdr;
2912 u16 content_len;
2913 u16 chunk_len;
2914 bool handled;
2915
2916 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK))
2917 return;
2918
2919 log_ptr += sizeof(*c2h_hdr);
2920 len -= sizeof(*c2h_hdr);
2921
2922 while (len > sizeof(*log_hdr)) {
2923 log_hdr = log_ptr;
2924 content_len = le16_to_cpu(log_hdr->len);
2925 chunk_len = content_len + sizeof(*log_hdr);
2926
2927 if (chunk_len > len)
2928 break;
2929
2930 switch (log_hdr->type) {
2931 case RTW89_RF_RUN_LOG:
2932 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
2933 log_hdr->content, content_len);
2934 if (handled)
2935 break;
2936
2937 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
2938 rfk_name, content_len, log_hdr->content);
2939 break;
2940 case RTW89_RF_RPT_LOG:
2941 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
2942 log_hdr->content, content_len);
2943 break;
2944 default:
2945 return;
2946 }
2947
2948 log_ptr += chunk_len;
2949 len -= chunk_len;
2950 }
2951 }
2952
2953 static void
rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2954 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2955 {
2956 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2957 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK");
2958 }
2959
2960 static void
rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2961 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2962 {
2963 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2964 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK");
2965 }
2966
2967 static void
rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2968 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2969 {
2970 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2971 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK");
2972 }
2973
2974 static void
rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2975 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2976 {
2977 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2978 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK");
2979 }
2980
2981 static void
rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2982 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2983 {
2984 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2985 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI");
2986 }
2987
2988 static void
rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2989 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2990 {
2991 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2992 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK");
2993 }
2994
2995 static
2996 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
2997 struct sk_buff *c2h, u32 len) = {
2998 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk,
2999 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk,
3000 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack,
3001 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck,
3002 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi,
3003 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk,
3004 };
3005
3006 static
rtw89_phy_rfk_report_prep(struct rtw89_dev * rtwdev)3007 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
3008 {
3009 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3010
3011 wait->state = RTW89_RFK_STATE_START;
3012 wait->start_time = ktime_get();
3013 reinit_completion(&wait->completion);
3014 }
3015
3016 static
rtw89_phy_rfk_report_wait(struct rtw89_dev * rtwdev,const char * rfk_name,unsigned int ms)3017 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
3018 unsigned int ms)
3019 {
3020 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3021 unsigned long time_left;
3022
3023 /* Since we can't receive C2H event during SER, use a fixed delay. */
3024 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3025 fsleep(1000 * ms / 2);
3026 goto out;
3027 }
3028
3029 time_left = wait_for_completion_timeout(&wait->completion,
3030 msecs_to_jiffies(ms));
3031 if (time_left == 0) {
3032 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
3033 return -ETIMEDOUT;
3034 } else if (wait->state != RTW89_RFK_STATE_OK) {
3035 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
3036 rfk_name, wait->state);
3037 return -EFAULT;
3038 }
3039
3040 out:
3041 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3042 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3043
3044 return 0;
3045 }
3046
3047 static void
rtw89_phy_c2h_rfk_report_state(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3048 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3049 {
3050 const struct rtw89_c2h_rfk_report *report =
3051 (const struct rtw89_c2h_rfk_report *)c2h->data;
3052 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3053
3054 wait->state = report->state;
3055 wait->version = report->version;
3056
3057 complete(&wait->completion);
3058
3059 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3060 "RFK report state %d with version %d (%*ph)\n",
3061 wait->state, wait->version,
3062 (int)(len - sizeof(report->hdr)), &report->state);
3063 }
3064
3065 static void
rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3066 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3067 {
3068 }
3069
3070 static
3071 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3072 struct sk_buff *c2h, u32 len) = {
3073 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state,
3074 [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr,
3075 };
3076
rtw89_phy_c2h_chk_atomic(struct rtw89_dev * rtwdev,u8 class,u8 func)3077 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
3078 {
3079 switch (class) {
3080 case RTW89_PHY_C2H_RFK_LOG:
3081 switch (func) {
3082 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3083 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3084 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3085 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3086 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3087 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3088 return true;
3089 default:
3090 return false;
3091 }
3092 case RTW89_PHY_C2H_RFK_REPORT:
3093 switch (func) {
3094 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE:
3095 return true;
3096 default:
3097 return false;
3098 }
3099 default:
3100 return false;
3101 }
3102 }
3103
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3104 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3105 u32 len, u8 class, u8 func)
3106 {
3107 void (*handler)(struct rtw89_dev *rtwdev,
3108 struct sk_buff *c2h, u32 len) = NULL;
3109
3110 switch (class) {
3111 case RTW89_PHY_C2H_CLASS_RA:
3112 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
3113 handler = rtw89_phy_c2h_ra_handler[func];
3114 break;
3115 case RTW89_PHY_C2H_RFK_LOG:
3116 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler))
3117 handler = rtw89_phy_c2h_rfk_log_handler[func];
3118 break;
3119 case RTW89_PHY_C2H_RFK_REPORT:
3120 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler))
3121 handler = rtw89_phy_c2h_rfk_report_handler[func];
3122 break;
3123 case RTW89_PHY_C2H_CLASS_DM:
3124 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY)
3125 return;
3126 fallthrough;
3127 default:
3128 rtw89_info(rtwdev, "PHY c2h class %d not support\n", class);
3129 return;
3130 }
3131 if (!handler) {
3132 rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class,
3133 func);
3134 return;
3135 }
3136 handler(rtwdev, skb, len);
3137 }
3138
rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,unsigned int ms)3139 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
3140 enum rtw89_phy_idx phy_idx,
3141 unsigned int ms)
3142 {
3143 int ret;
3144
3145 rtw89_phy_rfk_report_prep(rtwdev);
3146
3147 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3148 if (ret)
3149 return ret;
3150
3151 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3152 }
3153 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
3154
rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)3155 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
3156 enum rtw89_phy_idx phy_idx,
3157 const struct rtw89_chan *chan,
3158 enum rtw89_tssi_mode tssi_mode,
3159 unsigned int ms)
3160 {
3161 int ret;
3162
3163 rtw89_phy_rfk_report_prep(rtwdev);
3164
3165 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
3166 if (ret)
3167 return ret;
3168
3169 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
3170 }
3171 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait);
3172
rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3173 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
3174 enum rtw89_phy_idx phy_idx,
3175 const struct rtw89_chan *chan,
3176 unsigned int ms)
3177 {
3178 int ret;
3179
3180 rtw89_phy_rfk_report_prep(rtwdev);
3181
3182 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
3183 if (ret)
3184 return ret;
3185
3186 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
3187 }
3188 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait);
3189
rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3190 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
3191 enum rtw89_phy_idx phy_idx,
3192 const struct rtw89_chan *chan,
3193 unsigned int ms)
3194 {
3195 int ret;
3196
3197 rtw89_phy_rfk_report_prep(rtwdev);
3198
3199 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
3200 if (ret)
3201 return ret;
3202
3203 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
3204 }
3205 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait);
3206
rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3207 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
3208 enum rtw89_phy_idx phy_idx,
3209 const struct rtw89_chan *chan,
3210 unsigned int ms)
3211 {
3212 int ret;
3213
3214 rtw89_phy_rfk_report_prep(rtwdev);
3215
3216 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
3217 if (ret)
3218 return ret;
3219
3220 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
3221 }
3222 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait);
3223
rtw89_phy_rfk_dack_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3224 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
3225 enum rtw89_phy_idx phy_idx,
3226 const struct rtw89_chan *chan,
3227 unsigned int ms)
3228 {
3229 int ret;
3230
3231 rtw89_phy_rfk_report_prep(rtwdev);
3232
3233 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
3234 if (ret)
3235 return ret;
3236
3237 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
3238 }
3239 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait);
3240
rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3241 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
3242 enum rtw89_phy_idx phy_idx,
3243 const struct rtw89_chan *chan,
3244 unsigned int ms)
3245 {
3246 int ret;
3247
3248 rtw89_phy_rfk_report_prep(rtwdev);
3249
3250 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan);
3251 if (ret)
3252 return ret;
3253
3254 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
3255 }
3256 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait);
3257
phy_tssi_get_cck_group(u8 ch)3258 static u32 phy_tssi_get_cck_group(u8 ch)
3259 {
3260 switch (ch) {
3261 case 1 ... 2:
3262 return 0;
3263 case 3 ... 5:
3264 return 1;
3265 case 6 ... 8:
3266 return 2;
3267 case 9 ... 11:
3268 return 3;
3269 case 12 ... 13:
3270 return 4;
3271 case 14:
3272 return 5;
3273 }
3274
3275 return 0;
3276 }
3277
3278 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31)
3279 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx))
3280 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT)
3281 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \
3282 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT)
3283 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \
3284 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
3285
phy_tssi_get_ofdm_group(u8 ch)3286 static u32 phy_tssi_get_ofdm_group(u8 ch)
3287 {
3288 switch (ch) {
3289 case 1 ... 2:
3290 return 0;
3291 case 3 ... 5:
3292 return 1;
3293 case 6 ... 8:
3294 return 2;
3295 case 9 ... 11:
3296 return 3;
3297 case 12 ... 14:
3298 return 4;
3299 case 36 ... 40:
3300 return 5;
3301 case 41 ... 43:
3302 return PHY_TSSI_EXTRA_GROUP(5);
3303 case 44 ... 48:
3304 return 6;
3305 case 49 ... 51:
3306 return PHY_TSSI_EXTRA_GROUP(6);
3307 case 52 ... 56:
3308 return 7;
3309 case 57 ... 59:
3310 return PHY_TSSI_EXTRA_GROUP(7);
3311 case 60 ... 64:
3312 return 8;
3313 case 100 ... 104:
3314 return 9;
3315 case 105 ... 107:
3316 return PHY_TSSI_EXTRA_GROUP(9);
3317 case 108 ... 112:
3318 return 10;
3319 case 113 ... 115:
3320 return PHY_TSSI_EXTRA_GROUP(10);
3321 case 116 ... 120:
3322 return 11;
3323 case 121 ... 123:
3324 return PHY_TSSI_EXTRA_GROUP(11);
3325 case 124 ... 128:
3326 return 12;
3327 case 129 ... 131:
3328 return PHY_TSSI_EXTRA_GROUP(12);
3329 case 132 ... 136:
3330 return 13;
3331 case 137 ... 139:
3332 return PHY_TSSI_EXTRA_GROUP(13);
3333 case 140 ... 144:
3334 return 14;
3335 case 149 ... 153:
3336 return 15;
3337 case 154 ... 156:
3338 return PHY_TSSI_EXTRA_GROUP(15);
3339 case 157 ... 161:
3340 return 16;
3341 case 162 ... 164:
3342 return PHY_TSSI_EXTRA_GROUP(16);
3343 case 165 ... 169:
3344 return 17;
3345 case 170 ... 172:
3346 return PHY_TSSI_EXTRA_GROUP(17);
3347 case 173 ... 177:
3348 return 18;
3349 }
3350
3351 return 0;
3352 }
3353
phy_tssi_get_6g_ofdm_group(u8 ch)3354 static u32 phy_tssi_get_6g_ofdm_group(u8 ch)
3355 {
3356 switch (ch) {
3357 case 1 ... 5:
3358 return 0;
3359 case 6 ... 8:
3360 return PHY_TSSI_EXTRA_GROUP(0);
3361 case 9 ... 13:
3362 return 1;
3363 case 14 ... 16:
3364 return PHY_TSSI_EXTRA_GROUP(1);
3365 case 17 ... 21:
3366 return 2;
3367 case 22 ... 24:
3368 return PHY_TSSI_EXTRA_GROUP(2);
3369 case 25 ... 29:
3370 return 3;
3371 case 33 ... 37:
3372 return 4;
3373 case 38 ... 40:
3374 return PHY_TSSI_EXTRA_GROUP(4);
3375 case 41 ... 45:
3376 return 5;
3377 case 46 ... 48:
3378 return PHY_TSSI_EXTRA_GROUP(5);
3379 case 49 ... 53:
3380 return 6;
3381 case 54 ... 56:
3382 return PHY_TSSI_EXTRA_GROUP(6);
3383 case 57 ... 61:
3384 return 7;
3385 case 65 ... 69:
3386 return 8;
3387 case 70 ... 72:
3388 return PHY_TSSI_EXTRA_GROUP(8);
3389 case 73 ... 77:
3390 return 9;
3391 case 78 ... 80:
3392 return PHY_TSSI_EXTRA_GROUP(9);
3393 case 81 ... 85:
3394 return 10;
3395 case 86 ... 88:
3396 return PHY_TSSI_EXTRA_GROUP(10);
3397 case 89 ... 93:
3398 return 11;
3399 case 97 ... 101:
3400 return 12;
3401 case 102 ... 104:
3402 return PHY_TSSI_EXTRA_GROUP(12);
3403 case 105 ... 109:
3404 return 13;
3405 case 110 ... 112:
3406 return PHY_TSSI_EXTRA_GROUP(13);
3407 case 113 ... 117:
3408 return 14;
3409 case 118 ... 120:
3410 return PHY_TSSI_EXTRA_GROUP(14);
3411 case 121 ... 125:
3412 return 15;
3413 case 129 ... 133:
3414 return 16;
3415 case 134 ... 136:
3416 return PHY_TSSI_EXTRA_GROUP(16);
3417 case 137 ... 141:
3418 return 17;
3419 case 142 ... 144:
3420 return PHY_TSSI_EXTRA_GROUP(17);
3421 case 145 ... 149:
3422 return 18;
3423 case 150 ... 152:
3424 return PHY_TSSI_EXTRA_GROUP(18);
3425 case 153 ... 157:
3426 return 19;
3427 case 161 ... 165:
3428 return 20;
3429 case 166 ... 168:
3430 return PHY_TSSI_EXTRA_GROUP(20);
3431 case 169 ... 173:
3432 return 21;
3433 case 174 ... 176:
3434 return PHY_TSSI_EXTRA_GROUP(21);
3435 case 177 ... 181:
3436 return 22;
3437 case 182 ... 184:
3438 return PHY_TSSI_EXTRA_GROUP(22);
3439 case 185 ... 189:
3440 return 23;
3441 case 193 ... 197:
3442 return 24;
3443 case 198 ... 200:
3444 return PHY_TSSI_EXTRA_GROUP(24);
3445 case 201 ... 205:
3446 return 25;
3447 case 206 ... 208:
3448 return PHY_TSSI_EXTRA_GROUP(25);
3449 case 209 ... 213:
3450 return 26;
3451 case 214 ... 216:
3452 return PHY_TSSI_EXTRA_GROUP(26);
3453 case 217 ... 221:
3454 return 27;
3455 case 225 ... 229:
3456 return 28;
3457 case 230 ... 232:
3458 return PHY_TSSI_EXTRA_GROUP(28);
3459 case 233 ... 237:
3460 return 29;
3461 case 238 ... 240:
3462 return PHY_TSSI_EXTRA_GROUP(29);
3463 case 241 ... 245:
3464 return 30;
3465 case 246 ... 248:
3466 return PHY_TSSI_EXTRA_GROUP(30);
3467 case 249 ... 253:
3468 return 31;
3469 }
3470
3471 return 0;
3472 }
3473
phy_tssi_get_trim_group(u8 ch)3474 static u32 phy_tssi_get_trim_group(u8 ch)
3475 {
3476 switch (ch) {
3477 case 1 ... 8:
3478 return 0;
3479 case 9 ... 14:
3480 return 1;
3481 case 36 ... 48:
3482 return 2;
3483 case 49 ... 51:
3484 return PHY_TSSI_EXTRA_GROUP(2);
3485 case 52 ... 64:
3486 return 3;
3487 case 100 ... 112:
3488 return 4;
3489 case 113 ... 115:
3490 return PHY_TSSI_EXTRA_GROUP(4);
3491 case 116 ... 128:
3492 return 5;
3493 case 132 ... 144:
3494 return 6;
3495 case 149 ... 177:
3496 return 7;
3497 }
3498
3499 return 0;
3500 }
3501
phy_tssi_get_6g_trim_group(u8 ch)3502 static u32 phy_tssi_get_6g_trim_group(u8 ch)
3503 {
3504 switch (ch) {
3505 case 1 ... 13:
3506 return 0;
3507 case 14 ... 16:
3508 return PHY_TSSI_EXTRA_GROUP(0);
3509 case 17 ... 29:
3510 return 1;
3511 case 33 ... 45:
3512 return 2;
3513 case 46 ... 48:
3514 return PHY_TSSI_EXTRA_GROUP(2);
3515 case 49 ... 61:
3516 return 3;
3517 case 65 ... 77:
3518 return 4;
3519 case 78 ... 80:
3520 return PHY_TSSI_EXTRA_GROUP(4);
3521 case 81 ... 93:
3522 return 5;
3523 case 97 ... 109:
3524 return 6;
3525 case 110 ... 112:
3526 return PHY_TSSI_EXTRA_GROUP(6);
3527 case 113 ... 125:
3528 return 7;
3529 case 129 ... 141:
3530 return 8;
3531 case 142 ... 144:
3532 return PHY_TSSI_EXTRA_GROUP(8);
3533 case 145 ... 157:
3534 return 9;
3535 case 161 ... 173:
3536 return 10;
3537 case 174 ... 176:
3538 return PHY_TSSI_EXTRA_GROUP(10);
3539 case 177 ... 189:
3540 return 11;
3541 case 193 ... 205:
3542 return 12;
3543 case 206 ... 208:
3544 return PHY_TSSI_EXTRA_GROUP(12);
3545 case 209 ... 221:
3546 return 13;
3547 case 225 ... 237:
3548 return 14;
3549 case 238 ... 240:
3550 return PHY_TSSI_EXTRA_GROUP(14);
3551 case 241 ... 253:
3552 return 15;
3553 }
3554
3555 return 0;
3556 }
3557
phy_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)3558 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
3559 enum rtw89_phy_idx phy,
3560 const struct rtw89_chan *chan,
3561 enum rtw89_rf_path path)
3562 {
3563 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3564 enum rtw89_band band = chan->band_type;
3565 u8 ch = chan->channel;
3566 u32 gidx_1st;
3567 u32 gidx_2nd;
3568 s8 de_1st;
3569 s8 de_2nd;
3570 u32 gidx;
3571 s8 val;
3572
3573 if (band == RTW89_BAND_6G)
3574 goto calc_6g;
3575
3576 gidx = phy_tssi_get_ofdm_group(ch);
3577
3578 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3579 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3580 path, gidx);
3581
3582 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
3583 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
3584 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
3585 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3586 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3587 val = (de_1st + de_2nd) / 2;
3588
3589 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3590 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3591 path, val, de_1st, de_2nd);
3592 } else {
3593 val = tssi_info->tssi_mcs[path][gidx];
3594
3595 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3596 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3597 }
3598
3599 return val;
3600
3601 calc_6g:
3602 gidx = phy_tssi_get_6g_ofdm_group(ch);
3603
3604 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3605 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3606 path, gidx);
3607
3608 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
3609 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
3610 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
3611 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
3612 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
3613 val = (de_1st + de_2nd) / 2;
3614
3615 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3616 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3617 path, val, de_1st, de_2nd);
3618 } else {
3619 val = tssi_info->tssi_6g_mcs[path][gidx];
3620
3621 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3622 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3623 }
3624
3625 return val;
3626 }
3627
phy_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)3628 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
3629 enum rtw89_phy_idx phy,
3630 const struct rtw89_chan *chan,
3631 enum rtw89_rf_path path)
3632 {
3633 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3634 enum rtw89_band band = chan->band_type;
3635 u8 ch = chan->channel;
3636 u32 tgidx_1st;
3637 u32 tgidx_2nd;
3638 s8 tde_1st;
3639 s8 tde_2nd;
3640 u32 tgidx;
3641 s8 val;
3642
3643 if (band == RTW89_BAND_6G)
3644 goto calc_6g;
3645
3646 tgidx = phy_tssi_get_trim_group(ch);
3647
3648 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3649 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3650 path, tgidx);
3651
3652 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
3653 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
3654 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
3655 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3656 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3657 val = (tde_1st + tde_2nd) / 2;
3658
3659 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3660 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3661 path, val, tde_1st, tde_2nd);
3662 } else {
3663 val = tssi_info->tssi_trim[path][tgidx];
3664
3665 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3666 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3667 path, val);
3668 }
3669
3670 return val;
3671
3672 calc_6g:
3673 tgidx = phy_tssi_get_6g_trim_group(ch);
3674
3675 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3676 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3677 path, tgidx);
3678
3679 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
3680 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
3681 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
3682 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
3683 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
3684 val = (tde_1st + tde_2nd) / 2;
3685
3686 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3687 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3688 path, val, tde_1st, tde_2nd);
3689 } else {
3690 val = tssi_info->tssi_trim_6g[path][tgidx];
3691
3692 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3693 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3694 path, val);
3695 }
3696
3697 return val;
3698 }
3699
rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)3700 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
3701 enum rtw89_phy_idx phy,
3702 const struct rtw89_chan *chan,
3703 struct rtw89_h2c_rf_tssi *h2c)
3704 {
3705 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3706 u8 ch = chan->channel;
3707 s8 trim_de;
3708 s8 ofdm_de;
3709 s8 cck_de;
3710 u8 gidx;
3711 s8 val;
3712 int i;
3713
3714 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
3715 phy, ch);
3716
3717 for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
3718 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
3719 h2c->curr_tssi_trim_de[i] = trim_de;
3720
3721 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3722 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de);
3723
3724 gidx = phy_tssi_get_cck_group(ch);
3725 cck_de = tssi_info->tssi_cck[i][gidx];
3726 val = u32_get_bits(cck_de + trim_de, 0xff);
3727
3728 h2c->curr_tssi_cck_de[i] = 0x0;
3729 h2c->curr_tssi_cck_de_20m[i] = val;
3730 h2c->curr_tssi_cck_de_40m[i] = val;
3731 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
3732
3733 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3734 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de);
3735
3736 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
3737 val = u32_get_bits(ofdm_de + trim_de, 0xff);
3738
3739 h2c->curr_tssi_ofdm_de[i] = 0x0;
3740 h2c->curr_tssi_ofdm_de_20m[i] = val;
3741 h2c->curr_tssi_ofdm_de_40m[i] = val;
3742 h2c->curr_tssi_ofdm_de_80m[i] = val;
3743 h2c->curr_tssi_ofdm_de_160m[i] = val;
3744 h2c->curr_tssi_ofdm_de_320m[i] = val;
3745 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
3746
3747 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3748 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de);
3749 }
3750 }
3751
rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)3752 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
3753 enum rtw89_phy_idx phy,
3754 const struct rtw89_chan *chan,
3755 struct rtw89_h2c_rf_tssi *h2c)
3756 {
3757 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
3758 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3759 const s8 *thm_up[RF_PATH_B + 1] = {};
3760 const s8 *thm_down[RF_PATH_B + 1] = {};
3761 u8 subband = chan->subband_type;
3762 s8 thm_ofst[128] = {0};
3763 u8 thermal;
3764 u8 path;
3765 u8 i, j;
3766
3767 switch (subband) {
3768 default:
3769 case RTW89_CH_2G:
3770 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
3771 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
3772 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
3773 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
3774 break;
3775 case RTW89_CH_5G_BAND_1:
3776 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
3777 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
3778 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
3779 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
3780 break;
3781 case RTW89_CH_5G_BAND_3:
3782 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
3783 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
3784 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
3785 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
3786 break;
3787 case RTW89_CH_5G_BAND_4:
3788 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
3789 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
3790 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
3791 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
3792 break;
3793 case RTW89_CH_6G_BAND_IDX0:
3794 case RTW89_CH_6G_BAND_IDX1:
3795 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
3796 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
3797 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
3798 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
3799 break;
3800 case RTW89_CH_6G_BAND_IDX2:
3801 case RTW89_CH_6G_BAND_IDX3:
3802 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
3803 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
3804 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
3805 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
3806 break;
3807 case RTW89_CH_6G_BAND_IDX4:
3808 case RTW89_CH_6G_BAND_IDX5:
3809 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
3810 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
3811 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
3812 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
3813 break;
3814 case RTW89_CH_6G_BAND_IDX6:
3815 case RTW89_CH_6G_BAND_IDX7:
3816 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
3817 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
3818 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
3819 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
3820 break;
3821 }
3822
3823 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3824 "[TSSI] tmeter tbl on subband: %u\n", subband);
3825
3826 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
3827 thermal = tssi_info->thermal[path];
3828 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3829 "path: %u, pg thermal: 0x%x\n", path, thermal);
3830
3831 if (thermal == 0xff) {
3832 h2c->pg_thermal[path] = 0x38;
3833 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
3834 continue;
3835 }
3836
3837 h2c->pg_thermal[path] = thermal;
3838
3839 i = 0;
3840 for (j = 0; j < 64; j++)
3841 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
3842 thm_up[path][i++] :
3843 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
3844
3845 i = 1;
3846 for (j = 127; j >= 64; j--)
3847 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
3848 -thm_down[path][i++] :
3849 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
3850
3851 for (i = 0; i < 128; i += 4) {
3852 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
3853 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
3854 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
3855 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
3856
3857 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3858 "thm ofst [%x]: %02x %02x %02x %02x\n",
3859 i, thm_ofst[i], thm_ofst[i + 1],
3860 thm_ofst[i + 2], thm_ofst[i + 3]);
3861 }
3862 }
3863 }
3864
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)3865 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
3866 {
3867 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
3868 u32 reg_mask;
3869
3870 if (sc_xo)
3871 reg_mask = xtal->sc_xo_mask;
3872 else
3873 reg_mask = xtal->sc_xi_mask;
3874
3875 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
3876 }
3877
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)3878 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
3879 u8 val)
3880 {
3881 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
3882 u32 reg_mask;
3883
3884 if (sc_xo)
3885 reg_mask = xtal->sc_xo_mask;
3886 else
3887 reg_mask = xtal->sc_xi_mask;
3888
3889 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
3890 }
3891
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)3892 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
3893 u8 crystal_cap, bool force)
3894 {
3895 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3896 const struct rtw89_chip_info *chip = rtwdev->chip;
3897 u8 sc_xi_val, sc_xo_val;
3898
3899 if (!force && cfo->crystal_cap == crystal_cap)
3900 return;
3901 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
3902 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
3903 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
3904 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
3905 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
3906 } else {
3907 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
3908 crystal_cap, XTAL_SC_XO_MASK);
3909 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
3910 crystal_cap, XTAL_SC_XI_MASK);
3911 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
3912 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
3913 }
3914 cfo->crystal_cap = sc_xi_val;
3915 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
3916
3917 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
3918 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
3919 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
3920 cfo->x_cap_ofst);
3921 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
3922 }
3923
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)3924 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
3925 {
3926 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3927 u8 cap;
3928
3929 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
3930 cfo->is_adjust = false;
3931 if (cfo->crystal_cap == cfo->def_x_cap)
3932 return;
3933 cap = cfo->crystal_cap;
3934 cap += (cap > cfo->def_x_cap ? -1 : 1);
3935 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
3936 rtw89_debug(rtwdev, RTW89_DBG_CFO,
3937 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
3938 cfo->def_x_cap);
3939 }
3940
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)3941 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
3942 {
3943 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
3944 bool is_linked = rtwdev->total_sta_assoc > 0;
3945 s32 cfo_avg_312;
3946 s32 dcfo_comp_val;
3947 int sign;
3948
3949 if (rtwdev->chip->chip_id == RTL8922A)
3950 return;
3951
3952 if (!is_linked) {
3953 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
3954 is_linked);
3955 return;
3956 }
3957 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
3958 if (curr_cfo == 0)
3959 return;
3960 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
3961 sign = curr_cfo > 0 ? 1 : -1;
3962 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val;
3963 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
3964 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
3965 cfo_avg_312 = -cfo_avg_312;
3966 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
3967 cfo_avg_312);
3968 }
3969
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)3970 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
3971 {
3972 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
3973 const struct rtw89_chip_info *chip = rtwdev->chip;
3974 const struct rtw89_cfo_regs *cfo = phy->cfo;
3975
3976 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
3977 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
3978
3979 if (chip->chip_gen == RTW89_CHIP_AX) {
3980 if (chip->cfo_hw_comp) {
3981 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
3982 B_AX_PWR_UL_CFO_MASK, 0x6);
3983 } else {
3984 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
3985 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
3986 B_AX_PWR_UL_CFO_MASK);
3987 }
3988 }
3989 }
3990
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)3991 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
3992 {
3993 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3994 struct rtw89_efuse *efuse = &rtwdev->efuse;
3995
3996 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
3997 cfo->crystal_cap = cfo->crystal_cap_default;
3998 cfo->def_x_cap = cfo->crystal_cap;
3999 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4000 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4001 cfo->is_adjust = false;
4002 cfo->divergence_lock_en = false;
4003 cfo->x_cap_ofst = 0;
4004 cfo->lock_cnt = 0;
4005 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4006 cfo->apply_compensation = false;
4007 cfo->residual_cfo_acc = 0;
4008 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
4009 cfo->crystal_cap_default);
4010 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
4011 rtw89_dcfo_comp_init(rtwdev);
4012 cfo->cfo_timer_ms = 2000;
4013 cfo->cfo_trig_by_timer_en = false;
4014 cfo->phy_cfo_trk_cnt = 0;
4015 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4016 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
4017 }
4018
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)4019 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
4020 s32 curr_cfo)
4021 {
4022 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4023 int crystal_cap = cfo->crystal_cap;
4024 s32 cfo_abs = abs(curr_cfo);
4025 int sign;
4026
4027 if (curr_cfo == 0) {
4028 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
4029 return;
4030 }
4031 if (!cfo->is_adjust) {
4032 if (cfo_abs > CFO_TRK_ENABLE_TH)
4033 cfo->is_adjust = true;
4034 } else {
4035 if (cfo_abs <= CFO_TRK_STOP_TH)
4036 cfo->is_adjust = false;
4037 }
4038 if (!cfo->is_adjust) {
4039 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
4040 return;
4041 }
4042 sign = curr_cfo > 0 ? 1 : -1;
4043 if (cfo_abs > CFO_TRK_STOP_TH_4)
4044 crystal_cap += 3 * sign;
4045 else if (cfo_abs > CFO_TRK_STOP_TH_3)
4046 crystal_cap += 3 * sign;
4047 else if (cfo_abs > CFO_TRK_STOP_TH_2)
4048 crystal_cap += 1 * sign;
4049 else if (cfo_abs > CFO_TRK_STOP_TH_1)
4050 crystal_cap += 1 * sign;
4051 else
4052 return;
4053
4054 crystal_cap = clamp(crystal_cap, 0, 127);
4055 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
4056 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4057 "X_cap{Curr,Default}={0x%x,0x%x}\n",
4058 cfo->crystal_cap, cfo->def_x_cap);
4059 }
4060
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)4061 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
4062 {
4063 const struct rtw89_chip_info *chip = rtwdev->chip;
4064 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4065 s32 cfo_khz_all = 0;
4066 s32 cfo_cnt_all = 0;
4067 s32 cfo_all_avg = 0;
4068 u8 i;
4069
4070 if (rtwdev->total_sta_assoc != 1)
4071 return 0;
4072 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
4073 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4074 if (cfo->cfo_cnt[i] == 0)
4075 continue;
4076 cfo_khz_all += cfo->cfo_tail[i];
4077 cfo_cnt_all += cfo->cfo_cnt[i];
4078 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
4079 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4080 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
4081 cfo_cnt_all);
4082 }
4083 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4084 "CFO track for macid = %d\n", i);
4085 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4086 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
4087 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
4088 return cfo_all_avg;
4089 }
4090
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)4091 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
4092 {
4093 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4094 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4095 s32 target_cfo = 0;
4096 s32 cfo_khz_all = 0;
4097 s32 cfo_khz_all_tp_wgt = 0;
4098 s32 cfo_avg = 0;
4099 s32 max_cfo_lb = BIT(31);
4100 s32 min_cfo_ub = GENMASK(30, 0);
4101 u16 cfo_cnt_all = 0;
4102 u8 active_entry_cnt = 0;
4103 u8 sta_cnt = 0;
4104 u32 tp_all = 0;
4105 u8 i;
4106 u8 cfo_tol = 0;
4107
4108 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
4109 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
4110 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
4111 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4112 if (cfo->cfo_cnt[i] == 0)
4113 continue;
4114 cfo_khz_all += cfo->cfo_tail[i];
4115 cfo_cnt_all += cfo->cfo_cnt[i];
4116 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
4117 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4118 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
4119 cfo_khz_all, cfo_cnt_all, cfo_avg);
4120 target_cfo = cfo_avg;
4121 }
4122 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
4123 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
4124 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4125 if (cfo->cfo_cnt[i] == 0)
4126 continue;
4127 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4128 (s32)cfo->cfo_cnt[i]);
4129 cfo_khz_all += cfo->cfo_avg[i];
4130 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4131 "Macid=%d, cfo_avg=%d\n", i,
4132 cfo->cfo_avg[i]);
4133 }
4134 sta_cnt = rtwdev->total_sta_assoc;
4135 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
4136 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4137 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
4138 cfo_khz_all, sta_cnt, cfo_avg);
4139 target_cfo = cfo_avg;
4140 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
4141 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
4142 cfo_tol = cfo->sta_cfo_tolerance;
4143 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4144 sta_cnt++;
4145 if (cfo->cfo_cnt[i] != 0) {
4146 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4147 (s32)cfo->cfo_cnt[i]);
4148 active_entry_cnt++;
4149 } else {
4150 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
4151 }
4152 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
4153 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
4154 cfo_khz_all += cfo->cfo_avg[i];
4155 /* need tp for each entry */
4156 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4157 "[%d] cfo_avg=%d, tp=tbd\n",
4158 i, cfo->cfo_avg[i]);
4159 if (sta_cnt >= rtwdev->total_sta_assoc)
4160 break;
4161 }
4162 tp_all = stats->rx_throughput; /* need tp for each entry */
4163 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
4164
4165 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
4166 sta_cnt);
4167 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
4168 active_entry_cnt);
4169 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4170 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
4171 cfo_khz_all_tp_wgt, cfo_avg);
4172 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
4173 max_cfo_lb, min_cfo_ub);
4174 if (max_cfo_lb <= min_cfo_ub) {
4175 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4176 "cfo win_size=%d\n",
4177 min_cfo_ub - max_cfo_lb);
4178 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
4179 } else {
4180 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4181 "No intersection of cfo tolerance windows\n");
4182 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
4183 }
4184 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
4185 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4186 }
4187 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
4188 return target_cfo;
4189 }
4190
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)4191 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
4192 {
4193 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4194
4195 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
4196 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
4197 cfo->packet_count = 0;
4198 cfo->packet_count_pre = 0;
4199 cfo->cfo_avg_pre = 0;
4200 }
4201
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)4202 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
4203 {
4204 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4205 s32 new_cfo = 0;
4206 bool x_cap_update = false;
4207 u8 pre_x_cap = cfo->crystal_cap;
4208 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4209
4210 cfo->dcfo_avg = 0;
4211 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
4212 rtwdev->total_sta_assoc);
4213 if (rtwdev->total_sta_assoc == 0) {
4214 rtw89_phy_cfo_reset(rtwdev);
4215 return;
4216 }
4217 if (cfo->packet_count == 0) {
4218 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
4219 return;
4220 }
4221 if (cfo->packet_count == cfo->packet_count_pre) {
4222 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
4223 return;
4224 }
4225 if (rtwdev->total_sta_assoc == 1)
4226 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
4227 else
4228 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
4229 if (cfo->divergence_lock_en) {
4230 cfo->lock_cnt++;
4231 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
4232 cfo->divergence_lock_en = false;
4233 cfo->lock_cnt = 0;
4234 } else {
4235 rtw89_phy_cfo_reset(rtwdev);
4236 }
4237 return;
4238 }
4239 if (cfo->crystal_cap >= cfo->x_cap_ub ||
4240 cfo->crystal_cap <= cfo->x_cap_lb) {
4241 cfo->divergence_lock_en = true;
4242 rtw89_phy_cfo_reset(rtwdev);
4243 return;
4244 }
4245
4246 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
4247 cfo->cfo_avg_pre = new_cfo;
4248 cfo->dcfo_avg_pre = cfo->dcfo_avg;
4249 x_cap_update = cfo->crystal_cap != pre_x_cap;
4250 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
4251 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4252 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
4253 cfo->x_cap_ofst);
4254 if (x_cap_update) {
4255 if (cfo->dcfo_avg > 0)
4256 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4257 else
4258 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4259 }
4260 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4261 rtw89_phy_cfo_statistics_reset(rtwdev);
4262 }
4263
rtw89_phy_cfo_track_work(struct work_struct * work)4264 void rtw89_phy_cfo_track_work(struct work_struct *work)
4265 {
4266 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4267 cfo_track_work.work);
4268 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4269
4270 mutex_lock(&rtwdev->mutex);
4271 if (!cfo->cfo_trig_by_timer_en)
4272 goto out;
4273 rtw89_leave_ps_mode(rtwdev);
4274 rtw89_phy_cfo_dm(rtwdev);
4275 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4276 msecs_to_jiffies(cfo->cfo_timer_ms));
4277 out:
4278 mutex_unlock(&rtwdev->mutex);
4279 }
4280
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)4281 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
4282 {
4283 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4284
4285 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4286 msecs_to_jiffies(cfo->cfo_timer_ms));
4287 }
4288
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)4289 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
4290 {
4291 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4292 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4293 bool is_ul_ofdma = false, ofdma_acc_en = false;
4294
4295 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
4296 is_ul_ofdma = true;
4297 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
4298 is_ul_ofdma)
4299 ofdma_acc_en = true;
4300
4301 switch (cfo->phy_cfo_status) {
4302 case RTW89_PHY_DCFO_STATE_NORMAL:
4303 if (stats->tx_throughput >= CFO_TP_UPPER) {
4304 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
4305 cfo->cfo_trig_by_timer_en = true;
4306 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
4307 rtw89_phy_cfo_start_work(rtwdev);
4308 }
4309 break;
4310 case RTW89_PHY_DCFO_STATE_ENHANCE:
4311 if (stats->tx_throughput <= CFO_TP_LOWER)
4312 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4313 else if (ofdma_acc_en &&
4314 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
4315 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
4316 else
4317 cfo->phy_cfo_trk_cnt++;
4318
4319 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
4320 cfo->phy_cfo_trk_cnt = 0;
4321 cfo->cfo_trig_by_timer_en = false;
4322 }
4323 break;
4324 case RTW89_PHY_DCFO_STATE_HOLD:
4325 if (stats->tx_throughput <= CFO_TP_LOWER) {
4326 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4327 cfo->phy_cfo_trk_cnt = 0;
4328 cfo->cfo_trig_by_timer_en = false;
4329 } else {
4330 cfo->phy_cfo_trk_cnt++;
4331 }
4332 break;
4333 default:
4334 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4335 cfo->phy_cfo_trk_cnt = 0;
4336 break;
4337 }
4338 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4339 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
4340 stats->tx_throughput, cfo->phy_cfo_status,
4341 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
4342 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
4343 if (cfo->cfo_trig_by_timer_en)
4344 return;
4345 rtw89_phy_cfo_dm(rtwdev);
4346 }
4347
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)4348 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
4349 struct rtw89_rx_phy_ppdu *phy_ppdu)
4350 {
4351 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4352 u8 macid = phy_ppdu->mac_id;
4353
4354 if (macid >= CFO_TRACK_MAX_USER) {
4355 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
4356 return;
4357 }
4358
4359 cfo->cfo_tail[macid] += cfo_val;
4360 cfo->cfo_cnt[macid]++;
4361 cfo->packet_count++;
4362 }
4363
rtw89_phy_ul_tb_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4364 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4365 {
4366 const struct rtw89_chip_info *chip = rtwdev->chip;
4367 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4368 rtwvif_link->chanctx_idx);
4369 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4370
4371 if (!chip->ul_tb_waveform_ctrl)
4372 return;
4373
4374 rtwvif_link->def_tri_idx =
4375 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
4376
4377 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
4378 rtwvif_link->dyn_tb_bedge_en = false;
4379 else if (chan->band_type >= RTW89_BAND_5G &&
4380 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
4381 rtwvif_link->dyn_tb_bedge_en = true;
4382 else
4383 rtwvif_link->dyn_tb_bedge_en = false;
4384
4385 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4386 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
4387 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
4388 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4389 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
4390 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
4391 }
4392
4393 struct rtw89_phy_ul_tb_check_data {
4394 bool valid;
4395 bool high_tf_client;
4396 bool low_tf_client;
4397 bool dyn_tb_bedge_en;
4398 u8 def_tri_idx;
4399 };
4400
4401 struct rtw89_phy_power_diff {
4402 u32 q_00;
4403 u32 q_11;
4404 u32 q_matrix_en;
4405 u32 ultb_1t_norm_160;
4406 u32 ultb_2t_norm_160;
4407 u32 com1_norm_1sts;
4408 u32 com2_resp_1sts_path;
4409 };
4410
rtw89_phy_ofdma_power_diff(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4411 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
4412 struct rtw89_vif_link *rtwvif_link)
4413 {
4414 static const struct rtw89_phy_power_diff table[2] = {
4415 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3},
4416 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1},
4417 };
4418 const struct rtw89_phy_power_diff *param;
4419 u32 reg;
4420
4421 if (!rtwdev->chip->ul_tb_pwr_diff)
4422 return;
4423
4424 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
4425 rtwvif_link->pwr_diff_en = false;
4426 return;
4427 }
4428
4429 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
4430 param = &table[rtwvif_link->pwr_diff_en];
4431
4432 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
4433 param->q_00);
4434 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
4435 param->q_11);
4436 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
4437 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
4438
4439 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
4440 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
4441 param->ultb_1t_norm_160);
4442
4443 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
4444 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
4445 param->ultb_2t_norm_160);
4446
4447 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
4448 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
4449 param->com1_norm_1sts);
4450
4451 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
4452 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
4453 param->com2_resp_1sts_path);
4454 }
4455
4456 static
rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4457 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
4458 struct rtw89_vif_link *rtwvif_link,
4459 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4460 {
4461 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4462 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4463
4464 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
4465 return;
4466
4467 if (!vif->cfg.assoc)
4468 return;
4469
4470 if (rtwdev->chip->ul_tb_waveform_ctrl) {
4471 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
4472 ul_tb_data->high_tf_client = true;
4473 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
4474 ul_tb_data->low_tf_client = true;
4475
4476 ul_tb_data->valid = true;
4477 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
4478 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
4479 }
4480
4481 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link);
4482 }
4483
rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev * rtwdev,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4484 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
4485 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4486 {
4487 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4488
4489 if (!rtwdev->chip->ul_tb_waveform_ctrl)
4490 return;
4491
4492 if (ul_tb_data->dyn_tb_bedge_en) {
4493 if (ul_tb_data->high_tf_client) {
4494 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
4495 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4496 "[ULTB] Turn off if_bandedge\n");
4497 } else if (ul_tb_data->low_tf_client) {
4498 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
4499 ul_tb_info->def_if_bandedge);
4500 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4501 "[ULTB] Set to default if_bandedge = %d\n",
4502 ul_tb_info->def_if_bandedge);
4503 }
4504 }
4505
4506 if (ul_tb_info->dyn_tb_tri_en) {
4507 if (ul_tb_data->high_tf_client) {
4508 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4509 B_TXSHAPE_TRIANGULAR_CFG, 0);
4510 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4511 "[ULTB] Turn off Tx triangle\n");
4512 } else if (ul_tb_data->low_tf_client) {
4513 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4514 B_TXSHAPE_TRIANGULAR_CFG,
4515 ul_tb_data->def_tri_idx);
4516 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4517 "[ULTB] Set to default tx_shap_idx = %d\n",
4518 ul_tb_data->def_tri_idx);
4519 }
4520 }
4521 }
4522
rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev * rtwdev)4523 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
4524 {
4525 const struct rtw89_chip_info *chip = rtwdev->chip;
4526 struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
4527 struct rtw89_vif_link *rtwvif_link;
4528 struct rtw89_vif *rtwvif;
4529 unsigned int link_id;
4530
4531 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
4532 return;
4533
4534 if (rtwdev->total_sta_assoc != 1)
4535 return;
4536
4537 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4538 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4539 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data);
4540
4541 if (!ul_tb_data.valid)
4542 return;
4543
4544 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
4545 }
4546
rtw89_phy_ul_tb_info_init(struct rtw89_dev * rtwdev)4547 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
4548 {
4549 const struct rtw89_chip_info *chip = rtwdev->chip;
4550 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4551
4552 if (!chip->ul_tb_waveform_ctrl)
4553 return;
4554
4555 ul_tb_info->dyn_tb_tri_en = true;
4556 ul_tb_info->def_if_bandedge =
4557 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
4558 }
4559
4560 static
rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats * antdiv_sts)4561 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
4562 {
4563 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
4564 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
4565 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
4566 antdiv_sts->pkt_cnt_cck = 0;
4567 antdiv_sts->pkt_cnt_ofdm = 0;
4568 antdiv_sts->pkt_cnt_non_legacy = 0;
4569 antdiv_sts->evm = 0;
4570 }
4571
rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_antdiv_stats * stats)4572 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
4573 struct rtw89_rx_phy_ppdu *phy_ppdu,
4574 struct rtw89_antdiv_stats *stats)
4575 {
4576 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
4577 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
4578 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
4579 stats->pkt_cnt_cck++;
4580 } else {
4581 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
4582 stats->pkt_cnt_ofdm++;
4583 stats->evm += phy_ppdu->ofdm.evm_min;
4584 }
4585 } else {
4586 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
4587 stats->pkt_cnt_non_legacy++;
4588 stats->evm += phy_ppdu->ofdm.evm_min;
4589 }
4590 }
4591
rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats * stats)4592 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
4593 {
4594 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
4595 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
4596 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
4597 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
4598 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
4599 return ewma_rssi_read(&stats->ofdm_rssi_avg);
4600 else
4601 return ewma_rssi_read(&stats->cck_rssi_avg);
4602 }
4603
rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats * stats)4604 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
4605 {
4606 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
4607 }
4608
rtw89_phy_antdiv_parse(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)4609 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
4610 struct rtw89_rx_phy_ppdu *phy_ppdu)
4611 {
4612 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
4613 struct rtw89_hal *hal = &rtwdev->hal;
4614
4615 if (!hal->ant_diversity || hal->ant_diversity_fixed)
4616 return;
4617
4618 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
4619
4620 if (!antdiv->get_stats)
4621 return;
4622
4623 if (hal->antenna_rx == RF_A)
4624 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
4625 else if (hal->antenna_rx == RF_B)
4626 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
4627 }
4628
rtw89_phy_antdiv_reg_init(struct rtw89_dev * rtwdev)4629 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
4630 {
4631 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
4632 0x0, RTW89_PHY_0);
4633 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
4634 0x0, RTW89_PHY_0);
4635
4636 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
4637 0x0, RTW89_PHY_0);
4638 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
4639 0x0, RTW89_PHY_0);
4640
4641 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
4642 0x0, RTW89_PHY_0);
4643
4644 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
4645 0x0100, RTW89_PHY_0);
4646
4647 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
4648 0x1, RTW89_PHY_0);
4649 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
4650 0x0, RTW89_PHY_0);
4651 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
4652 0x0, RTW89_PHY_0);
4653 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
4654 0x0, RTW89_PHY_0);
4655 }
4656
rtw89_phy_antdiv_sts_reset(struct rtw89_dev * rtwdev)4657 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
4658 {
4659 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
4660
4661 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
4662 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
4663 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
4664 }
4665
rtw89_phy_antdiv_init(struct rtw89_dev * rtwdev)4666 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
4667 {
4668 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
4669 struct rtw89_hal *hal = &rtwdev->hal;
4670
4671 if (!hal->ant_diversity)
4672 return;
4673
4674 antdiv->get_stats = false;
4675 antdiv->rssi_pre = 0;
4676 rtw89_phy_antdiv_sts_reset(rtwdev);
4677 rtw89_phy_antdiv_reg_init(rtwdev);
4678 }
4679
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)4680 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
4681 {
4682 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
4683 int i;
4684 u8 th;
4685
4686 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
4687 th = rtw89_chip_get_thermal(rtwdev, i);
4688 if (th)
4689 ewma_thermal_add(&phystat->avg_thermal[i], th);
4690
4691 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
4692 "path(%d) thermal cur=%u avg=%ld", i, th,
4693 ewma_thermal_read(&phystat->avg_thermal[i]));
4694 }
4695 }
4696
4697 struct rtw89_phy_iter_rssi_data {
4698 struct rtw89_dev *rtwdev;
4699 struct rtw89_phy_ch_info *ch_info;
4700 bool rssi_changed;
4701 };
4702
4703 static
__rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link * rtwsta_link,struct rtw89_phy_iter_rssi_data * rssi_data)4704 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link,
4705 struct rtw89_phy_iter_rssi_data *rssi_data)
4706 {
4707 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info;
4708 unsigned long rssi_curr;
4709
4710 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
4711
4712 if (rssi_curr < ch_info->rssi_min) {
4713 ch_info->rssi_min = rssi_curr;
4714 ch_info->rssi_min_macid = rtwsta_link->mac_id;
4715 }
4716
4717 if (rtwsta_link->prev_rssi == 0) {
4718 rtwsta_link->prev_rssi = rssi_curr;
4719 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
4720 (3 << RSSI_FACTOR)) {
4721 rtwsta_link->prev_rssi = rssi_curr;
4722 rssi_data->rssi_changed = true;
4723 }
4724 }
4725
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)4726 static void rtw89_phy_stat_rssi_update_iter(void *data,
4727 struct ieee80211_sta *sta)
4728 {
4729 struct rtw89_phy_iter_rssi_data *rssi_data =
4730 (struct rtw89_phy_iter_rssi_data *)data;
4731 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4732 struct rtw89_sta_link *rtwsta_link;
4733 unsigned int link_id;
4734
4735 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
4736 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data);
4737 }
4738
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)4739 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
4740 {
4741 struct rtw89_phy_iter_rssi_data rssi_data = {0};
4742
4743 rssi_data.rtwdev = rtwdev;
4744 rssi_data.ch_info = &rtwdev->ch_info;
4745 rssi_data.ch_info->rssi_min = U8_MAX;
4746 ieee80211_iterate_stations_atomic(rtwdev->hw,
4747 rtw89_phy_stat_rssi_update_iter,
4748 &rssi_data);
4749 if (rssi_data.rssi_changed)
4750 rtw89_btc_ntfy_wl_sta(rtwdev);
4751 }
4752
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)4753 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
4754 {
4755 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
4756 int i;
4757
4758 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
4759 ewma_thermal_init(&phystat->avg_thermal[i]);
4760
4761 rtw89_phy_stat_thermal_update(rtwdev);
4762
4763 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
4764 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
4765 }
4766
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)4767 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
4768 {
4769 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
4770
4771 rtw89_phy_stat_thermal_update(rtwdev);
4772 rtw89_phy_stat_rssi_update(rtwdev);
4773
4774 phystat->last_pkt_stat = phystat->cur_pkt_stat;
4775 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
4776 }
4777
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,u32 time_us)4778 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)
4779 {
4780 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4781
4782 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
4783 }
4784
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,u16 idx)4785 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
4786 {
4787 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4788
4789 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
4790 }
4791
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev)4792 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
4793 {
4794 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4795 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4796 const struct rtw89_ccx_regs *ccx = phy->ccx;
4797
4798 env->ccx_manual_ctrl = false;
4799 env->ccx_ongoing = false;
4800 env->ccx_rac_lv = RTW89_RAC_RELEASE;
4801 env->ccx_period = 0;
4802 env->ccx_unit_idx = RTW89_CCX_32_US;
4803
4804 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1);
4805 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1);
4806 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
4807 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
4808 RTW89_CCX_EDCCA_BW20_0);
4809 }
4810
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,u16 report,u16 score)4811 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,
4812 u16 score)
4813 {
4814 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4815 u32 numer = 0;
4816 u16 ret = 0;
4817
4818 numer = report * score + (env->ccx_period >> 1);
4819 if (env->ccx_period)
4820 ret = numer / env->ccx_period;
4821
4822 return ret >= score ? score - 1 : ret;
4823 }
4824
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)4825 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
4826 u16 time_ms, u32 *period,
4827 u32 *unit_idx)
4828 {
4829 u32 idx;
4830 u8 quotient;
4831
4832 if (time_ms >= CCX_MAX_PERIOD)
4833 time_ms = CCX_MAX_PERIOD;
4834
4835 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
4836
4837 if (quotient < 4)
4838 idx = RTW89_CCX_4_US;
4839 else if (quotient < 8)
4840 idx = RTW89_CCX_8_US;
4841 else if (quotient < 16)
4842 idx = RTW89_CCX_16_US;
4843 else
4844 idx = RTW89_CCX_32_US;
4845
4846 *unit_idx = idx;
4847 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
4848
4849 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4850 "[Trigger Time] period:%d, unit_idx:%d\n",
4851 *period, *unit_idx);
4852 }
4853
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev)4854 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)
4855 {
4856 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4857
4858 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4859 "lv:(%d)->(0)\n", env->ccx_rac_lv);
4860
4861 env->ccx_ongoing = false;
4862 env->ccx_rac_lv = RTW89_RAC_RELEASE;
4863 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
4864 }
4865
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)4866 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
4867 struct rtw89_ccx_para_info *para)
4868 {
4869 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4870 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
4871 u8 i = 0;
4872 u16 *ifs_th_l = env->ifs_clm_th_l;
4873 u16 *ifs_th_h = env->ifs_clm_th_h;
4874 u32 ifs_th0_us = 0, ifs_th_times = 0;
4875 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
4876
4877 if (!is_update)
4878 goto ifs_update_finished;
4879
4880 switch (para->ifs_clm_app) {
4881 case RTW89_IFS_CLM_INIT:
4882 case RTW89_IFS_CLM_BACKGROUND:
4883 case RTW89_IFS_CLM_ACS:
4884 case RTW89_IFS_CLM_DBG:
4885 case RTW89_IFS_CLM_DIG:
4886 case RTW89_IFS_CLM_TDMA_DIG:
4887 ifs_th0_us = IFS_CLM_TH0_UPPER;
4888 ifs_th_times = IFS_CLM_TH_MUL;
4889 break;
4890 case RTW89_IFS_CLM_DBG_MANUAL:
4891 ifs_th0_us = para->ifs_clm_manual_th0;
4892 ifs_th_times = para->ifs_clm_manual_th_times;
4893 break;
4894 default:
4895 break;
4896 }
4897
4898 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
4899 * low[i] = high[i-1] + 1
4900 * high[i] = high[i-1] * ifs_th_times
4901 */
4902 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
4903 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
4904 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev,
4905 ifs_th0_us);
4906 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
4907 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
4908 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
4909 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]);
4910 }
4911
4912 ifs_update_finished:
4913 if (!is_update)
4914 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4915 "No need to update IFS_TH\n");
4916
4917 return is_update;
4918 }
4919
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev)4920 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
4921 {
4922 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4923 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4924 const struct rtw89_ccx_regs *ccx = phy->ccx;
4925 u8 i = 0;
4926
4927 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
4928 env->ifs_clm_th_l[0]);
4929 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
4930 env->ifs_clm_th_l[1]);
4931 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
4932 env->ifs_clm_th_l[2]);
4933 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
4934 env->ifs_clm_th_l[3]);
4935
4936 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
4937 env->ifs_clm_th_h[0]);
4938 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
4939 env->ifs_clm_th_h[1]);
4940 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
4941 env->ifs_clm_th_h[2]);
4942 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
4943 env->ifs_clm_th_h[3]);
4944
4945 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
4946 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4947 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
4948 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
4949 }
4950
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev)4951 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
4952 {
4953 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4954 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4955 const struct rtw89_ccx_regs *ccx = phy->ccx;
4956 struct rtw89_ccx_para_info para = {0};
4957
4958 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
4959 env->ifs_clm_mntr_time = 0;
4960
4961 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
4962 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶))
4963 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
4964
4965 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true);
4966 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true);
4967 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true);
4968 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true);
4969 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true);
4970 }
4971
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,enum rtw89_env_racing_lv level)4972 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
4973 enum rtw89_env_racing_lv level)
4974 {
4975 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4976 int ret = 0;
4977
4978 if (level >= RTW89_RAC_MAX_NUM) {
4979 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4980 "[WARNING] Wrong LV=%d\n", level);
4981 return -EINVAL;
4982 }
4983
4984 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4985 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
4986 env->ccx_rac_lv, level);
4987
4988 if (env->ccx_ongoing) {
4989 if (level <= env->ccx_rac_lv)
4990 ret = -EINVAL;
4991 else
4992 env->ccx_ongoing = false;
4993 }
4994
4995 if (ret == 0)
4996 env->ccx_rac_lv = level;
4997
4998 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
4999 !ret);
5000
5001 return ret;
5002 }
5003
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev)5004 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
5005 {
5006 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5007 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5008 const struct rtw89_ccx_regs *ccx = phy->ccx;
5009
5010 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0);
5011 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0);
5012 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1);
5013 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
5014
5015 env->ccx_ongoing = true;
5016 }
5017
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev)5018 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
5019 {
5020 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5021 u8 i = 0;
5022 u32 res = 0;
5023
5024 env->ifs_clm_tx_ratio =
5025 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
5026 env->ifs_clm_edcca_excl_cca_ratio =
5027 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
5028 PERCENT);
5029 env->ifs_clm_cck_fa_ratio =
5030 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
5031 env->ifs_clm_ofdm_fa_ratio =
5032 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
5033 env->ifs_clm_cck_cca_excl_fa_ratio =
5034 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
5035 PERCENT);
5036 env->ifs_clm_ofdm_cca_excl_fa_ratio =
5037 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
5038 PERCENT);
5039 env->ifs_clm_cck_fa_permil =
5040 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
5041 env->ifs_clm_ofdm_fa_permil =
5042 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
5043
5044 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
5045 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
5046 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
5047 } else {
5048 env->ifs_clm_ifs_avg[i] =
5049 rtw89_phy_ccx_idx_to_us(rtwdev,
5050 env->ifs_clm_avg[i]);
5051 }
5052
5053 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
5054 res += env->ifs_clm_his[i] >> 1;
5055 if (env->ifs_clm_his[i])
5056 res /= env->ifs_clm_his[i];
5057 else
5058 res = 0;
5059 env->ifs_clm_cca_avg[i] = res;
5060 }
5061
5062 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5063 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5064 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
5065 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5066 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
5067 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
5068 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5069 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
5070 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
5071 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5072 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
5073 env->ifs_clm_cck_cca_excl_fa_ratio,
5074 env->ifs_clm_ofdm_cca_excl_fa_ratio);
5075 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5076 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
5077 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5078 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
5079 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
5080 env->ifs_clm_cca_avg[i]);
5081 }
5082
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev)5083 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
5084 {
5085 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5086 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5087 const struct rtw89_ccx_regs *ccx = phy->ccx;
5088 u8 i = 0;
5089
5090 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5091 ccx->ifs_cnt_done_mask) == 0) {
5092 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5093 "Get IFS_CLM report Fail\n");
5094 return false;
5095 }
5096
5097 env->ifs_clm_tx =
5098 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5099 ccx->ifs_clm_tx_cnt_msk);
5100 env->ifs_clm_edcca_excl_cca =
5101 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5102 ccx->ifs_clm_edcca_excl_cca_fa_mask);
5103 env->ifs_clm_cckcca_excl_fa =
5104 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5105 ccx->ifs_clm_cckcca_excl_fa_mask);
5106 env->ifs_clm_ofdmcca_excl_fa =
5107 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5108 ccx->ifs_clm_ofdmcca_excl_fa_mask);
5109 env->ifs_clm_cckfa =
5110 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5111 ccx->ifs_clm_cck_fa_mask);
5112 env->ifs_clm_ofdmfa =
5113 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5114 ccx->ifs_clm_ofdm_fa_mask);
5115
5116 env->ifs_clm_his[0] =
5117 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5118 ccx->ifs_t1_his_mask);
5119 env->ifs_clm_his[1] =
5120 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5121 ccx->ifs_t2_his_mask);
5122 env->ifs_clm_his[2] =
5123 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5124 ccx->ifs_t3_his_mask);
5125 env->ifs_clm_his[3] =
5126 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5127 ccx->ifs_t4_his_mask);
5128
5129 env->ifs_clm_avg[0] =
5130 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5131 ccx->ifs_t1_avg_mask);
5132 env->ifs_clm_avg[1] =
5133 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5134 ccx->ifs_t2_avg_mask);
5135 env->ifs_clm_avg[2] =
5136 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5137 ccx->ifs_t3_avg_mask);
5138 env->ifs_clm_avg[3] =
5139 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5140 ccx->ifs_t4_avg_mask);
5141
5142 env->ifs_clm_cca[0] =
5143 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5144 ccx->ifs_t1_cca_mask);
5145 env->ifs_clm_cca[1] =
5146 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5147 ccx->ifs_t2_cca_mask);
5148 env->ifs_clm_cca[2] =
5149 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5150 ccx->ifs_t3_cca_mask);
5151 env->ifs_clm_cca[3] =
5152 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5153 ccx->ifs_t4_cca_mask);
5154
5155 env->ifs_clm_total_ifs =
5156 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5157 ccx->ifs_total_mask);
5158
5159 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
5160 env->ifs_clm_total_ifs);
5161 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5162 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5163 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
5164 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5165 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
5166 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
5167 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5168 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
5169 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
5170
5171 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
5172 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5173 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5174 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
5175 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
5176
5177 rtw89_phy_ifs_clm_get_utility(rtwdev);
5178
5179 return true;
5180 }
5181
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)5182 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
5183 struct rtw89_ccx_para_info *para)
5184 {
5185 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5186 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5187 const struct rtw89_ccx_regs *ccx = phy->ccx;
5188 u32 period = 0;
5189 u32 unit_idx = 0;
5190
5191 if (para->mntr_time == 0) {
5192 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5193 "[WARN] MNTR_TIME is 0\n");
5194 return -EINVAL;
5195 }
5196
5197 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
5198 return -EINVAL;
5199
5200 if (para->mntr_time != env->ifs_clm_mntr_time) {
5201 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
5202 &period, &unit_idx);
5203 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5204 ccx->ifs_clm_period_mask, period);
5205 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5206 ccx->ifs_clm_cnt_unit_mask,
5207 unit_idx);
5208
5209 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5210 "Update IFS-CLM time ((%d)) -> ((%d))\n",
5211 env->ifs_clm_mntr_time, para->mntr_time);
5212
5213 env->ifs_clm_mntr_time = para->mntr_time;
5214 env->ccx_period = (u16)period;
5215 env->ccx_unit_idx = (u8)unit_idx;
5216 }
5217
5218 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) {
5219 env->ifs_clm_app = para->ifs_clm_app;
5220 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
5221 }
5222
5223 return 0;
5224 }
5225
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)5226 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
5227 {
5228 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5229 struct rtw89_ccx_para_info para = {0};
5230 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5231
5232 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5233 if (env->ccx_manual_ctrl) {
5234 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5235 "CCX in manual ctrl\n");
5236 return;
5237 }
5238
5239 /* only ifs_clm for now */
5240 if (rtw89_phy_ifs_clm_get_result(rtwdev))
5241 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5242
5243 rtw89_phy_ccx_racing_release(rtwdev);
5244 para.mntr_time = 1900;
5245 para.rac_lv = RTW89_RAC_LV_1;
5246 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5247
5248 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0)
5249 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5250 if (chk_result)
5251 rtw89_phy_ccx_trigger(rtwdev);
5252
5253 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5254 "get_result=0x%x, chk_result:0x%x\n",
5255 env->ccx_watchdog_result, chk_result);
5256 }
5257
rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap * ie_page)5258 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page)
5259 {
5260 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM ||
5261 *ie_page == RTW89_RSVD_9)
5262 return false;
5263 else if (*ie_page > RTW89_RSVD_9)
5264 *ie_page -= 1;
5265
5266 return true;
5267 }
5268
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)5269 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
5270 {
5271 static const u8 ie_page_shift = 2;
5272
5273 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
5274 }
5275
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page)5276 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
5277 enum rtw89_phy_status_bitmap ie_page)
5278 {
5279 u32 addr;
5280
5281 if (!rtw89_physts_ie_page_valid(&ie_page))
5282 return 0;
5283
5284 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5285
5286 return rtw89_phy_read32(rtwdev, addr);
5287 }
5288
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val)5289 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
5290 enum rtw89_phy_status_bitmap ie_page,
5291 u32 val)
5292 {
5293 const struct rtw89_chip_info *chip = rtwdev->chip;
5294 u32 addr;
5295
5296 if (!rtw89_physts_ie_page_valid(&ie_page))
5297 return;
5298
5299 if (chip->chip_id == RTL8852A)
5300 val &= B_PHY_STS_BITMAP_MSK_52A;
5301
5302 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5303 rtw89_phy_write32(rtwdev, addr, val);
5304 }
5305
rtw89_physts_enable_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap bitmap,enum rtw89_phy_status_ie_type ie,bool enable)5306 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
5307 enum rtw89_phy_status_bitmap bitmap,
5308 enum rtw89_phy_status_ie_type ie,
5309 bool enable)
5310 {
5311 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap);
5312
5313 if (enable)
5314 val |= BIT(ie);
5315 else
5316 val &= ~BIT(ie);
5317
5318 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val);
5319 }
5320
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)5321 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
5322 bool enable,
5323 enum rtw89_phy_idx phy_idx)
5324 {
5325 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5326 const struct rtw89_physts_regs *physts = phy->physts;
5327
5328 if (enable) {
5329 rtw89_phy_write32_clr(rtwdev, physts->setting_addr,
5330 physts->dis_trigger_fail_mask);
5331 rtw89_phy_write32_clr(rtwdev, physts->setting_addr,
5332 physts->dis_trigger_brk_mask);
5333 } else {
5334 rtw89_phy_write32_set(rtwdev, physts->setting_addr,
5335 physts->dis_trigger_fail_mask);
5336 rtw89_phy_write32_set(rtwdev, physts->setting_addr,
5337 physts->dis_trigger_brk_mask);
5338 }
5339 }
5340
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)5341 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
5342 {
5343 u8 i;
5344
5345 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0);
5346
5347 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
5348 if (i >= RTW89_CCK_PKT)
5349 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5350 RTW89_PHYSTS_IE09_FTR_0,
5351 true);
5352 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) ||
5353 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT))
5354 continue;
5355 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5356 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A,
5357 true);
5358 }
5359 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
5360 RTW89_PHYSTS_IE13_DL_MU_DEF, true);
5361 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
5362 RTW89_PHYSTS_IE13_DL_MU_DEF, true);
5363
5364 /* force IE01 for channel index, only channel field is valid */
5365 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
5366 RTW89_PHYSTS_IE01_CMN_OFDM, true);
5367 }
5368
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,int type)5369 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)
5370 {
5371 const struct rtw89_chip_info *chip = rtwdev->chip;
5372 struct rtw89_dig_info *dig = &rtwdev->dig;
5373 const struct rtw89_phy_dig_gain_cfg *cfg;
5374 const char *msg;
5375 u8 i;
5376 s8 gain_base;
5377 s8 *gain_arr;
5378 u32 tmp;
5379
5380 switch (type) {
5381 case RTW89_DIG_GAIN_LNA_G:
5382 gain_arr = dig->lna_gain_g;
5383 gain_base = LNA0_GAIN;
5384 cfg = chip->dig_table->cfg_lna_g;
5385 msg = "lna_gain_g";
5386 break;
5387 case RTW89_DIG_GAIN_TIA_G:
5388 gain_arr = dig->tia_gain_g;
5389 gain_base = TIA0_GAIN_G;
5390 cfg = chip->dig_table->cfg_tia_g;
5391 msg = "tia_gain_g";
5392 break;
5393 case RTW89_DIG_GAIN_LNA_A:
5394 gain_arr = dig->lna_gain_a;
5395 gain_base = LNA0_GAIN;
5396 cfg = chip->dig_table->cfg_lna_a;
5397 msg = "lna_gain_a";
5398 break;
5399 case RTW89_DIG_GAIN_TIA_A:
5400 gain_arr = dig->tia_gain_a;
5401 gain_base = TIA0_GAIN_A;
5402 cfg = chip->dig_table->cfg_tia_a;
5403 msg = "tia_gain_a";
5404 break;
5405 default:
5406 return;
5407 }
5408
5409 for (i = 0; i < cfg->size; i++) {
5410 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
5411 cfg->table[i].mask);
5412 tmp >>= DIG_GAIN_SHIFT;
5413 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
5414 gain_base += DIG_GAIN;
5415
5416 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
5417 msg, i, gain_arr[i]);
5418 }
5419 }
5420
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev)5421 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)
5422 {
5423 struct rtw89_dig_info *dig = &rtwdev->dig;
5424 u32 tmp;
5425 u8 i;
5426
5427 if (!rtwdev->hal.support_igi)
5428 return;
5429
5430 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW,
5431 B_PATH0_IB_PKPW_MSK);
5432 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
5433 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
5434 B_PATH0_IB_PBK_MSK);
5435 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
5436 dig->ib_pkpwr, dig->ib_pbk);
5437
5438 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
5439 rtw89_phy_dig_read_gain_table(rtwdev, i);
5440 }
5441
5442 static const u8 rssi_nolink = 22;
5443 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
5444 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
5445 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
5446 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
5447
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev)5448 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)
5449 {
5450 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
5451 struct rtw89_dig_info *dig = &rtwdev->dig;
5452 bool is_linked = rtwdev->total_sta_assoc > 0;
5453
5454 if (is_linked) {
5455 dig->igi_rssi = ch_info->rssi_min >> 1;
5456 } else {
5457 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
5458 dig->igi_rssi = rssi_nolink;
5459 }
5460 }
5461
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev)5462 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)
5463 {
5464 struct rtw89_dig_info *dig = &rtwdev->dig;
5465 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
5466 bool is_linked = rtwdev->total_sta_assoc > 0;
5467 const u16 *fa_th_src = NULL;
5468
5469 switch (chan->band_type) {
5470 case RTW89_BAND_2G:
5471 dig->lna_gain = dig->lna_gain_g;
5472 dig->tia_gain = dig->tia_gain_g;
5473 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
5474 dig->force_gaincode_idx_en = false;
5475 dig->dyn_pd_th_en = true;
5476 break;
5477 case RTW89_BAND_5G:
5478 default:
5479 dig->lna_gain = dig->lna_gain_a;
5480 dig->tia_gain = dig->tia_gain_a;
5481 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
5482 dig->force_gaincode_idx_en = true;
5483 dig->dyn_pd_th_en = true;
5484 break;
5485 }
5486 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
5487 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
5488 }
5489
5490 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20;
5491 static const u8 igi_max_performance_mode = 0x5a;
5492 static const u8 dynamic_pd_threshold_max;
5493
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev)5494 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)
5495 {
5496 struct rtw89_dig_info *dig = &rtwdev->dig;
5497
5498 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
5499 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
5500 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
5501 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
5502 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
5503 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
5504
5505 dig->dyn_igi_max = igi_max_performance_mode;
5506 dig->dyn_igi_min = dynamic_igi_min;
5507 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
5508 dig->pd_low_th_ofst = pd_low_th_offset;
5509 dig->is_linked_pre = false;
5510 }
5511
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)5512 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
5513 {
5514 rtw89_phy_dig_update_gain_para(rtwdev);
5515 rtw89_phy_dig_reset(rtwdev);
5516 }
5517
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)5518 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
5519 {
5520 struct rtw89_dig_info *dig = &rtwdev->dig;
5521 u8 lna_idx;
5522
5523 if (rssi < dig->igi_rssi_th[0])
5524 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
5525 else if (rssi < dig->igi_rssi_th[1])
5526 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
5527 else if (rssi < dig->igi_rssi_th[2])
5528 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
5529 else if (rssi < dig->igi_rssi_th[3])
5530 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
5531 else if (rssi < dig->igi_rssi_th[4])
5532 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
5533 else
5534 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
5535
5536 return lna_idx;
5537 }
5538
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)5539 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
5540 {
5541 struct rtw89_dig_info *dig = &rtwdev->dig;
5542 u8 tia_idx;
5543
5544 if (rssi < dig->igi_rssi_th[0])
5545 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
5546 else
5547 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
5548
5549 return tia_idx;
5550 }
5551
5552 #define IB_PBK_BASE 110
5553 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)5554 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
5555 struct rtw89_agc_gaincode_set *set)
5556 {
5557 struct rtw89_dig_info *dig = &rtwdev->dig;
5558 s8 lna_gain = dig->lna_gain[set->lna_idx];
5559 s8 tia_gain = dig->tia_gain[set->tia_idx];
5560 s32 wb_rssi = rssi + lna_gain + tia_gain;
5561 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
5562 u8 rxb_idx;
5563
5564 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
5565 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
5566
5567 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
5568 wb_rssi, rxb_idx_tmp);
5569
5570 return rxb_idx;
5571 }
5572
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)5573 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
5574 struct rtw89_agc_gaincode_set *set)
5575 {
5576 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
5577 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
5578 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
5579
5580 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5581 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
5582 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
5583 }
5584
5585 #define IGI_OFFSET_MAX 25
5586 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev)5587 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
5588 {
5589 struct rtw89_dig_info *dig = &rtwdev->dig;
5590 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5591 enum rtw89_dig_noisy_level noisy_lv;
5592 u8 igi_offset = dig->fa_rssi_ofst;
5593 u16 fa_ratio = 0;
5594
5595 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
5596
5597 if (fa_ratio < dig->fa_th[0])
5598 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
5599 else if (fa_ratio < dig->fa_th[1])
5600 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
5601 else if (fa_ratio < dig->fa_th[2])
5602 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
5603 else if (fa_ratio < dig->fa_th[3])
5604 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
5605 else
5606 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
5607
5608 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
5609 igi_offset = 0;
5610 else
5611 igi_offset += noisy_lv * IGI_OFFSET_MUL;
5612
5613 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
5614 dig->fa_rssi_ofst = igi_offset;
5615
5616 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5617 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
5618 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
5619
5620 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5621 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
5622 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
5623 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
5624 noisy_lv, igi_offset);
5625 }
5626
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,u8 lna_idx)5627 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
5628 {
5629 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5630
5631 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr,
5632 dig_regs->p0_lna_init.mask, lna_idx);
5633 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr,
5634 dig_regs->p1_lna_init.mask, lna_idx);
5635 }
5636
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,u8 tia_idx)5637 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
5638 {
5639 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5640
5641 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr,
5642 dig_regs->p0_tia_init.mask, tia_idx);
5643 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr,
5644 dig_regs->p1_tia_init.mask, tia_idx);
5645 }
5646
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,u8 rxb_idx)5647 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
5648 {
5649 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5650
5651 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr,
5652 dig_regs->p0_rxb_init.mask, rxb_idx);
5653 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr,
5654 dig_regs->p1_rxb_init.mask, rxb_idx);
5655 }
5656
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,const struct rtw89_agc_gaincode_set set)5657 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
5658 const struct rtw89_agc_gaincode_set set)
5659 {
5660 if (!rtwdev->hal.support_igi)
5661 return;
5662
5663 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx);
5664 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx);
5665 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx);
5666
5667 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
5668 set.lna_idx, set.tia_idx, set.rxb_idx);
5669 }
5670
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,bool enable)5671 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
5672 bool enable)
5673 {
5674 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5675
5676 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
5677 dig_regs->p0_p20_pagcugc_en.mask, enable);
5678 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
5679 dig_regs->p0_s20_pagcugc_en.mask, enable);
5680 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
5681 dig_regs->p1_p20_pagcugc_en.mask, enable);
5682 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
5683 dig_regs->p1_s20_pagcugc_en.mask, enable);
5684
5685 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
5686 }
5687
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev)5688 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev)
5689 {
5690 struct rtw89_dig_info *dig = &rtwdev->dig;
5691
5692 if (!rtwdev->hal.support_igi)
5693 return;
5694
5695 if (dig->force_gaincode_idx_en) {
5696 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
5697 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5698 "Force gaincode index enabled.\n");
5699 } else {
5700 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
5701 &dig->cur_gaincode);
5702 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
5703 }
5704 }
5705
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,u8 rssi,bool enable)5706 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
5707 bool enable)
5708 {
5709 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
5710 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5711 enum rtw89_bandwidth cbw = chan->band_width;
5712 struct rtw89_dig_info *dig = &rtwdev->dig;
5713 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
5714 u8 ofdm_cca_th;
5715 s8 cck_cca_th;
5716 u32 pd_val = 0;
5717
5718 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
5719 under_region += PD_TH_SB_FLTR_CMP_VAL;
5720
5721 switch (cbw) {
5722 case RTW89_CHANNEL_WIDTH_40:
5723 under_region += PD_TH_BW40_CMP_VAL;
5724 break;
5725 case RTW89_CHANNEL_WIDTH_80:
5726 under_region += PD_TH_BW80_CMP_VAL;
5727 break;
5728 case RTW89_CHANNEL_WIDTH_160:
5729 under_region += PD_TH_BW160_CMP_VAL;
5730 break;
5731 case RTW89_CHANNEL_WIDTH_20:
5732 fallthrough;
5733 default:
5734 under_region += PD_TH_BW20_CMP_VAL;
5735 break;
5736 }
5737
5738 dig->dyn_pd_th_max = dig->igi_rssi;
5739
5740 final_rssi = min_t(u8, rssi, dig->igi_rssi);
5741 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
5742 PD_TH_MAX_RSSI + under_region);
5743
5744 if (enable) {
5745 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
5746 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5747 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
5748 final_rssi, ofdm_cca_th, under_region, pd_val);
5749 } else {
5750 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5751 "Dynamic PD th disabled, Set PD_low_bd=0\n");
5752 }
5753
5754 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
5755 dig_regs->pd_lower_bound_mask, pd_val);
5756 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
5757 dig_regs->pd_spatial_reuse_en, enable);
5758
5759 if (!rtwdev->hal.support_cckpd)
5760 return;
5761
5762 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
5763 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
5764
5765 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5766 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
5767 final_rssi, cck_cca_th, under_region, pd_val);
5768
5769 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg,
5770 dig_regs->bmode_cca_rssi_limit_en, enable);
5771 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
5772 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val);
5773 }
5774
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev)5775 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
5776 {
5777 struct rtw89_dig_info *dig = &rtwdev->dig;
5778
5779 dig->bypass_dig = false;
5780 rtw89_phy_dig_para_reset(rtwdev);
5781 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
5782 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false);
5783 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
5784 rtw89_phy_dig_update_para(rtwdev);
5785 }
5786
5787 #define IGI_RSSI_MIN 10
5788 #define ABS_IGI_MIN 0xc
rtw89_phy_dig(struct rtw89_dev * rtwdev)5789 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
5790 {
5791 struct rtw89_dig_info *dig = &rtwdev->dig;
5792 bool is_linked = rtwdev->total_sta_assoc > 0;
5793 u8 igi_min;
5794
5795 if (unlikely(dig->bypass_dig)) {
5796 dig->bypass_dig = false;
5797 return;
5798 }
5799
5800 rtw89_phy_dig_update_rssi_info(rtwdev);
5801
5802 if (!dig->is_linked_pre && is_linked) {
5803 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
5804 rtw89_phy_dig_update_para(rtwdev);
5805 dig->igi_fa_rssi = dig->igi_rssi;
5806 } else if (dig->is_linked_pre && !is_linked) {
5807 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
5808 rtw89_phy_dig_update_para(rtwdev);
5809 dig->igi_fa_rssi = dig->igi_rssi;
5810 }
5811 dig->is_linked_pre = is_linked;
5812
5813 rtw89_phy_dig_igi_offset_by_env(rtwdev);
5814
5815 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
5816 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
5817 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
5818
5819 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
5820 dig->igi_fa_rssi += dig->fa_rssi_ofst;
5821 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
5822 dig->dyn_igi_max);
5823 } else {
5824 dig->igi_fa_rssi = dig->dyn_igi_max;
5825 }
5826
5827 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5828 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
5829 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
5830 dig->igi_fa_rssi);
5831
5832 rtw89_phy_dig_config_igi(rtwdev);
5833
5834 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
5835
5836 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
5837 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true);
5838 else
5839 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
5840 }
5841
__rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)5842 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev,
5843 struct rtw89_sta_link *rtwsta_link)
5844 {
5845 struct rtw89_hal *hal = &rtwdev->hal;
5846 u8 rssi_a, rssi_b;
5847 u32 candidate;
5848
5849 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
5850 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
5851
5852 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
5853 candidate = RF_A;
5854 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
5855 candidate = RF_B;
5856 else
5857 return;
5858
5859 if (hal->antenna_tx == candidate)
5860 return;
5861
5862 hal->antenna_tx = candidate;
5863 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link);
5864
5865 if (hal->antenna_tx == RF_A) {
5866 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
5867 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
5868 } else if (hal->antenna_tx == RF_B) {
5869 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
5870 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
5871 }
5872 }
5873
rtw89_phy_tx_path_div_sta_iter(void * data,struct ieee80211_sta * sta)5874 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
5875 {
5876 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
5877 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
5878 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
5879 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
5880 struct rtw89_vif_link *rtwvif_link;
5881 struct rtw89_sta_link *rtwsta_link;
5882 unsigned int link_id;
5883 bool *done = data;
5884
5885 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n"))
5886 return;
5887
5888 if (sta->tdls)
5889 return;
5890
5891 if (*done)
5892 return;
5893
5894 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5895 rtwvif_link = rtwsta_link->rtwvif_link;
5896 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
5897 continue;
5898
5899 *done = true;
5900 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link);
5901 return;
5902 }
5903 }
5904
rtw89_phy_tx_path_div_track(struct rtw89_dev * rtwdev)5905 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
5906 {
5907 struct rtw89_hal *hal = &rtwdev->hal;
5908 bool done = false;
5909
5910 if (!hal->tx_path_diversity)
5911 return;
5912
5913 ieee80211_iterate_stations_atomic(rtwdev->hw,
5914 rtw89_phy_tx_path_div_sta_iter,
5915 &done);
5916 }
5917
5918 #define ANTDIV_MAIN 0
5919 #define ANTDIV_AUX 1
5920
rtw89_phy_antdiv_set_ant(struct rtw89_dev * rtwdev)5921 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
5922 {
5923 struct rtw89_hal *hal = &rtwdev->hal;
5924 u8 default_ant, optional_ant;
5925
5926 if (!hal->ant_diversity || hal->antenna_tx == 0)
5927 return;
5928
5929 if (hal->antenna_tx == RF_B) {
5930 default_ant = ANTDIV_AUX;
5931 optional_ant = ANTDIV_MAIN;
5932 } else {
5933 default_ant = ANTDIV_MAIN;
5934 optional_ant = ANTDIV_AUX;
5935 }
5936
5937 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
5938 default_ant, RTW89_PHY_0);
5939 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
5940 default_ant, RTW89_PHY_0);
5941 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
5942 optional_ant, RTW89_PHY_0);
5943 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
5944 default_ant, RTW89_PHY_0);
5945 }
5946
rtw89_phy_swap_hal_antenna(struct rtw89_dev * rtwdev)5947 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
5948 {
5949 struct rtw89_hal *hal = &rtwdev->hal;
5950
5951 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
5952 hal->antenna_tx = hal->antenna_rx;
5953 }
5954
rtw89_phy_antdiv_decision_state(struct rtw89_dev * rtwdev)5955 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
5956 {
5957 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5958 struct rtw89_hal *hal = &rtwdev->hal;
5959 bool no_change = false;
5960 u8 main_rssi, aux_rssi;
5961 u8 main_evm, aux_evm;
5962 u32 candidate;
5963
5964 antdiv->get_stats = false;
5965 antdiv->training_count = 0;
5966
5967 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
5968 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
5969 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
5970 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
5971
5972 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
5973 candidate = RF_A;
5974 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
5975 candidate = RF_B;
5976 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
5977 candidate = RF_A;
5978 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
5979 candidate = RF_B;
5980 else
5981 no_change = true;
5982
5983 if (no_change) {
5984 /* swap back from training antenna to original */
5985 rtw89_phy_swap_hal_antenna(rtwdev);
5986 return;
5987 }
5988
5989 hal->antenna_tx = candidate;
5990 hal->antenna_rx = candidate;
5991 }
5992
rtw89_phy_antdiv_training_state(struct rtw89_dev * rtwdev)5993 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
5994 {
5995 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5996 u64 state_period;
5997
5998 if (antdiv->training_count % 2 == 0) {
5999 if (antdiv->training_count == 0)
6000 rtw89_phy_antdiv_sts_reset(rtwdev);
6001
6002 antdiv->get_stats = true;
6003 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
6004 } else {
6005 antdiv->get_stats = false;
6006 state_period = msecs_to_jiffies(ANTDIV_DELAY);
6007
6008 rtw89_phy_swap_hal_antenna(rtwdev);
6009 rtw89_phy_antdiv_set_ant(rtwdev);
6010 }
6011
6012 antdiv->training_count++;
6013 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work,
6014 state_period);
6015 }
6016
rtw89_phy_antdiv_work(struct work_struct * work)6017 void rtw89_phy_antdiv_work(struct work_struct *work)
6018 {
6019 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
6020 antdiv_work.work);
6021 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6022
6023 mutex_lock(&rtwdev->mutex);
6024
6025 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
6026 rtw89_phy_antdiv_training_state(rtwdev);
6027 } else {
6028 rtw89_phy_antdiv_decision_state(rtwdev);
6029 rtw89_phy_antdiv_set_ant(rtwdev);
6030 }
6031
6032 mutex_unlock(&rtwdev->mutex);
6033 }
6034
rtw89_phy_antdiv_track(struct rtw89_dev * rtwdev)6035 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
6036 {
6037 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6038 struct rtw89_hal *hal = &rtwdev->hal;
6039 u8 rssi, rssi_pre;
6040
6041 if (!hal->ant_diversity || hal->ant_diversity_fixed)
6042 return;
6043
6044 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
6045 rssi_pre = antdiv->rssi_pre;
6046 antdiv->rssi_pre = rssi;
6047 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
6048
6049 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
6050 return;
6051
6052 antdiv->training_count = 0;
6053 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0);
6054 }
6055
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)6056 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
6057 {
6058 rtw89_phy_ccx_top_setting_init(rtwdev);
6059 rtw89_phy_ifs_clm_setting_init(rtwdev);
6060 }
6061
rtw89_phy_edcca_init(struct rtw89_dev * rtwdev)6062 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
6063 {
6064 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6065 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6066
6067 memset(edcca_bak, 0, sizeof(*edcca_bak));
6068
6069 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
6070 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
6071 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
6072 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
6073 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
6074 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
6075 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
6076 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
6077 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
6078 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
6079 }
6080
6081 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st,
6082 edcca_regs->tx_collision_t2r_st_mask, 0x29);
6083 }
6084
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)6085 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
6086 {
6087 rtw89_phy_stat_init(rtwdev);
6088
6089 rtw89_chip_bb_sethw(rtwdev);
6090
6091 rtw89_phy_env_monitor_init(rtwdev);
6092 rtw89_physts_parsing_init(rtwdev);
6093 rtw89_phy_dig_init(rtwdev);
6094 rtw89_phy_cfo_init(rtwdev);
6095 rtw89_phy_bb_wrap_init(rtwdev);
6096 rtw89_phy_edcca_init(rtwdev);
6097 rtw89_phy_ch_info_init(rtwdev);
6098 rtw89_phy_ul_tb_info_init(rtwdev);
6099 rtw89_phy_antdiv_init(rtwdev);
6100 rtw89_chip_rfe_gpio(rtwdev);
6101 rtw89_phy_antdiv_set_ant(rtwdev);
6102
6103 rtw89_chip_rfk_hw_init(rtwdev);
6104 rtw89_phy_init_rf_nctl(rtwdev);
6105 rtw89_chip_rfk_init(rtwdev);
6106 rtw89_chip_set_txpwr_ctrl(rtwdev);
6107 rtw89_chip_power_trim(rtwdev);
6108 rtw89_chip_cfg_txrx_path(rtwdev);
6109 }
6110
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6111 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
6112 struct rtw89_vif_link *rtwvif_link)
6113 {
6114 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6115 const struct rtw89_chip_info *chip = rtwdev->chip;
6116 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
6117 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
6118 struct ieee80211_bss_conf *bss_conf;
6119 u8 bss_color;
6120
6121 rcu_read_lock();
6122
6123 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6124 if (!bss_conf->he_support || !vif->cfg.assoc) {
6125 rcu_read_unlock();
6126 return;
6127 }
6128
6129 bss_color = bss_conf->he_bss_color.color;
6130
6131 rcu_read_unlock();
6132
6133 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
6134 phy_idx);
6135 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
6136 bss_color, phy_idx);
6137 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
6138 vif->cfg.aid, phy_idx);
6139 }
6140
rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc * desc)6141 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
6142 {
6143 return desc->ch != 0;
6144 }
6145
rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc * desc,const struct rtw89_chan * chan)6146 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
6147 const struct rtw89_chan *chan)
6148 {
6149 if (!rfk_chan_validate_desc(desc))
6150 return false;
6151
6152 if (desc->ch != chan->channel)
6153 return false;
6154
6155 if (desc->has_band && desc->band != chan->band_type)
6156 return false;
6157
6158 if (desc->has_bw && desc->bw != chan->band_width)
6159 return false;
6160
6161 return true;
6162 }
6163
6164 struct rfk_chan_iter_data {
6165 const struct rtw89_rfk_chan_desc desc;
6166 unsigned int found;
6167 };
6168
rfk_chan_iter_search(const struct rtw89_chan * chan,void * data)6169 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
6170 {
6171 struct rfk_chan_iter_data *iter_data = data;
6172
6173 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
6174 iter_data->found++;
6175
6176 return 0;
6177 }
6178
rtw89_rfk_chan_lookup(struct rtw89_dev * rtwdev,const struct rtw89_rfk_chan_desc * desc,u8 desc_nr,const struct rtw89_chan * target_chan)6179 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
6180 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
6181 const struct rtw89_chan *target_chan)
6182 {
6183 int sel = -1;
6184 u8 i;
6185
6186 for (i = 0; i < desc_nr; i++) {
6187 struct rfk_chan_iter_data iter_data = {
6188 .desc = desc[i],
6189 };
6190
6191 if (rfk_chan_is_equivalent(&desc[i], target_chan))
6192 return i;
6193
6194 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
6195 if (!iter_data.found && sel == -1)
6196 sel = i;
6197 }
6198
6199 if (sel == -1) {
6200 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6201 "no idle rfk entry; force replace the first\n");
6202 sel = 0;
6203 }
6204
6205 return sel;
6206 }
6207 EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
6208
6209 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6210 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6211 {
6212 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
6213 }
6214
6215 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6216 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6217 {
6218 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
6219 }
6220
6221 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6222 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6223 {
6224 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
6225 }
6226
6227 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6228 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6229 {
6230 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
6231 }
6232
6233 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6234 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6235 {
6236 udelay(def->data);
6237 }
6238
6239 static void
6240 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
6241 [RTW89_RFK_F_WRF] = _rfk_write_rf,
6242 [RTW89_RFK_F_WM] = _rfk_write32_mask,
6243 [RTW89_RFK_F_WS] = _rfk_write32_set,
6244 [RTW89_RFK_F_WC] = _rfk_write32_clr,
6245 [RTW89_RFK_F_DELAY] = _rfk_delay,
6246 };
6247
6248 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
6249
6250 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)6251 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
6252 {
6253 const struct rtw89_reg5_def *p = tbl->defs;
6254 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
6255
6256 for (; p < end; p++)
6257 _rfk_handler[p->flag](rtwdev, p);
6258 }
6259 EXPORT_SYMBOL(rtw89_rfk_parser);
6260
6261 #define RTW89_TSSI_FAST_MODE_NUM 4
6262
6263 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
6264 {0xD934, 0xff0000},
6265 {0xD934, 0xff000000},
6266 {0xD938, 0xff},
6267 {0xD934, 0xff00},
6268 };
6269
6270 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
6271 {0xD930, 0xff0000},
6272 {0xD930, 0xff000000},
6273 {0xD934, 0xff},
6274 {0xD930, 0xff00},
6275 };
6276
6277 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)6278 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
6279 enum rtw89_mac_idx mac_idx,
6280 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
6281 u32 val)
6282 {
6283 const struct rtw89_reg_def *regs;
6284 u32 reg;
6285 int i;
6286
6287 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
6288 regs = rtw89_tssi_fastmode_regs_flat;
6289 else
6290 regs = rtw89_tssi_fastmode_regs_level;
6291
6292 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
6293 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6294 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
6295 }
6296 }
6297
6298 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
6299 {0xD91C, 0xff000000},
6300 {0xD920, 0xff},
6301 {0xD920, 0xff00},
6302 {0xD920, 0xff0000},
6303 {0xD920, 0xff000000},
6304 {0xD924, 0xff},
6305 {0xD924, 0xff00},
6306 {0xD914, 0xff000000},
6307 {0xD918, 0xff},
6308 {0xD918, 0xff00},
6309 {0xD918, 0xff0000},
6310 {0xD918, 0xff000000},
6311 {0xD91C, 0xff},
6312 {0xD91C, 0xff00},
6313 {0xD91C, 0xff0000},
6314 };
6315
6316 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
6317 {0xD910, 0xff},
6318 {0xD910, 0xff00},
6319 {0xD910, 0xff0000},
6320 {0xD910, 0xff000000},
6321 {0xD914, 0xff},
6322 {0xD914, 0xff00},
6323 {0xD914, 0xff0000},
6324 {0xD908, 0xff},
6325 {0xD908, 0xff00},
6326 {0xD908, 0xff0000},
6327 {0xD908, 0xff000000},
6328 {0xD90C, 0xff},
6329 {0xD90C, 0xff00},
6330 {0xD90C, 0xff0000},
6331 {0xD90C, 0xff000000},
6332 };
6333
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)6334 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
6335 enum rtw89_mac_idx mac_idx,
6336 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
6337 {
6338 const struct rtw89_chip_info *chip = rtwdev->chip;
6339 const struct rtw89_reg_def *regs;
6340 const u32 *data;
6341 u32 reg;
6342 int i;
6343
6344 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
6345 return;
6346
6347 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
6348 regs = rtw89_tssi_bandedge_regs_flat;
6349 else
6350 regs = rtw89_tssi_bandedge_regs_level;
6351
6352 data = chip->tssi_dbw_table->data[bandedge_cfg];
6353
6354 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
6355 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6356 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
6357 }
6358
6359 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
6360 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
6361
6362 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
6363 data[RTW89_TSSI_SBW20]);
6364 }
6365 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
6366
6367 static
6368 const u8 rtw89_ch_base_table[16] = {1, 0xff,
6369 36, 100, 132, 149, 0xff,
6370 1, 33, 65, 97, 129, 161, 193, 225, 0xff};
6371 #define RTW89_CH_BASE_IDX_2G 0
6372 #define RTW89_CH_BASE_IDX_5G_FIRST 2
6373 #define RTW89_CH_BASE_IDX_5G_LAST 5
6374 #define RTW89_CH_BASE_IDX_6G_FIRST 7
6375 #define RTW89_CH_BASE_IDX_6G_LAST 14
6376
6377 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)
6378 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0)
6379
rtw89_encode_chan_idx(struct rtw89_dev * rtwdev,u8 central_ch,u8 band)6380 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
6381 {
6382 u8 chan_idx;
6383 u8 last, first;
6384 u8 idx;
6385
6386 switch (band) {
6387 case RTW89_BAND_2G:
6388 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) |
6389 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch);
6390 return chan_idx;
6391 case RTW89_BAND_5G:
6392 first = RTW89_CH_BASE_IDX_5G_FIRST;
6393 last = RTW89_CH_BASE_IDX_5G_LAST;
6394 break;
6395 case RTW89_BAND_6G:
6396 first = RTW89_CH_BASE_IDX_6G_FIRST;
6397 last = RTW89_CH_BASE_IDX_6G_LAST;
6398 break;
6399 default:
6400 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
6401 return 0;
6402 }
6403
6404 for (idx = last; idx >= first; idx--)
6405 if (central_ch >= rtw89_ch_base_table[idx])
6406 break;
6407
6408 if (idx < first) {
6409 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
6410 return 0;
6411 }
6412
6413 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) |
6414 FIELD_PREP(RTW89_CH_OFFSET_MASK,
6415 (central_ch - rtw89_ch_base_table[idx]) >> 1);
6416 return chan_idx;
6417 }
6418 EXPORT_SYMBOL(rtw89_encode_chan_idx);
6419
rtw89_decode_chan_idx(struct rtw89_dev * rtwdev,u8 chan_idx,u8 * ch,enum nl80211_band * band)6420 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
6421 u8 *ch, enum nl80211_band *band)
6422 {
6423 u8 idx, offset;
6424
6425 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx);
6426 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx);
6427
6428 if (idx == RTW89_CH_BASE_IDX_2G) {
6429 *band = NL80211_BAND_2GHZ;
6430 *ch = offset;
6431 return;
6432 }
6433
6434 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
6435 *ch = rtw89_ch_base_table[idx] + (offset << 1);
6436 }
6437 EXPORT_SYMBOL(rtw89_decode_chan_idx);
6438
rtw89_phy_config_edcca(struct rtw89_dev * rtwdev,bool scan)6439 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan)
6440 {
6441 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6442 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6443
6444 if (scan) {
6445 edcca_bak->a =
6446 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6447 edcca_regs->edcca_mask);
6448 edcca_bak->p =
6449 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6450 edcca_regs->edcca_p_mask);
6451 edcca_bak->ppdu =
6452 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level,
6453 edcca_regs->ppdu_mask);
6454
6455 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6456 edcca_regs->edcca_mask, EDCCA_MAX);
6457 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6458 edcca_regs->edcca_p_mask, EDCCA_MAX);
6459 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6460 edcca_regs->ppdu_mask, EDCCA_MAX);
6461 } else {
6462 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6463 edcca_regs->edcca_mask,
6464 edcca_bak->a);
6465 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6466 edcca_regs->edcca_p_mask,
6467 edcca_bak->p);
6468 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6469 edcca_regs->ppdu_mask,
6470 edcca_bak->ppdu);
6471 }
6472 }
6473
rtw89_phy_edcca_log(struct rtw89_dev * rtwdev)6474 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev)
6475 {
6476 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6477 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
6478 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
6479 u8 path, per20_bitmap;
6480 u8 pwdb[8];
6481 u32 tmp;
6482
6483 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
6484 return;
6485
6486 if (rtwdev->chip->chip_id == RTL8922A)
6487 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6488 edcca_regs->rpt_sel_be_mask, 0);
6489
6490 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6491 edcca_regs->rpt_sel_mask, 0);
6492 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6493 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
6494 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
6495 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
6496 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20);
6497 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20);
6498 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB);
6499 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1);
6500 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
6501 pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
6502
6503 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6504 edcca_regs->rpt_sel_mask, 4);
6505 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6506 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
6507 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
6508
6509 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a,
6510 MASKBYTE0);
6511
6512 if (rtwdev->chip->chip_id == RTL8922A) {
6513 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6514 edcca_regs->rpt_sel_be_mask, 4);
6515 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6516 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
6517 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
6518 pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
6519 pwdb[3] = u32_get_bits(tmp, MASKBYTE0);
6520
6521 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6522 edcca_regs->rpt_sel_be_mask, 5);
6523 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6524 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
6525 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
6526 pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
6527 pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
6528 } else {
6529 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6530 edcca_regs->rpt_sel_mask, 0);
6531 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6532 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
6533 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
6534
6535 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6536 edcca_regs->rpt_sel_mask, 1);
6537 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6538 pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
6539 pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
6540
6541 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6542 edcca_regs->rpt_sel_mask, 2);
6543 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6544 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
6545 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
6546
6547 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6548 edcca_regs->rpt_sel_mask, 3);
6549 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6550 pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
6551 pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
6552 }
6553
6554 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6555 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap);
6556
6557 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6558 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
6559 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5],
6560 pwdb[6], pwdb[7]);
6561
6562 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6563 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n",
6564 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80);
6565
6566 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6567 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n",
6568 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80);
6569 }
6570
rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev * rtwdev)6571 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev)
6572 {
6573 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
6574 bool is_linked = rtwdev->total_sta_assoc > 0;
6575 u8 rssi_min = ch_info->rssi_min >> 1;
6576 u8 edcca_thre;
6577
6578 if (!is_linked) {
6579 edcca_thre = EDCCA_MAX;
6580 } else {
6581 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
6582 EDCCA_TH_REF;
6583 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB);
6584 }
6585
6586 return edcca_thre;
6587 }
6588
rtw89_phy_edcca_thre_calc(struct rtw89_dev * rtwdev)6589 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev)
6590 {
6591 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6592 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6593 u8 th;
6594
6595 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev);
6596 if (th == edcca_bak->th_old)
6597 return;
6598
6599 edcca_bak->th_old = th;
6600
6601 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6602 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th);
6603
6604 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6605 edcca_regs->edcca_mask, th);
6606 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6607 edcca_regs->edcca_p_mask, th);
6608 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6609 edcca_regs->ppdu_mask, th);
6610 }
6611
rtw89_phy_edcca_track(struct rtw89_dev * rtwdev)6612 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
6613 {
6614 struct rtw89_hal *hal = &rtwdev->hal;
6615
6616 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
6617 return;
6618
6619 rtw89_phy_edcca_thre_calc(rtwdev);
6620 rtw89_phy_edcca_log(rtwdev);
6621 }
6622
rtw89_phy_get_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6623 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
6624 enum rtw89_phy_idx phy_idx)
6625 {
6626 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6627 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
6628 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
6629
6630 switch (rtwdev->mlo_dbcc_mode) {
6631 case MLO_1_PLUS_1_1RF:
6632 if (phy_idx == RTW89_PHY_0)
6633 return RF_A;
6634 else
6635 return RF_B;
6636 case MLO_1_PLUS_1_2RF:
6637 if (phy_idx == RTW89_PHY_0)
6638 return RF_A;
6639 else
6640 return RF_D;
6641 case MLO_0_PLUS_2_1RF:
6642 case MLO_2_PLUS_0_1RF:
6643 /* for both PHY 0/1 */
6644 return RF_AB;
6645 case MLO_0_PLUS_2_2RF:
6646 case MLO_2_PLUS_0_2RF:
6647 case MLO_2_PLUS_2_2RF:
6648 default:
6649 if (phy_idx == RTW89_PHY_0)
6650 return RF_AB;
6651 else
6652 return RF_CD;
6653 }
6654 }
6655 EXPORT_SYMBOL(rtw89_phy_get_kpath);
6656
rtw89_phy_get_syn_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6657 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
6658 enum rtw89_phy_idx phy_idx)
6659 {
6660 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6661 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
6662 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
6663
6664 switch (rtwdev->mlo_dbcc_mode) {
6665 case MLO_1_PLUS_1_1RF:
6666 if (phy_idx == RTW89_PHY_0)
6667 return RF_PATH_A;
6668 else
6669 return RF_PATH_B;
6670 case MLO_1_PLUS_1_2RF:
6671 if (phy_idx == RTW89_PHY_0)
6672 return RF_PATH_A;
6673 else
6674 return RF_PATH_D;
6675 case MLO_0_PLUS_2_1RF:
6676 case MLO_2_PLUS_0_1RF:
6677 if (phy_idx == RTW89_PHY_0)
6678 return RF_PATH_A;
6679 else
6680 return RF_PATH_B;
6681 case MLO_0_PLUS_2_2RF:
6682 case MLO_2_PLUS_0_2RF:
6683 case MLO_2_PLUS_2_2RF:
6684 default:
6685 if (phy_idx == RTW89_PHY_0)
6686 return RF_PATH_A;
6687 else
6688 return RF_PATH_C;
6689 }
6690 }
6691 EXPORT_SYMBOL(rtw89_phy_get_syn_sel);
6692
6693 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
6694 .setting_addr = R_CCX,
6695 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
6696 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
6697 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
6698 .en_mask = B_CCX_EN_MSK,
6699 .ifs_cnt_addr = R_IFS_COUNTER,
6700 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
6701 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
6702 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
6703 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
6704 .ifs_t1_addr = R_IFS_T1,
6705 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
6706 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
6707 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
6708 .ifs_t2_addr = R_IFS_T2,
6709 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
6710 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
6711 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
6712 .ifs_t3_addr = R_IFS_T3,
6713 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
6714 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
6715 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
6716 .ifs_t4_addr = R_IFS_T4,
6717 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
6718 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
6719 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
6720 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
6721 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
6722 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
6723 .ifs_clm_cca_addr = R_IFS_CLM_CCA,
6724 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
6725 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
6726 .ifs_clm_fa_addr = R_IFS_CLM_FA,
6727 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
6728 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
6729 .ifs_his_addr = R_IFS_HIS,
6730 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
6731 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
6732 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
6733 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
6734 .ifs_avg_l_addr = R_IFS_AVG_L,
6735 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
6736 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
6737 .ifs_avg_h_addr = R_IFS_AVG_H,
6738 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
6739 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
6740 .ifs_cca_l_addr = R_IFS_CCA_L,
6741 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
6742 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
6743 .ifs_cca_h_addr = R_IFS_CCA_H,
6744 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
6745 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
6746 .ifs_total_addr = R_IFSCNT,
6747 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
6748 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
6749 };
6750
6751 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
6752 .setting_addr = R_PLCP_HISTOGRAM,
6753 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
6754 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
6755 };
6756
6757 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
6758 .comp = R_DCFO_WEIGHT,
6759 .weighting_mask = B_DCFO_WEIGHT_MSK,
6760 .comp_seg0 = R_DCFO_OPT,
6761 .valid_0_mask = B_DCFO_OPT_EN,
6762 };
6763
6764 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
6765 .cr_base = 0x10000,
6766 .ccx = &rtw89_ccx_regs_ax,
6767 .physts = &rtw89_physts_regs_ax,
6768 .cfo = &rtw89_cfo_regs_ax,
6769 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
6770 .config_bb_gain = rtw89_phy_config_bb_gain_ax,
6771 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
6772 .bb_wrap_init = NULL,
6773 .ch_info_init = NULL,
6774
6775 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
6776 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
6777 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax,
6778 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax,
6779 };
6780 EXPORT_SYMBOL(rtw89_phy_gen_ax);
6781