1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Rockchip SoCs.
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
7 *
8 * Author: Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #include "pcie-designware.h"
25
26 /*
27 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write
28 * mask for the lower 16 bits.
29 */
30 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
31 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
33
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
35
36 #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
37 #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
38 #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
39 #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
40 #define PCIE_CLIENT_INTR_STATUS_MISC 0x10
41 #define PCIE_CLIENT_INTR_MASK_MISC 0x24
42 #define PCIE_SMLH_LINKUP BIT(16)
43 #define PCIE_RDLH_LINKUP BIT(17)
44 #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
45 #define PCIE_RDLH_LINK_UP_CHGED BIT(1)
46 #define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
47 #define PCIE_CLIENT_GENERAL_CONTROL 0x0
48 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
49 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
50 #define PCIE_CLIENT_GENERAL_DEBUG 0x104
51 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
52 #define PCIE_CLIENT_LTSSM_STATUS 0x300
53 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
54 #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
55
56 struct rockchip_pcie {
57 struct dw_pcie pci;
58 void __iomem *apb_base;
59 struct phy *phy;
60 struct clk_bulk_data *clks;
61 unsigned int clk_cnt;
62 struct reset_control *rst;
63 struct gpio_desc *rst_gpio;
64 struct regulator *vpcie3v3;
65 struct irq_domain *irq_domain;
66 const struct rockchip_pcie_of_data *data;
67 };
68
69 struct rockchip_pcie_of_data {
70 enum dw_pcie_device_mode mode;
71 const struct pci_epc_features *epc_features;
72 };
73
rockchip_pcie_readl_apb(struct rockchip_pcie * rockchip,u32 reg)74 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
75 {
76 return readl_relaxed(rockchip->apb_base + reg);
77 }
78
rockchip_pcie_writel_apb(struct rockchip_pcie * rockchip,u32 val,u32 reg)79 static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,
80 u32 reg)
81 {
82 writel_relaxed(val, rockchip->apb_base + reg);
83 }
84
rockchip_pcie_intx_handler(struct irq_desc * desc)85 static void rockchip_pcie_intx_handler(struct irq_desc *desc)
86 {
87 struct irq_chip *chip = irq_desc_get_chip(desc);
88 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
89 unsigned long reg, hwirq;
90
91 chained_irq_enter(chip, desc);
92
93 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
94
95 for_each_set_bit(hwirq, ®, 4)
96 generic_handle_domain_irq(rockchip->irq_domain, hwirq);
97
98 chained_irq_exit(chip, desc);
99 }
100
rockchip_intx_mask(struct irq_data * data)101 static void rockchip_intx_mask(struct irq_data *data)
102 {
103 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
104 HIWORD_UPDATE_BIT(BIT(data->hwirq)),
105 PCIE_CLIENT_INTR_MASK_LEGACY);
106 };
107
rockchip_intx_unmask(struct irq_data * data)108 static void rockchip_intx_unmask(struct irq_data *data)
109 {
110 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
111 HIWORD_DISABLE_BIT(BIT(data->hwirq)),
112 PCIE_CLIENT_INTR_MASK_LEGACY);
113 };
114
115 static struct irq_chip rockchip_intx_irq_chip = {
116 .name = "INTx",
117 .irq_mask = rockchip_intx_mask,
118 .irq_unmask = rockchip_intx_unmask,
119 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
120 };
121
rockchip_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)122 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
123 irq_hw_number_t hwirq)
124 {
125 irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
126 irq_set_chip_data(irq, domain->host_data);
127
128 return 0;
129 }
130
131 static const struct irq_domain_ops intx_domain_ops = {
132 .map = rockchip_pcie_intx_map,
133 };
134
rockchip_pcie_init_irq_domain(struct rockchip_pcie * rockchip)135 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
136 {
137 struct device *dev = rockchip->pci.dev;
138 struct device_node *intc;
139
140 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
141 if (!intc) {
142 dev_err(dev, "missing child interrupt-controller node\n");
143 return -EINVAL;
144 }
145
146 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
147 &intx_domain_ops, rockchip);
148 of_node_put(intc);
149 if (!rockchip->irq_domain) {
150 dev_err(dev, "failed to get a INTx IRQ domain\n");
151 return -EINVAL;
152 }
153
154 return 0;
155 }
156
rockchip_pcie_get_ltssm(struct rockchip_pcie * rockchip)157 static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
158 {
159 return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
160 }
161
rockchip_pcie_enable_ltssm(struct rockchip_pcie * rockchip)162 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
163 {
164 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
165 PCIE_CLIENT_GENERAL_CONTROL);
166 }
167
rockchip_pcie_disable_ltssm(struct rockchip_pcie * rockchip)168 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
169 {
170 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
171 PCIE_CLIENT_GENERAL_CONTROL);
172 }
173
rockchip_pcie_link_up(struct dw_pcie * pci)174 static int rockchip_pcie_link_up(struct dw_pcie *pci)
175 {
176 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
177 u32 val = rockchip_pcie_get_ltssm(rockchip);
178
179 if ((val & PCIE_LINKUP) == PCIE_LINKUP)
180 return 1;
181
182 return 0;
183 }
184
rockchip_pcie_start_link(struct dw_pcie * pci)185 static int rockchip_pcie_start_link(struct dw_pcie *pci)
186 {
187 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
188
189 /* Reset device */
190 gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
191
192 rockchip_pcie_enable_ltssm(rockchip);
193
194 /*
195 * PCIe requires the refclk to be stable for 100µs prior to releasing
196 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
197 * Express Card Electromechanical Specification, 1.1. However, we don't
198 * know if the refclk is coming from RC's PHY or external OSC. If it's
199 * from RC, so enabling LTSSM is the just right place to release #PERST.
200 * We need more extra time as before, rather than setting just
201 * 100us as we don't know how long should the device need to reset.
202 */
203 msleep(100);
204 gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
205
206 return 0;
207 }
208
rockchip_pcie_stop_link(struct dw_pcie * pci)209 static void rockchip_pcie_stop_link(struct dw_pcie *pci)
210 {
211 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
212
213 rockchip_pcie_disable_ltssm(rockchip);
214 }
215
rockchip_pcie_host_init(struct dw_pcie_rp * pp)216 static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
217 {
218 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
219 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
220 struct device *dev = rockchip->pci.dev;
221 int irq, ret;
222
223 irq = of_irq_get_byname(dev->of_node, "legacy");
224 if (irq < 0)
225 return irq;
226
227 ret = rockchip_pcie_init_irq_domain(rockchip);
228 if (ret < 0)
229 dev_err(dev, "failed to init irq domain\n");
230
231 irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
232 rockchip);
233
234 return 0;
235 }
236
237 static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
238 .init = rockchip_pcie_host_init,
239 };
240
rockchip_pcie_ep_init(struct dw_pcie_ep * ep)241 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
242 {
243 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
244 enum pci_barno bar;
245
246 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
247 dw_pcie_ep_reset_bar(pci, bar);
248 };
249
rockchip_pcie_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)250 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
251 unsigned int type, u16 interrupt_num)
252 {
253 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
254
255 switch (type) {
256 case PCI_IRQ_INTX:
257 return dw_pcie_ep_raise_intx_irq(ep, func_no);
258 case PCI_IRQ_MSI:
259 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
260 case PCI_IRQ_MSIX:
261 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
262 default:
263 dev_err(pci->dev, "UNKNOWN IRQ type\n");
264 }
265
266 return 0;
267 }
268
269 static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
270 .linkup_notifier = true,
271 .msi_capable = true,
272 .msix_capable = true,
273 .align = SZ_64K,
274 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
275 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
276 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
277 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
278 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
279 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
280 };
281
282 /*
283 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
284 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
285 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by
286 * default.) If the host could write to BAR4, the iATU settings (for all other
287 * BARs) would be overwritten, resulting in (all other BARs) no longer working.
288 */
289 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
290 .linkup_notifier = true,
291 .msi_capable = true,
292 .msix_capable = true,
293 .align = SZ_64K,
294 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
295 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
296 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
297 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
298 .bar[BAR_4] = { .type = BAR_RESERVED, },
299 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
300 };
301
302 static const struct pci_epc_features *
rockchip_pcie_get_features(struct dw_pcie_ep * ep)303 rockchip_pcie_get_features(struct dw_pcie_ep *ep)
304 {
305 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
306 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
307
308 return rockchip->data->epc_features;
309 }
310
311 static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
312 .init = rockchip_pcie_ep_init,
313 .raise_irq = rockchip_pcie_raise_irq,
314 .get_features = rockchip_pcie_get_features,
315 };
316
rockchip_pcie_clk_init(struct rockchip_pcie * rockchip)317 static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
318 {
319 struct device *dev = rockchip->pci.dev;
320 int ret;
321
322 ret = devm_clk_bulk_get_all(dev, &rockchip->clks);
323 if (ret < 0)
324 return dev_err_probe(dev, ret, "failed to get clocks\n");
325
326 rockchip->clk_cnt = ret;
327
328 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);
329 if (ret)
330 return dev_err_probe(dev, ret, "failed to enable clocks\n");
331
332 return 0;
333 }
334
rockchip_pcie_resource_get(struct platform_device * pdev,struct rockchip_pcie * rockchip)335 static int rockchip_pcie_resource_get(struct platform_device *pdev,
336 struct rockchip_pcie *rockchip)
337 {
338 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
339 if (IS_ERR(rockchip->apb_base))
340 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base),
341 "failed to map apb registers\n");
342
343 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
344 GPIOD_OUT_LOW);
345 if (IS_ERR(rockchip->rst_gpio))
346 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio),
347 "failed to get reset gpio\n");
348
349 rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
350 if (IS_ERR(rockchip->rst))
351 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
352 "failed to get reset lines\n");
353
354 return 0;
355 }
356
rockchip_pcie_phy_init(struct rockchip_pcie * rockchip)357 static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
358 {
359 struct device *dev = rockchip->pci.dev;
360 int ret;
361
362 rockchip->phy = devm_phy_get(dev, "pcie-phy");
363 if (IS_ERR(rockchip->phy))
364 return dev_err_probe(dev, PTR_ERR(rockchip->phy),
365 "missing PHY\n");
366
367 ret = phy_init(rockchip->phy);
368 if (ret < 0)
369 return ret;
370
371 ret = phy_power_on(rockchip->phy);
372 if (ret)
373 phy_exit(rockchip->phy);
374
375 return ret;
376 }
377
rockchip_pcie_phy_deinit(struct rockchip_pcie * rockchip)378 static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
379 {
380 phy_power_off(rockchip->phy);
381 phy_exit(rockchip->phy);
382 }
383
384 static const struct dw_pcie_ops dw_pcie_ops = {
385 .link_up = rockchip_pcie_link_up,
386 .start_link = rockchip_pcie_start_link,
387 .stop_link = rockchip_pcie_stop_link,
388 };
389
rockchip_pcie_ep_sys_irq_thread(int irq,void * arg)390 static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
391 {
392 struct rockchip_pcie *rockchip = arg;
393 struct dw_pcie *pci = &rockchip->pci;
394 struct device *dev = pci->dev;
395 u32 reg, val;
396
397 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
398 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
399
400 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
401 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
402
403 if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
404 dev_dbg(dev, "hot reset or link-down reset\n");
405 dw_pcie_ep_linkdown(&pci->ep);
406 }
407
408 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
409 val = rockchip_pcie_get_ltssm(rockchip);
410 if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
411 dev_dbg(dev, "link up\n");
412 dw_pcie_ep_linkup(&pci->ep);
413 }
414 }
415
416 return IRQ_HANDLED;
417 }
418
rockchip_pcie_configure_rc(struct rockchip_pcie * rockchip)419 static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip)
420 {
421 struct dw_pcie_rp *pp;
422 u32 val;
423
424 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))
425 return -ENODEV;
426
427 /* LTSSM enable control mode */
428 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
429 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
430
431 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
432 PCIE_CLIENT_GENERAL_CONTROL);
433
434 pp = &rockchip->pci.pp;
435 pp->ops = &rockchip_pcie_host_ops;
436
437 return dw_pcie_host_init(pp);
438 }
439
rockchip_pcie_configure_ep(struct platform_device * pdev,struct rockchip_pcie * rockchip)440 static int rockchip_pcie_configure_ep(struct platform_device *pdev,
441 struct rockchip_pcie *rockchip)
442 {
443 struct device *dev = &pdev->dev;
444 int irq, ret;
445 u32 val;
446
447 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
448 return -ENODEV;
449
450 irq = platform_get_irq_byname(pdev, "sys");
451 if (irq < 0) {
452 dev_err(dev, "missing sys IRQ resource\n");
453 return irq;
454 }
455
456 ret = devm_request_threaded_irq(dev, irq, NULL,
457 rockchip_pcie_ep_sys_irq_thread,
458 IRQF_ONESHOT, "pcie-sys", rockchip);
459 if (ret) {
460 dev_err(dev, "failed to request PCIe sys IRQ\n");
461 return ret;
462 }
463
464 /* LTSSM enable control mode */
465 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
466 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
467
468 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
469 PCIE_CLIENT_GENERAL_CONTROL);
470
471 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
472 rockchip->pci.ep.page_size = SZ_64K;
473
474 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
475
476 ret = dw_pcie_ep_init(&rockchip->pci.ep);
477 if (ret) {
478 dev_err(dev, "failed to initialize endpoint\n");
479 return ret;
480 }
481
482 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);
483 if (ret) {
484 dev_err(dev, "failed to initialize DWC endpoint registers\n");
485 dw_pcie_ep_deinit(&rockchip->pci.ep);
486 return ret;
487 }
488
489 pci_epc_init_notify(rockchip->pci.ep.epc);
490
491 /* unmask DLL up/down indicator and hot reset/link-down reset */
492 rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC);
493
494 return ret;
495 }
496
rockchip_pcie_probe(struct platform_device * pdev)497 static int rockchip_pcie_probe(struct platform_device *pdev)
498 {
499 struct device *dev = &pdev->dev;
500 struct rockchip_pcie *rockchip;
501 const struct rockchip_pcie_of_data *data;
502 int ret;
503
504 data = of_device_get_match_data(dev);
505 if (!data)
506 return -EINVAL;
507
508 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
509 if (!rockchip)
510 return -ENOMEM;
511
512 platform_set_drvdata(pdev, rockchip);
513
514 rockchip->pci.dev = dev;
515 rockchip->pci.ops = &dw_pcie_ops;
516 rockchip->data = data;
517
518 ret = rockchip_pcie_resource_get(pdev, rockchip);
519 if (ret)
520 return ret;
521
522 ret = reset_control_assert(rockchip->rst);
523 if (ret)
524 return ret;
525
526 /* DON'T MOVE ME: must be enable before PHY init */
527 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
528 if (IS_ERR(rockchip->vpcie3v3)) {
529 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
530 return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
531 "failed to get vpcie3v3 regulator\n");
532 rockchip->vpcie3v3 = NULL;
533 } else {
534 ret = regulator_enable(rockchip->vpcie3v3);
535 if (ret)
536 return dev_err_probe(dev, ret,
537 "failed to enable vpcie3v3 regulator\n");
538 }
539
540 ret = rockchip_pcie_phy_init(rockchip);
541 if (ret)
542 goto disable_regulator;
543
544 ret = reset_control_deassert(rockchip->rst);
545 if (ret)
546 goto deinit_phy;
547
548 ret = rockchip_pcie_clk_init(rockchip);
549 if (ret)
550 goto deinit_phy;
551
552 switch (data->mode) {
553 case DW_PCIE_RC_TYPE:
554 ret = rockchip_pcie_configure_rc(rockchip);
555 if (ret)
556 goto deinit_clk;
557 break;
558 case DW_PCIE_EP_TYPE:
559 ret = rockchip_pcie_configure_ep(pdev, rockchip);
560 if (ret)
561 goto deinit_clk;
562 break;
563 default:
564 dev_err(dev, "INVALID device type %d\n", data->mode);
565 ret = -EINVAL;
566 goto deinit_clk;
567 }
568
569 return 0;
570
571 deinit_clk:
572 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
573 deinit_phy:
574 rockchip_pcie_phy_deinit(rockchip);
575 disable_regulator:
576 if (rockchip->vpcie3v3)
577 regulator_disable(rockchip->vpcie3v3);
578
579 return ret;
580 }
581
582 static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
583 .mode = DW_PCIE_RC_TYPE,
584 };
585
586 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {
587 .mode = DW_PCIE_EP_TYPE,
588 .epc_features = &rockchip_pcie_epc_features_rk3568,
589 };
590
591 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {
592 .mode = DW_PCIE_EP_TYPE,
593 .epc_features = &rockchip_pcie_epc_features_rk3588,
594 };
595
596 static const struct of_device_id rockchip_pcie_of_match[] = {
597 {
598 .compatible = "rockchip,rk3568-pcie",
599 .data = &rockchip_pcie_rc_of_data_rk3568,
600 },
601 {
602 .compatible = "rockchip,rk3568-pcie-ep",
603 .data = &rockchip_pcie_ep_of_data_rk3568,
604 },
605 {
606 .compatible = "rockchip,rk3588-pcie-ep",
607 .data = &rockchip_pcie_ep_of_data_rk3588,
608 },
609 {},
610 };
611
612 static struct platform_driver rockchip_pcie_driver = {
613 .driver = {
614 .name = "rockchip-dw-pcie",
615 .of_match_table = rockchip_pcie_of_match,
616 .suppress_bind_attrs = true,
617 },
618 .probe = rockchip_pcie_probe,
619 };
620 builtin_platform_driver(rockchip_pcie_driver);
621