1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip AXI PCIe endpoint controller driver
4 *
5 * Copyright (c) 2018 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/configfs.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/pci-epc.h>
16 #include <linux/platform_device.h>
17 #include <linux/pci-epf.h>
18 #include <linux/sizes.h>
19
20 #include "pcie-rockchip.h"
21
22 /**
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
25 * @epc: PCI EPC device
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
29 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
30 * dedicated outbound regions is mapped.
31 * @irq_cpu_addr: base address in the CPU space where a write access triggers
32 * the sending of a memory write (MSI) / normal message (INTX
33 * IRQ) TLP through the PCIe bus.
34 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
35 * dedicated outbound region.
36 * @irq_pci_fn: the latest PCI function that has updated the mapping of
37 * the MSI/INTX IRQ dedicated outbound region.
38 * @irq_pending: bitmask of asserted INTX IRQs.
39 */
40 struct rockchip_pcie_ep {
41 struct rockchip_pcie rockchip;
42 struct pci_epc *epc;
43 u32 max_regions;
44 unsigned long ob_region_map;
45 phys_addr_t *ob_addr;
46 phys_addr_t irq_phys_addr;
47 void __iomem *irq_cpu_addr;
48 u64 irq_pci_addr;
49 u8 irq_pci_fn;
50 u8 irq_pending;
51 };
52
rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie * rockchip,u32 region)53 static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
54 u32 region)
55 {
56 rockchip_pcie_write(rockchip, 0,
57 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
58 rockchip_pcie_write(rockchip, 0,
59 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
60 rockchip_pcie_write(rockchip, 0,
61 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
62 rockchip_pcie_write(rockchip, 0,
63 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
64 }
65
rockchip_pcie_ep_ob_atu_num_bits(struct rockchip_pcie * rockchip,u64 pci_addr,size_t size)66 static int rockchip_pcie_ep_ob_atu_num_bits(struct rockchip_pcie *rockchip,
67 u64 pci_addr, size_t size)
68 {
69 int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1));
70
71 return clamp(num_pass_bits,
72 ROCKCHIP_PCIE_AT_MIN_NUM_BITS,
73 ROCKCHIP_PCIE_AT_MAX_NUM_BITS);
74 }
75
rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie * rockchip,u8 fn,u32 r,u64 cpu_addr,u64 pci_addr,size_t size)76 static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
77 u32 r, u64 cpu_addr, u64 pci_addr,
78 size_t size)
79 {
80 int num_pass_bits;
81 u32 addr0, addr1, desc0;
82
83 num_pass_bits = rockchip_pcie_ep_ob_atu_num_bits(rockchip,
84 pci_addr, size);
85
86 addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
87 (lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
88 addr1 = upper_32_bits(pci_addr);
89 desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | AXI_WRAPPER_MEM_WRITE;
90
91 /* PCI bus address region */
92 rockchip_pcie_write(rockchip, addr0,
93 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
94 rockchip_pcie_write(rockchip, addr1,
95 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
96 rockchip_pcie_write(rockchip, desc0,
97 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
98 rockchip_pcie_write(rockchip, 0,
99 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
100 }
101
rockchip_pcie_ep_write_header(struct pci_epc * epc,u8 fn,u8 vfn,struct pci_epf_header * hdr)102 static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
103 struct pci_epf_header *hdr)
104 {
105 u32 reg;
106 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
107 struct rockchip_pcie *rockchip = &ep->rockchip;
108
109 /* All functions share the same vendor ID with function 0 */
110 if (fn == 0) {
111 rockchip_pcie_write(rockchip,
112 hdr->vendorid | hdr->subsys_vendor_id << 16,
113 PCIE_CORE_CONFIG_VENDOR);
114 }
115
116 reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);
117 reg = (reg & 0xFFFF) | (hdr->deviceid << 16);
118 rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);
119
120 rockchip_pcie_write(rockchip,
121 hdr->revid |
122 hdr->progif_code << 8 |
123 hdr->subclass_code << 16 |
124 hdr->baseclass_code << 24,
125 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
126 rockchip_pcie_write(rockchip, hdr->cache_line_size,
127 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
128 PCI_CACHE_LINE_SIZE);
129 rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
130 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
131 PCI_SUBSYSTEM_VENDOR_ID);
132 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
133 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
134 PCI_INTERRUPT_LINE);
135
136 return 0;
137 }
138
rockchip_pcie_ep_set_bar(struct pci_epc * epc,u8 fn,u8 vfn,struct pci_epf_bar * epf_bar)139 static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
140 struct pci_epf_bar *epf_bar)
141 {
142 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
143 struct rockchip_pcie *rockchip = &ep->rockchip;
144 dma_addr_t bar_phys = epf_bar->phys_addr;
145 enum pci_barno bar = epf_bar->barno;
146 int flags = epf_bar->flags;
147 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
148 u64 sz;
149
150 /* BAR size is 2^(aperture + 7) */
151 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
152
153 /*
154 * roundup_pow_of_two() returns an unsigned long, which is not suited
155 * for 64bit values.
156 */
157 sz = 1ULL << fls64(sz - 1);
158 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
159
160 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
161 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
162 } else {
163 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
164 bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
165
166 if (is_64bits && (bar & 1))
167 return -EINVAL;
168
169 if (is_64bits && is_prefetch)
170 ctrl =
171 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
172 else if (is_prefetch)
173 ctrl =
174 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
175 else if (is_64bits)
176 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
177 else
178 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
179 }
180
181 if (bar < BAR_4) {
182 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
183 b = bar;
184 } else {
185 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
186 b = bar - BAR_4;
187 }
188
189 addr0 = lower_32_bits(bar_phys);
190 addr1 = upper_32_bits(bar_phys);
191
192 cfg = rockchip_pcie_read(rockchip, reg);
193 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
194 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
195 cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
196 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
197
198 rockchip_pcie_write(rockchip, cfg, reg);
199 rockchip_pcie_write(rockchip, addr0,
200 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
201 rockchip_pcie_write(rockchip, addr1,
202 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
203
204 return 0;
205 }
206
rockchip_pcie_ep_clear_bar(struct pci_epc * epc,u8 fn,u8 vfn,struct pci_epf_bar * epf_bar)207 static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
208 struct pci_epf_bar *epf_bar)
209 {
210 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
211 struct rockchip_pcie *rockchip = &ep->rockchip;
212 u32 reg, cfg, b, ctrl;
213 enum pci_barno bar = epf_bar->barno;
214
215 if (bar < BAR_4) {
216 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
217 b = bar;
218 } else {
219 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
220 b = bar - BAR_4;
221 }
222
223 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
224 cfg = rockchip_pcie_read(rockchip, reg);
225 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
226 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
227 cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
228
229 rockchip_pcie_write(rockchip, cfg, reg);
230 rockchip_pcie_write(rockchip, 0x0,
231 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
232 rockchip_pcie_write(rockchip, 0x0,
233 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
234 }
235
rockchip_ob_region(phys_addr_t addr)236 static inline u32 rockchip_ob_region(phys_addr_t addr)
237 {
238 return (addr >> ilog2(SZ_1M)) & 0x1f;
239 }
240
rockchip_pcie_ep_map_addr(struct pci_epc * epc,u8 fn,u8 vfn,phys_addr_t addr,u64 pci_addr,size_t size)241 static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
242 phys_addr_t addr, u64 pci_addr,
243 size_t size)
244 {
245 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
246 struct rockchip_pcie *pcie = &ep->rockchip;
247 u32 r = rockchip_ob_region(addr);
248
249 rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, addr, pci_addr, size);
250
251 set_bit(r, &ep->ob_region_map);
252 ep->ob_addr[r] = addr;
253
254 return 0;
255 }
256
rockchip_pcie_ep_unmap_addr(struct pci_epc * epc,u8 fn,u8 vfn,phys_addr_t addr)257 static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
258 phys_addr_t addr)
259 {
260 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
261 struct rockchip_pcie *rockchip = &ep->rockchip;
262 u32 r;
263
264 for (r = 0; r < ep->max_regions; r++)
265 if (ep->ob_addr[r] == addr)
266 break;
267
268 if (r == ep->max_regions)
269 return;
270
271 rockchip_pcie_clear_ep_ob_atu(rockchip, r);
272
273 ep->ob_addr[r] = 0;
274 clear_bit(r, &ep->ob_region_map);
275 }
276
rockchip_pcie_ep_set_msi(struct pci_epc * epc,u8 fn,u8 vfn,u8 multi_msg_cap)277 static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
278 u8 multi_msg_cap)
279 {
280 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
281 struct rockchip_pcie *rockchip = &ep->rockchip;
282 u32 flags;
283
284 flags = rockchip_pcie_read(rockchip,
285 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
286 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
287 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
288 flags |=
289 (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
290 (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
291 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
292 rockchip_pcie_write(rockchip, flags,
293 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
294 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
295 return 0;
296 }
297
rockchip_pcie_ep_get_msi(struct pci_epc * epc,u8 fn,u8 vfn)298 static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
299 {
300 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
301 struct rockchip_pcie *rockchip = &ep->rockchip;
302 u32 flags;
303
304 flags = rockchip_pcie_read(rockchip,
305 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
306 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
307 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
308 return -EINVAL;
309
310 return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
311 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
312 }
313
rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep * ep,u8 fn,u8 intx,bool do_assert)314 static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
315 u8 intx, bool do_assert)
316 {
317 struct rockchip_pcie *rockchip = &ep->rockchip;
318
319 intx &= 3;
320
321 if (do_assert) {
322 ep->irq_pending |= BIT(intx);
323 rockchip_pcie_write(rockchip,
324 PCIE_CLIENT_INT_IN_ASSERT |
325 PCIE_CLIENT_INT_PEND_ST_PEND,
326 PCIE_CLIENT_LEGACY_INT_CTRL);
327 } else {
328 ep->irq_pending &= ~BIT(intx);
329 rockchip_pcie_write(rockchip,
330 PCIE_CLIENT_INT_IN_DEASSERT |
331 PCIE_CLIENT_INT_PEND_ST_NORMAL,
332 PCIE_CLIENT_LEGACY_INT_CTRL);
333 }
334 }
335
rockchip_pcie_ep_send_intx_irq(struct rockchip_pcie_ep * ep,u8 fn,u8 intx)336 static int rockchip_pcie_ep_send_intx_irq(struct rockchip_pcie_ep *ep, u8 fn,
337 u8 intx)
338 {
339 u16 cmd;
340
341 cmd = rockchip_pcie_read(&ep->rockchip,
342 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
343 ROCKCHIP_PCIE_EP_CMD_STATUS);
344
345 if (cmd & PCI_COMMAND_INTX_DISABLE)
346 return -EINVAL;
347
348 /*
349 * Should add some delay between toggling INTx per TRM vaguely saying
350 * it depends on some cycles of the AHB bus clock to function it. So
351 * add sufficient 1ms here.
352 */
353 rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
354 mdelay(1);
355 rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
356 return 0;
357 }
358
rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep * ep,u8 fn,u8 interrupt_num)359 static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
360 u8 interrupt_num)
361 {
362 struct rockchip_pcie *rockchip = &ep->rockchip;
363 u32 flags, mme, data, data_mask;
364 u8 msi_count;
365 u64 pci_addr;
366 u32 r;
367
368 /* Check MSI enable bit */
369 flags = rockchip_pcie_read(&ep->rockchip,
370 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
371 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
372 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
373 return -EINVAL;
374
375 /* Get MSI numbers from MME */
376 mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
377 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
378 msi_count = 1 << mme;
379 if (!interrupt_num || interrupt_num > msi_count)
380 return -EINVAL;
381
382 /* Set MSI private data */
383 data_mask = msi_count - 1;
384 data = rockchip_pcie_read(rockchip,
385 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
386 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
387 PCI_MSI_DATA_64);
388 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
389
390 /* Get MSI PCI address */
391 pci_addr = rockchip_pcie_read(rockchip,
392 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
393 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
394 PCI_MSI_ADDRESS_HI);
395 pci_addr <<= 32;
396 pci_addr |= rockchip_pcie_read(rockchip,
397 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
398 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
399 PCI_MSI_ADDRESS_LO);
400
401 /* Set the outbound region if needed. */
402 if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) ||
403 ep->irq_pci_fn != fn)) {
404 r = rockchip_ob_region(ep->irq_phys_addr);
405 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
406 ep->irq_phys_addr,
407 pci_addr & PCIE_ADDR_MASK,
408 ~PCIE_ADDR_MASK + 1);
409 ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK);
410 ep->irq_pci_fn = fn;
411 }
412
413 writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK));
414 return 0;
415 }
416
rockchip_pcie_ep_raise_irq(struct pci_epc * epc,u8 fn,u8 vfn,unsigned int type,u16 interrupt_num)417 static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
418 unsigned int type, u16 interrupt_num)
419 {
420 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
421
422 switch (type) {
423 case PCI_IRQ_INTX:
424 return rockchip_pcie_ep_send_intx_irq(ep, fn, 0);
425 case PCI_IRQ_MSI:
426 return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
427 default:
428 return -EINVAL;
429 }
430 }
431
rockchip_pcie_ep_start(struct pci_epc * epc)432 static int rockchip_pcie_ep_start(struct pci_epc *epc)
433 {
434 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
435 struct rockchip_pcie *rockchip = &ep->rockchip;
436 struct pci_epf *epf;
437 u32 cfg;
438
439 cfg = BIT(0);
440 list_for_each_entry(epf, &epc->pci_epf, list)
441 cfg |= BIT(epf->func_no);
442
443 rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
444
445 return 0;
446 }
447
448 static const struct pci_epc_features rockchip_pcie_epc_features = {
449 .linkup_notifier = false,
450 .msi_capable = true,
451 .msix_capable = false,
452 .align = 256,
453 };
454
455 static const struct pci_epc_features*
rockchip_pcie_ep_get_features(struct pci_epc * epc,u8 func_no,u8 vfunc_no)456 rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
457 {
458 return &rockchip_pcie_epc_features;
459 }
460
461 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
462 .write_header = rockchip_pcie_ep_write_header,
463 .set_bar = rockchip_pcie_ep_set_bar,
464 .clear_bar = rockchip_pcie_ep_clear_bar,
465 .map_addr = rockchip_pcie_ep_map_addr,
466 .unmap_addr = rockchip_pcie_ep_unmap_addr,
467 .set_msi = rockchip_pcie_ep_set_msi,
468 .get_msi = rockchip_pcie_ep_get_msi,
469 .raise_irq = rockchip_pcie_ep_raise_irq,
470 .start = rockchip_pcie_ep_start,
471 .get_features = rockchip_pcie_ep_get_features,
472 };
473
rockchip_pcie_parse_ep_dt(struct rockchip_pcie * rockchip,struct rockchip_pcie_ep * ep)474 static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
475 struct rockchip_pcie_ep *ep)
476 {
477 struct device *dev = rockchip->dev;
478 int err;
479
480 err = rockchip_pcie_parse_dt(rockchip);
481 if (err)
482 return err;
483
484 err = rockchip_pcie_get_phys(rockchip);
485 if (err)
486 return err;
487
488 err = of_property_read_u32(dev->of_node,
489 "rockchip,max-outbound-regions",
490 &ep->max_regions);
491 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
492 ep->max_regions = MAX_REGION_LIMIT;
493
494 ep->ob_region_map = 0;
495
496 err = of_property_read_u8(dev->of_node, "max-functions",
497 &ep->epc->max_functions);
498 if (err < 0)
499 ep->epc->max_functions = 1;
500
501 return 0;
502 }
503
504 static const struct of_device_id rockchip_pcie_ep_of_match[] = {
505 { .compatible = "rockchip,rk3399-pcie-ep"},
506 {},
507 };
508
rockchip_pcie_ep_probe(struct platform_device * pdev)509 static int rockchip_pcie_ep_probe(struct platform_device *pdev)
510 {
511 struct device *dev = &pdev->dev;
512 struct rockchip_pcie_ep *ep;
513 struct rockchip_pcie *rockchip;
514 struct pci_epc *epc;
515 size_t max_regions;
516 struct pci_epc_mem_window *windows = NULL;
517 int err, i;
518 u32 cfg_msi, cfg_msix_cp;
519
520 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
521 if (!ep)
522 return -ENOMEM;
523
524 rockchip = &ep->rockchip;
525 rockchip->is_rc = false;
526 rockchip->dev = dev;
527
528 epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
529 if (IS_ERR(epc)) {
530 dev_err(dev, "failed to create epc device\n");
531 return PTR_ERR(epc);
532 }
533
534 ep->epc = epc;
535 epc_set_drvdata(epc, ep);
536
537 err = rockchip_pcie_parse_ep_dt(rockchip, ep);
538 if (err)
539 return err;
540
541 err = rockchip_pcie_enable_clocks(rockchip);
542 if (err)
543 return err;
544
545 err = rockchip_pcie_init_port(rockchip);
546 if (err)
547 goto err_disable_clocks;
548
549 /* Establish the link automatically */
550 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
551 PCIE_CLIENT_CONFIG);
552
553 max_regions = ep->max_regions;
554 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),
555 GFP_KERNEL);
556
557 if (!ep->ob_addr) {
558 err = -ENOMEM;
559 goto err_uninit_port;
560 }
561
562 /* Only enable function 0 by default */
563 rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
564
565 windows = devm_kcalloc(dev, ep->max_regions,
566 sizeof(struct pci_epc_mem_window), GFP_KERNEL);
567 if (!windows) {
568 err = -ENOMEM;
569 goto err_uninit_port;
570 }
571 for (i = 0; i < ep->max_regions; i++) {
572 windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i);
573 windows[i].size = SZ_1M;
574 windows[i].page_size = SZ_1M;
575 }
576 err = pci_epc_multi_mem_init(epc, windows, ep->max_regions);
577 devm_kfree(dev, windows);
578
579 if (err < 0) {
580 dev_err(dev, "failed to initialize the memory space\n");
581 goto err_uninit_port;
582 }
583
584 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
585 SZ_1M);
586 if (!ep->irq_cpu_addr) {
587 dev_err(dev, "failed to reserve memory space for MSI\n");
588 err = -ENOMEM;
589 goto err_epc_mem_exit;
590 }
591
592 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
593
594 /*
595 * MSI-X is not supported but the controller still advertises the MSI-X
596 * capability by default, which can lead to the Root Complex side
597 * allocating MSI-X vectors which cannot be used. Avoid this by skipping
598 * the MSI-X capability entry in the PCIe capabilities linked-list: get
599 * the next pointer from the MSI-X entry and set that in the MSI
600 * capability entry (which is the previous entry). This way the MSI-X
601 * entry is skipped (left out of the linked-list) and not advertised.
602 */
603 cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
604 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
605
606 cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK;
607
608 cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
609 ROCKCHIP_PCIE_EP_MSIX_CAP_REG) &
610 ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK;
611
612 cfg_msi |= cfg_msix_cp;
613
614 rockchip_pcie_write(rockchip, cfg_msi,
615 PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
616
617 rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
618 PCIE_CLIENT_CONFIG);
619
620 pci_epc_init_notify(epc);
621
622 return 0;
623 err_epc_mem_exit:
624 pci_epc_mem_exit(epc);
625 err_uninit_port:
626 rockchip_pcie_deinit_phys(rockchip);
627 err_disable_clocks:
628 rockchip_pcie_disable_clocks(rockchip);
629 return err;
630 }
631
632 static struct platform_driver rockchip_pcie_ep_driver = {
633 .driver = {
634 .name = "rockchip-pcie-ep",
635 .of_match_table = rockchip_pcie_ep_of_match,
636 },
637 .probe = rockchip_pcie_ep_probe,
638 };
639
640 builtin_platform_driver(rockchip_pcie_ep_driver);
641