1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip AXI PCIe host controller driver
4 *
5 * Copyright (c) 2016 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
9 *
10 * Bits taken from Synopsys DesignWare Host controller driver and
11 * ARM PCI Host generic driver.
12 */
13
14 #include <linux/bitfield.h>
15 #include <linux/bitrev.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/iopoll.h>
22 #include <linux/irq.h>
23 #include <linux/irqchip/chained_irq.h>
24 #include <linux/irqdomain.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/of_pci.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/reset.h>
35 #include <linux/regmap.h>
36
37 #include "../pci.h"
38 #include "pcie-rockchip.h"
39
rockchip_pcie_enable_bw_int(struct rockchip_pcie * rockchip)40 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
41 {
42 u32 status;
43
44 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
45 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
46 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
47 }
48
rockchip_pcie_clr_bw_int(struct rockchip_pcie * rockchip)49 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
50 {
51 u32 status;
52
53 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
54 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
55 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
56 }
57
rockchip_pcie_update_txcredit_mui(struct rockchip_pcie * rockchip)58 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
59 {
60 u32 val;
61
62 /* Update Tx credit maximum update interval */
63 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
64 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
65 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
66 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
67 }
68
rockchip_pcie_valid_device(struct rockchip_pcie * rockchip,struct pci_bus * bus,int dev)69 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
70 struct pci_bus *bus, int dev)
71 {
72 /*
73 * Access only one slot on each root port.
74 * Do not read more than one device on the bus directly attached
75 * to RC's downstream side.
76 */
77 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent))
78 return dev == 0;
79
80 return 1;
81 }
82
rockchip_pcie_lane_map(struct rockchip_pcie * rockchip)83 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
84 {
85 u32 val;
86 u8 map;
87
88 if (rockchip->legacy_phy)
89 return GENMASK(MAX_LANE_NUM - 1, 0);
90
91 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
92 map = val & PCIE_CORE_LANE_MAP_MASK;
93
94 /* The link may be using a reverse-indexed mapping. */
95 if (val & PCIE_CORE_LANE_MAP_REVERSE)
96 map = bitrev8(map) >> 4;
97
98 return map;
99 }
100
rockchip_pcie_rd_own_conf(struct rockchip_pcie * rockchip,int where,int size,u32 * val)101 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
102 int where, int size, u32 *val)
103 {
104 void __iomem *addr;
105
106 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
107
108 if (!IS_ALIGNED((uintptr_t)addr, size)) {
109 *val = 0;
110 return PCIBIOS_BAD_REGISTER_NUMBER;
111 }
112
113 if (size == 4) {
114 *val = readl(addr);
115 } else if (size == 2) {
116 *val = readw(addr);
117 } else if (size == 1) {
118 *val = readb(addr);
119 } else {
120 *val = 0;
121 return PCIBIOS_BAD_REGISTER_NUMBER;
122 }
123 return PCIBIOS_SUCCESSFUL;
124 }
125
rockchip_pcie_wr_own_conf(struct rockchip_pcie * rockchip,int where,int size,u32 val)126 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
127 int where, int size, u32 val)
128 {
129 u32 mask, tmp, offset;
130 void __iomem *addr;
131
132 offset = where & ~0x3;
133 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
134
135 if (size == 4) {
136 writel(val, addr);
137 return PCIBIOS_SUCCESSFUL;
138 }
139
140 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
141
142 /*
143 * N.B. This read/modify/write isn't safe in general because it can
144 * corrupt RW1C bits in adjacent registers. But the hardware
145 * doesn't support smaller writes.
146 */
147 tmp = readl(addr) & mask;
148 tmp |= val << ((where & 0x3) * 8);
149 writel(tmp, addr);
150
151 return PCIBIOS_SUCCESSFUL;
152 }
153
rockchip_pcie_rd_other_conf(struct rockchip_pcie * rockchip,struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)154 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
155 struct pci_bus *bus, u32 devfn,
156 int where, int size, u32 *val)
157 {
158 void __iomem *addr;
159
160 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
161
162 if (!IS_ALIGNED((uintptr_t)addr, size)) {
163 *val = 0;
164 return PCIBIOS_BAD_REGISTER_NUMBER;
165 }
166
167 if (pci_is_root_bus(bus->parent))
168 rockchip_pcie_cfg_configuration_accesses(rockchip,
169 AXI_WRAPPER_TYPE0_CFG);
170 else
171 rockchip_pcie_cfg_configuration_accesses(rockchip,
172 AXI_WRAPPER_TYPE1_CFG);
173
174 if (size == 4) {
175 *val = readl(addr);
176 } else if (size == 2) {
177 *val = readw(addr);
178 } else if (size == 1) {
179 *val = readb(addr);
180 } else {
181 *val = 0;
182 return PCIBIOS_BAD_REGISTER_NUMBER;
183 }
184 return PCIBIOS_SUCCESSFUL;
185 }
186
rockchip_pcie_wr_other_conf(struct rockchip_pcie * rockchip,struct pci_bus * bus,u32 devfn,int where,int size,u32 val)187 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
188 struct pci_bus *bus, u32 devfn,
189 int where, int size, u32 val)
190 {
191 void __iomem *addr;
192
193 addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
194
195 if (!IS_ALIGNED((uintptr_t)addr, size))
196 return PCIBIOS_BAD_REGISTER_NUMBER;
197
198 if (pci_is_root_bus(bus->parent))
199 rockchip_pcie_cfg_configuration_accesses(rockchip,
200 AXI_WRAPPER_TYPE0_CFG);
201 else
202 rockchip_pcie_cfg_configuration_accesses(rockchip,
203 AXI_WRAPPER_TYPE1_CFG);
204
205 if (size == 4)
206 writel(val, addr);
207 else if (size == 2)
208 writew(val, addr);
209 else if (size == 1)
210 writeb(val, addr);
211 else
212 return PCIBIOS_BAD_REGISTER_NUMBER;
213
214 return PCIBIOS_SUCCESSFUL;
215 }
216
rockchip_pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)217 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
218 int size, u32 *val)
219 {
220 struct rockchip_pcie *rockchip = bus->sysdata;
221
222 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 if (pci_is_root_bus(bus))
226 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
227
228 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size,
229 val);
230 }
231
rockchip_pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)232 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
233 int where, int size, u32 val)
234 {
235 struct rockchip_pcie *rockchip = bus->sysdata;
236
237 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
238 return PCIBIOS_DEVICE_NOT_FOUND;
239
240 if (pci_is_root_bus(bus))
241 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
242
243 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size,
244 val);
245 }
246
247 static struct pci_ops rockchip_pcie_ops = {
248 .read = rockchip_pcie_rd_conf,
249 .write = rockchip_pcie_wr_conf,
250 };
251
rockchip_pcie_set_power_limit(struct rockchip_pcie * rockchip)252 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
253 {
254 int curr;
255 u32 status, scale, power;
256
257 if (IS_ERR(rockchip->vpcie3v3))
258 return;
259
260 /*
261 * Set RC's captured slot power limit and scale if
262 * vpcie3v3 available. The default values are both zero
263 * which means the software should set these two according
264 * to the actual power supply.
265 */
266 curr = regulator_get_current_limit(rockchip->vpcie3v3);
267 if (curr <= 0)
268 return;
269
270 scale = 3; /* 0.001x */
271 curr = curr / 1000; /* convert to mA */
272 power = (curr * 3300) / 1000; /* milliwatt */
273 while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) {
274 if (!scale) {
275 dev_warn(rockchip->dev, "invalid power supply\n");
276 return;
277 }
278 scale--;
279 power = power / 10;
280 }
281
282 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP);
283 status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power);
284 status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale);
285 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP);
286 }
287
288 /**
289 * rockchip_pcie_host_init_port - Initialize hardware
290 * @rockchip: PCIe port information
291 */
rockchip_pcie_host_init_port(struct rockchip_pcie * rockchip)292 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
293 {
294 struct device *dev = rockchip->dev;
295 int err, i = MAX_LANE_NUM;
296 u32 status;
297
298 gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
299
300 err = rockchip_pcie_init_port(rockchip);
301 if (err)
302 return err;
303
304 /* Fix the transmitted FTS count desired to exit from L0s. */
305 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
306 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
307 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
308 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
309
310 rockchip_pcie_set_power_limit(rockchip);
311
312 /* Set RC's clock architecture as common clock */
313 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
314 status |= PCI_EXP_LNKSTA_SLC << 16;
315 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
316
317 /* Set RC's RCB to 128 */
318 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
319 status |= PCI_EXP_LNKCTL_RCB;
320 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
321
322 /* Enable Gen1 training */
323 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
324 PCIE_CLIENT_CONFIG);
325
326 msleep(PCIE_T_PVPERL_MS);
327 gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
328
329 msleep(PCIE_T_RRS_READY_MS);
330
331 /* 500ms timeout value should be enough for Gen1/2 training */
332 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
333 status, PCIE_LINK_UP(status), 20,
334 500 * USEC_PER_MSEC);
335 if (err) {
336 dev_err(dev, "PCIe link training gen1 timeout!\n");
337 goto err_power_off_phy;
338 }
339
340 if (rockchip->link_gen == 2) {
341 /*
342 * Enable retrain for gen2. This should be configured only after
343 * gen1 finished.
344 */
345 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
346 status &= ~PCI_EXP_LNKCTL2_TLS;
347 status |= PCI_EXP_LNKCTL2_TLS_5_0GT;
348 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
349 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
350 status |= PCI_EXP_LNKCTL_RL;
351 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
352
353 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
354 status, PCIE_LINK_IS_GEN2(status), 20,
355 500 * USEC_PER_MSEC);
356 if (err)
357 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
358 }
359
360 /* Check the final link width from negotiated lane counter from MGMT */
361 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
362 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
363 PCIE_CORE_PL_CONF_LANE_SHIFT);
364 dev_dbg(dev, "current link width is x%d\n", status);
365
366 /* Power off unused lane(s) */
367 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
368 for (i = 0; i < MAX_LANE_NUM; i++) {
369 if (!(rockchip->lanes_map & BIT(i))) {
370 dev_dbg(dev, "idling lane %d\n", i);
371 phy_power_off(rockchip->phys[i]);
372 }
373 }
374
375 rockchip_pcie_write(rockchip, PCI_VENDOR_ID_ROCKCHIP,
376 PCIE_CORE_CONFIG_VENDOR);
377 rockchip_pcie_write(rockchip,
378 PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
379 PCIE_RC_CONFIG_RID_CCR);
380
381 /* Clear THP cap's next cap pointer to remove L1 substate cap */
382 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
383 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
384 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
385
386 /* Clear L0s from RC's link cap */
387 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
388 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP);
389 status &= ~PCI_EXP_LNKCAP_ASPM_L0S;
390 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP);
391 }
392
393 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL);
394 status &= ~PCI_EXP_DEVCTL_PAYLOAD;
395 status |= PCI_EXP_DEVCTL_PAYLOAD_256B;
396 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL);
397
398 return 0;
399 err_power_off_phy:
400 while (i--)
401 phy_power_off(rockchip->phys[i]);
402 i = MAX_LANE_NUM;
403 while (i--)
404 phy_exit(rockchip->phys[i]);
405 return err;
406 }
407
rockchip_pcie_subsys_irq_handler(int irq,void * arg)408 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
409 {
410 struct rockchip_pcie *rockchip = arg;
411 struct device *dev = rockchip->dev;
412 u32 reg;
413 u32 sub_reg;
414
415 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
416 if (reg & PCIE_CLIENT_INT_LOCAL) {
417 dev_dbg(dev, "local interrupt received\n");
418 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
419 if (sub_reg & PCIE_CORE_INT_PRFPE)
420 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
421
422 if (sub_reg & PCIE_CORE_INT_CRFPE)
423 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
424
425 if (sub_reg & PCIE_CORE_INT_RRPE)
426 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
427
428 if (sub_reg & PCIE_CORE_INT_PRFO)
429 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
430
431 if (sub_reg & PCIE_CORE_INT_CRFO)
432 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
433
434 if (sub_reg & PCIE_CORE_INT_RT)
435 dev_dbg(dev, "replay timer timed out\n");
436
437 if (sub_reg & PCIE_CORE_INT_RTR)
438 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
439
440 if (sub_reg & PCIE_CORE_INT_PE)
441 dev_dbg(dev, "phy error detected on receive side\n");
442
443 if (sub_reg & PCIE_CORE_INT_MTR)
444 dev_dbg(dev, "malformed TLP received from the link\n");
445
446 if (sub_reg & PCIE_CORE_INT_UCR)
447 dev_dbg(dev, "Unexpected Completion received from the link\n");
448
449 if (sub_reg & PCIE_CORE_INT_FCE)
450 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
451
452 if (sub_reg & PCIE_CORE_INT_CT)
453 dev_dbg(dev, "a request timed out waiting for completion\n");
454
455 if (sub_reg & PCIE_CORE_INT_UTC)
456 dev_dbg(dev, "unmapped TC error\n");
457
458 if (sub_reg & PCIE_CORE_INT_MMVC)
459 dev_dbg(dev, "MSI mask register changes\n");
460
461 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
462 } else if (reg & PCIE_CLIENT_INT_PHY) {
463 dev_dbg(dev, "phy link changes\n");
464 rockchip_pcie_update_txcredit_mui(rockchip);
465 rockchip_pcie_clr_bw_int(rockchip);
466 }
467
468 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
469 PCIE_CLIENT_INT_STATUS);
470
471 return IRQ_HANDLED;
472 }
473
rockchip_pcie_client_irq_handler(int irq,void * arg)474 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
475 {
476 struct rockchip_pcie *rockchip = arg;
477 struct device *dev = rockchip->dev;
478 u32 reg;
479
480 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
481 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
482 dev_dbg(dev, "legacy done interrupt received\n");
483
484 if (reg & PCIE_CLIENT_INT_MSG)
485 dev_dbg(dev, "message done interrupt received\n");
486
487 if (reg & PCIE_CLIENT_INT_HOT_RST)
488 dev_dbg(dev, "hot reset interrupt received\n");
489
490 if (reg & PCIE_CLIENT_INT_DPA)
491 dev_dbg(dev, "dpa interrupt received\n");
492
493 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
494 dev_dbg(dev, "fatal error interrupt received\n");
495
496 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
497 dev_dbg(dev, "no fatal error interrupt received\n");
498
499 if (reg & PCIE_CLIENT_INT_CORR_ERR)
500 dev_dbg(dev, "correctable error interrupt received\n");
501
502 if (reg & PCIE_CLIENT_INT_PHY)
503 dev_dbg(dev, "phy interrupt received\n");
504
505 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
506 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
507 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
508 PCIE_CLIENT_INT_NFATAL_ERR |
509 PCIE_CLIENT_INT_CORR_ERR |
510 PCIE_CLIENT_INT_PHY),
511 PCIE_CLIENT_INT_STATUS);
512
513 return IRQ_HANDLED;
514 }
515
rockchip_pcie_intx_handler(struct irq_desc * desc)516 static void rockchip_pcie_intx_handler(struct irq_desc *desc)
517 {
518 struct irq_chip *chip = irq_desc_get_chip(desc);
519 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
520 struct device *dev = rockchip->dev;
521 u32 reg;
522 u32 hwirq;
523 int ret;
524
525 chained_irq_enter(chip, desc);
526
527 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
528 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
529
530 while (reg) {
531 hwirq = ffs(reg) - 1;
532 reg &= ~BIT(hwirq);
533
534 ret = generic_handle_domain_irq(rockchip->irq_domain, hwirq);
535 if (ret)
536 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
537 }
538
539 chained_irq_exit(chip, desc);
540 }
541
rockchip_pcie_setup_irq(struct rockchip_pcie * rockchip)542 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
543 {
544 int irq, err;
545 struct device *dev = rockchip->dev;
546 struct platform_device *pdev = to_platform_device(dev);
547
548 irq = platform_get_irq_byname(pdev, "sys");
549 if (irq < 0)
550 return irq;
551
552 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
553 IRQF_SHARED, "pcie-sys", rockchip);
554 if (err) {
555 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
556 return err;
557 }
558
559 irq = platform_get_irq_byname(pdev, "legacy");
560 if (irq < 0)
561 return irq;
562
563 irq_set_chained_handler_and_data(irq,
564 rockchip_pcie_intx_handler,
565 rockchip);
566
567 irq = platform_get_irq_byname(pdev, "client");
568 if (irq < 0)
569 return irq;
570
571 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
572 IRQF_SHARED, "pcie-client", rockchip);
573 if (err) {
574 dev_err(dev, "failed to request PCIe client IRQ\n");
575 return err;
576 }
577
578 return 0;
579 }
580
581 /**
582 * rockchip_pcie_parse_host_dt - Parse Device Tree
583 * @rockchip: PCIe port information
584 *
585 * Return: '0' on success and error value on failure
586 */
rockchip_pcie_parse_host_dt(struct rockchip_pcie * rockchip)587 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
588 {
589 struct device *dev = rockchip->dev;
590 int err;
591
592 err = rockchip_pcie_parse_dt(rockchip);
593 if (err)
594 return err;
595
596 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
597 if (IS_ERR(rockchip->vpcie12v)) {
598 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
599 return PTR_ERR(rockchip->vpcie12v);
600 dev_info(dev, "no vpcie12v regulator found\n");
601 }
602
603 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
604 if (IS_ERR(rockchip->vpcie3v3)) {
605 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
606 return PTR_ERR(rockchip->vpcie3v3);
607 dev_info(dev, "no vpcie3v3 regulator found\n");
608 }
609
610 rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
611 if (IS_ERR(rockchip->vpcie1v8))
612 return PTR_ERR(rockchip->vpcie1v8);
613
614 rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
615 if (IS_ERR(rockchip->vpcie0v9))
616 return PTR_ERR(rockchip->vpcie0v9);
617
618 return 0;
619 }
620
rockchip_pcie_set_vpcie(struct rockchip_pcie * rockchip)621 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
622 {
623 struct device *dev = rockchip->dev;
624 int err;
625
626 if (!IS_ERR(rockchip->vpcie12v)) {
627 err = regulator_enable(rockchip->vpcie12v);
628 if (err) {
629 dev_err(dev, "fail to enable vpcie12v regulator\n");
630 goto err_out;
631 }
632 }
633
634 if (!IS_ERR(rockchip->vpcie3v3)) {
635 err = regulator_enable(rockchip->vpcie3v3);
636 if (err) {
637 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
638 goto err_disable_12v;
639 }
640 }
641
642 err = regulator_enable(rockchip->vpcie1v8);
643 if (err) {
644 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
645 goto err_disable_3v3;
646 }
647
648 err = regulator_enable(rockchip->vpcie0v9);
649 if (err) {
650 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
651 goto err_disable_1v8;
652 }
653
654 return 0;
655
656 err_disable_1v8:
657 regulator_disable(rockchip->vpcie1v8);
658 err_disable_3v3:
659 if (!IS_ERR(rockchip->vpcie3v3))
660 regulator_disable(rockchip->vpcie3v3);
661 err_disable_12v:
662 if (!IS_ERR(rockchip->vpcie12v))
663 regulator_disable(rockchip->vpcie12v);
664 err_out:
665 return err;
666 }
667
rockchip_pcie_enable_interrupts(struct rockchip_pcie * rockchip)668 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
669 {
670 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
671 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
672 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
673 PCIE_CORE_INT_MASK);
674
675 rockchip_pcie_enable_bw_int(rockchip);
676 }
677
rockchip_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)678 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
679 irq_hw_number_t hwirq)
680 {
681 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
682 irq_set_chip_data(irq, domain->host_data);
683
684 return 0;
685 }
686
687 static const struct irq_domain_ops intx_domain_ops = {
688 .map = rockchip_pcie_intx_map,
689 };
690
rockchip_pcie_init_irq_domain(struct rockchip_pcie * rockchip)691 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
692 {
693 struct device *dev = rockchip->dev;
694 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
695
696 if (!intc) {
697 dev_err(dev, "missing child interrupt-controller node\n");
698 return -EINVAL;
699 }
700
701 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
702 &intx_domain_ops, rockchip);
703 of_node_put(intc);
704 if (!rockchip->irq_domain) {
705 dev_err(dev, "failed to get a INTx IRQ domain\n");
706 return -EINVAL;
707 }
708
709 return 0;
710 }
711
rockchip_pcie_prog_ob_atu(struct rockchip_pcie * rockchip,int region_no,int type,u8 num_pass_bits,u32 lower_addr,u32 upper_addr)712 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
713 int region_no, int type, u8 num_pass_bits,
714 u32 lower_addr, u32 upper_addr)
715 {
716 u32 ob_addr_0;
717 u32 ob_addr_1;
718 u32 ob_desc_0;
719 u32 aw_offset;
720
721 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
722 return -EINVAL;
723 if (num_pass_bits + 1 < 8)
724 return -EINVAL;
725 if (num_pass_bits > 63)
726 return -EINVAL;
727 if (region_no == 0) {
728 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
729 return -EINVAL;
730 }
731 if (region_no != 0) {
732 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
733 return -EINVAL;
734 }
735
736 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
737
738 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
739 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
740 ob_addr_1 = upper_addr;
741 ob_desc_0 = (1 << 23 | type);
742
743 rockchip_pcie_write(rockchip, ob_addr_0,
744 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
745 rockchip_pcie_write(rockchip, ob_addr_1,
746 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
747 rockchip_pcie_write(rockchip, ob_desc_0,
748 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
749 rockchip_pcie_write(rockchip, 0,
750 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
751
752 return 0;
753 }
754
rockchip_pcie_prog_ib_atu(struct rockchip_pcie * rockchip,int region_no,u8 num_pass_bits,u32 lower_addr,u32 upper_addr)755 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
756 int region_no, u8 num_pass_bits,
757 u32 lower_addr, u32 upper_addr)
758 {
759 u32 ib_addr_0;
760 u32 ib_addr_1;
761 u32 aw_offset;
762
763 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
764 return -EINVAL;
765 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
766 return -EINVAL;
767 if (num_pass_bits > 63)
768 return -EINVAL;
769
770 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
771
772 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
773 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
774 ib_addr_1 = upper_addr;
775
776 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
777 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
778
779 return 0;
780 }
781
rockchip_pcie_cfg_atu(struct rockchip_pcie * rockchip)782 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
783 {
784 struct device *dev = rockchip->dev;
785 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
786 struct resource_entry *entry;
787 u64 pci_addr, size;
788 int offset;
789 int err;
790 int reg_no;
791
792 rockchip_pcie_cfg_configuration_accesses(rockchip,
793 AXI_WRAPPER_TYPE0_CFG);
794 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
795 if (!entry)
796 return -ENODEV;
797
798 size = resource_size(entry->res);
799 pci_addr = entry->res->start - entry->offset;
800 rockchip->msg_bus_addr = pci_addr;
801
802 for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
803 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
804 AXI_WRAPPER_MEM_WRITE,
805 20 - 1,
806 pci_addr + (reg_no << 20),
807 0);
808 if (err) {
809 dev_err(dev, "program RC mem outbound ATU failed\n");
810 return err;
811 }
812 }
813
814 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
815 if (err) {
816 dev_err(dev, "program RC mem inbound ATU failed\n");
817 return err;
818 }
819
820 entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
821 if (!entry)
822 return -ENODEV;
823
824 /* store the register number offset to program RC io outbound ATU */
825 offset = size >> 20;
826
827 size = resource_size(entry->res);
828 pci_addr = entry->res->start - entry->offset;
829
830 for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
831 err = rockchip_pcie_prog_ob_atu(rockchip,
832 reg_no + 1 + offset,
833 AXI_WRAPPER_IO_WRITE,
834 20 - 1,
835 pci_addr + (reg_no << 20),
836 0);
837 if (err) {
838 dev_err(dev, "program RC io outbound ATU failed\n");
839 return err;
840 }
841 }
842
843 /* assign message regions */
844 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
845 AXI_WRAPPER_NOR_MSG,
846 20 - 1, 0, 0);
847
848 rockchip->msg_bus_addr += ((reg_no + offset) << 20);
849 return err;
850 }
851
rockchip_pcie_wait_l2(struct rockchip_pcie * rockchip)852 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
853 {
854 u32 value;
855 int err;
856
857 /* send PME_TURN_OFF message */
858 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
859
860 /* read LTSSM and wait for falling into L2 link state */
861 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
862 value, PCIE_LINK_IS_L2(value), 20,
863 jiffies_to_usecs(5 * HZ));
864 if (err) {
865 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
866 return err;
867 }
868
869 return 0;
870 }
871
rockchip_pcie_suspend_noirq(struct device * dev)872 static int rockchip_pcie_suspend_noirq(struct device *dev)
873 {
874 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
875 int ret;
876
877 /* disable core and cli int since we don't need to ack PME_ACK */
878 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
879 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK);
880 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
881
882 ret = rockchip_pcie_wait_l2(rockchip);
883 if (ret) {
884 rockchip_pcie_enable_interrupts(rockchip);
885 return ret;
886 }
887
888 rockchip_pcie_deinit_phys(rockchip);
889
890 rockchip_pcie_disable_clocks(rockchip);
891
892 regulator_disable(rockchip->vpcie0v9);
893
894 return ret;
895 }
896
rockchip_pcie_resume_noirq(struct device * dev)897 static int rockchip_pcie_resume_noirq(struct device *dev)
898 {
899 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
900 int err;
901
902 err = regulator_enable(rockchip->vpcie0v9);
903 if (err) {
904 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
905 return err;
906 }
907
908 err = rockchip_pcie_enable_clocks(rockchip);
909 if (err)
910 goto err_disable_0v9;
911
912 err = rockchip_pcie_host_init_port(rockchip);
913 if (err)
914 goto err_pcie_resume;
915
916 err = rockchip_pcie_cfg_atu(rockchip);
917 if (err)
918 goto err_err_deinit_port;
919
920 /* Need this to enter L1 again */
921 rockchip_pcie_update_txcredit_mui(rockchip);
922 rockchip_pcie_enable_interrupts(rockchip);
923
924 return 0;
925
926 err_err_deinit_port:
927 rockchip_pcie_deinit_phys(rockchip);
928 err_pcie_resume:
929 rockchip_pcie_disable_clocks(rockchip);
930 err_disable_0v9:
931 regulator_disable(rockchip->vpcie0v9);
932 return err;
933 }
934
rockchip_pcie_probe(struct platform_device * pdev)935 static int rockchip_pcie_probe(struct platform_device *pdev)
936 {
937 struct rockchip_pcie *rockchip;
938 struct device *dev = &pdev->dev;
939 struct pci_host_bridge *bridge;
940 int err;
941
942 if (!dev->of_node)
943 return -ENODEV;
944
945 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
946 if (!bridge)
947 return -ENOMEM;
948
949 rockchip = pci_host_bridge_priv(bridge);
950
951 platform_set_drvdata(pdev, rockchip);
952 rockchip->dev = dev;
953 rockchip->is_rc = true;
954
955 err = rockchip_pcie_parse_host_dt(rockchip);
956 if (err)
957 return err;
958
959 err = rockchip_pcie_enable_clocks(rockchip);
960 if (err)
961 return err;
962
963 err = rockchip_pcie_set_vpcie(rockchip);
964 if (err) {
965 dev_err(dev, "failed to set vpcie regulator\n");
966 goto err_set_vpcie;
967 }
968
969 err = rockchip_pcie_host_init_port(rockchip);
970 if (err)
971 goto err_vpcie;
972
973 err = rockchip_pcie_init_irq_domain(rockchip);
974 if (err < 0)
975 goto err_deinit_port;
976
977 err = rockchip_pcie_cfg_atu(rockchip);
978 if (err)
979 goto err_remove_irq_domain;
980
981 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
982 if (!rockchip->msg_region) {
983 err = -ENOMEM;
984 goto err_remove_irq_domain;
985 }
986
987 bridge->sysdata = rockchip;
988 bridge->ops = &rockchip_pcie_ops;
989
990 err = rockchip_pcie_setup_irq(rockchip);
991 if (err)
992 goto err_remove_irq_domain;
993
994 rockchip_pcie_enable_interrupts(rockchip);
995
996 err = pci_host_probe(bridge);
997 if (err < 0)
998 goto err_remove_irq_domain;
999
1000 return 0;
1001
1002 err_remove_irq_domain:
1003 irq_domain_remove(rockchip->irq_domain);
1004 err_deinit_port:
1005 rockchip_pcie_deinit_phys(rockchip);
1006 err_vpcie:
1007 if (!IS_ERR(rockchip->vpcie12v))
1008 regulator_disable(rockchip->vpcie12v);
1009 if (!IS_ERR(rockchip->vpcie3v3))
1010 regulator_disable(rockchip->vpcie3v3);
1011 regulator_disable(rockchip->vpcie1v8);
1012 regulator_disable(rockchip->vpcie0v9);
1013 err_set_vpcie:
1014 rockchip_pcie_disable_clocks(rockchip);
1015 return err;
1016 }
1017
rockchip_pcie_remove(struct platform_device * pdev)1018 static void rockchip_pcie_remove(struct platform_device *pdev)
1019 {
1020 struct device *dev = &pdev->dev;
1021 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1022 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
1023
1024 pci_stop_root_bus(bridge->bus);
1025 pci_remove_root_bus(bridge->bus);
1026 irq_domain_remove(rockchip->irq_domain);
1027
1028 rockchip_pcie_deinit_phys(rockchip);
1029
1030 rockchip_pcie_disable_clocks(rockchip);
1031
1032 if (!IS_ERR(rockchip->vpcie12v))
1033 regulator_disable(rockchip->vpcie12v);
1034 if (!IS_ERR(rockchip->vpcie3v3))
1035 regulator_disable(rockchip->vpcie3v3);
1036 regulator_disable(rockchip->vpcie1v8);
1037 regulator_disable(rockchip->vpcie0v9);
1038 }
1039
1040 static const struct dev_pm_ops rockchip_pcie_pm_ops = {
1041 NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq,
1042 rockchip_pcie_resume_noirq)
1043 };
1044
1045 static const struct of_device_id rockchip_pcie_of_match[] = {
1046 { .compatible = "rockchip,rk3399-pcie", },
1047 {}
1048 };
1049 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match);
1050
1051 static struct platform_driver rockchip_pcie_driver = {
1052 .driver = {
1053 .name = "rockchip-pcie",
1054 .of_match_table = rockchip_pcie_of_match,
1055 .pm = &rockchip_pcie_pm_ops,
1056 },
1057 .probe = rockchip_pcie_probe,
1058 .remove = rockchip_pcie_remove,
1059 };
1060 module_platform_driver(rockchip_pcie_driver);
1061
1062 MODULE_AUTHOR("Rockchip Inc");
1063 MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
1064 MODULE_LICENSE("GPL v2");
1065