1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Express Downstream Port Containment services driver
4 * Author: Keith Busch <keith.busch@intel.com>
5 *
6 * Copyright (C) 2016 Intel Corp.
7 */
8
9 #define dev_fmt(fmt) "DPC: " fmt
10
11 #include <linux/aer.h>
12 #include <linux/bitfield.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17
18 #include "portdrv.h"
19 #include "../pci.h"
20
21 #define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL | \
22 PCI_EXP_DPC_CTL_EN_NONFATAL)
23
24 static const char * const rp_pio_error_string[] = {
25 "Configuration Request received UR Completion", /* Bit Position 0 */
26 "Configuration Request received CA Completion", /* Bit Position 1 */
27 "Configuration Request Completion Timeout", /* Bit Position 2 */
28 NULL,
29 NULL,
30 NULL,
31 NULL,
32 NULL,
33 "I/O Request received UR Completion", /* Bit Position 8 */
34 "I/O Request received CA Completion", /* Bit Position 9 */
35 "I/O Request Completion Timeout", /* Bit Position 10 */
36 NULL,
37 NULL,
38 NULL,
39 NULL,
40 NULL,
41 "Memory Request received UR Completion", /* Bit Position 16 */
42 "Memory Request received CA Completion", /* Bit Position 17 */
43 "Memory Request Completion Timeout", /* Bit Position 18 */
44 };
45
pci_save_dpc_state(struct pci_dev * dev)46 void pci_save_dpc_state(struct pci_dev *dev)
47 {
48 struct pci_cap_saved_state *save_state;
49 u16 *cap;
50
51 if (!pci_is_pcie(dev))
52 return;
53
54 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
55 if (!save_state)
56 return;
57
58 cap = (u16 *)&save_state->cap.data[0];
59 pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
60 }
61
pci_restore_dpc_state(struct pci_dev * dev)62 void pci_restore_dpc_state(struct pci_dev *dev)
63 {
64 struct pci_cap_saved_state *save_state;
65 u16 *cap;
66
67 if (!pci_is_pcie(dev))
68 return;
69
70 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
71 if (!save_state)
72 return;
73
74 cap = (u16 *)&save_state->cap.data[0];
75 pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
76 }
77
78 static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue);
79
80 #ifdef CONFIG_HOTPLUG_PCI_PCIE
dpc_completed(struct pci_dev * pdev)81 static bool dpc_completed(struct pci_dev *pdev)
82 {
83 u16 status;
84
85 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
86 if ((!PCI_POSSIBLE_ERROR(status)) && (status & PCI_EXP_DPC_STATUS_TRIGGER))
87 return false;
88
89 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
90 return false;
91
92 return true;
93 }
94
95 /**
96 * pci_dpc_recovered - whether DPC triggered and has recovered successfully
97 * @pdev: PCI device
98 *
99 * Return true if DPC was triggered for @pdev and has recovered successfully.
100 * Wait for recovery if it hasn't completed yet. Called from the PCIe hotplug
101 * driver to recognize and ignore Link Down/Up events caused by DPC.
102 */
pci_dpc_recovered(struct pci_dev * pdev)103 bool pci_dpc_recovered(struct pci_dev *pdev)
104 {
105 struct pci_host_bridge *host;
106
107 if (!pdev->dpc_cap)
108 return false;
109
110 /*
111 * Synchronization between hotplug and DPC is not supported
112 * if DPC is owned by firmware and EDR is not enabled.
113 */
114 host = pci_find_host_bridge(pdev->bus);
115 if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR))
116 return false;
117
118 /*
119 * Need a timeout in case DPC never completes due to failure of
120 * dpc_wait_rp_inactive(). The spec doesn't mandate a time limit,
121 * but reports indicate that DPC completes within 4 seconds.
122 */
123 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
124 msecs_to_jiffies(4000));
125
126 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
127 }
128 #endif /* CONFIG_HOTPLUG_PCI_PCIE */
129
dpc_wait_rp_inactive(struct pci_dev * pdev)130 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
131 {
132 unsigned long timeout = jiffies + HZ;
133 u16 cap = pdev->dpc_cap, status;
134
135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
136 while (status & PCI_EXP_DPC_RP_BUSY &&
137 !time_after(jiffies, timeout)) {
138 msleep(10);
139 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
140 }
141 if (status & PCI_EXP_DPC_RP_BUSY) {
142 pci_warn(pdev, "root port still busy\n");
143 return -EBUSY;
144 }
145 return 0;
146 }
147
dpc_reset_link(struct pci_dev * pdev)148 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
149 {
150 pci_ers_result_t ret;
151 u16 cap;
152
153 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
154
155 /*
156 * DPC disables the Link automatically in hardware, so it has
157 * already been reset by the time we get here.
158 */
159 cap = pdev->dpc_cap;
160
161 /*
162 * Wait until the Link is inactive, then clear DPC Trigger Status
163 * to allow the Port to leave DPC.
164 */
165 if (!pcie_wait_for_link(pdev, false))
166 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
167
168 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
169 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
170 ret = PCI_ERS_RESULT_DISCONNECT;
171 goto out;
172 }
173
174 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
175 PCI_EXP_DPC_STATUS_TRIGGER);
176
177 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {
178 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
179 ret = PCI_ERS_RESULT_DISCONNECT;
180 } else {
181 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
182 ret = PCI_ERS_RESULT_RECOVERED;
183 }
184 out:
185 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
186 wake_up_all(&dpc_completed_waitqueue);
187 return ret;
188 }
189
dpc_process_rp_pio_error(struct pci_dev * pdev)190 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
191 {
192 u16 cap = pdev->dpc_cap, dpc_status, first_error;
193 u32 status, mask, sev, syserr, exc, log, prefix;
194 struct pcie_tlp_log tlp_log;
195 int i;
196
197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
198 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
199 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
200 status, mask);
201
202 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
203 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
204 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
205 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
206 sev, syserr, exc);
207
208 /* Get First Error Pointer */
209 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
210 first_error = FIELD_GET(PCI_EXP_DPC_RP_PIO_FEP, dpc_status);
211
212 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
213 if ((status & ~mask) & (1 << i))
214 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
215 first_error == i ? " (First)" : "");
216 }
217
218 if (pdev->dpc_rp_log_size < 4)
219 goto clear_status;
220 pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, &tlp_log);
221 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
222 tlp_log.dw[0], tlp_log.dw[1], tlp_log.dw[2], tlp_log.dw[3]);
223
224 if (pdev->dpc_rp_log_size < 5)
225 goto clear_status;
226 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
227 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
228
229 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
230 pci_read_config_dword(pdev,
231 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG + i * 4, &prefix);
232 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
233 }
234 clear_status:
235 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
236 }
237
dpc_get_aer_uncorrect_severity(struct pci_dev * dev,struct aer_err_info * info)238 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
239 struct aer_err_info *info)
240 {
241 int pos = dev->aer_cap;
242 u32 status, mask, sev;
243
244 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
245 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
246 status &= ~mask;
247 if (!status)
248 return 0;
249
250 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
251 status &= sev;
252 if (status)
253 info->severity = AER_FATAL;
254 else
255 info->severity = AER_NONFATAL;
256
257 return 1;
258 }
259
dpc_process_error(struct pci_dev * pdev)260 void dpc_process_error(struct pci_dev *pdev)
261 {
262 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
263 struct aer_err_info info = {};
264
265 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
266
267 reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN;
268
269 switch (reason) {
270 case PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR:
271 pci_warn(pdev, "containment event, status:%#06x: unmasked uncorrectable error detected\n",
272 status);
273 if (dpc_get_aer_uncorrect_severity(pdev, &info) &&
274 aer_get_device_error_info(pdev, &info)) {
275 aer_print_error(pdev, &info);
276 pci_aer_clear_nonfatal_status(pdev);
277 pci_aer_clear_fatal_status(pdev);
278 }
279 break;
280 case PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE:
281 case PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE:
282 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
283 &source);
284 pci_warn(pdev, "containment event, status:%#06x, %s received from %04x:%02x:%02x.%d\n",
285 status,
286 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE) ?
287 "ERR_FATAL" : "ERR_NONFATAL",
288 pci_domain_nr(pdev->bus), PCI_BUS_NUM(source),
289 PCI_SLOT(source), PCI_FUNC(source));
290 break;
291 case PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT:
292 ext_reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT;
293 pci_warn(pdev, "containment event, status:%#06x: %s detected\n",
294 status,
295 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) ?
296 "RP PIO error" :
297 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER) ?
298 "software trigger" :
299 "reserved error");
300 /* show RP PIO error detail information */
301 if (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO &&
302 pdev->dpc_rp_extensions)
303 dpc_process_rp_pio_error(pdev);
304 break;
305 }
306 }
307
pci_clear_surpdn_errors(struct pci_dev * pdev)308 static void pci_clear_surpdn_errors(struct pci_dev *pdev)
309 {
310 if (pdev->dpc_rp_extensions)
311 pci_write_config_dword(pdev, pdev->dpc_cap +
312 PCI_EXP_DPC_RP_PIO_STATUS, ~0);
313
314 /*
315 * In practice, Surprise Down errors have been observed to also set
316 * error bits in the Status Register as well as the Fatal Error
317 * Detected bit in the Device Status Register.
318 */
319 pci_write_config_word(pdev, PCI_STATUS, 0xffff);
320
321 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_FED);
322 }
323
dpc_handle_surprise_removal(struct pci_dev * pdev)324 static void dpc_handle_surprise_removal(struct pci_dev *pdev)
325 {
326 if (!pcie_wait_for_link(pdev, false)) {
327 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
328 goto out;
329 }
330
331 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))
332 goto out;
333
334 pci_aer_raw_clear_status(pdev);
335 pci_clear_surpdn_errors(pdev);
336
337 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS,
338 PCI_EXP_DPC_STATUS_TRIGGER);
339
340 out:
341 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
342 wake_up_all(&dpc_completed_waitqueue);
343 }
344
dpc_is_surprise_removal(struct pci_dev * pdev)345 static bool dpc_is_surprise_removal(struct pci_dev *pdev)
346 {
347 u16 status;
348
349 if (!pdev->is_hotplug_bridge)
350 return false;
351
352 if (pci_read_config_word(pdev, pdev->aer_cap + PCI_ERR_UNCOR_STATUS,
353 &status))
354 return false;
355
356 return status & PCI_ERR_UNC_SURPDN;
357 }
358
dpc_handler(int irq,void * context)359 static irqreturn_t dpc_handler(int irq, void *context)
360 {
361 struct pci_dev *pdev = context;
362
363 /*
364 * According to PCIe r6.0 sec 6.7.6, errors are an expected side effect
365 * of async removal and should be ignored by software.
366 */
367 if (dpc_is_surprise_removal(pdev)) {
368 dpc_handle_surprise_removal(pdev);
369 return IRQ_HANDLED;
370 }
371
372 dpc_process_error(pdev);
373
374 /* We configure DPC so it only triggers on ERR_FATAL */
375 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
376
377 return IRQ_HANDLED;
378 }
379
dpc_irq(int irq,void * context)380 static irqreturn_t dpc_irq(int irq, void *context)
381 {
382 struct pci_dev *pdev = context;
383 u16 cap = pdev->dpc_cap, status;
384
385 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
386
387 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || PCI_POSSIBLE_ERROR(status))
388 return IRQ_NONE;
389
390 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
391 PCI_EXP_DPC_STATUS_INTERRUPT);
392 if (status & PCI_EXP_DPC_STATUS_TRIGGER)
393 return IRQ_WAKE_THREAD;
394 return IRQ_HANDLED;
395 }
396
pci_dpc_init(struct pci_dev * pdev)397 void pci_dpc_init(struct pci_dev *pdev)
398 {
399 u16 cap;
400
401 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
402 if (!pdev->dpc_cap)
403 return;
404
405 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
406 if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
407 return;
408
409 pdev->dpc_rp_extensions = true;
410
411 /* Quirks may set dpc_rp_log_size if device or firmware is buggy */
412 if (!pdev->dpc_rp_log_size) {
413 pdev->dpc_rp_log_size =
414 FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap);
415 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
416 pci_err(pdev, "RP PIO log size %u is invalid\n",
417 pdev->dpc_rp_log_size);
418 pdev->dpc_rp_log_size = 0;
419 }
420 }
421 }
422
dpc_enable(struct pcie_device * dev)423 static void dpc_enable(struct pcie_device *dev)
424 {
425 struct pci_dev *pdev = dev->port;
426 int dpc = pdev->dpc_cap;
427 u16 ctl;
428
429 /*
430 * Clear DPC Interrupt Status so we don't get an interrupt for an
431 * old event when setting DPC Interrupt Enable.
432 */
433 pci_write_config_word(pdev, dpc + PCI_EXP_DPC_STATUS,
434 PCI_EXP_DPC_STATUS_INTERRUPT);
435
436 pci_read_config_word(pdev, dpc + PCI_EXP_DPC_CTL, &ctl);
437 ctl &= ~PCI_EXP_DPC_CTL_EN_MASK;
438 ctl |= PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
439 pci_write_config_word(pdev, dpc + PCI_EXP_DPC_CTL, ctl);
440 }
441
dpc_disable(struct pcie_device * dev)442 static void dpc_disable(struct pcie_device *dev)
443 {
444 struct pci_dev *pdev = dev->port;
445 int dpc = pdev->dpc_cap;
446 u16 ctl;
447
448 /* Disable DPC triggering and DPC interrupts */
449 pci_read_config_word(pdev, dpc + PCI_EXP_DPC_CTL, &ctl);
450 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
451 pci_write_config_word(pdev, dpc + PCI_EXP_DPC_CTL, ctl);
452 }
453
454 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
dpc_probe(struct pcie_device * dev)455 static int dpc_probe(struct pcie_device *dev)
456 {
457 struct pci_dev *pdev = dev->port;
458 struct device *device = &dev->device;
459 int status;
460 u16 cap;
461
462 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
463 return -ENOTSUPP;
464
465 status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
466 dpc_handler, IRQF_SHARED,
467 "pcie-dpc", pdev);
468 if (status) {
469 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
470 status);
471 return status;
472 }
473
474 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
475 dpc_enable(dev);
476
477 pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
478 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
479 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
480 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
481 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
482 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
483
484 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
485 return status;
486 }
487
dpc_suspend(struct pcie_device * dev)488 static int dpc_suspend(struct pcie_device *dev)
489 {
490 dpc_disable(dev);
491 return 0;
492 }
493
dpc_resume(struct pcie_device * dev)494 static int dpc_resume(struct pcie_device *dev)
495 {
496 dpc_enable(dev);
497 return 0;
498 }
499
dpc_remove(struct pcie_device * dev)500 static void dpc_remove(struct pcie_device *dev)
501 {
502 dpc_disable(dev);
503 }
504
505 static struct pcie_port_service_driver dpcdriver = {
506 .name = "dpc",
507 .port_type = PCIE_ANY_PORT,
508 .service = PCIE_PORT_SERVICE_DPC,
509 .probe = dpc_probe,
510 .suspend = dpc_suspend,
511 .resume = dpc_resume,
512 .remove = dpc_remove,
513 };
514
pcie_dpc_init(void)515 int __init pcie_dpc_init(void)
516 {
517 return pcie_port_service_register(&dpcdriver);
518 }
519