1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RISC-V performance counter support.
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 *
7 * This code is based on ARM perf event code which is in turn based on
8 * sparc64 and x86 code.
9 */
10
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
12
13 #include <linux/mod_devicetable.h>
14 #include <linux/perf/riscv_pmu.h>
15 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/of_irq.h>
19 #include <linux/of.h>
20 #include <linux/cpu_pm.h>
21 #include <linux/sched/clock.h>
22 #include <linux/soc/andes/irq.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/errata_list.h>
26 #include <asm/sbi.h>
27 #include <asm/cpufeature.h>
28 #include <asm/vendor_extensions.h>
29 #include <asm/vendor_extensions/andes.h>
30
31 #define ALT_SBI_PMU_OVERFLOW(__ovl) \
32 asm volatile(ALTERNATIVE_2( \
33 "csrr %0, " __stringify(CSR_SCOUNTOVF), \
34 "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
35 THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
36 CONFIG_ERRATA_THEAD_PMU, \
37 "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \
38 ANDES_VENDOR_ID, \
39 RISCV_ISA_VENDOR_EXT_XANDESPMU + RISCV_VENDOR_EXT_ALTERNATIVES_BASE, \
40 CONFIG_ANDES_CUSTOM_PMU) \
41 : "=r" (__ovl) : \
42 : "memory")
43
44 #define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask) \
45 asm volatile(ALTERNATIVE( \
46 "csrc " __stringify(CSR_IP) ", %0\n\t", \
47 "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \
48 ANDES_VENDOR_ID, \
49 RISCV_ISA_VENDOR_EXT_XANDESPMU + RISCV_VENDOR_EXT_ALTERNATIVES_BASE, \
50 CONFIG_ANDES_CUSTOM_PMU) \
51 : : "r"(__irq_mask) \
52 : "memory")
53
54 #define SYSCTL_NO_USER_ACCESS 0
55 #define SYSCTL_USER_ACCESS 1
56 #define SYSCTL_LEGACY 2
57
58 #define PERF_EVENT_FLAG_NO_USER_ACCESS BIT(SYSCTL_NO_USER_ACCESS)
59 #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS)
60 #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY)
61
62 PMU_FORMAT_ATTR(event, "config:0-47");
63 PMU_FORMAT_ATTR(firmware, "config:62-63");
64
65 static bool sbi_v2_available;
66 static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available);
67 #define sbi_pmu_snapshot_available() \
68 static_branch_unlikely(&sbi_pmu_snapshot_available)
69
70 static struct attribute *riscv_arch_formats_attr[] = {
71 &format_attr_event.attr,
72 &format_attr_firmware.attr,
73 NULL,
74 };
75
76 static struct attribute_group riscv_pmu_format_group = {
77 .name = "format",
78 .attrs = riscv_arch_formats_attr,
79 };
80
81 static const struct attribute_group *riscv_pmu_attr_groups[] = {
82 &riscv_pmu_format_group,
83 NULL,
84 };
85
86 /* Allow user mode access by default */
87 static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS;
88
89 /*
90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
91 * per_cpu in case of harts with different pmu counters
92 */
93 static union sbi_pmu_ctr_info *pmu_ctr_list;
94 static bool riscv_pmu_use_irq;
95 static unsigned int riscv_pmu_irq_num;
96 static unsigned int riscv_pmu_irq_mask;
97 static unsigned int riscv_pmu_irq;
98
99 /* Cache the available counters in a bitmask */
100 static unsigned long cmask;
101
102 struct sbi_pmu_event_data {
103 union {
104 union {
105 struct hw_gen_event {
106 uint32_t event_code:16;
107 uint32_t event_type:4;
108 uint32_t reserved:12;
109 } hw_gen_event;
110 struct hw_cache_event {
111 uint32_t result_id:1;
112 uint32_t op_id:2;
113 uint32_t cache_id:13;
114 uint32_t event_type:4;
115 uint32_t reserved:12;
116 } hw_cache_event;
117 };
118 uint32_t event_idx;
119 };
120 };
121
122 static struct sbi_pmu_event_data pmu_hw_event_map[] = {
123 [PERF_COUNT_HW_CPU_CYCLES] = {.hw_gen_event = {
124 SBI_PMU_HW_CPU_CYCLES,
125 SBI_PMU_EVENT_TYPE_HW, 0}},
126 [PERF_COUNT_HW_INSTRUCTIONS] = {.hw_gen_event = {
127 SBI_PMU_HW_INSTRUCTIONS,
128 SBI_PMU_EVENT_TYPE_HW, 0}},
129 [PERF_COUNT_HW_CACHE_REFERENCES] = {.hw_gen_event = {
130 SBI_PMU_HW_CACHE_REFERENCES,
131 SBI_PMU_EVENT_TYPE_HW, 0}},
132 [PERF_COUNT_HW_CACHE_MISSES] = {.hw_gen_event = {
133 SBI_PMU_HW_CACHE_MISSES,
134 SBI_PMU_EVENT_TYPE_HW, 0}},
135 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = {.hw_gen_event = {
136 SBI_PMU_HW_BRANCH_INSTRUCTIONS,
137 SBI_PMU_EVENT_TYPE_HW, 0}},
138 [PERF_COUNT_HW_BRANCH_MISSES] = {.hw_gen_event = {
139 SBI_PMU_HW_BRANCH_MISSES,
140 SBI_PMU_EVENT_TYPE_HW, 0}},
141 [PERF_COUNT_HW_BUS_CYCLES] = {.hw_gen_event = {
142 SBI_PMU_HW_BUS_CYCLES,
143 SBI_PMU_EVENT_TYPE_HW, 0}},
144 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = {.hw_gen_event = {
145 SBI_PMU_HW_STALLED_CYCLES_FRONTEND,
146 SBI_PMU_EVENT_TYPE_HW, 0}},
147 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = {.hw_gen_event = {
148 SBI_PMU_HW_STALLED_CYCLES_BACKEND,
149 SBI_PMU_EVENT_TYPE_HW, 0}},
150 [PERF_COUNT_HW_REF_CPU_CYCLES] = {.hw_gen_event = {
151 SBI_PMU_HW_REF_CPU_CYCLES,
152 SBI_PMU_EVENT_TYPE_HW, 0}},
153 };
154
155 #define C(x) PERF_COUNT_HW_CACHE_##x
156 static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
157 [PERF_COUNT_HW_CACHE_OP_MAX]
158 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
159 [C(L1D)] = {
160 [C(OP_READ)] = {
161 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
162 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
163 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
164 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
165 },
166 [C(OP_WRITE)] = {
167 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
168 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
169 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
170 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
171 },
172 [C(OP_PREFETCH)] = {
173 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
174 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
175 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
176 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
177 },
178 },
179 [C(L1I)] = {
180 [C(OP_READ)] = {
181 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
182 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
183 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
184 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
185 },
186 [C(OP_WRITE)] = {
187 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
188 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
189 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
190 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
191 },
192 [C(OP_PREFETCH)] = {
193 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
194 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
195 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
196 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
197 },
198 },
199 [C(LL)] = {
200 [C(OP_READ)] = {
201 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
202 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
203 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
204 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
205 },
206 [C(OP_WRITE)] = {
207 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
208 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
209 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
210 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
211 },
212 [C(OP_PREFETCH)] = {
213 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
214 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
215 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
216 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
217 },
218 },
219 [C(DTLB)] = {
220 [C(OP_READ)] = {
221 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
222 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
223 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
224 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
225 },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
228 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
229 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
230 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
231 },
232 [C(OP_PREFETCH)] = {
233 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
234 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
235 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
236 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
237 },
238 },
239 [C(ITLB)] = {
240 [C(OP_READ)] = {
241 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
242 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
243 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
244 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
245 },
246 [C(OP_WRITE)] = {
247 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
248 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
249 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
250 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
251 },
252 [C(OP_PREFETCH)] = {
253 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
254 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
255 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
256 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
257 },
258 },
259 [C(BPU)] = {
260 [C(OP_READ)] = {
261 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
262 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
263 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
264 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
265 },
266 [C(OP_WRITE)] = {
267 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
268 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
269 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
270 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
271 },
272 [C(OP_PREFETCH)] = {
273 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
274 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
275 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
276 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
277 },
278 },
279 [C(NODE)] = {
280 [C(OP_READ)] = {
281 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
282 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
283 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
284 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
285 },
286 [C(OP_WRITE)] = {
287 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
288 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
289 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
290 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
291 },
292 [C(OP_PREFETCH)] = {
293 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
294 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
295 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
296 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
297 },
298 },
299 };
300
pmu_sbi_check_event(struct sbi_pmu_event_data * edata)301 static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata)
302 {
303 struct sbiret ret;
304
305 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH,
306 0, cmask, 0, edata->event_idx, 0, 0);
307 if (!ret.error) {
308 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
309 ret.value, 0x1, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
310 } else if (ret.error == SBI_ERR_NOT_SUPPORTED) {
311 /* This event cannot be monitored by any counter */
312 edata->event_idx = -ENOENT;
313 }
314 }
315
pmu_sbi_check_std_events(struct work_struct * work)316 static void pmu_sbi_check_std_events(struct work_struct *work)
317 {
318 for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++)
319 pmu_sbi_check_event(&pmu_hw_event_map[i]);
320
321 for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++)
322 for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++)
323 for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++)
324 pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]);
325 }
326
327 static DECLARE_WORK(check_std_events_work, pmu_sbi_check_std_events);
328
pmu_sbi_ctr_get_width(int idx)329 static int pmu_sbi_ctr_get_width(int idx)
330 {
331 return pmu_ctr_list[idx].width;
332 }
333
pmu_sbi_ctr_is_fw(int cidx)334 static bool pmu_sbi_ctr_is_fw(int cidx)
335 {
336 union sbi_pmu_ctr_info *info;
337
338 info = &pmu_ctr_list[cidx];
339 if (!info)
340 return false;
341
342 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
343 }
344
345 /*
346 * Returns the counter width of a programmable counter and number of hardware
347 * counters. As we don't support heterogeneous CPUs yet, it is okay to just
348 * return the counter width of the first programmable counter.
349 */
riscv_pmu_get_hpm_info(u32 * hw_ctr_width,u32 * num_hw_ctr)350 int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr)
351 {
352 int i;
353 union sbi_pmu_ctr_info *info;
354 u32 hpm_width = 0, hpm_count = 0;
355
356 if (!cmask)
357 return -EINVAL;
358
359 for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) {
360 info = &pmu_ctr_list[i];
361 if (!info)
362 continue;
363 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET)
364 hpm_width = info->width;
365 if (info->type == SBI_PMU_CTR_TYPE_HW)
366 hpm_count++;
367 }
368
369 *hw_ctr_width = hpm_width;
370 *num_hw_ctr = hpm_count;
371
372 return 0;
373 }
374 EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info);
375
pmu_sbi_csr_index(struct perf_event * event)376 static uint8_t pmu_sbi_csr_index(struct perf_event *event)
377 {
378 return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE;
379 }
380
pmu_sbi_get_filter_flags(struct perf_event * event)381 static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event)
382 {
383 unsigned long cflags = 0;
384 bool guest_events = false;
385
386 if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS)
387 guest_events = true;
388 if (event->attr.exclude_kernel)
389 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH;
390 if (event->attr.exclude_user)
391 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH;
392 if (guest_events && event->attr.exclude_hv)
393 cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
394 if (event->attr.exclude_host)
395 cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH;
396 if (event->attr.exclude_guest)
397 cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH;
398
399 return cflags;
400 }
401
pmu_sbi_ctr_get_idx(struct perf_event * event)402 static int pmu_sbi_ctr_get_idx(struct perf_event *event)
403 {
404 struct hw_perf_event *hwc = &event->hw;
405 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
406 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
407 struct sbiret ret;
408 int idx;
409 uint64_t cbase = 0, cmask = rvpmu->cmask;
410 unsigned long cflags = 0;
411
412 cflags = pmu_sbi_get_filter_flags(event);
413
414 /*
415 * In legacy mode, we have to force the fixed counters for those events
416 * but not in the user access mode as we want to use the other counters
417 * that support sampling/filtering.
418 */
419 if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) {
420 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) {
421 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
422 cmask = 1;
423 } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) {
424 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
425 cmask = BIT(CSR_INSTRET - CSR_CYCLE);
426 }
427 }
428
429 /* retrieve the available counter index */
430 #if defined(CONFIG_32BIT)
431 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
432 cmask, cflags, hwc->event_base, hwc->config,
433 hwc->config >> 32);
434 #else
435 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
436 cmask, cflags, hwc->event_base, hwc->config, 0);
437 #endif
438 if (ret.error) {
439 pr_debug("Not able to find a counter for event %lx config %llx\n",
440 hwc->event_base, hwc->config);
441 return sbi_err_map_linux_errno(ret.error);
442 }
443
444 idx = ret.value;
445 if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value)
446 return -ENOENT;
447
448 /* Additional sanity check for the counter id */
449 if (pmu_sbi_ctr_is_fw(idx)) {
450 if (!test_and_set_bit(idx, cpuc->used_fw_ctrs))
451 return idx;
452 } else {
453 if (!test_and_set_bit(idx, cpuc->used_hw_ctrs))
454 return idx;
455 }
456
457 return -ENOENT;
458 }
459
pmu_sbi_ctr_clear_idx(struct perf_event * event)460 static void pmu_sbi_ctr_clear_idx(struct perf_event *event)
461 {
462
463 struct hw_perf_event *hwc = &event->hw;
464 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
465 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
466 int idx = hwc->idx;
467
468 if (pmu_sbi_ctr_is_fw(idx))
469 clear_bit(idx, cpuc->used_fw_ctrs);
470 else
471 clear_bit(idx, cpuc->used_hw_ctrs);
472 }
473
pmu_event_find_cache(u64 config)474 static int pmu_event_find_cache(u64 config)
475 {
476 unsigned int cache_type, cache_op, cache_result, ret;
477
478 cache_type = (config >> 0) & 0xff;
479 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
480 return -EINVAL;
481
482 cache_op = (config >> 8) & 0xff;
483 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
484 return -EINVAL;
485
486 cache_result = (config >> 16) & 0xff;
487 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
488 return -EINVAL;
489
490 ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx;
491
492 return ret;
493 }
494
pmu_sbi_is_fw_event(struct perf_event * event)495 static bool pmu_sbi_is_fw_event(struct perf_event *event)
496 {
497 u32 type = event->attr.type;
498 u64 config = event->attr.config;
499
500 if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1))
501 return true;
502 else
503 return false;
504 }
505
pmu_sbi_event_map(struct perf_event * event,u64 * econfig)506 static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
507 {
508 u32 type = event->attr.type;
509 u64 config = event->attr.config;
510 int ret = -ENOENT;
511
512 /*
513 * Ensure we are finished checking standard hardware events for
514 * validity before allowing userspace to configure any events.
515 */
516 flush_work(&check_std_events_work);
517
518 switch (type) {
519 case PERF_TYPE_HARDWARE:
520 if (config >= PERF_COUNT_HW_MAX)
521 return -EINVAL;
522 ret = pmu_hw_event_map[event->attr.config].event_idx;
523 break;
524 case PERF_TYPE_HW_CACHE:
525 ret = pmu_event_find_cache(config);
526 break;
527 case PERF_TYPE_RAW:
528 /*
529 * As per SBI specification, the upper 16 bits must be unused
530 * for a hardware raw event.
531 * Bits 63:62 are used to distinguish between raw events
532 * 00 - Hardware raw event
533 * 10 - SBI firmware events
534 * 11 - Risc-V platform specific firmware event
535 */
536
537 switch (config >> 62) {
538 case 0:
539 ret = RISCV_PMU_RAW_EVENT_IDX;
540 *econfig = config & RISCV_PMU_RAW_EVENT_MASK;
541 break;
542 case 2:
543 ret = (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16);
544 break;
545 case 3:
546 /*
547 * For Risc-V platform specific firmware events
548 * Event code - 0xFFFF
549 * Event data - raw event encoding
550 */
551 ret = SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT;
552 *econfig = config & RISCV_PMU_PLAT_FW_EVENT_MASK;
553 break;
554 default:
555 break;
556 }
557 break;
558 default:
559 break;
560 }
561
562 return ret;
563 }
564
pmu_sbi_snapshot_free(struct riscv_pmu * pmu)565 static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu)
566 {
567 int cpu;
568
569 for_each_possible_cpu(cpu) {
570 struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
571
572 if (!cpu_hw_evt->snapshot_addr)
573 continue;
574
575 free_page((unsigned long)cpu_hw_evt->snapshot_addr);
576 cpu_hw_evt->snapshot_addr = NULL;
577 cpu_hw_evt->snapshot_addr_phys = 0;
578 }
579 }
580
pmu_sbi_snapshot_alloc(struct riscv_pmu * pmu)581 static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu)
582 {
583 int cpu;
584 struct page *snapshot_page;
585
586 for_each_possible_cpu(cpu) {
587 struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
588
589 snapshot_page = alloc_page(GFP_ATOMIC | __GFP_ZERO);
590 if (!snapshot_page) {
591 pmu_sbi_snapshot_free(pmu);
592 return -ENOMEM;
593 }
594 cpu_hw_evt->snapshot_addr = page_to_virt(snapshot_page);
595 cpu_hw_evt->snapshot_addr_phys = page_to_phys(snapshot_page);
596 }
597
598 return 0;
599 }
600
pmu_sbi_snapshot_disable(void)601 static int pmu_sbi_snapshot_disable(void)
602 {
603 struct sbiret ret;
604
605 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, SBI_SHMEM_DISABLE,
606 SBI_SHMEM_DISABLE, 0, 0, 0, 0);
607 if (ret.error) {
608 pr_warn("failed to disable snapshot shared memory\n");
609 return sbi_err_map_linux_errno(ret.error);
610 }
611
612 return 0;
613 }
614
pmu_sbi_snapshot_setup(struct riscv_pmu * pmu,int cpu)615 static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu)
616 {
617 struct cpu_hw_events *cpu_hw_evt;
618 struct sbiret ret = {0};
619
620 cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
621 if (!cpu_hw_evt->snapshot_addr_phys)
622 return -EINVAL;
623
624 if (cpu_hw_evt->snapshot_set_done)
625 return 0;
626
627 if (IS_ENABLED(CONFIG_32BIT))
628 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
629 cpu_hw_evt->snapshot_addr_phys,
630 (u64)(cpu_hw_evt->snapshot_addr_phys) >> 32, 0, 0, 0, 0);
631 else
632 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
633 cpu_hw_evt->snapshot_addr_phys, 0, 0, 0, 0, 0);
634
635 /* Free up the snapshot area memory and fall back to SBI PMU calls without snapshot */
636 if (ret.error) {
637 if (ret.error != SBI_ERR_NOT_SUPPORTED)
638 pr_warn("pmu snapshot setup failed with error %ld\n", ret.error);
639 return sbi_err_map_linux_errno(ret.error);
640 }
641
642 memset(cpu_hw_evt->snapshot_cval_shcopy, 0, sizeof(u64) * RISCV_MAX_COUNTERS);
643 cpu_hw_evt->snapshot_set_done = true;
644
645 return 0;
646 }
647
pmu_sbi_ctr_read(struct perf_event * event)648 static u64 pmu_sbi_ctr_read(struct perf_event *event)
649 {
650 struct hw_perf_event *hwc = &event->hw;
651 int idx = hwc->idx;
652 struct sbiret ret;
653 u64 val = 0;
654 struct riscv_pmu *pmu = to_riscv_pmu(event->pmu);
655 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
656 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
657 union sbi_pmu_ctr_info info = pmu_ctr_list[idx];
658
659 /* Read the value from the shared memory directly only if counter is stopped */
660 if (sbi_pmu_snapshot_available() && (hwc->state & PERF_HES_STOPPED)) {
661 val = sdata->ctr_values[idx];
662 return val;
663 }
664
665 if (pmu_sbi_is_fw_event(event)) {
666 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
667 hwc->idx, 0, 0, 0, 0, 0);
668 if (ret.error)
669 return 0;
670
671 val = ret.value;
672 if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) {
673 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI,
674 hwc->idx, 0, 0, 0, 0, 0);
675 if (!ret.error)
676 val |= ((u64)ret.value << 32);
677 else
678 WARN_ONCE(1, "Unable to read upper 32 bits of firmware counter error: %ld\n",
679 ret.error);
680 }
681 } else {
682 val = riscv_pmu_ctr_read_csr(info.csr);
683 if (IS_ENABLED(CONFIG_32BIT))
684 val |= ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32;
685 }
686
687 return val;
688 }
689
pmu_sbi_set_scounteren(void * arg)690 static void pmu_sbi_set_scounteren(void *arg)
691 {
692 struct perf_event *event = (struct perf_event *)arg;
693
694 if (event->hw.idx != -1)
695 csr_write(CSR_SCOUNTEREN,
696 csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event)));
697 }
698
pmu_sbi_reset_scounteren(void * arg)699 static void pmu_sbi_reset_scounteren(void *arg)
700 {
701 struct perf_event *event = (struct perf_event *)arg;
702
703 if (event->hw.idx != -1)
704 csr_write(CSR_SCOUNTEREN,
705 csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event)));
706 }
707
pmu_sbi_ctr_start(struct perf_event * event,u64 ival)708 static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
709 {
710 struct sbiret ret;
711 struct hw_perf_event *hwc = &event->hw;
712 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
713
714 /* There is no benefit setting SNAPSHOT FLAG for a single counter */
715 #if defined(CONFIG_32BIT)
716 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
717 1, flag, ival, ival >> 32, 0);
718 #else
719 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
720 1, flag, ival, 0, 0);
721 #endif
722 if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
723 pr_err("Starting counter idx %d failed with error %d\n",
724 hwc->idx, sbi_err_map_linux_errno(ret.error));
725
726 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) &&
727 (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
728 pmu_sbi_set_scounteren((void *)event);
729 }
730
pmu_sbi_ctr_stop(struct perf_event * event,unsigned long flag)731 static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
732 {
733 struct sbiret ret;
734 struct hw_perf_event *hwc = &event->hw;
735 struct riscv_pmu *pmu = to_riscv_pmu(event->pmu);
736 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
737 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
738
739 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) &&
740 (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
741 pmu_sbi_reset_scounteren((void *)event);
742
743 if (sbi_pmu_snapshot_available())
744 flag |= SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT;
745
746 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0);
747 if (!ret.error && sbi_pmu_snapshot_available()) {
748 /*
749 * The counter snapshot is based on the index base specified by hwc->idx.
750 * The actual counter value is updated in shared memory at index 0 when counter
751 * mask is 0x01. To ensure accurate counter values, it's necessary to transfer
752 * the counter value to shared memory. However, if hwc->idx is zero, the counter
753 * value is already correctly updated in shared memory, requiring no further
754 * adjustment.
755 */
756 if (hwc->idx > 0) {
757 sdata->ctr_values[hwc->idx] = sdata->ctr_values[0];
758 sdata->ctr_values[0] = 0;
759 }
760 } else if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
761 flag != SBI_PMU_STOP_FLAG_RESET) {
762 pr_err("Stopping counter idx %d failed with error %d\n",
763 hwc->idx, sbi_err_map_linux_errno(ret.error));
764 }
765 }
766
pmu_sbi_find_num_ctrs(void)767 static int pmu_sbi_find_num_ctrs(void)
768 {
769 struct sbiret ret;
770
771 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0);
772 if (!ret.error)
773 return ret.value;
774 else
775 return sbi_err_map_linux_errno(ret.error);
776 }
777
pmu_sbi_get_ctrinfo(int nctr,unsigned long * mask)778 static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
779 {
780 struct sbiret ret;
781 int i, num_hw_ctr = 0, num_fw_ctr = 0;
782 union sbi_pmu_ctr_info cinfo;
783
784 pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL);
785 if (!pmu_ctr_list)
786 return -ENOMEM;
787
788 for (i = 0; i < nctr; i++) {
789 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
790 if (ret.error)
791 /* The logical counter ids are not expected to be contiguous */
792 continue;
793
794 *mask |= BIT(i);
795
796 cinfo.value = ret.value;
797 if (cinfo.type == SBI_PMU_CTR_TYPE_FW)
798 num_fw_ctr++;
799 else
800 num_hw_ctr++;
801 pmu_ctr_list[i].value = cinfo.value;
802 }
803
804 pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr);
805
806 return 0;
807 }
808
pmu_sbi_stop_all(struct riscv_pmu * pmu)809 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
810 {
811 /*
812 * No need to check the error because we are disabling all the counters
813 * which may include counters that are not enabled yet.
814 */
815 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
816 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
817 }
818
pmu_sbi_stop_hw_ctrs(struct riscv_pmu * pmu)819 static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
820 {
821 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
822 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
823 unsigned long flag = 0;
824 int i, idx;
825 struct sbiret ret;
826 u64 temp_ctr_overflow_mask = 0;
827
828 if (sbi_pmu_snapshot_available())
829 flag = SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT;
830
831 /* Reset the shadow copy to avoid save/restore any value from previous overflow */
832 memset(cpu_hw_evt->snapshot_cval_shcopy, 0, sizeof(u64) * RISCV_MAX_COUNTERS);
833
834 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
835 /* No need to check the error here as we can't do anything about the error */
836 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, i * BITS_PER_LONG,
837 cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0);
838 if (!ret.error && sbi_pmu_snapshot_available()) {
839 /* Save the counter values to avoid clobbering */
840 for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG)
841 cpu_hw_evt->snapshot_cval_shcopy[i * BITS_PER_LONG + idx] =
842 sdata->ctr_values[idx];
843 /* Save the overflow mask to avoid clobbering */
844 temp_ctr_overflow_mask |= sdata->ctr_overflow_mask << (i * BITS_PER_LONG);
845 }
846 }
847
848 /* Restore the counter values to the shared memory for used hw counters */
849 if (sbi_pmu_snapshot_available()) {
850 for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS)
851 sdata->ctr_values[idx] = cpu_hw_evt->snapshot_cval_shcopy[idx];
852 if (temp_ctr_overflow_mask)
853 sdata->ctr_overflow_mask = temp_ctr_overflow_mask;
854 }
855 }
856
857 /*
858 * This function starts all the used counters in two step approach.
859 * Any counter that did not overflow can be start in a single step
860 * while the overflowed counters need to be started with updated initialization
861 * value.
862 */
pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events * cpu_hw_evt,u64 ctr_ovf_mask)863 static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt,
864 u64 ctr_ovf_mask)
865 {
866 int idx = 0, i;
867 struct perf_event *event;
868 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
869 unsigned long ctr_start_mask = 0;
870 uint64_t max_period;
871 struct hw_perf_event *hwc;
872 u64 init_val = 0;
873
874 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
875 ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask;
876 /* Start all the counters that did not overflow in a single shot */
877 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr_start_mask,
878 0, 0, 0, 0);
879 }
880
881 /* Reinitialize and start all the counter that overflowed */
882 while (ctr_ovf_mask) {
883 if (ctr_ovf_mask & 0x01) {
884 event = cpu_hw_evt->events[idx];
885 hwc = &event->hw;
886 max_period = riscv_pmu_ctr_get_width_mask(event);
887 init_val = local64_read(&hwc->prev_count) & max_period;
888 #if defined(CONFIG_32BIT)
889 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
890 flag, init_val, init_val >> 32, 0);
891 #else
892 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
893 flag, init_val, 0, 0);
894 #endif
895 perf_event_update_userpage(event);
896 }
897 ctr_ovf_mask = ctr_ovf_mask >> 1;
898 idx++;
899 }
900 }
901
pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events * cpu_hw_evt,u64 ctr_ovf_mask)902 static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt,
903 u64 ctr_ovf_mask)
904 {
905 int i, idx = 0;
906 struct perf_event *event;
907 unsigned long flag = SBI_PMU_START_FLAG_INIT_SNAPSHOT;
908 u64 max_period, init_val = 0;
909 struct hw_perf_event *hwc;
910 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
911
912 for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
913 if (ctr_ovf_mask & BIT(idx)) {
914 event = cpu_hw_evt->events[idx];
915 hwc = &event->hw;
916 max_period = riscv_pmu_ctr_get_width_mask(event);
917 init_val = local64_read(&hwc->prev_count) & max_period;
918 cpu_hw_evt->snapshot_cval_shcopy[idx] = init_val;
919 }
920 /*
921 * We do not need to update the non-overflow counters the previous
922 * value should have been there already.
923 */
924 }
925
926 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) {
927 /* Restore the counter values to relative indices for used hw counters */
928 for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG)
929 sdata->ctr_values[idx] =
930 cpu_hw_evt->snapshot_cval_shcopy[idx + i * BITS_PER_LONG];
931 /* Start all the counters in a single shot */
932 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx * BITS_PER_LONG,
933 cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0);
934 }
935 }
936
pmu_sbi_start_overflow_mask(struct riscv_pmu * pmu,u64 ctr_ovf_mask)937 static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
938 u64 ctr_ovf_mask)
939 {
940 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
941
942 if (sbi_pmu_snapshot_available())
943 pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask);
944 else
945 pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask);
946 }
947
pmu_sbi_ovf_handler(int irq,void * dev)948 static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
949 {
950 struct perf_sample_data data;
951 struct pt_regs *regs;
952 struct hw_perf_event *hw_evt;
953 union sbi_pmu_ctr_info *info;
954 int lidx, hidx, fidx;
955 struct riscv_pmu *pmu;
956 struct perf_event *event;
957 u64 overflow;
958 u64 overflowed_ctrs = 0;
959 struct cpu_hw_events *cpu_hw_evt = dev;
960 u64 start_clock = sched_clock();
961 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr;
962
963 if (WARN_ON_ONCE(!cpu_hw_evt))
964 return IRQ_NONE;
965
966 /* Firmware counter don't support overflow yet */
967 fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
968 if (fidx == RISCV_MAX_COUNTERS) {
969 csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
970 return IRQ_NONE;
971 }
972
973 event = cpu_hw_evt->events[fidx];
974 if (!event) {
975 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
976 return IRQ_NONE;
977 }
978
979 pmu = to_riscv_pmu(event->pmu);
980 pmu_sbi_stop_hw_ctrs(pmu);
981
982 /* Overflow status register should only be read after counter are stopped */
983 if (sbi_pmu_snapshot_available())
984 overflow = sdata->ctr_overflow_mask;
985 else
986 ALT_SBI_PMU_OVERFLOW(overflow);
987
988 /*
989 * Overflow interrupt pending bit should only be cleared after stopping
990 * all the counters to avoid any race condition.
991 */
992 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
993
994 /* No overflow bit is set */
995 if (!overflow)
996 return IRQ_NONE;
997
998 regs = get_irq_regs();
999
1000 for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
1001 struct perf_event *event = cpu_hw_evt->events[lidx];
1002
1003 /* Skip if invalid event or user did not request a sampling */
1004 if (!event || !is_sampling_event(event))
1005 continue;
1006
1007 info = &pmu_ctr_list[lidx];
1008 /* Do a sanity check */
1009 if (!info || info->type != SBI_PMU_CTR_TYPE_HW)
1010 continue;
1011
1012 if (sbi_pmu_snapshot_available())
1013 /* SBI implementation already updated the logical indicies */
1014 hidx = lidx;
1015 else
1016 /* compute hardware counter index */
1017 hidx = info->csr - CSR_CYCLE;
1018
1019 /* check if the corresponding bit is set in sscountovf or overflow mask in shmem */
1020 if (!(overflow & BIT(hidx)))
1021 continue;
1022
1023 /*
1024 * Keep a track of overflowed counters so that they can be started
1025 * with updated initial value.
1026 */
1027 overflowed_ctrs |= BIT(lidx);
1028 hw_evt = &event->hw;
1029 /* Update the event states here so that we know the state while reading */
1030 hw_evt->state |= PERF_HES_STOPPED;
1031 riscv_pmu_event_update(event);
1032 hw_evt->state |= PERF_HES_UPTODATE;
1033 perf_sample_data_init(&data, 0, hw_evt->last_period);
1034 if (riscv_pmu_event_set_period(event)) {
1035 /*
1036 * Unlike other ISAs, RISC-V don't have to disable interrupts
1037 * to avoid throttling here. As per the specification, the
1038 * interrupt remains disabled until the OF bit is set.
1039 * Interrupts are enabled again only during the start.
1040 * TODO: We will need to stop the guest counters once
1041 * virtualization support is added.
1042 */
1043 perf_event_overflow(event, &data, regs);
1044 }
1045 /* Reset the state as we are going to start the counter after the loop */
1046 hw_evt->state = 0;
1047 }
1048
1049 pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
1050 perf_sample_event_took(sched_clock() - start_clock);
1051
1052 return IRQ_HANDLED;
1053 }
1054
pmu_sbi_starting_cpu(unsigned int cpu,struct hlist_node * node)1055 static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
1056 {
1057 struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
1058 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
1059
1060 /*
1061 * We keep enabling userspace access to CYCLE, TIME and INSTRET via the
1062 * legacy option but that will be removed in the future.
1063 */
1064 if (sysctl_perf_user_access == SYSCTL_LEGACY)
1065 csr_write(CSR_SCOUNTEREN, 0x7);
1066 else
1067 csr_write(CSR_SCOUNTEREN, 0x2);
1068
1069 /* Stop all the counters so that they can be enabled from perf */
1070 pmu_sbi_stop_all(pmu);
1071
1072 if (riscv_pmu_use_irq) {
1073 cpu_hw_evt->irq = riscv_pmu_irq;
1074 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
1075 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
1076 }
1077
1078 if (sbi_pmu_snapshot_available())
1079 return pmu_sbi_snapshot_setup(pmu, cpu);
1080
1081 return 0;
1082 }
1083
pmu_sbi_dying_cpu(unsigned int cpu,struct hlist_node * node)1084 static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
1085 {
1086 if (riscv_pmu_use_irq) {
1087 disable_percpu_irq(riscv_pmu_irq);
1088 }
1089
1090 /* Disable all counters access for user mode now */
1091 csr_write(CSR_SCOUNTEREN, 0x0);
1092
1093 if (sbi_pmu_snapshot_available())
1094 return pmu_sbi_snapshot_disable();
1095
1096 return 0;
1097 }
1098
pmu_sbi_setup_irqs(struct riscv_pmu * pmu,struct platform_device * pdev)1099 static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev)
1100 {
1101 int ret;
1102 struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
1103 struct irq_domain *domain = NULL;
1104
1105 if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
1106 riscv_pmu_irq_num = RV_IRQ_PMU;
1107 riscv_pmu_use_irq = true;
1108 } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
1109 riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
1110 riscv_cached_marchid(0) == 0 &&
1111 riscv_cached_mimpid(0) == 0) {
1112 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
1113 riscv_pmu_use_irq = true;
1114 } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID,
1115 RISCV_ISA_VENDOR_EXT_XANDESPMU) &&
1116 IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) {
1117 riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI;
1118 riscv_pmu_use_irq = true;
1119 }
1120
1121 riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
1122
1123 if (!riscv_pmu_use_irq)
1124 return -EOPNOTSUPP;
1125
1126 domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(),
1127 DOMAIN_BUS_ANY);
1128 if (!domain) {
1129 pr_err("Failed to find INTC IRQ root domain\n");
1130 return -ENODEV;
1131 }
1132
1133 riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num);
1134 if (!riscv_pmu_irq) {
1135 pr_err("Failed to map PMU interrupt for node\n");
1136 return -ENODEV;
1137 }
1138
1139 ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
1140 if (ret) {
1141 pr_err("registering percpu irq failed [%d]\n", ret);
1142 return ret;
1143 }
1144
1145 return 0;
1146 }
1147
1148 #ifdef CONFIG_CPU_PM
riscv_pm_pmu_notify(struct notifier_block * b,unsigned long cmd,void * v)1149 static int riscv_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
1150 void *v)
1151 {
1152 struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb);
1153 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
1154 int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS);
1155 struct perf_event *event;
1156 int idx;
1157
1158 if (!enabled)
1159 return NOTIFY_OK;
1160
1161 for (idx = 0; idx < RISCV_MAX_COUNTERS; idx++) {
1162 event = cpuc->events[idx];
1163 if (!event)
1164 continue;
1165
1166 switch (cmd) {
1167 case CPU_PM_ENTER:
1168 /*
1169 * Stop and update the counter
1170 */
1171 riscv_pmu_stop(event, PERF_EF_UPDATE);
1172 break;
1173 case CPU_PM_EXIT:
1174 case CPU_PM_ENTER_FAILED:
1175 /*
1176 * Restore and enable the counter.
1177 */
1178 riscv_pmu_start(event, PERF_EF_RELOAD);
1179 break;
1180 default:
1181 break;
1182 }
1183 }
1184
1185 return NOTIFY_OK;
1186 }
1187
riscv_pm_pmu_register(struct riscv_pmu * pmu)1188 static int riscv_pm_pmu_register(struct riscv_pmu *pmu)
1189 {
1190 pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify;
1191 return cpu_pm_register_notifier(&pmu->riscv_pm_nb);
1192 }
1193
riscv_pm_pmu_unregister(struct riscv_pmu * pmu)1194 static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu)
1195 {
1196 cpu_pm_unregister_notifier(&pmu->riscv_pm_nb);
1197 }
1198 #else
riscv_pm_pmu_register(struct riscv_pmu * pmu)1199 static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; }
riscv_pm_pmu_unregister(struct riscv_pmu * pmu)1200 static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { }
1201 #endif
1202
riscv_pmu_destroy(struct riscv_pmu * pmu)1203 static void riscv_pmu_destroy(struct riscv_pmu *pmu)
1204 {
1205 if (sbi_v2_available) {
1206 if (sbi_pmu_snapshot_available()) {
1207 pmu_sbi_snapshot_disable();
1208 pmu_sbi_snapshot_free(pmu);
1209 }
1210 }
1211 riscv_pm_pmu_unregister(pmu);
1212 cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1213 }
1214
pmu_sbi_event_init(struct perf_event * event)1215 static void pmu_sbi_event_init(struct perf_event *event)
1216 {
1217 /*
1218 * The permissions are set at event_init so that we do not depend
1219 * on the sysctl value that can change.
1220 */
1221 if (sysctl_perf_user_access == SYSCTL_NO_USER_ACCESS)
1222 event->hw.flags |= PERF_EVENT_FLAG_NO_USER_ACCESS;
1223 else if (sysctl_perf_user_access == SYSCTL_USER_ACCESS)
1224 event->hw.flags |= PERF_EVENT_FLAG_USER_ACCESS;
1225 else
1226 event->hw.flags |= PERF_EVENT_FLAG_LEGACY;
1227 }
1228
pmu_sbi_event_mapped(struct perf_event * event,struct mm_struct * mm)1229 static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struct *mm)
1230 {
1231 if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS)
1232 return;
1233
1234 if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) {
1235 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
1236 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) {
1237 return;
1238 }
1239 }
1240
1241 /*
1242 * The user mmapped the event to directly access it: this is where
1243 * we determine based on sysctl_perf_user_access if we grant userspace
1244 * the direct access to this event. That means that within the same
1245 * task, some events may be directly accessible and some other may not,
1246 * if the user changes the value of sysctl_perf_user_accesss in the
1247 * meantime.
1248 */
1249
1250 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1251
1252 /*
1253 * We must enable userspace access *before* advertising in the user page
1254 * that it is possible to do so to avoid any race.
1255 * And we must notify all cpus here because threads that currently run
1256 * on other cpus will try to directly access the counter too without
1257 * calling pmu_sbi_ctr_start.
1258 */
1259 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS)
1260 on_each_cpu_mask(mm_cpumask(mm),
1261 pmu_sbi_set_scounteren, (void *)event, 1);
1262 }
1263
pmu_sbi_event_unmapped(struct perf_event * event,struct mm_struct * mm)1264 static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_struct *mm)
1265 {
1266 if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS)
1267 return;
1268
1269 if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) {
1270 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
1271 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) {
1272 return;
1273 }
1274 }
1275
1276 /*
1277 * Here we can directly remove user access since the user does not have
1278 * access to the user page anymore so we avoid the racy window where the
1279 * user could have read cap_user_rdpmc to true right before we disable
1280 * it.
1281 */
1282 event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
1283
1284 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS)
1285 on_each_cpu_mask(mm_cpumask(mm),
1286 pmu_sbi_reset_scounteren, (void *)event, 1);
1287 }
1288
riscv_pmu_update_counter_access(void * info)1289 static void riscv_pmu_update_counter_access(void *info)
1290 {
1291 if (sysctl_perf_user_access == SYSCTL_LEGACY)
1292 csr_write(CSR_SCOUNTEREN, 0x7);
1293 else
1294 csr_write(CSR_SCOUNTEREN, 0x2);
1295 }
1296
riscv_pmu_proc_user_access_handler(const struct ctl_table * table,int write,void * buffer,size_t * lenp,loff_t * ppos)1297 static int riscv_pmu_proc_user_access_handler(const struct ctl_table *table,
1298 int write, void *buffer,
1299 size_t *lenp, loff_t *ppos)
1300 {
1301 int prev = sysctl_perf_user_access;
1302 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1303
1304 /*
1305 * Test against the previous value since we clear SCOUNTEREN when
1306 * sysctl_perf_user_access is set to SYSCTL_USER_ACCESS, but we should
1307 * not do that if that was already the case.
1308 */
1309 if (ret || !write || prev == sysctl_perf_user_access)
1310 return ret;
1311
1312 on_each_cpu(riscv_pmu_update_counter_access, NULL, 1);
1313
1314 return 0;
1315 }
1316
1317 static struct ctl_table sbi_pmu_sysctl_table[] = {
1318 {
1319 .procname = "perf_user_access",
1320 .data = &sysctl_perf_user_access,
1321 .maxlen = sizeof(unsigned int),
1322 .mode = 0644,
1323 .proc_handler = riscv_pmu_proc_user_access_handler,
1324 .extra1 = SYSCTL_ZERO,
1325 .extra2 = SYSCTL_TWO,
1326 },
1327 };
1328
pmu_sbi_device_probe(struct platform_device * pdev)1329 static int pmu_sbi_device_probe(struct platform_device *pdev)
1330 {
1331 struct riscv_pmu *pmu = NULL;
1332 int ret = -ENODEV;
1333 int num_counters;
1334
1335 pr_info("SBI PMU extension is available\n");
1336 pmu = riscv_pmu_alloc();
1337 if (!pmu)
1338 return -ENOMEM;
1339
1340 num_counters = pmu_sbi_find_num_ctrs();
1341 if (num_counters < 0) {
1342 pr_err("SBI PMU extension doesn't provide any counters\n");
1343 goto out_free;
1344 }
1345
1346 /* It is possible to get from SBI more than max number of counters */
1347 if (num_counters > RISCV_MAX_COUNTERS) {
1348 num_counters = RISCV_MAX_COUNTERS;
1349 pr_info("SBI returned more than maximum number of counters. Limiting the number of counters to %d\n", num_counters);
1350 }
1351
1352 /* cache all the information about counters now */
1353 if (pmu_sbi_get_ctrinfo(num_counters, &cmask))
1354 goto out_free;
1355
1356 ret = pmu_sbi_setup_irqs(pmu, pdev);
1357 if (ret < 0) {
1358 pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n");
1359 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1360 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
1361 }
1362
1363 pmu->pmu.attr_groups = riscv_pmu_attr_groups;
1364 pmu->pmu.parent = &pdev->dev;
1365 pmu->cmask = cmask;
1366 pmu->ctr_start = pmu_sbi_ctr_start;
1367 pmu->ctr_stop = pmu_sbi_ctr_stop;
1368 pmu->event_map = pmu_sbi_event_map;
1369 pmu->ctr_get_idx = pmu_sbi_ctr_get_idx;
1370 pmu->ctr_get_width = pmu_sbi_ctr_get_width;
1371 pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
1372 pmu->ctr_read = pmu_sbi_ctr_read;
1373 pmu->event_init = pmu_sbi_event_init;
1374 pmu->event_mapped = pmu_sbi_event_mapped;
1375 pmu->event_unmapped = pmu_sbi_event_unmapped;
1376 pmu->csr_index = pmu_sbi_csr_index;
1377
1378 ret = riscv_pm_pmu_register(pmu);
1379 if (ret)
1380 goto out_unregister;
1381
1382 ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
1383 if (ret)
1384 goto out_unregister;
1385
1386 /* SBI PMU Snapsphot is only available in SBI v2.0 */
1387 if (sbi_v2_available) {
1388 int cpu;
1389
1390 ret = pmu_sbi_snapshot_alloc(pmu);
1391 if (ret)
1392 goto out_unregister;
1393
1394 cpu = get_cpu();
1395 ret = pmu_sbi_snapshot_setup(pmu, cpu);
1396 put_cpu();
1397
1398 if (ret) {
1399 /* Snapshot is an optional feature. Continue if not available */
1400 pmu_sbi_snapshot_free(pmu);
1401 } else {
1402 pr_info("SBI PMU snapshot detected\n");
1403 /*
1404 * We enable it once here for the boot cpu. If snapshot shmem setup
1405 * fails during cpu hotplug process, it will fail to start the cpu
1406 * as we can not handle hetergenous PMUs with different snapshot
1407 * capability.
1408 */
1409 static_branch_enable(&sbi_pmu_snapshot_available);
1410 }
1411 }
1412
1413 register_sysctl("kernel", sbi_pmu_sysctl_table);
1414
1415 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1416 if (ret)
1417 goto out_unregister;
1418
1419 /* Asynchronously check which standard events are available */
1420 schedule_work(&check_std_events_work);
1421
1422 return 0;
1423
1424 out_unregister:
1425 riscv_pmu_destroy(pmu);
1426
1427 out_free:
1428 kfree(pmu);
1429 return ret;
1430 }
1431
1432 static struct platform_driver pmu_sbi_driver = {
1433 .probe = pmu_sbi_device_probe,
1434 .driver = {
1435 .name = RISCV_PMU_SBI_PDEV_NAME,
1436 },
1437 };
1438
pmu_sbi_devinit(void)1439 static int __init pmu_sbi_devinit(void)
1440 {
1441 int ret;
1442 struct platform_device *pdev;
1443
1444 if (sbi_spec_version < sbi_mk_version(0, 3) ||
1445 !sbi_probe_extension(SBI_EXT_PMU)) {
1446 return 0;
1447 }
1448
1449 if (sbi_spec_version >= sbi_mk_version(2, 0))
1450 sbi_v2_available = true;
1451
1452 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
1453 "perf/riscv/pmu:starting",
1454 pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
1455 if (ret) {
1456 pr_err("CPU hotplug notifier could not be registered: %d\n",
1457 ret);
1458 return ret;
1459 }
1460
1461 ret = platform_driver_register(&pmu_sbi_driver);
1462 if (ret)
1463 return ret;
1464
1465 pdev = platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NULL, 0);
1466 if (IS_ERR(pdev)) {
1467 platform_driver_unregister(&pmu_sbi_driver);
1468 return PTR_ERR(pdev);
1469 }
1470
1471 /* Notify legacy implementation that SBI pmu is available*/
1472 riscv_pmu_legacy_skip_init();
1473
1474 return ret;
1475 }
1476 device_initcall(pmu_sbi_devinit)
1477