1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip PCIe PHY driver
4 *
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
6 * Copyright (C) 2016 ROCKCHIP, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20
21 /*
22 * The higher 16-bit of this register is used for write protection
23 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
24 */
25 #define HIWORD_UPDATE(val, mask, shift) \
26 ((val) << (shift) | (mask) << ((shift) + 16))
27
28 #define PHY_MAX_LANE_NUM 4
29 #define PHY_CFG_DATA_SHIFT 7
30 #define PHY_CFG_ADDR_SHIFT 1
31 #define PHY_CFG_DATA_MASK 0xf
32 #define PHY_CFG_ADDR_MASK 0x3f
33 #define PHY_CFG_WR_ENABLE 1
34 #define PHY_CFG_WR_DISABLE 0
35 #define PHY_CFG_WR_SHIFT 0
36 #define PHY_CFG_WR_MASK 1
37 #define PHY_CFG_PLL_LOCK 0x10
38 #define PHY_CFG_CLK_TEST 0x10
39 #define PHY_CFG_CLK_SCC 0x12
40 #define PHY_CFG_SEPE_RATE BIT(3)
41 #define PHY_CFG_PLL_100M BIT(3)
42 #define PHY_PLL_LOCKED BIT(9)
43 #define PHY_PLL_OUTPUT BIT(10)
44 #define PHY_LANE_A_STATUS 0x30
45 #define PHY_LANE_B_STATUS 0x31
46 #define PHY_LANE_C_STATUS 0x32
47 #define PHY_LANE_D_STATUS 0x33
48 #define PHY_LANE_RX_DET_SHIFT 11
49 #define PHY_LANE_RX_DET_TH 0x1
50 #define PHY_LANE_IDLE_OFF 0x1
51 #define PHY_LANE_IDLE_MASK 0x1
52 #define PHY_LANE_IDLE_A_SHIFT 3
53 #define PHY_LANE_IDLE_B_SHIFT 4
54 #define PHY_LANE_IDLE_C_SHIFT 5
55 #define PHY_LANE_IDLE_D_SHIFT 6
56
57 struct rockchip_pcie_data {
58 unsigned int pcie_conf;
59 unsigned int pcie_status;
60 unsigned int pcie_laneoff;
61 };
62
63 struct rockchip_pcie_phy {
64 const struct rockchip_pcie_data *phy_data;
65 struct regmap *reg_base;
66 struct phy_pcie_instance {
67 struct phy *phy;
68 u32 index;
69 } phys[PHY_MAX_LANE_NUM];
70 struct mutex pcie_mutex;
71 struct reset_control *phy_rst;
72 struct clk *clk_pciephy_ref;
73 int pwr_cnt;
74 int init_cnt;
75 };
76
to_pcie_phy(struct phy_pcie_instance * inst)77 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
78 {
79 return container_of(inst, struct rockchip_pcie_phy,
80 phys[inst->index]);
81 }
82
rockchip_pcie_phy_of_xlate(struct device * dev,const struct of_phandle_args * args)83 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
84 const struct of_phandle_args *args)
85 {
86 struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
87
88 if (args->args_count == 0)
89 return rk_phy->phys[0].phy;
90
91 if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
92 return ERR_PTR(-ENODEV);
93
94 return rk_phy->phys[args->args[0]].phy;
95 }
96
97
phy_wr_cfg(struct rockchip_pcie_phy * rk_phy,u32 addr,u32 data)98 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
99 u32 addr, u32 data)
100 {
101 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
102 HIWORD_UPDATE(data,
103 PHY_CFG_DATA_MASK,
104 PHY_CFG_DATA_SHIFT) |
105 HIWORD_UPDATE(addr,
106 PHY_CFG_ADDR_MASK,
107 PHY_CFG_ADDR_SHIFT));
108 udelay(1);
109 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
110 HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
111 PHY_CFG_WR_MASK,
112 PHY_CFG_WR_SHIFT));
113 udelay(1);
114 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
115 HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
116 PHY_CFG_WR_MASK,
117 PHY_CFG_WR_SHIFT));
118 }
119
rockchip_pcie_phy_power_off(struct phy * phy)120 static int rockchip_pcie_phy_power_off(struct phy *phy)
121 {
122 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
123 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
124 int err = 0;
125
126 mutex_lock(&rk_phy->pcie_mutex);
127
128 regmap_write(rk_phy->reg_base,
129 rk_phy->phy_data->pcie_laneoff,
130 HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
131 PHY_LANE_IDLE_MASK,
132 PHY_LANE_IDLE_A_SHIFT + inst->index));
133
134 if (--rk_phy->pwr_cnt)
135 goto err_out;
136
137 err = reset_control_assert(rk_phy->phy_rst);
138 if (err) {
139 dev_err(&phy->dev, "assert phy_rst err %d\n", err);
140 goto err_restore;
141 }
142
143 err_out:
144 mutex_unlock(&rk_phy->pcie_mutex);
145 return 0;
146
147 err_restore:
148 rk_phy->pwr_cnt++;
149 regmap_write(rk_phy->reg_base,
150 rk_phy->phy_data->pcie_laneoff,
151 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
152 PHY_LANE_IDLE_MASK,
153 PHY_LANE_IDLE_A_SHIFT + inst->index));
154 mutex_unlock(&rk_phy->pcie_mutex);
155 return err;
156 }
157
rockchip_pcie_phy_power_on(struct phy * phy)158 static int rockchip_pcie_phy_power_on(struct phy *phy)
159 {
160 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
161 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
162 int err = 0;
163 u32 status;
164 unsigned long timeout;
165
166 mutex_lock(&rk_phy->pcie_mutex);
167
168 if (rk_phy->pwr_cnt++)
169 goto err_out;
170
171 err = reset_control_deassert(rk_phy->phy_rst);
172 if (err) {
173 dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
174 goto err_pwr_cnt;
175 }
176
177 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
178 HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
179 PHY_CFG_ADDR_MASK,
180 PHY_CFG_ADDR_SHIFT));
181
182 regmap_write(rk_phy->reg_base,
183 rk_phy->phy_data->pcie_laneoff,
184 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
185 PHY_LANE_IDLE_MASK,
186 PHY_LANE_IDLE_A_SHIFT + inst->index));
187
188 /*
189 * No documented timeout value for phy operation below,
190 * so we make it large enough here. And we use loop-break
191 * method which should not be harmful.
192 */
193 timeout = jiffies + msecs_to_jiffies(1000);
194
195 err = -EINVAL;
196 while (time_before(jiffies, timeout)) {
197 regmap_read(rk_phy->reg_base,
198 rk_phy->phy_data->pcie_status,
199 &status);
200 if (status & PHY_PLL_LOCKED) {
201 dev_dbg(&phy->dev, "pll locked!\n");
202 err = 0;
203 break;
204 }
205 msleep(20);
206 }
207
208 if (err) {
209 dev_err(&phy->dev, "pll lock timeout!\n");
210 goto err_pll_lock;
211 }
212
213 phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
214 phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
215
216 err = -ETIMEDOUT;
217 while (time_before(jiffies, timeout)) {
218 regmap_read(rk_phy->reg_base,
219 rk_phy->phy_data->pcie_status,
220 &status);
221 if (!(status & PHY_PLL_OUTPUT)) {
222 dev_dbg(&phy->dev, "pll output enable done!\n");
223 err = 0;
224 break;
225 }
226 msleep(20);
227 }
228
229 if (err) {
230 dev_err(&phy->dev, "pll output enable timeout!\n");
231 goto err_pll_lock;
232 }
233
234 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
235 HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
236 PHY_CFG_ADDR_MASK,
237 PHY_CFG_ADDR_SHIFT));
238 err = -EINVAL;
239 while (time_before(jiffies, timeout)) {
240 regmap_read(rk_phy->reg_base,
241 rk_phy->phy_data->pcie_status,
242 &status);
243 if (status & PHY_PLL_LOCKED) {
244 dev_dbg(&phy->dev, "pll relocked!\n");
245 err = 0;
246 break;
247 }
248 msleep(20);
249 }
250
251 if (err) {
252 dev_err(&phy->dev, "pll relock timeout!\n");
253 goto err_pll_lock;
254 }
255
256 err_out:
257 mutex_unlock(&rk_phy->pcie_mutex);
258 return 0;
259
260 err_pll_lock:
261 reset_control_assert(rk_phy->phy_rst);
262 err_pwr_cnt:
263 rk_phy->pwr_cnt--;
264 mutex_unlock(&rk_phy->pcie_mutex);
265 return err;
266 }
267
rockchip_pcie_phy_init(struct phy * phy)268 static int rockchip_pcie_phy_init(struct phy *phy)
269 {
270 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
271 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
272 int err = 0;
273
274 mutex_lock(&rk_phy->pcie_mutex);
275
276 if (rk_phy->init_cnt++)
277 goto err_out;
278
279 err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
280 if (err) {
281 dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
282 goto err_refclk;
283 }
284
285 err = reset_control_assert(rk_phy->phy_rst);
286 if (err) {
287 dev_err(&phy->dev, "assert phy_rst err %d\n", err);
288 goto err_reset;
289 }
290
291 err_out:
292 mutex_unlock(&rk_phy->pcie_mutex);
293 return 0;
294
295 err_reset:
296
297 clk_disable_unprepare(rk_phy->clk_pciephy_ref);
298 err_refclk:
299 rk_phy->init_cnt--;
300 mutex_unlock(&rk_phy->pcie_mutex);
301 return err;
302 }
303
rockchip_pcie_phy_exit(struct phy * phy)304 static int rockchip_pcie_phy_exit(struct phy *phy)
305 {
306 struct phy_pcie_instance *inst = phy_get_drvdata(phy);
307 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
308
309 mutex_lock(&rk_phy->pcie_mutex);
310
311 if (--rk_phy->init_cnt)
312 goto err_init_cnt;
313
314 clk_disable_unprepare(rk_phy->clk_pciephy_ref);
315
316 err_init_cnt:
317 mutex_unlock(&rk_phy->pcie_mutex);
318 return 0;
319 }
320
321 static const struct phy_ops ops = {
322 .init = rockchip_pcie_phy_init,
323 .exit = rockchip_pcie_phy_exit,
324 .power_on = rockchip_pcie_phy_power_on,
325 .power_off = rockchip_pcie_phy_power_off,
326 .owner = THIS_MODULE,
327 };
328
329 static const struct rockchip_pcie_data rk3399_pcie_data = {
330 .pcie_conf = 0xe220,
331 .pcie_status = 0xe2a4,
332 .pcie_laneoff = 0xe214,
333 };
334
335 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
336 {
337 .compatible = "rockchip,rk3399-pcie-phy",
338 .data = &rk3399_pcie_data,
339 },
340 {}
341 };
342
343 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
344
rockchip_pcie_phy_probe(struct platform_device * pdev)345 static int rockchip_pcie_phy_probe(struct platform_device *pdev)
346 {
347 struct device *dev = &pdev->dev;
348 struct rockchip_pcie_phy *rk_phy;
349 struct phy_provider *phy_provider;
350 struct regmap *grf;
351 int i;
352 u32 phy_num;
353
354 grf = syscon_node_to_regmap(dev->parent->of_node);
355 if (IS_ERR(grf)) {
356 dev_err(dev, "Cannot find GRF syscon\n");
357 return PTR_ERR(grf);
358 }
359
360 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
361 if (!rk_phy)
362 return -ENOMEM;
363
364 rk_phy->phy_data = device_get_match_data(&pdev->dev);
365 if (!rk_phy->phy_data)
366 return -EINVAL;
367
368 rk_phy->reg_base = grf;
369
370 mutex_init(&rk_phy->pcie_mutex);
371
372 rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
373 if (IS_ERR(rk_phy->phy_rst)) {
374 if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
375 dev_err(dev,
376 "missing phy property for reset controller\n");
377 return PTR_ERR(rk_phy->phy_rst);
378 }
379
380 rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
381 if (IS_ERR(rk_phy->clk_pciephy_ref)) {
382 dev_err(dev, "refclk not found.\n");
383 return PTR_ERR(rk_phy->clk_pciephy_ref);
384 }
385
386 /* parse #phy-cells to see if it's legacy PHY model */
387 if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
388 return -ENOENT;
389
390 phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
391 dev_dbg(dev, "phy number is %d\n", phy_num);
392
393 for (i = 0; i < phy_num; i++) {
394 rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
395 if (IS_ERR(rk_phy->phys[i].phy)) {
396 dev_err(dev, "failed to create PHY%d\n", i);
397 return PTR_ERR(rk_phy->phys[i].phy);
398 }
399 rk_phy->phys[i].index = i;
400 phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
401 }
402
403 platform_set_drvdata(pdev, rk_phy);
404 phy_provider = devm_of_phy_provider_register(dev,
405 rockchip_pcie_phy_of_xlate);
406
407 return PTR_ERR_OR_ZERO(phy_provider);
408 }
409
410 static struct platform_driver rockchip_pcie_driver = {
411 .probe = rockchip_pcie_phy_probe,
412 .driver = {
413 .name = "rockchip-pcie-phy",
414 .of_match_table = rockchip_pcie_phy_dt_ids,
415 },
416 };
417
418 module_platform_driver(rockchip_pcie_driver);
419
420 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
421 MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
422 MODULE_LICENSE("GPL v2");
423