1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 *
6 * Author: Algea Cao <algea.cao@rock-chips.com>
7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
8 */
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rational.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define GRF_HDPTX_CON0 0x00
25 #define HDPTX_I_PLL_EN BIT(7)
26 #define HDPTX_I_BIAS_EN BIT(6)
27 #define HDPTX_I_BGR_EN BIT(5)
28 #define GRF_HDPTX_STATUS 0x80
29 #define HDPTX_O_PLL_LOCK_DONE BIT(3)
30 #define HDPTX_O_PHY_CLK_RDY BIT(2)
31 #define HDPTX_O_PHY_RDY BIT(1)
32 #define HDPTX_O_SB_RDY BIT(0)
33
34 #define HDTPX_REG(_n, _min, _max) \
35 ( \
36 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
37 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
38 ((0x##_n) * 4) \
39 )
40
41 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
42 #define SB_REG(n) HDTPX_REG(n, 0100, 0129)
43 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
44 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
45
46 /* CMN_REG(0008) */
47 #define LCPLL_EN_MASK BIT(6)
48 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
49 /* CMN_REG(001e) */
50 #define LCPLL_PI_EN_MASK BIT(5)
51 #define LCPLL_100M_CLK_EN_MASK BIT(0)
52 /* CMN_REG(0025) */
53 #define LCPLL_PMS_IQDIV_RSTN BIT(4)
54 /* CMN_REG(0028) */
55 #define LCPLL_SDC_FRAC_EN BIT(2)
56 #define LCPLL_SDC_FRAC_RSTN BIT(0)
57 /* CMN_REG(002d) */
58 #define LCPLL_SDC_N_MASK GENMASK(3, 1)
59 /* CMN_REG(002e) */
60 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
61 /* CMN_REG(002f) */
62 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
63 #define LCPLL_SDC_NDIV_RSTN BIT(0)
64 /* CMN_REG(003d) */
65 #define ROPLL_LCVCO_EN BIT(4)
66 /* CMN_REG(004e) */
67 #define ROPLL_PI_EN BIT(5)
68 /* CMN_REG(005c) */
69 #define ROPLL_PMS_IQDIV_RSTN BIT(5)
70 /* CMN_REG(005e) */
71 #define ROPLL_SDM_EN_MASK BIT(6)
72 #define ROPLL_SDM_FRAC_EN_RBR BIT(3)
73 #define ROPLL_SDM_FRAC_EN_HBR BIT(2)
74 #define ROPLL_SDM_FRAC_EN_HBR2 BIT(1)
75 #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
76 /* CMN_REG(0064) */
77 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
78 /* CMN_REG(0069) */
79 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
80 /* CMN_REG(0074) */
81 #define ROPLL_SDC_NDIV_RSTN BIT(2)
82 #define ROPLL_SSC_EN BIT(0)
83 /* CMN_REG(0081) */
84 #define OVRD_PLL_CD_CLK_EN BIT(8)
85 #define PLL_CD_HSCLK_EAST_EN BIT(0)
86 /* CMN_REG(0086) */
87 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
88 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
89 #define PLL_PCG_CLK_EN BIT(0)
90 /* CMN_REG(0087) */
91 #define PLL_FRL_MODE_EN BIT(3)
92 #define PLL_TX_HS_CLK_EN BIT(2)
93 /* CMN_REG(0089) */
94 #define LCPLL_ALONE_MODE BIT(1)
95 /* CMN_REG(0097) */
96 #define DIG_CLK_SEL BIT(1)
97 #define LCPLL_REF BIT(1)
98 #define ROPLL_REF 0
99 /* CMN_REG(0099) */
100 #define CMN_ROPLL_ALONE_MODE BIT(2)
101 #define ROPLL_ALONE_MODE BIT(2)
102 /* CMN_REG(009a) */
103 #define HS_SPEED_SEL BIT(0)
104 #define DIV_10_CLOCK BIT(0)
105 /* CMN_REG(009b) */
106 #define IS_SPEED_SEL BIT(4)
107 #define LINK_SYMBOL_CLOCK BIT(4)
108 #define LINK_SYMBOL_CLOCK1_2 0
109
110 /* SB_REG(0102) */
111 #define OVRD_SB_RXTERM_EN_MASK BIT(5)
112 #define SB_RXTERM_EN_MASK BIT(4)
113 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
114 /* SB_REG(0103) */
115 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
116 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
117 #define SB_RX_RESCAL_DONE_MASK BIT(0)
118 /* SB_REG(0104) */
119 #define OVRD_SB_EN_MASK BIT(5)
120 #define SB_EN_MASK BIT(4)
121 /* SB_REG(0105) */
122 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
123 #define SB_EARC_CMDC_EN_MASK BIT(5)
124 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
125 /* SB_REG(0106) */
126 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
127 /* SB_REG(0109) */
128 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
129 /* SB_REG(010f) */
130 #define OVRD_SB_VREG_EN_MASK BIT(7)
131 #define SB_VREG_EN_MASK BIT(6)
132 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
133 #define SB_VREG_LPF_BYPASS_MASK BIT(4)
134 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
135 /* SB_REG(0110) */
136 #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
137 /* SB_REG(0113) */
138 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
139 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
140 /* SB_REG(0114) */
141 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
142 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
143 /* SB_REG(0115) */
144 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
145 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
146 /* SB_REG(0116) */
147 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
148 /* SB_REG(0117) */
149 #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
150 /* SB_REG(011b) */
151 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
152 #define SB_AFC_TOL_MASK GENMASK(3, 0)
153 /* SB_REG(011f) */
154 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
155 #define SB_RCAL_RSTN_MASK BIT(1)
156 /* SB_REG(0120) */
157 #define SB_EARC_EN_MASK BIT(1)
158 #define SB_EARC_AFC_EN_MASK BIT(2)
159 /* SB_REG(0123) */
160 #define OVRD_SB_READY_MASK BIT(5)
161 #define SB_READY_MASK BIT(4)
162
163 /* LNTOP_REG(0200) */
164 #define PROTOCOL_SEL BIT(2)
165 #define HDMI_MODE BIT(2)
166 #define HDMI_TMDS_FRL_SEL BIT(1)
167 /* LNTOP_REG(0206) */
168 #define DATA_BUS_SEL BIT(0)
169 #define DATA_BUS_36_40 BIT(0)
170 /* LNTOP_REG(0207) */
171 #define LANE_EN 0xf
172 #define ALL_LANE_EN 0xf
173
174 /* LANE_REG(0312) */
175 #define LN0_TX_SER_RATE_SEL_RBR BIT(5)
176 #define LN0_TX_SER_RATE_SEL_HBR BIT(4)
177 #define LN0_TX_SER_RATE_SEL_HBR2 BIT(3)
178 #define LN0_TX_SER_RATE_SEL_HBR3 BIT(2)
179 /* LANE_REG(0412) */
180 #define LN1_TX_SER_RATE_SEL_RBR BIT(5)
181 #define LN1_TX_SER_RATE_SEL_HBR BIT(4)
182 #define LN1_TX_SER_RATE_SEL_HBR2 BIT(3)
183 #define LN1_TX_SER_RATE_SEL_HBR3 BIT(2)
184 /* LANE_REG(0512) */
185 #define LN2_TX_SER_RATE_SEL_RBR BIT(5)
186 #define LN2_TX_SER_RATE_SEL_HBR BIT(4)
187 #define LN2_TX_SER_RATE_SEL_HBR2 BIT(3)
188 #define LN2_TX_SER_RATE_SEL_HBR3 BIT(2)
189 /* LANE_REG(0612) */
190 #define LN3_TX_SER_RATE_SEL_RBR BIT(5)
191 #define LN3_TX_SER_RATE_SEL_HBR BIT(4)
192 #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
193 #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
194
195 #define HDMI14_MAX_RATE 340000000
196 #define HDMI20_MAX_RATE 600000000
197
198 struct lcpll_config {
199 u32 bit_rate;
200 u8 lcvco_mode_en;
201 u8 pi_en;
202 u8 clk_en_100m;
203 u8 pms_mdiv;
204 u8 pms_mdiv_afc;
205 u8 pms_pdiv;
206 u8 pms_refdiv;
207 u8 pms_sdiv;
208 u8 pi_cdiv_rstn;
209 u8 pi_cdiv_sel;
210 u8 sdm_en;
211 u8 sdm_rstn;
212 u8 sdc_frac_en;
213 u8 sdc_rstn;
214 u8 sdm_deno;
215 u8 sdm_num_sign;
216 u8 sdm_num;
217 u8 sdc_n;
218 u8 sdc_n2;
219 u8 sdc_num;
220 u8 sdc_deno;
221 u8 sdc_ndiv_rstn;
222 u8 ssc_en;
223 u8 ssc_fm_dev;
224 u8 ssc_fm_freq;
225 u8 ssc_clk_div_sel;
226 u8 cd_tx_ser_rate_sel;
227 };
228
229 struct ropll_config {
230 u32 bit_rate;
231 u8 pms_mdiv;
232 u8 pms_mdiv_afc;
233 u8 pms_pdiv;
234 u8 pms_refdiv;
235 u8 pms_sdiv;
236 u8 pms_iqdiv_rstn;
237 u8 ref_clk_sel;
238 u8 sdm_en;
239 u8 sdm_rstn;
240 u8 sdc_frac_en;
241 u8 sdc_rstn;
242 u8 sdm_clk_div;
243 u8 sdm_deno;
244 u8 sdm_num_sign;
245 u8 sdm_num;
246 u8 sdc_n;
247 u8 sdc_num;
248 u8 sdc_deno;
249 u8 sdc_ndiv_rstn;
250 u8 ssc_en;
251 u8 ssc_fm_dev;
252 u8 ssc_fm_freq;
253 u8 ssc_clk_div_sel;
254 u8 ana_cpp_ctrl;
255 u8 ana_lpf_c_sel;
256 u8 cd_tx_ser_rate_sel;
257 };
258
259 enum rk_hdptx_reset {
260 RST_PHY = 0,
261 RST_APB,
262 RST_INIT,
263 RST_CMN,
264 RST_LANE,
265 RST_ROPLL,
266 RST_LCPLL,
267 RST_MAX
268 };
269
270 #define MAX_HDPTX_PHY_NUM 2
271
272 struct rk_hdptx_phy_cfg {
273 unsigned int num_phys;
274 unsigned int phy_ids[MAX_HDPTX_PHY_NUM];
275 };
276
277 struct rk_hdptx_phy {
278 struct device *dev;
279 struct regmap *regmap;
280 struct regmap *grf;
281
282 /* PHY const config */
283 const struct rk_hdptx_phy_cfg *cfgs;
284 int phy_id;
285
286 struct phy *phy;
287 struct phy_config *phy_cfg;
288 struct clk_bulk_data *clks;
289 int nr_clks;
290 struct reset_control_bulk_data rsts[RST_MAX];
291
292 /* clk provider */
293 struct clk_hw hw;
294 unsigned long rate;
295
296 atomic_t usage_count;
297 };
298
299 static const struct ropll_config ropll_tmds_cfg[] = {
300 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
301 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
302 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
303 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
304 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
305 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
306 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
307 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
308 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
309 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
310 { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
311 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
312 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
313 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
314 { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
315 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
316 { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
317 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
318 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
319 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
320 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
321 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
322 { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
323 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
324 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
325 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
326 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
327 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
328 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
329 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
330 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
331 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
332 { 502500, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5,
333 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
334 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
335 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
336 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
337 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
338 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
339 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
340 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
341 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
342 };
343
344 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
345 REG_SEQ0(CMN_REG(0009), 0x0c),
346 REG_SEQ0(CMN_REG(000a), 0x83),
347 REG_SEQ0(CMN_REG(000b), 0x06),
348 REG_SEQ0(CMN_REG(000c), 0x20),
349 REG_SEQ0(CMN_REG(000d), 0xb8),
350 REG_SEQ0(CMN_REG(000e), 0x0f),
351 REG_SEQ0(CMN_REG(000f), 0x0f),
352 REG_SEQ0(CMN_REG(0010), 0x04),
353 REG_SEQ0(CMN_REG(0011), 0x00),
354 REG_SEQ0(CMN_REG(0012), 0x26),
355 REG_SEQ0(CMN_REG(0013), 0x22),
356 REG_SEQ0(CMN_REG(0014), 0x24),
357 REG_SEQ0(CMN_REG(0015), 0x77),
358 REG_SEQ0(CMN_REG(0016), 0x08),
359 REG_SEQ0(CMN_REG(0017), 0x00),
360 REG_SEQ0(CMN_REG(0018), 0x04),
361 REG_SEQ0(CMN_REG(0019), 0x48),
362 REG_SEQ0(CMN_REG(001a), 0x01),
363 REG_SEQ0(CMN_REG(001b), 0x00),
364 REG_SEQ0(CMN_REG(001c), 0x01),
365 REG_SEQ0(CMN_REG(001d), 0x64),
366 REG_SEQ0(CMN_REG(001f), 0x00),
367 REG_SEQ0(CMN_REG(0026), 0x53),
368 REG_SEQ0(CMN_REG(0029), 0x01),
369 REG_SEQ0(CMN_REG(0030), 0x00),
370 REG_SEQ0(CMN_REG(0031), 0x20),
371 REG_SEQ0(CMN_REG(0032), 0x30),
372 REG_SEQ0(CMN_REG(0033), 0x0b),
373 REG_SEQ0(CMN_REG(0034), 0x23),
374 REG_SEQ0(CMN_REG(0035), 0x00),
375 REG_SEQ0(CMN_REG(0038), 0x00),
376 REG_SEQ0(CMN_REG(0039), 0x00),
377 REG_SEQ0(CMN_REG(003a), 0x00),
378 REG_SEQ0(CMN_REG(003b), 0x00),
379 REG_SEQ0(CMN_REG(003c), 0x80),
380 REG_SEQ0(CMN_REG(003e), 0x0c),
381 REG_SEQ0(CMN_REG(003f), 0x83),
382 REG_SEQ0(CMN_REG(0040), 0x06),
383 REG_SEQ0(CMN_REG(0041), 0x20),
384 REG_SEQ0(CMN_REG(0042), 0xb8),
385 REG_SEQ0(CMN_REG(0043), 0x00),
386 REG_SEQ0(CMN_REG(0044), 0x46),
387 REG_SEQ0(CMN_REG(0045), 0x24),
388 REG_SEQ0(CMN_REG(0046), 0xff),
389 REG_SEQ0(CMN_REG(0047), 0x00),
390 REG_SEQ0(CMN_REG(0048), 0x44),
391 REG_SEQ0(CMN_REG(0049), 0xfa),
392 REG_SEQ0(CMN_REG(004a), 0x08),
393 REG_SEQ0(CMN_REG(004b), 0x00),
394 REG_SEQ0(CMN_REG(004c), 0x01),
395 REG_SEQ0(CMN_REG(004d), 0x64),
396 REG_SEQ0(CMN_REG(004e), 0x14),
397 REG_SEQ0(CMN_REG(004f), 0x00),
398 REG_SEQ0(CMN_REG(0050), 0x00),
399 REG_SEQ0(CMN_REG(005d), 0x0c),
400 REG_SEQ0(CMN_REG(005f), 0x01),
401 REG_SEQ0(CMN_REG(006b), 0x04),
402 REG_SEQ0(CMN_REG(0073), 0x30),
403 REG_SEQ0(CMN_REG(0074), 0x00),
404 REG_SEQ0(CMN_REG(0075), 0x20),
405 REG_SEQ0(CMN_REG(0076), 0x30),
406 REG_SEQ0(CMN_REG(0077), 0x08),
407 REG_SEQ0(CMN_REG(0078), 0x0c),
408 REG_SEQ0(CMN_REG(0079), 0x00),
409 REG_SEQ0(CMN_REG(007b), 0x00),
410 REG_SEQ0(CMN_REG(007c), 0x00),
411 REG_SEQ0(CMN_REG(007d), 0x00),
412 REG_SEQ0(CMN_REG(007e), 0x00),
413 REG_SEQ0(CMN_REG(007f), 0x00),
414 REG_SEQ0(CMN_REG(0080), 0x00),
415 REG_SEQ0(CMN_REG(0081), 0x09),
416 REG_SEQ0(CMN_REG(0082), 0x04),
417 REG_SEQ0(CMN_REG(0083), 0x24),
418 REG_SEQ0(CMN_REG(0084), 0x20),
419 REG_SEQ0(CMN_REG(0085), 0x03),
420 REG_SEQ0(CMN_REG(0086), 0x01),
421 REG_SEQ0(CMN_REG(0087), 0x0c),
422 REG_SEQ0(CMN_REG(008a), 0x55),
423 REG_SEQ0(CMN_REG(008b), 0x25),
424 REG_SEQ0(CMN_REG(008c), 0x2c),
425 REG_SEQ0(CMN_REG(008d), 0x22),
426 REG_SEQ0(CMN_REG(008e), 0x14),
427 REG_SEQ0(CMN_REG(008f), 0x20),
428 REG_SEQ0(CMN_REG(0090), 0x00),
429 REG_SEQ0(CMN_REG(0091), 0x00),
430 REG_SEQ0(CMN_REG(0092), 0x00),
431 REG_SEQ0(CMN_REG(0093), 0x00),
432 REG_SEQ0(CMN_REG(009a), 0x11),
433 REG_SEQ0(CMN_REG(009b), 0x10),
434 };
435
436 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
437 REG_SEQ0(CMN_REG(0008), 0x00),
438 REG_SEQ0(CMN_REG(0011), 0x01),
439 REG_SEQ0(CMN_REG(0017), 0x20),
440 REG_SEQ0(CMN_REG(001e), 0x14),
441 REG_SEQ0(CMN_REG(0020), 0x00),
442 REG_SEQ0(CMN_REG(0021), 0x00),
443 REG_SEQ0(CMN_REG(0022), 0x11),
444 REG_SEQ0(CMN_REG(0023), 0x00),
445 REG_SEQ0(CMN_REG(0024), 0x00),
446 REG_SEQ0(CMN_REG(0025), 0x53),
447 REG_SEQ0(CMN_REG(0026), 0x00),
448 REG_SEQ0(CMN_REG(0027), 0x00),
449 REG_SEQ0(CMN_REG(0028), 0x01),
450 REG_SEQ0(CMN_REG(002a), 0x00),
451 REG_SEQ0(CMN_REG(002b), 0x00),
452 REG_SEQ0(CMN_REG(002c), 0x00),
453 REG_SEQ0(CMN_REG(002d), 0x00),
454 REG_SEQ0(CMN_REG(002e), 0x04),
455 REG_SEQ0(CMN_REG(002f), 0x00),
456 REG_SEQ0(CMN_REG(0030), 0x20),
457 REG_SEQ0(CMN_REG(0031), 0x30),
458 REG_SEQ0(CMN_REG(0032), 0x0b),
459 REG_SEQ0(CMN_REG(0033), 0x23),
460 REG_SEQ0(CMN_REG(0034), 0x00),
461 REG_SEQ0(CMN_REG(003d), 0x40),
462 REG_SEQ0(CMN_REG(0042), 0x78),
463 REG_SEQ0(CMN_REG(004e), 0x34),
464 REG_SEQ0(CMN_REG(005c), 0x25),
465 REG_SEQ0(CMN_REG(005e), 0x4f),
466 REG_SEQ0(CMN_REG(0074), 0x04),
467 REG_SEQ0(CMN_REG(0081), 0x01),
468 REG_SEQ0(CMN_REG(0087), 0x04),
469 REG_SEQ0(CMN_REG(0089), 0x00),
470 REG_SEQ0(CMN_REG(0095), 0x00),
471 REG_SEQ0(CMN_REG(0097), 0x02),
472 REG_SEQ0(CMN_REG(0099), 0x04),
473 REG_SEQ0(CMN_REG(009b), 0x00),
474 };
475
476 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
477 REG_SEQ0(SB_REG(0114), 0x00),
478 REG_SEQ0(SB_REG(0115), 0x00),
479 REG_SEQ0(SB_REG(0116), 0x00),
480 REG_SEQ0(SB_REG(0117), 0x00),
481 };
482
483 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
484 REG_SEQ0(LNTOP_REG(0201), 0x00),
485 REG_SEQ0(LNTOP_REG(0202), 0x00),
486 REG_SEQ0(LNTOP_REG(0203), 0x0f),
487 REG_SEQ0(LNTOP_REG(0204), 0xff),
488 REG_SEQ0(LNTOP_REG(0205), 0xff),
489 };
490
491 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
492 REG_SEQ0(LNTOP_REG(0201), 0x07),
493 REG_SEQ0(LNTOP_REG(0202), 0xc1),
494 REG_SEQ0(LNTOP_REG(0203), 0xf0),
495 REG_SEQ0(LNTOP_REG(0204), 0x7c),
496 REG_SEQ0(LNTOP_REG(0205), 0x1f),
497 };
498
499 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
500 REG_SEQ0(LANE_REG(0303), 0x0c),
501 REG_SEQ0(LANE_REG(0307), 0x20),
502 REG_SEQ0(LANE_REG(030a), 0x17),
503 REG_SEQ0(LANE_REG(030b), 0x77),
504 REG_SEQ0(LANE_REG(030c), 0x77),
505 REG_SEQ0(LANE_REG(030d), 0x77),
506 REG_SEQ0(LANE_REG(030e), 0x38),
507 REG_SEQ0(LANE_REG(0310), 0x03),
508 REG_SEQ0(LANE_REG(0311), 0x0f),
509 REG_SEQ0(LANE_REG(0316), 0x02),
510 REG_SEQ0(LANE_REG(031b), 0x01),
511 REG_SEQ0(LANE_REG(031f), 0x15),
512 REG_SEQ0(LANE_REG(0320), 0xa0),
513 REG_SEQ0(LANE_REG(0403), 0x0c),
514 REG_SEQ0(LANE_REG(0407), 0x20),
515 REG_SEQ0(LANE_REG(040a), 0x17),
516 REG_SEQ0(LANE_REG(040b), 0x77),
517 REG_SEQ0(LANE_REG(040c), 0x77),
518 REG_SEQ0(LANE_REG(040d), 0x77),
519 REG_SEQ0(LANE_REG(040e), 0x38),
520 REG_SEQ0(LANE_REG(0410), 0x03),
521 REG_SEQ0(LANE_REG(0411), 0x0f),
522 REG_SEQ0(LANE_REG(0416), 0x02),
523 REG_SEQ0(LANE_REG(041b), 0x01),
524 REG_SEQ0(LANE_REG(041f), 0x15),
525 REG_SEQ0(LANE_REG(0420), 0xa0),
526 REG_SEQ0(LANE_REG(0503), 0x0c),
527 REG_SEQ0(LANE_REG(0507), 0x20),
528 REG_SEQ0(LANE_REG(050a), 0x17),
529 REG_SEQ0(LANE_REG(050b), 0x77),
530 REG_SEQ0(LANE_REG(050c), 0x77),
531 REG_SEQ0(LANE_REG(050d), 0x77),
532 REG_SEQ0(LANE_REG(050e), 0x38),
533 REG_SEQ0(LANE_REG(0510), 0x03),
534 REG_SEQ0(LANE_REG(0511), 0x0f),
535 REG_SEQ0(LANE_REG(0516), 0x02),
536 REG_SEQ0(LANE_REG(051b), 0x01),
537 REG_SEQ0(LANE_REG(051f), 0x15),
538 REG_SEQ0(LANE_REG(0520), 0xa0),
539 REG_SEQ0(LANE_REG(0603), 0x0c),
540 REG_SEQ0(LANE_REG(0607), 0x20),
541 REG_SEQ0(LANE_REG(060a), 0x17),
542 REG_SEQ0(LANE_REG(060b), 0x77),
543 REG_SEQ0(LANE_REG(060c), 0x77),
544 REG_SEQ0(LANE_REG(060d), 0x77),
545 REG_SEQ0(LANE_REG(060e), 0x38),
546 REG_SEQ0(LANE_REG(0610), 0x03),
547 REG_SEQ0(LANE_REG(0611), 0x0f),
548 REG_SEQ0(LANE_REG(0616), 0x02),
549 REG_SEQ0(LANE_REG(061b), 0x01),
550 REG_SEQ0(LANE_REG(061f), 0x15),
551 REG_SEQ0(LANE_REG(0620), 0xa0),
552 };
553
554 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
555 REG_SEQ0(LANE_REG(0312), 0x00),
556 REG_SEQ0(LANE_REG(031e), 0x00),
557 REG_SEQ0(LANE_REG(0412), 0x00),
558 REG_SEQ0(LANE_REG(041e), 0x00),
559 REG_SEQ0(LANE_REG(0512), 0x00),
560 REG_SEQ0(LANE_REG(051e), 0x00),
561 REG_SEQ0(LANE_REG(0612), 0x00),
562 REG_SEQ0(LANE_REG(061e), 0x08),
563 REG_SEQ0(LANE_REG(0303), 0x2f),
564 REG_SEQ0(LANE_REG(0403), 0x2f),
565 REG_SEQ0(LANE_REG(0503), 0x2f),
566 REG_SEQ0(LANE_REG(0603), 0x2f),
567 REG_SEQ0(LANE_REG(0305), 0x03),
568 REG_SEQ0(LANE_REG(0405), 0x03),
569 REG_SEQ0(LANE_REG(0505), 0x03),
570 REG_SEQ0(LANE_REG(0605), 0x03),
571 REG_SEQ0(LANE_REG(0306), 0x1c),
572 REG_SEQ0(LANE_REG(0406), 0x1c),
573 REG_SEQ0(LANE_REG(0506), 0x1c),
574 REG_SEQ0(LANE_REG(0606), 0x1c),
575 };
576
rk_hdptx_phy_is_rw_reg(struct device * dev,unsigned int reg)577 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
578 {
579 switch (reg) {
580 case 0x0000 ... 0x029c:
581 case 0x0400 ... 0x04a4:
582 case 0x0800 ... 0x08a4:
583 case 0x0c00 ... 0x0cb4:
584 case 0x1000 ... 0x10b4:
585 case 0x1400 ... 0x14b4:
586 case 0x1800 ... 0x18b4:
587 return true;
588 }
589
590 return false;
591 }
592
593 static const struct regmap_config rk_hdptx_phy_regmap_config = {
594 .reg_bits = 32,
595 .reg_stride = 4,
596 .val_bits = 32,
597 .writeable_reg = rk_hdptx_phy_is_rw_reg,
598 .readable_reg = rk_hdptx_phy_is_rw_reg,
599 .fast_io = true,
600 .max_register = 0x18b4,
601 };
602
603 #define rk_hdptx_multi_reg_write(hdptx, seq) \
604 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq))
605
rk_hdptx_pre_power_up(struct rk_hdptx_phy * hdptx)606 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx)
607 {
608 u32 val;
609
610 reset_control_assert(hdptx->rsts[RST_APB].rstc);
611 usleep_range(20, 25);
612 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
613
614 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
615 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
616 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
617
618 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
619 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
620 }
621
rk_hdptx_post_enable_lane(struct rk_hdptx_phy * hdptx)622 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
623 {
624 u32 val;
625 int ret;
626
627 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
628
629 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
630 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
631 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
632
633 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
634 (val & HDPTX_O_PHY_RDY) &&
635 (val & HDPTX_O_PLL_LOCK_DONE),
636 100, 5000);
637 if (ret) {
638 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret);
639 return ret;
640 }
641
642 dev_dbg(hdptx->dev, "PHY lane locked\n");
643
644 return 0;
645 }
646
rk_hdptx_post_enable_pll(struct rk_hdptx_phy * hdptx)647 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
648 {
649 u32 val;
650 int ret;
651
652 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
653 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
654 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
655
656 usleep_range(10, 15);
657 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
658
659 usleep_range(10, 15);
660 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
661 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
662
663 usleep_range(10, 15);
664 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
665
666 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
667 val & HDPTX_O_PHY_CLK_RDY, 20, 400);
668 if (ret) {
669 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret);
670 return ret;
671 }
672
673 dev_dbg(hdptx->dev, "PHY clk ready\n");
674
675 return 0;
676 }
677
rk_hdptx_phy_disable(struct rk_hdptx_phy * hdptx)678 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
679 {
680 u32 val;
681
682 /* reset phy and apb, or phy locked flag may keep 1 */
683 reset_control_assert(hdptx->rsts[RST_PHY].rstc);
684 usleep_range(20, 30);
685 reset_control_deassert(hdptx->rsts[RST_PHY].rstc);
686
687 reset_control_assert(hdptx->rsts[RST_APB].rstc);
688 usleep_range(20, 30);
689 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
690
691 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
692 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
693 regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
694 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80);
695 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80);
696 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80);
697 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80);
698
699 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
700 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
701 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
702
703 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
704 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
705 }
706
rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,struct ropll_config * cfg)707 static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
708 struct ropll_config *cfg)
709 {
710 const unsigned int fout = data_rate / 2, fref = 24000;
711 unsigned long k = 0, lc, k_sub, lc_sub;
712 unsigned int fvco, sdc;
713 u32 mdiv, sdiv, n = 8;
714
715 if (fout > 0xfffffff)
716 return false;
717
718 for (sdiv = 16; sdiv >= 1; sdiv--) {
719 if (sdiv % 2 && sdiv != 1)
720 continue;
721
722 fvco = fout * sdiv;
723
724 if (fvco < 2000000 || fvco > 4000000)
725 continue;
726
727 mdiv = DIV_ROUND_UP(fvco, fref);
728 if (mdiv < 20 || mdiv > 255)
729 continue;
730
731 if (fref * mdiv - fvco) {
732 for (sdc = 264000; sdc <= 750000; sdc += fref)
733 if (sdc * n > fref * mdiv)
734 break;
735
736 if (sdc > 750000)
737 continue;
738
739 rational_best_approximation(fref * mdiv - fvco,
740 sdc / 16,
741 GENMASK(6, 0),
742 GENMASK(7, 0),
743 &k, &lc);
744
745 rational_best_approximation(sdc * n - fref * mdiv,
746 sdc,
747 GENMASK(6, 0),
748 GENMASK(7, 0),
749 &k_sub, &lc_sub);
750 }
751
752 break;
753 }
754
755 if (sdiv < 1)
756 return false;
757
758 if (cfg) {
759 cfg->pms_mdiv = mdiv;
760 cfg->pms_mdiv_afc = mdiv;
761 cfg->pms_pdiv = 1;
762 cfg->pms_refdiv = 1;
763 cfg->pms_sdiv = sdiv - 1;
764
765 cfg->sdm_en = k > 0 ? 1 : 0;
766 if (cfg->sdm_en) {
767 cfg->sdm_deno = lc;
768 cfg->sdm_num_sign = 1;
769 cfg->sdm_num = k;
770 cfg->sdc_n = n - 3;
771 cfg->sdc_num = k_sub;
772 cfg->sdc_deno = lc_sub;
773 }
774 }
775
776 return true;
777 }
778
rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy * hdptx,unsigned int rate)779 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
780 unsigned int rate)
781 {
782 const struct ropll_config *cfg = NULL;
783 struct ropll_config rc = {0};
784 int ret, i;
785
786 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
787 if (rate == ropll_tmds_cfg[i].bit_rate) {
788 cfg = &ropll_tmds_cfg[i];
789 break;
790 }
791
792 if (!cfg) {
793 if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
794 cfg = &rc;
795 } else {
796 dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
797 return -EINVAL;
798 }
799 }
800
801 dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n",
802 cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
803 cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
804
805 rk_hdptx_pre_power_up(hdptx);
806
807 reset_control_assert(hdptx->rsts[RST_ROPLL].rstc);
808 usleep_range(20, 30);
809 reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc);
810
811 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
812 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
813
814 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
815 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
816 regmap_write(hdptx->regmap, CMN_REG(0059),
817 (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
818 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
819
820 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
821 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
822 if (!cfg->sdm_en)
823 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
824
825 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
826 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
827
828 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
829 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
830
831 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
832 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
833
834 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
835 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
836
837 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
838 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
839
840 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
841 PLL_PCG_CLK_EN);
842
843 ret = rk_hdptx_post_enable_pll(hdptx);
844 if (!ret)
845 hdptx->rate = rate * 100;
846
847 return ret;
848 }
849
rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy * hdptx,unsigned int rate)850 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
851 unsigned int rate)
852 {
853 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
854
855 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
856
857 if (rate > HDMI14_MAX_RATE / 100) {
858 /* For 1/40 bitrate clk */
859 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
860 } else {
861 /* For 1/10 bitrate clk */
862 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
863 }
864
865 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
866 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
867
868 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
869 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
870
871 return rk_hdptx_post_enable_lane(hdptx);
872 }
873
rk_hdptx_phy_consumer_get(struct rk_hdptx_phy * hdptx,unsigned int rate)874 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
875 unsigned int rate)
876 {
877 u32 status;
878 int ret;
879
880 if (atomic_inc_return(&hdptx->usage_count) > 1)
881 return 0;
882
883 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
884 if (ret)
885 goto dec_usage;
886
887 if (status & HDPTX_O_PLL_LOCK_DONE)
888 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
889
890 if (rate) {
891 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
892 if (ret)
893 goto dec_usage;
894 }
895
896 return 0;
897
898 dec_usage:
899 atomic_dec(&hdptx->usage_count);
900 return ret;
901 }
902
rk_hdptx_phy_consumer_put(struct rk_hdptx_phy * hdptx,bool force)903 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
904 {
905 u32 status;
906 int ret;
907
908 ret = atomic_dec_return(&hdptx->usage_count);
909 if (ret > 0)
910 return 0;
911
912 if (ret < 0) {
913 dev_warn(hdptx->dev, "Usage count underflow!\n");
914 ret = -EINVAL;
915 } else {
916 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
917 if (!ret) {
918 if (status & HDPTX_O_PLL_LOCK_DONE)
919 rk_hdptx_phy_disable(hdptx);
920 return 0;
921 } else if (force) {
922 return 0;
923 }
924 }
925
926 atomic_inc(&hdptx->usage_count);
927 return ret;
928 }
929
rk_hdptx_phy_power_on(struct phy * phy)930 static int rk_hdptx_phy_power_on(struct phy *phy)
931 {
932 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
933 int bus_width = phy_get_bus_width(hdptx->phy);
934 int ret;
935
936 /*
937 * FIXME: Temporary workaround to pass pixel_clk_rate
938 * from the HDMI bridge driver until phy_configure_opts_hdmi
939 * becomes available in the PHY API.
940 */
941 unsigned int rate = bus_width & 0xfffffff;
942
943 dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
944 __func__, bus_width, rate);
945
946 ret = rk_hdptx_phy_consumer_get(hdptx, rate);
947 if (ret)
948 return ret;
949
950 ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
951 if (ret)
952 rk_hdptx_phy_consumer_put(hdptx, true);
953
954 return ret;
955 }
956
rk_hdptx_phy_power_off(struct phy * phy)957 static int rk_hdptx_phy_power_off(struct phy *phy)
958 {
959 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
960
961 return rk_hdptx_phy_consumer_put(hdptx, false);
962 }
963
964 static const struct phy_ops rk_hdptx_phy_ops = {
965 .power_on = rk_hdptx_phy_power_on,
966 .power_off = rk_hdptx_phy_power_off,
967 .owner = THIS_MODULE,
968 };
969
to_rk_hdptx_phy(struct clk_hw * hw)970 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
971 {
972 return container_of(hw, struct rk_hdptx_phy, hw);
973 }
974
rk_hdptx_phy_clk_prepare(struct clk_hw * hw)975 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
976 {
977 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
978
979 return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
980 }
981
rk_hdptx_phy_clk_unprepare(struct clk_hw * hw)982 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
983 {
984 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
985
986 rk_hdptx_phy_consumer_put(hdptx, true);
987 }
988
rk_hdptx_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)989 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
990 unsigned long parent_rate)
991 {
992 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
993
994 return hdptx->rate;
995 }
996
rk_hdptx_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)997 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
998 unsigned long *parent_rate)
999 {
1000 u32 bit_rate = rate / 100;
1001 int i;
1002
1003 if (rate > HDMI20_MAX_RATE)
1004 return rate;
1005
1006 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
1007 if (bit_rate == ropll_tmds_cfg[i].bit_rate)
1008 break;
1009
1010 if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
1011 !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
1012 return -EINVAL;
1013
1014 return rate;
1015 }
1016
rk_hdptx_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1017 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1018 unsigned long parent_rate)
1019 {
1020 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1021
1022 return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
1023 }
1024
1025 static const struct clk_ops hdptx_phy_clk_ops = {
1026 .prepare = rk_hdptx_phy_clk_prepare,
1027 .unprepare = rk_hdptx_phy_clk_unprepare,
1028 .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
1029 .round_rate = rk_hdptx_phy_clk_round_rate,
1030 .set_rate = rk_hdptx_phy_clk_set_rate,
1031 };
1032
rk_hdptx_phy_clk_register(struct rk_hdptx_phy * hdptx)1033 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
1034 {
1035 struct device *dev = hdptx->dev;
1036 const char *name, *pname;
1037 struct clk *refclk;
1038 int ret;
1039
1040 refclk = devm_clk_get(dev, "ref");
1041 if (IS_ERR(refclk))
1042 return dev_err_probe(dev, PTR_ERR(refclk),
1043 "Failed to get ref clock\n");
1044
1045 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
1046 pname = __clk_get_name(refclk);
1047
1048 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
1049 CLK_GET_RATE_NOCACHE);
1050
1051 ret = devm_clk_hw_register(dev, &hdptx->hw);
1052 if (ret)
1053 return dev_err_probe(dev, ret, "Failed to register clock\n");
1054
1055 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
1056 if (ret)
1057 return dev_err_probe(dev, ret,
1058 "Failed to register clk provider\n");
1059 return 0;
1060 }
1061
rk_hdptx_phy_runtime_suspend(struct device * dev)1062 static int rk_hdptx_phy_runtime_suspend(struct device *dev)
1063 {
1064 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1065
1066 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1067
1068 return 0;
1069 }
1070
rk_hdptx_phy_runtime_resume(struct device * dev)1071 static int rk_hdptx_phy_runtime_resume(struct device *dev)
1072 {
1073 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1074 int ret;
1075
1076 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1077 if (ret)
1078 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret);
1079
1080 return ret;
1081 }
1082
rk_hdptx_phy_probe(struct platform_device * pdev)1083 static int rk_hdptx_phy_probe(struct platform_device *pdev)
1084 {
1085 struct phy_provider *phy_provider;
1086 struct device *dev = &pdev->dev;
1087 struct rk_hdptx_phy *hdptx;
1088 struct resource *res;
1089 void __iomem *regs;
1090 int ret, id;
1091
1092 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1093 if (!hdptx)
1094 return -ENOMEM;
1095
1096 hdptx->dev = dev;
1097
1098 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1099 if (IS_ERR(regs))
1100 return dev_err_probe(dev, PTR_ERR(regs),
1101 "Failed to ioremap resource\n");
1102
1103 hdptx->cfgs = device_get_match_data(dev);
1104 if (!hdptx->cfgs)
1105 return dev_err_probe(dev, -EINVAL, "missing match data\n");
1106
1107 /* find the phy-id from the io address */
1108 hdptx->phy_id = -ENODEV;
1109 for (id = 0; id < hdptx->cfgs->num_phys; id++) {
1110 if (res->start == hdptx->cfgs->phy_ids[id]) {
1111 hdptx->phy_id = id;
1112 break;
1113 }
1114 }
1115
1116 if (hdptx->phy_id < 0)
1117 return dev_err_probe(dev, -ENODEV, "no matching device found\n");
1118
1119 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
1120 if (ret < 0)
1121 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1122 if (ret == 0)
1123 return dev_err_probe(dev, -EINVAL, "Missing clocks\n");
1124
1125 hdptx->nr_clks = ret;
1126
1127 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
1128 &rk_hdptx_phy_regmap_config);
1129 if (IS_ERR(hdptx->regmap))
1130 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
1131 "Failed to init regmap\n");
1132
1133 hdptx->rsts[RST_PHY].id = "phy";
1134 hdptx->rsts[RST_APB].id = "apb";
1135 hdptx->rsts[RST_INIT].id = "init";
1136 hdptx->rsts[RST_CMN].id = "cmn";
1137 hdptx->rsts[RST_LANE].id = "lane";
1138 hdptx->rsts[RST_ROPLL].id = "ropll";
1139 hdptx->rsts[RST_LCPLL].id = "lcpll";
1140
1141 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts);
1142 if (ret)
1143 return dev_err_probe(dev, ret, "Failed to get resets\n");
1144
1145 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1146 "rockchip,grf");
1147 if (IS_ERR(hdptx->grf))
1148 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
1149 "Could not get GRF syscon\n");
1150
1151 platform_set_drvdata(pdev, hdptx);
1152
1153 ret = devm_pm_runtime_enable(dev);
1154 if (ret)
1155 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
1156
1157 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
1158 if (IS_ERR(hdptx->phy))
1159 return dev_err_probe(dev, PTR_ERR(hdptx->phy),
1160 "Failed to create HDMI PHY\n");
1161
1162 phy_set_drvdata(hdptx->phy, hdptx);
1163 phy_set_bus_width(hdptx->phy, 8);
1164
1165 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1166 if (IS_ERR(phy_provider))
1167 return dev_err_probe(dev, PTR_ERR(phy_provider),
1168 "Failed to register PHY provider\n");
1169
1170 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
1171 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1172 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1173
1174 return rk_hdptx_phy_clk_register(hdptx);
1175 }
1176
1177 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
1178 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend,
1179 rk_hdptx_phy_runtime_resume, NULL)
1180 };
1181
1182 static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = {
1183 .num_phys = 2,
1184 .phy_ids = {
1185 0xfed60000,
1186 0xfed70000,
1187 },
1188 };
1189
1190 static const struct of_device_id rk_hdptx_phy_of_match[] = {
1191 {
1192 .compatible = "rockchip,rk3588-hdptx-phy",
1193 .data = &rk3588_hdptx_phy_cfgs
1194 },
1195 {}
1196 };
1197 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match);
1198
1199 static struct platform_driver rk_hdptx_phy_driver = {
1200 .probe = rk_hdptx_phy_probe,
1201 .driver = {
1202 .name = "rockchip-hdptx-phy",
1203 .pm = &rk_hdptx_phy_pm_ops,
1204 .of_match_table = rk_hdptx_phy_of_match,
1205 },
1206 };
1207 module_platform_driver(rk_hdptx_phy_driver);
1208
1209 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
1210 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
1211 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
1212 MODULE_LICENSE("GPL");
1213