1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
4 *
5 * Copyright (C) 2022 9elements GmbH
6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
7 * Naresh Solanki <Naresh.Solanki@9elements.com>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/bitmap.h>
12 #include <linux/cleanup.h>
13 #include <linux/dmi.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/seq_file.h>
25
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31
32 /* Fast access registers */
33 #define CY8C95X0_INPUT 0x00
34 #define CY8C95X0_OUTPUT 0x08
35 #define CY8C95X0_INTSTATUS 0x10
36
37 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x))
38 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x))
39 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x))
40
41 /* Port Select configures the port */
42 #define CY8C95X0_PORTSEL 0x18
43 /* Port settings, write PORTSEL first */
44 #define CY8C95X0_INTMASK 0x19
45 #define CY8C95X0_SELPWM 0x1A
46 #define CY8C95X0_INVERT 0x1B
47 #define CY8C95X0_DIRECTION 0x1C
48 /* Drive mode register change state on writing '1' */
49 #define CY8C95X0_DRV_PU 0x1D
50 #define CY8C95X0_DRV_PD 0x1E
51 #define CY8C95X0_DRV_ODH 0x1F
52 #define CY8C95X0_DRV_ODL 0x20
53 #define CY8C95X0_DRV_PP_FAST 0x21
54 #define CY8C95X0_DRV_PP_SLOW 0x22
55 #define CY8C95X0_DRV_HIZ 0x23
56 #define CY8C95X0_DEVID 0x2E
57 #define CY8C95X0_WATCHDOG 0x2F
58 #define CY8C95X0_COMMAND 0x30
59
60 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
61
62 #define MAX_BANK 8
63 #define BANK_SZ 8
64 #define MAX_LINE (MAX_BANK * BANK_SZ)
65 #define MUXED_STRIDE 16
66 #define CY8C95X0_GPIO_MASK GENMASK(7, 0)
67 #define CY8C95X0_VIRTUAL 0x40
68 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
69 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
70
71 static const struct i2c_device_id cy8c95x0_id[] = {
72 { "cy8c9520", 20, },
73 { "cy8c9540", 40, },
74 { "cy8c9560", 60, },
75 { }
76 };
77 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
78
79 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
80
81 static const struct of_device_id cy8c95x0_dt_ids[] = {
82 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
83 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
84 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
85 { }
86 };
87 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
88
89 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
90
91 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
92 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
93 { }
94 };
95
cy8c95x0_acpi_get_irq(struct device * dev)96 static int cy8c95x0_acpi_get_irq(struct device *dev)
97 {
98 int ret;
99
100 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
101 if (ret)
102 dev_warn(dev, "can't add GPIO ACPI mapping\n");
103
104 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);
105 if (ret < 0)
106 return ret;
107
108 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
109 return ret;
110 }
111
112 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
113 {
114 /*
115 * On Intel Galileo Gen 1 board the IRQ pin is provided
116 * as an absolute number instead of being relative.
117 * Since first controller (gpio-sch.c) and second
118 * (gpio-dwapb.c) are at the fixed bases, we may safely
119 * refer to the number in the global space to get an IRQ
120 * out of it.
121 */
122 .matches = {
123 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
124 },
125 },
126 {}
127 };
128
129 /**
130 * struct cy8c95x0_pinctrl - driver data
131 * @regmap: Device's regmap. Only direct access registers.
132 * @irq_lock: IRQ bus lock
133 * @i2c_lock: Mutex to hold while using the regmap
134 * @irq_mask: I/O bits affected by interrupts
135 * @irq_trig_raise: I/O bits affected by raising voltage level
136 * @irq_trig_fall: I/O bits affected by falling voltage level
137 * @irq_trig_low: I/O bits affected by a low voltage level
138 * @irq_trig_high: I/O bits affected by a high voltage level
139 * @push_pull: I/O bits configured as push pull driver
140 * @shiftmask: Mask used to compensate for Gport2 width
141 * @nport: Number of Gports in this chip
142 * @gpio_chip: gpiolib chip
143 * @driver_data: private driver data
144 * @regulator: Pointer to the regulator for the IC
145 * @dev: struct device
146 * @pctldev: pin controller device
147 * @pinctrl_desc: pin controller description
148 * @name: Chip controller name
149 * @tpin: Total number of pins
150 * @gpio_reset: GPIO line handler that can reset the IC
151 */
152 struct cy8c95x0_pinctrl {
153 struct regmap *regmap;
154 struct mutex irq_lock;
155 struct mutex i2c_lock;
156 DECLARE_BITMAP(irq_mask, MAX_LINE);
157 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
158 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
159 DECLARE_BITMAP(irq_trig_low, MAX_LINE);
160 DECLARE_BITMAP(irq_trig_high, MAX_LINE);
161 DECLARE_BITMAP(push_pull, MAX_LINE);
162 DECLARE_BITMAP(shiftmask, MAX_LINE);
163 int nport;
164 struct gpio_chip gpio_chip;
165 unsigned long driver_data;
166 struct regulator *regulator;
167 struct device *dev;
168 struct pinctrl_dev *pctldev;
169 struct pinctrl_desc pinctrl_desc;
170 char name[32];
171 unsigned int tpin;
172 struct gpio_desc *gpio_reset;
173 };
174
175 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
176 PINCTRL_PIN(0, "gp00"),
177 PINCTRL_PIN(1, "gp01"),
178 PINCTRL_PIN(2, "gp02"),
179 PINCTRL_PIN(3, "gp03"),
180 PINCTRL_PIN(4, "gp04"),
181 PINCTRL_PIN(5, "gp05"),
182 PINCTRL_PIN(6, "gp06"),
183 PINCTRL_PIN(7, "gp07"),
184
185 PINCTRL_PIN(8, "gp10"),
186 PINCTRL_PIN(9, "gp11"),
187 PINCTRL_PIN(10, "gp12"),
188 PINCTRL_PIN(11, "gp13"),
189 PINCTRL_PIN(12, "gp14"),
190 PINCTRL_PIN(13, "gp15"),
191 PINCTRL_PIN(14, "gp16"),
192 PINCTRL_PIN(15, "gp17"),
193
194 PINCTRL_PIN(16, "gp20"),
195 PINCTRL_PIN(17, "gp21"),
196 PINCTRL_PIN(18, "gp22"),
197 PINCTRL_PIN(19, "gp23"),
198
199 PINCTRL_PIN(20, "gp30"),
200 PINCTRL_PIN(21, "gp31"),
201 PINCTRL_PIN(22, "gp32"),
202 PINCTRL_PIN(23, "gp33"),
203 PINCTRL_PIN(24, "gp34"),
204 PINCTRL_PIN(25, "gp35"),
205 PINCTRL_PIN(26, "gp36"),
206 PINCTRL_PIN(27, "gp37"),
207
208 PINCTRL_PIN(28, "gp40"),
209 PINCTRL_PIN(29, "gp41"),
210 PINCTRL_PIN(30, "gp42"),
211 PINCTRL_PIN(31, "gp43"),
212 PINCTRL_PIN(32, "gp44"),
213 PINCTRL_PIN(33, "gp45"),
214 PINCTRL_PIN(34, "gp46"),
215 PINCTRL_PIN(35, "gp47"),
216
217 PINCTRL_PIN(36, "gp50"),
218 PINCTRL_PIN(37, "gp51"),
219 PINCTRL_PIN(38, "gp52"),
220 PINCTRL_PIN(39, "gp53"),
221 PINCTRL_PIN(40, "gp54"),
222 PINCTRL_PIN(41, "gp55"),
223 PINCTRL_PIN(42, "gp56"),
224 PINCTRL_PIN(43, "gp57"),
225
226 PINCTRL_PIN(44, "gp60"),
227 PINCTRL_PIN(45, "gp61"),
228 PINCTRL_PIN(46, "gp62"),
229 PINCTRL_PIN(47, "gp63"),
230 PINCTRL_PIN(48, "gp64"),
231 PINCTRL_PIN(49, "gp65"),
232 PINCTRL_PIN(50, "gp66"),
233 PINCTRL_PIN(51, "gp67"),
234
235 PINCTRL_PIN(52, "gp70"),
236 PINCTRL_PIN(53, "gp71"),
237 PINCTRL_PIN(54, "gp72"),
238 PINCTRL_PIN(55, "gp73"),
239 PINCTRL_PIN(56, "gp74"),
240 PINCTRL_PIN(57, "gp75"),
241 PINCTRL_PIN(58, "gp76"),
242 PINCTRL_PIN(59, "gp77"),
243 };
244
245 static const char * const cy8c95x0_groups[] = {
246 "gp00",
247 "gp01",
248 "gp02",
249 "gp03",
250 "gp04",
251 "gp05",
252 "gp06",
253 "gp07",
254
255 "gp10",
256 "gp11",
257 "gp12",
258 "gp13",
259 "gp14",
260 "gp15",
261 "gp16",
262 "gp17",
263
264 "gp20",
265 "gp21",
266 "gp22",
267 "gp23",
268
269 "gp30",
270 "gp31",
271 "gp32",
272 "gp33",
273 "gp34",
274 "gp35",
275 "gp36",
276 "gp37",
277
278 "gp40",
279 "gp41",
280 "gp42",
281 "gp43",
282 "gp44",
283 "gp45",
284 "gp46",
285 "gp47",
286
287 "gp50",
288 "gp51",
289 "gp52",
290 "gp53",
291 "gp54",
292 "gp55",
293 "gp56",
294 "gp57",
295
296 "gp60",
297 "gp61",
298 "gp62",
299 "gp63",
300 "gp64",
301 "gp65",
302 "gp66",
303 "gp67",
304
305 "gp70",
306 "gp71",
307 "gp72",
308 "gp73",
309 "gp74",
310 "gp75",
311 "gp76",
312 "gp77",
313 };
314
315 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
316 unsigned int pin, bool input);
317
cypress_get_port(struct cy8c95x0_pinctrl * chip,unsigned int pin)318 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
319 {
320 /* Account for GPORT2 which only has 4 bits */
321 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
322 }
323
cypress_get_pin_mask(struct cy8c95x0_pinctrl * chip,unsigned int pin)324 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
325 {
326 /* Account for GPORT2 which only has 4 bits */
327 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
328 }
329
cy8c95x0_readable_register(struct device * dev,unsigned int reg)330 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
331 {
332 /*
333 * Only 12 registers are present per port (see Table 6 in the datasheet).
334 */
335 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12)
336 return false;
337
338 switch (reg) {
339 case 0x24 ... 0x27:
340 case 0x31 ... 0x3f:
341 return false;
342 default:
343 return true;
344 }
345 }
346
cy8c95x0_writeable_register(struct device * dev,unsigned int reg)347 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
348 {
349 /*
350 * Only 12 registers are present per port (see Table 6 in the datasheet).
351 */
352 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12)
353 return false;
354
355 switch (reg) {
356 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
357 return false;
358 case CY8C95X0_DEVID:
359 return false;
360 case 0x24 ... 0x27:
361 case 0x31 ... 0x3f:
362 return false;
363 default:
364 return true;
365 }
366 }
367
cy8c95x0_volatile_register(struct device * dev,unsigned int reg)368 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
369 {
370 switch (reg) {
371 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
372 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
373 case CY8C95X0_INTMASK:
374 case CY8C95X0_SELPWM:
375 case CY8C95X0_INVERT:
376 case CY8C95X0_DIRECTION:
377 case CY8C95X0_DRV_PU:
378 case CY8C95X0_DRV_PD:
379 case CY8C95X0_DRV_ODH:
380 case CY8C95X0_DRV_ODL:
381 case CY8C95X0_DRV_PP_FAST:
382 case CY8C95X0_DRV_PP_SLOW:
383 case CY8C95X0_DRV_HIZ:
384 return true;
385 default:
386 return false;
387 }
388 }
389
cy8c95x0_precious_register(struct device * dev,unsigned int reg)390 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
391 {
392 switch (reg) {
393 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
394 return true;
395 default:
396 return false;
397 }
398 }
399
cy8c95x0_muxed_register(unsigned int reg)400 static bool cy8c95x0_muxed_register(unsigned int reg)
401 {
402 switch (reg) {
403 case CY8C95X0_INTMASK:
404 case CY8C95X0_SELPWM:
405 case CY8C95X0_INVERT:
406 case CY8C95X0_DIRECTION:
407 case CY8C95X0_DRV_PU:
408 case CY8C95X0_DRV_PD:
409 case CY8C95X0_DRV_ODH:
410 case CY8C95X0_DRV_ODL:
411 case CY8C95X0_DRV_PP_FAST:
412 case CY8C95X0_DRV_PP_SLOW:
413 case CY8C95X0_DRV_HIZ:
414 return true;
415 default:
416 return false;
417 }
418 }
419
cy8c95x0_wc_register(unsigned int reg)420 static bool cy8c95x0_wc_register(unsigned int reg)
421 {
422 switch (reg) {
423 case CY8C95X0_DRV_PU:
424 case CY8C95X0_DRV_PD:
425 case CY8C95X0_DRV_ODH:
426 case CY8C95X0_DRV_ODL:
427 case CY8C95X0_DRV_PP_FAST:
428 case CY8C95X0_DRV_PP_SLOW:
429 case CY8C95X0_DRV_HIZ:
430 return true;
431 default:
432 return false;
433 }
434 }
435
cy8c95x0_quick_path_register(unsigned int reg)436 static bool cy8c95x0_quick_path_register(unsigned int reg)
437 {
438 switch (reg) {
439 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
440 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
441 case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7):
442 return true;
443 default:
444 return false;
445 }
446 }
447
448 static const struct regmap_range_cfg cy8c95x0_ranges[] = {
449 {
450 .range_min = CY8C95X0_VIRTUAL,
451 .range_max = 0, /* Updated at runtime */
452 .selector_reg = CY8C95X0_PORTSEL,
453 .selector_mask = 0x07,
454 .selector_shift = 0x0,
455 .window_start = CY8C95X0_PORTSEL,
456 .window_len = MUXED_STRIDE,
457 }
458 };
459
460 static const struct regmap_config cy8c9520_i2c_regmap = {
461 .reg_bits = 8,
462 .val_bits = 8,
463
464 .readable_reg = cy8c95x0_readable_register,
465 .writeable_reg = cy8c95x0_writeable_register,
466 .volatile_reg = cy8c95x0_volatile_register,
467 .precious_reg = cy8c95x0_precious_register,
468
469 .cache_type = REGCACHE_MAPLE,
470 .ranges = NULL, /* Updated at runtime */
471 .num_ranges = 1,
472 .max_register = 0, /* Updated at runtime */
473 .num_reg_defaults_raw = 0, /* Updated at runtime */
474 .use_single_read = true, /* Workaround for regcache bug */
475 #if IS_ENABLED(CONFIG_DEBUG_PINCTRL)
476 .disable_locking = false,
477 #else
478 .disable_locking = true,
479 #endif
480 };
481
cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl * chip,unsigned int reg,unsigned int port,unsigned int mask,unsigned int val,bool * change,bool async,bool force)482 static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
483 unsigned int reg,
484 unsigned int port,
485 unsigned int mask,
486 unsigned int val,
487 bool *change, bool async,
488 bool force)
489 {
490 int ret, off, i;
491
492 /* Caller should never modify PORTSEL directly */
493 if (reg == CY8C95X0_PORTSEL)
494 return -EINVAL;
495
496 /* Registers behind the PORTSEL mux have their own range in regmap */
497 if (cy8c95x0_muxed_register(reg)) {
498 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
499 } else {
500 /* Quick path direct access registers honor the port argument */
501 if (cy8c95x0_quick_path_register(reg))
502 off = reg + port;
503 else
504 off = reg;
505 }
506 guard(mutex)(&chip->i2c_lock);
507
508 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);
509 if (ret < 0)
510 return ret;
511
512 /* Mimic what hardware does and update the cache when a WC bit is written.
513 * Allows to mark the registers as non-volatile and reduces I/O cycles.
514 */
515 if (cy8c95x0_wc_register(reg) && (mask & val)) {
516 /* Writing a 1 clears set bits in the other drive mode registers */
517 regcache_cache_only(chip->regmap, true);
518 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
519 if (i == reg)
520 continue;
521
522 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
523 regmap_clear_bits(chip->regmap, off, mask & val);
524 }
525 regcache_cache_only(chip->regmap, false);
526 }
527
528 return ret;
529 }
530
531 /**
532 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache
533 * @chip: The pinctrl to work on
534 * @reg: The register to write to. Can be direct access or muxed register.
535 * MUST NOT be the PORTSEL register.
536 * @port: The port to be used for muxed registers or quick path direct access
537 * registers. Otherwise unused.
538 * @mask: Bitmask to change
539 * @val: New value for bitmask
540 *
541 * This function handles the register writes to the direct access registers and
542 * the muxed registers while caching all register accesses, internally handling
543 * the correct state of the PORTSEL register and protecting the access to muxed
544 * registers.
545 * The caller must only use this function to change registers behind the PORTSEL mux.
546 *
547 * Return: 0 for successful request, else a corresponding error value
548 */
cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl * chip,unsigned int reg,unsigned int port,unsigned int mask,unsigned int val)549 static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
550 unsigned int port, unsigned int mask, unsigned int val)
551 {
552 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true);
553 }
554
555 /**
556 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache
557 * @chip: The pinctrl to work on
558 * @reg: The register to write to. Can be direct access or muxed register.
559 * MUST NOT be the PORTSEL register.
560 * @port: The port to be used for muxed registers or quick path direct access
561 * registers. Otherwise unused.
562 * @mask: Bitmask to change
563 * @val: New value for bitmask
564 *
565 * This function handles the register updates to the direct access registers and
566 * the muxed registers while caching all register accesses, internally handling
567 * the correct state of the PORTSEL register and protecting the access to muxed
568 * registers.
569 * The caller must only use this function to change registers behind the PORTSEL mux.
570 *
571 * Return: 0 for successful request, else a corresponding error value
572 */
cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl * chip,unsigned int reg,unsigned int port,unsigned int mask,unsigned int val)573 static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
574 unsigned int port, unsigned int mask, unsigned int val)
575 {
576 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false);
577 }
578
579 /**
580 * cy8c95x0_regmap_read() - reads a register using the regmap cache
581 * @chip: The pinctrl to work on
582 * @reg: The register to read from. Can be direct access or muxed register.
583 * @port: The port to be used for muxed registers or quick path direct access
584 * registers. Otherwise unused.
585 * @read_val: Value read from hardware or cache
586 *
587 * This function handles the register reads from the direct access registers and
588 * the muxed registers while caching all register accesses, internally handling
589 * the correct state of the PORTSEL register and protecting the access to muxed
590 * registers.
591 * The caller must only use this function to read registers behind the PORTSEL mux.
592 *
593 * Return: 0 for successful request, else a corresponding error value
594 */
cy8c95x0_regmap_read(struct cy8c95x0_pinctrl * chip,unsigned int reg,unsigned int port,unsigned int * read_val)595 static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
596 unsigned int port, unsigned int *read_val)
597 {
598 int off, ret;
599
600 /* Registers behind the PORTSEL mux have their own range in regmap */
601 if (cy8c95x0_muxed_register(reg)) {
602 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
603 } else {
604 /* Quick path direct access registers honor the port argument */
605 if (cy8c95x0_quick_path_register(reg))
606 off = reg + port;
607 else
608 off = reg;
609 }
610 guard(mutex)(&chip->i2c_lock);
611
612 ret = regmap_read(chip->regmap, off, read_val);
613
614 return ret;
615 }
616
cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl * chip,int reg,unsigned long * val,unsigned long * mask)617 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
618 unsigned long *val, unsigned long *mask)
619 {
620 DECLARE_BITMAP(tmask, MAX_LINE);
621 DECLARE_BITMAP(tval, MAX_LINE);
622 int write_val;
623 int ret = 0;
624 int i;
625 u8 bits;
626
627 /* Add the 4 bit gap of Gport2 */
628 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
629 bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
630 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
631
632 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
633 bitmap_shift_left(tval, tval, 4, MAX_LINE);
634 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
635
636 for (i = 0; i < chip->nport; i++) {
637 /* Skip over unused banks */
638 bits = bitmap_get_value8(tmask, i * BANK_SZ);
639 if (!bits)
640 continue;
641
642 write_val = bitmap_get_value8(tval, i * BANK_SZ);
643
644 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val);
645 if (ret < 0)
646 goto out;
647 }
648 out:
649
650 if (ret < 0)
651 dev_err(chip->dev, "failed writing register %d, port %d: err %d\n", reg, i, ret);
652
653 return ret;
654 }
655
cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl * chip,int reg,unsigned long * val,unsigned long * mask)656 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
657 unsigned long *val, unsigned long *mask)
658 {
659 DECLARE_BITMAP(tmask, MAX_LINE);
660 DECLARE_BITMAP(tval, MAX_LINE);
661 DECLARE_BITMAP(tmp, MAX_LINE);
662 int read_val;
663 int ret = 0;
664 int i;
665 u8 bits;
666
667 /* Add the 4 bit gap of Gport2 */
668 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
669 bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
670 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
671
672 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
673 bitmap_shift_left(tval, tval, 4, MAX_LINE);
674 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
675
676 for (i = 0; i < chip->nport; i++) {
677 /* Skip over unused banks */
678 bits = bitmap_get_value8(tmask, i * BANK_SZ);
679 if (!bits)
680 continue;
681
682 ret = cy8c95x0_regmap_read(chip, reg, i, &read_val);
683 if (ret < 0)
684 goto out;
685
686 read_val &= bits;
687 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
688 bitmap_set_value8(tval, read_val, i * BANK_SZ);
689 }
690
691 /* Fill the 4 bit gap of Gport2 */
692 bitmap_shift_right(tmp, tval, 4, MAX_LINE);
693 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
694
695 out:
696 if (ret < 0)
697 dev_err(chip->dev, "failed reading register %d, port %d: err %d\n", reg, i, ret);
698
699 return ret;
700 }
701
cy8c95x0_gpio_direction_input(struct gpio_chip * gc,unsigned int off)702 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
703 {
704 return pinctrl_gpio_direction_input(gc, off);
705 }
706
cy8c95x0_gpio_direction_output(struct gpio_chip * gc,unsigned int off,int val)707 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
708 unsigned int off, int val)
709 {
710 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
711 u8 port = cypress_get_port(chip, off);
712 u8 bit = cypress_get_pin_mask(chip, off);
713 int ret;
714
715 /* Set output level */
716 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
717 if (ret)
718 return ret;
719
720 return pinctrl_gpio_direction_output(gc, off);
721 }
722
cy8c95x0_gpio_get_value(struct gpio_chip * gc,unsigned int off)723 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
724 {
725 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
726 u8 port = cypress_get_port(chip, off);
727 u8 bit = cypress_get_pin_mask(chip, off);
728 u32 reg_val;
729 int ret;
730
731 ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val);
732 if (ret < 0) {
733 /*
734 * NOTE:
735 * Diagnostic already emitted; that's all we should
736 * do unless gpio_*_value_cansleep() calls become different
737 * from their nonsleeping siblings (and report faults).
738 */
739 return 0;
740 }
741
742 return !!(reg_val & bit);
743 }
744
cy8c95x0_gpio_set_value(struct gpio_chip * gc,unsigned int off,int val)745 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
746 int val)
747 {
748 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
749 u8 port = cypress_get_port(chip, off);
750 u8 bit = cypress_get_pin_mask(chip, off);
751
752 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
753 }
754
cy8c95x0_gpio_get_direction(struct gpio_chip * gc,unsigned int off)755 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
756 {
757 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
758 u8 port = cypress_get_port(chip, off);
759 u8 bit = cypress_get_pin_mask(chip, off);
760 u32 reg_val;
761 int ret;
762
763 ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val);
764 if (ret < 0)
765 goto out;
766
767 if (reg_val & bit)
768 return GPIO_LINE_DIRECTION_IN;
769
770 return GPIO_LINE_DIRECTION_OUT;
771 out:
772 return ret;
773 }
774
cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl * chip,unsigned int off,unsigned long * config)775 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
776 unsigned int off,
777 unsigned long *config)
778 {
779 enum pin_config_param param = pinconf_to_config_param(*config);
780 u8 port = cypress_get_port(chip, off);
781 u8 bit = cypress_get_pin_mask(chip, off);
782 unsigned int reg;
783 u32 reg_val;
784 u16 arg = 0;
785 int ret;
786
787 switch (param) {
788 case PIN_CONFIG_BIAS_PULL_UP:
789 reg = CY8C95X0_DRV_PU;
790 break;
791 case PIN_CONFIG_BIAS_PULL_DOWN:
792 reg = CY8C95X0_DRV_PD;
793 break;
794 case PIN_CONFIG_BIAS_DISABLE:
795 reg = CY8C95X0_DRV_HIZ;
796 break;
797 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
798 reg = CY8C95X0_DRV_ODL;
799 break;
800 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
801 reg = CY8C95X0_DRV_ODH;
802 break;
803 case PIN_CONFIG_DRIVE_PUSH_PULL:
804 reg = CY8C95X0_DRV_PP_FAST;
805 break;
806 case PIN_CONFIG_INPUT_ENABLE:
807 reg = CY8C95X0_DIRECTION;
808 break;
809 case PIN_CONFIG_MODE_PWM:
810 reg = CY8C95X0_SELPWM;
811 break;
812 case PIN_CONFIG_OUTPUT:
813 reg = CY8C95X0_OUTPUT;
814 break;
815 case PIN_CONFIG_OUTPUT_ENABLE:
816 reg = CY8C95X0_DIRECTION;
817 break;
818
819 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
820 case PIN_CONFIG_BIAS_BUS_HOLD:
821 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
822 case PIN_CONFIG_DRIVE_STRENGTH:
823 case PIN_CONFIG_DRIVE_STRENGTH_UA:
824 case PIN_CONFIG_INPUT_DEBOUNCE:
825 case PIN_CONFIG_INPUT_SCHMITT:
826 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
827 case PIN_CONFIG_MODE_LOW_POWER:
828 case PIN_CONFIG_PERSIST_STATE:
829 case PIN_CONFIG_POWER_SOURCE:
830 case PIN_CONFIG_SKEW_DELAY:
831 case PIN_CONFIG_SLEEP_HARDWARE_STATE:
832 case PIN_CONFIG_SLEW_RATE:
833 default:
834 ret = -ENOTSUPP;
835 goto out;
836 }
837 /*
838 * Writing 1 to one of the drive mode registers will automatically
839 * clear conflicting set bits in the other drive mode registers.
840 */
841 ret = cy8c95x0_regmap_read(chip, reg, port, ®_val);
842 if (ret < 0)
843 goto out;
844
845 if (reg_val & bit)
846 arg = 1;
847 if (param == PIN_CONFIG_OUTPUT_ENABLE)
848 arg = !arg;
849
850 *config = pinconf_to_config_packed(param, (u16)arg);
851 out:
852 return ret;
853 }
854
cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl * chip,unsigned int off,unsigned long config)855 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
856 unsigned int off,
857 unsigned long config)
858 {
859 u8 port = cypress_get_port(chip, off);
860 u8 bit = cypress_get_pin_mask(chip, off);
861 unsigned long param = pinconf_to_config_param(config);
862 unsigned long arg = pinconf_to_config_argument(config);
863 unsigned int reg;
864 int ret;
865
866 switch (param) {
867 case PIN_CONFIG_BIAS_PULL_UP:
868 __clear_bit(off, chip->push_pull);
869 reg = CY8C95X0_DRV_PU;
870 break;
871 case PIN_CONFIG_BIAS_PULL_DOWN:
872 __clear_bit(off, chip->push_pull);
873 reg = CY8C95X0_DRV_PD;
874 break;
875 case PIN_CONFIG_BIAS_DISABLE:
876 __clear_bit(off, chip->push_pull);
877 reg = CY8C95X0_DRV_HIZ;
878 break;
879 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
880 __clear_bit(off, chip->push_pull);
881 reg = CY8C95X0_DRV_ODL;
882 break;
883 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
884 __clear_bit(off, chip->push_pull);
885 reg = CY8C95X0_DRV_ODH;
886 break;
887 case PIN_CONFIG_DRIVE_PUSH_PULL:
888 __set_bit(off, chip->push_pull);
889 reg = CY8C95X0_DRV_PP_FAST;
890 break;
891 case PIN_CONFIG_MODE_PWM:
892 reg = CY8C95X0_SELPWM;
893 break;
894 case PIN_CONFIG_OUTPUT_ENABLE:
895 ret = cy8c95x0_pinmux_direction(chip, off, !arg);
896 goto out;
897 case PIN_CONFIG_INPUT_ENABLE:
898 ret = cy8c95x0_pinmux_direction(chip, off, arg);
899 goto out;
900 default:
901 ret = -ENOTSUPP;
902 goto out;
903 }
904 /*
905 * Writing 1 to one of the drive mode registers will automatically
906 * clear conflicting set bits in the other drive mode registers.
907 */
908 ret = cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit);
909 out:
910 return ret;
911 }
912
cy8c95x0_gpio_get_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)913 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
914 unsigned long *mask, unsigned long *bits)
915 {
916 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
917
918 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
919 }
920
cy8c95x0_gpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)921 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
922 unsigned long *mask, unsigned long *bits)
923 {
924 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
925
926 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
927 }
928
cy8c95x0_add_pin_ranges(struct gpio_chip * gc)929 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
930 {
931 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
932 struct device *dev = chip->dev;
933 int ret;
934
935 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
936 if (ret)
937 dev_err(dev, "failed to add GPIO pin range\n");
938
939 return ret;
940 }
941
cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl * chip)942 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
943 {
944 struct gpio_chip *gc = &chip->gpio_chip;
945
946 gc->request = gpiochip_generic_request;
947 gc->free = gpiochip_generic_free;
948 gc->direction_input = cy8c95x0_gpio_direction_input;
949 gc->direction_output = cy8c95x0_gpio_direction_output;
950 gc->get = cy8c95x0_gpio_get_value;
951 gc->set = cy8c95x0_gpio_set_value;
952 gc->get_direction = cy8c95x0_gpio_get_direction;
953 gc->get_multiple = cy8c95x0_gpio_get_multiple;
954 gc->set_multiple = cy8c95x0_gpio_set_multiple;
955 gc->set_config = gpiochip_generic_config;
956 gc->can_sleep = true;
957 gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
958
959 gc->base = -1;
960 gc->ngpio = chip->tpin;
961
962 gc->parent = chip->dev;
963 gc->owner = THIS_MODULE;
964 gc->names = NULL;
965
966 gc->label = dev_name(chip->dev);
967
968 return devm_gpiochip_add_data(chip->dev, gc, chip);
969 }
970
cy8c95x0_irq_mask(struct irq_data * d)971 static void cy8c95x0_irq_mask(struct irq_data *d)
972 {
973 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
974 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
975 irq_hw_number_t hwirq = irqd_to_hwirq(d);
976
977 set_bit(hwirq, chip->irq_mask);
978 gpiochip_disable_irq(gc, hwirq);
979 }
980
cy8c95x0_irq_unmask(struct irq_data * d)981 static void cy8c95x0_irq_unmask(struct irq_data *d)
982 {
983 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
984 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
985 irq_hw_number_t hwirq = irqd_to_hwirq(d);
986
987 gpiochip_enable_irq(gc, hwirq);
988 clear_bit(hwirq, chip->irq_mask);
989 }
990
cy8c95x0_irq_bus_lock(struct irq_data * d)991 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
992 {
993 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
994 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
995
996 mutex_lock(&chip->irq_lock);
997 }
998
cy8c95x0_irq_bus_sync_unlock(struct irq_data * d)999 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
1000 {
1001 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1002 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1003 DECLARE_BITMAP(ones, MAX_LINE);
1004 DECLARE_BITMAP(irq_mask, MAX_LINE);
1005 DECLARE_BITMAP(reg_direction, MAX_LINE);
1006
1007 bitmap_fill(ones, MAX_LINE);
1008
1009 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
1010
1011 /* Switch direction to input if needed */
1012 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
1013 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
1014 bitmap_complement(irq_mask, irq_mask, MAX_LINE);
1015
1016 /* Look for any newly setup interrupt */
1017 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
1018
1019 mutex_unlock(&chip->irq_lock);
1020 }
1021
cy8c95x0_irq_set_type(struct irq_data * d,unsigned int type)1022 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
1023 {
1024 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1025 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1026 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1027 unsigned int trig_type;
1028
1029 switch (type) {
1030 case IRQ_TYPE_EDGE_RISING:
1031 case IRQ_TYPE_EDGE_FALLING:
1032 case IRQ_TYPE_EDGE_BOTH:
1033 trig_type = type;
1034 break;
1035 case IRQ_TYPE_LEVEL_HIGH:
1036 trig_type = IRQ_TYPE_EDGE_RISING;
1037 break;
1038 case IRQ_TYPE_LEVEL_LOW:
1039 trig_type = IRQ_TYPE_EDGE_FALLING;
1040 break;
1041 default:
1042 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
1043 return -EINVAL;
1044 }
1045
1046 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
1047 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
1048 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
1049 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
1050
1051 return 0;
1052 }
1053
cy8c95x0_irq_shutdown(struct irq_data * d)1054 static void cy8c95x0_irq_shutdown(struct irq_data *d)
1055 {
1056 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1057 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1058 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1059
1060 clear_bit(hwirq, chip->irq_trig_raise);
1061 clear_bit(hwirq, chip->irq_trig_fall);
1062 clear_bit(hwirq, chip->irq_trig_low);
1063 clear_bit(hwirq, chip->irq_trig_high);
1064 }
1065
1066 static const struct irq_chip cy8c95x0_irqchip = {
1067 .name = "cy8c95x0-irq",
1068 .irq_mask = cy8c95x0_irq_mask,
1069 .irq_unmask = cy8c95x0_irq_unmask,
1070 .irq_bus_lock = cy8c95x0_irq_bus_lock,
1071 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
1072 .irq_set_type = cy8c95x0_irq_set_type,
1073 .irq_shutdown = cy8c95x0_irq_shutdown,
1074 .flags = IRQCHIP_IMMUTABLE,
1075 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1076 };
1077
cy8c95x0_irq_pending(struct cy8c95x0_pinctrl * chip,unsigned long * pending)1078 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
1079 {
1080 DECLARE_BITMAP(ones, MAX_LINE);
1081 DECLARE_BITMAP(cur_stat, MAX_LINE);
1082 DECLARE_BITMAP(new_stat, MAX_LINE);
1083 DECLARE_BITMAP(trigger, MAX_LINE);
1084
1085 bitmap_fill(ones, MAX_LINE);
1086
1087 /* Read the current interrupt status from the device */
1088 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
1089 return false;
1090
1091 /* Check latched inputs */
1092 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
1093 return false;
1094
1095 /* Apply filter for rising/falling edge selection */
1096 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
1097 cur_stat, MAX_LINE);
1098
1099 bitmap_and(pending, new_stat, trigger, MAX_LINE);
1100
1101 return !bitmap_empty(pending, MAX_LINE);
1102 }
1103
cy8c95x0_irq_handler(int irq,void * devid)1104 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
1105 {
1106 struct cy8c95x0_pinctrl *chip = devid;
1107 struct gpio_chip *gc = &chip->gpio_chip;
1108 DECLARE_BITMAP(pending, MAX_LINE);
1109 int nested_irq, level;
1110 bool ret;
1111
1112 ret = cy8c95x0_irq_pending(chip, pending);
1113 if (!ret)
1114 return IRQ_RETVAL(0);
1115
1116 ret = 0;
1117 for_each_set_bit(level, pending, MAX_LINE) {
1118 /* Already accounted for 4bit gap in GPort2 */
1119 nested_irq = irq_find_mapping(gc->irq.domain, level);
1120
1121 if (unlikely(nested_irq <= 0)) {
1122 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1123 continue;
1124 }
1125
1126 if (test_bit(level, chip->irq_trig_low))
1127 while (!cy8c95x0_gpio_get_value(gc, level))
1128 handle_nested_irq(nested_irq);
1129 else if (test_bit(level, chip->irq_trig_high))
1130 while (cy8c95x0_gpio_get_value(gc, level))
1131 handle_nested_irq(nested_irq);
1132 else
1133 handle_nested_irq(nested_irq);
1134
1135 ret = 1;
1136 }
1137
1138 return IRQ_RETVAL(ret);
1139 }
1140
cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)1141 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1142 {
1143 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1144
1145 return chip->tpin;
1146 }
1147
cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)1148 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1149 unsigned int group)
1150 {
1151 return cy8c95x0_groups[group];
1152 }
1153
cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)1154 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1155 unsigned int group,
1156 const unsigned int **pins,
1157 unsigned int *num_pins)
1158 {
1159 *pins = &cy8c9560_pins[group].number;
1160 *num_pins = 1;
1161 return 0;
1162 }
1163
cy8c95x0_get_fname(unsigned int selector)1164 static const char *cy8c95x0_get_fname(unsigned int selector)
1165 {
1166 if (selector == 0)
1167 return "gpio";
1168 else
1169 return "pwm";
1170 }
1171
cy8c95x0_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)1172 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1173 unsigned int pin)
1174 {
1175 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1176 DECLARE_BITMAP(mask, MAX_LINE);
1177 DECLARE_BITMAP(pwm, MAX_LINE);
1178
1179 bitmap_zero(mask, MAX_LINE);
1180 __set_bit(pin, mask);
1181
1182 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) {
1183 seq_puts(s, "not available");
1184 return;
1185 }
1186
1187 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1188 }
1189
1190 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1191 .get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1192 .get_group_name = cy8c95x0_pinctrl_get_group_name,
1193 .get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1194 #ifdef CONFIG_OF
1195 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1196 .dt_free_map = pinconf_generic_dt_free_map,
1197 #endif
1198 .pin_dbg_show = cy8c95x0_pin_dbg_show,
1199 };
1200
cy8c95x0_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)1201 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1202 {
1203 return cy8c95x0_get_fname(selector);
1204 }
1205
cy8c95x0_get_functions_count(struct pinctrl_dev * pctldev)1206 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1207 {
1208 return 2;
1209 }
1210
cy8c95x0_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)1211 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1212 const char * const **groups,
1213 unsigned int * const num_groups)
1214 {
1215 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1216
1217 *groups = cy8c95x0_groups;
1218 *num_groups = chip->tpin;
1219 return 0;
1220 }
1221
cy8c95x0_set_mode(struct cy8c95x0_pinctrl * chip,unsigned int off,bool mode)1222 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1223 {
1224 u8 port = cypress_get_port(chip, off);
1225 u8 bit = cypress_get_pin_mask(chip, off);
1226
1227 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0);
1228 }
1229
cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl * chip,unsigned int selector,unsigned int group)1230 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1231 unsigned int selector, unsigned int group)
1232 {
1233 u8 port = cypress_get_port(chip, group);
1234 u8 bit = cypress_get_pin_mask(chip, group);
1235 int ret;
1236
1237 ret = cy8c95x0_set_mode(chip, group, selector);
1238 if (ret < 0)
1239 return ret;
1240
1241 if (selector == 0)
1242 return 0;
1243
1244 /* Set direction to output & set output to 1 so that PWM can work */
1245 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit);
1246 if (ret < 0)
1247 return ret;
1248
1249 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit);
1250 }
1251
cy8c95x0_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)1252 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1253 unsigned int group)
1254 {
1255 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1256
1257 return cy8c95x0_pinmux_mode(chip, selector, group);
1258 }
1259
cy8c95x0_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin)1260 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1261 struct pinctrl_gpio_range *range,
1262 unsigned int pin)
1263 {
1264 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1265
1266 return cy8c95x0_set_mode(chip, pin, false);
1267 }
1268
cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl * chip,unsigned int pin,bool input)1269 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1270 unsigned int pin, bool input)
1271 {
1272 u8 port = cypress_get_port(chip, pin);
1273 u8 bit = cypress_get_pin_mask(chip, pin);
1274 int ret;
1275
1276 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0);
1277 if (ret)
1278 return ret;
1279
1280 /*
1281 * Disable driving the pin by forcing it to HighZ. Only setting
1282 * the direction register isn't sufficient in Push-Pull mode.
1283 */
1284 if (input && test_bit(pin, chip->push_pull)) {
1285 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit);
1286 if (ret)
1287 return ret;
1288
1289 __clear_bit(pin, chip->push_pull);
1290 }
1291
1292 return 0;
1293 }
1294
cy8c95x0_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)1295 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1296 struct pinctrl_gpio_range *range,
1297 unsigned int pin, bool input)
1298 {
1299 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1300
1301 return cy8c95x0_pinmux_direction(chip, pin, input);
1302 }
1303
1304 static const struct pinmux_ops cy8c95x0_pmxops = {
1305 .get_functions_count = cy8c95x0_get_functions_count,
1306 .get_function_name = cy8c95x0_get_function_name,
1307 .get_function_groups = cy8c95x0_get_function_groups,
1308 .set_mux = cy8c95x0_set_mux,
1309 .gpio_request_enable = cy8c95x0_gpio_request_enable,
1310 .gpio_set_direction = cy8c95x0_gpio_set_direction,
1311 .strict = true,
1312 };
1313
cy8c95x0_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)1314 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1315 unsigned long *config)
1316 {
1317 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1318
1319 return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1320 }
1321
cy8c95x0_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1322 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1323 unsigned long *configs, unsigned int num_configs)
1324 {
1325 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1326 int ret = 0;
1327 int i;
1328
1329 for (i = 0; i < num_configs; i++) {
1330 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1331 if (ret)
1332 return ret;
1333 }
1334
1335 return ret;
1336 }
1337
1338 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1339 .pin_config_get = cy8c95x0_pinconf_get,
1340 .pin_config_set = cy8c95x0_pinconf_set,
1341 .is_generic = true,
1342 };
1343
cy8c95x0_irq_setup(struct cy8c95x0_pinctrl * chip,int irq)1344 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1345 {
1346 struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1347 DECLARE_BITMAP(pending_irqs, MAX_LINE);
1348 int ret;
1349
1350 mutex_init(&chip->irq_lock);
1351
1352 bitmap_zero(pending_irqs, MAX_LINE);
1353
1354 /* Read IRQ status register to clear all pending interrupts */
1355 ret = cy8c95x0_irq_pending(chip, pending_irqs);
1356 if (ret) {
1357 dev_err(chip->dev, "failed to clear irq status register\n");
1358 return ret;
1359 }
1360
1361 /* Mask all interrupts */
1362 bitmap_fill(chip->irq_mask, MAX_LINE);
1363
1364 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1365
1366 /* This will let us handle the parent IRQ in the driver */
1367 girq->parent_handler = NULL;
1368 girq->num_parents = 0;
1369 girq->parents = NULL;
1370 girq->default_type = IRQ_TYPE_NONE;
1371 girq->handler = handle_simple_irq;
1372 girq->threaded = true;
1373
1374 ret = devm_request_threaded_irq(chip->dev, irq,
1375 NULL, cy8c95x0_irq_handler,
1376 IRQF_ONESHOT | IRQF_SHARED,
1377 dev_name(chip->dev), chip);
1378 if (ret) {
1379 dev_err(chip->dev, "failed to request irq %d\n", irq);
1380 return ret;
1381 }
1382 dev_info(chip->dev, "Registered threaded IRQ\n");
1383
1384 return 0;
1385 }
1386
cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl * chip)1387 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1388 {
1389 struct pinctrl_desc *pd = &chip->pinctrl_desc;
1390
1391 pd->pctlops = &cy8c95x0_pinctrl_ops;
1392 pd->confops = &cy8c95x0_pinconf_ops;
1393 pd->pmxops = &cy8c95x0_pmxops;
1394 pd->name = dev_name(chip->dev);
1395 pd->pins = cy8c9560_pins;
1396 pd->npins = chip->tpin;
1397 pd->owner = THIS_MODULE;
1398
1399 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1400 if (IS_ERR(chip->pctldev))
1401 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1402 "can't register controller\n");
1403
1404 return 0;
1405 }
1406
cy8c95x0_detect(struct i2c_client * client,struct i2c_board_info * info)1407 static int cy8c95x0_detect(struct i2c_client *client,
1408 struct i2c_board_info *info)
1409 {
1410 struct i2c_adapter *adapter = client->adapter;
1411 int ret;
1412 const char *name;
1413
1414 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1415 return -ENODEV;
1416
1417 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1418 if (ret < 0)
1419 return ret;
1420 switch (ret & GENMASK(7, 4)) {
1421 case 0x20:
1422 name = cy8c95x0_id[0].name;
1423 break;
1424 case 0x40:
1425 name = cy8c95x0_id[1].name;
1426 break;
1427 case 0x60:
1428 name = cy8c95x0_id[2].name;
1429 break;
1430 default:
1431 return -ENODEV;
1432 }
1433
1434 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1435 strscpy(info->type, name, I2C_NAME_SIZE);
1436
1437 return 0;
1438 }
1439
cy8c95x0_probe(struct i2c_client * client)1440 static int cy8c95x0_probe(struct i2c_client *client)
1441 {
1442 struct cy8c95x0_pinctrl *chip;
1443 struct regmap_config regmap_conf;
1444 struct regmap_range_cfg regmap_range_conf;
1445 struct regulator *reg;
1446 int ret;
1447
1448 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
1449 if (!chip)
1450 return -ENOMEM;
1451
1452 chip->dev = &client->dev;
1453
1454 /* Set the device type */
1455 chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1456 if (!chip->driver_data)
1457 return -ENODEV;
1458
1459 i2c_set_clientdata(client, chip);
1460
1461 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1462 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1463
1464 memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
1465
1466 switch (chip->tpin) {
1467 case 20:
1468 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1469 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;
1470 break;
1471 case 40:
1472 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1473 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;
1474 break;
1475 case 60:
1476 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1477 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;
1478 break;
1479 default:
1480 return -ENODEV;
1481 }
1482
1483 reg = devm_regulator_get(&client->dev, "vdd");
1484 if (IS_ERR(reg)) {
1485 if (PTR_ERR(reg) == -EPROBE_DEFER)
1486 return -EPROBE_DEFER;
1487 } else {
1488 ret = regulator_enable(reg);
1489 if (ret) {
1490 dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
1491 return ret;
1492 }
1493 chip->regulator = reg;
1494 }
1495
1496 /* bring the chip out of reset if reset pin is provided */
1497 chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
1498 if (IS_ERR(chip->gpio_reset)) {
1499 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),
1500 "Failed to get GPIO 'reset'\n");
1501 goto err_exit;
1502 } else if (chip->gpio_reset) {
1503 usleep_range(1000, 2000);
1504 gpiod_set_value_cansleep(chip->gpio_reset, 0);
1505 usleep_range(250000, 300000);
1506
1507 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1508 }
1509
1510 /* Regmap for direct and paged registers */
1511 memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));
1512 regmap_conf.ranges = ®map_range_conf;
1513 regmap_conf.max_register = regmap_range_conf.range_max;
1514 regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;
1515
1516 chip->regmap = devm_regmap_init_i2c(client, ®map_conf);
1517 if (IS_ERR(chip->regmap)) {
1518 ret = PTR_ERR(chip->regmap);
1519 goto err_exit;
1520 }
1521
1522 bitmap_zero(chip->push_pull, MAX_LINE);
1523 bitmap_zero(chip->shiftmask, MAX_LINE);
1524 bitmap_set(chip->shiftmask, 0, 20);
1525 mutex_init(&chip->i2c_lock);
1526
1527 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1528 ret = cy8c95x0_acpi_get_irq(&client->dev);
1529 if (ret > 0)
1530 client->irq = ret;
1531 }
1532
1533 if (client->irq) {
1534 ret = cy8c95x0_irq_setup(chip, client->irq);
1535 if (ret)
1536 goto err_exit;
1537 }
1538
1539 ret = cy8c95x0_setup_pinctrl(chip);
1540 if (ret)
1541 goto err_exit;
1542
1543 ret = cy8c95x0_setup_gpiochip(chip);
1544 if (ret)
1545 goto err_exit;
1546
1547 return 0;
1548
1549 err_exit:
1550 if (!IS_ERR_OR_NULL(chip->regulator))
1551 regulator_disable(chip->regulator);
1552 return ret;
1553 }
1554
cy8c95x0_remove(struct i2c_client * client)1555 static void cy8c95x0_remove(struct i2c_client *client)
1556 {
1557 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
1558
1559 if (!IS_ERR_OR_NULL(chip->regulator))
1560 regulator_disable(chip->regulator);
1561 }
1562
1563 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1564 { "INT3490", 40, },
1565 { }
1566 };
1567 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1568
1569 static struct i2c_driver cy8c95x0_driver = {
1570 .driver = {
1571 .name = "cy8c95x0-pinctrl",
1572 .of_match_table = cy8c95x0_dt_ids,
1573 .acpi_match_table = cy8c95x0_acpi_ids,
1574 },
1575 .probe = cy8c95x0_probe,
1576 .remove = cy8c95x0_remove,
1577 .id_table = cy8c95x0_id,
1578 .detect = cy8c95x0_detect,
1579 };
1580 module_i2c_driver(cy8c95x0_driver);
1581
1582 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1583 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1584 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1585 MODULE_LICENSE("GPL");
1586