1 // SPDX-License-Identifier: GPL-2.0
2 // LPC interface for ChromeOS Embedded Controller
3 //
4 // Copyright (C) 2012-2015 Google, Inc
5 //
6 // This driver uses the ChromeOS EC byte-level message-based protocol for
7 // communicating the keyboard state (which keys are pressed) from a keyboard EC
8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing,
9 // but everything else (including deghosting) is done here. The main
10 // motivation for this is to keep the EC firmware as simple as possible, since
11 // it cannot be easily upgraded and EC flash/IRAM space is relatively
12 // expensive.
13
14 #include <linux/acpi.h>
15 #include <linux/dmi.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/kobject.h>
20 #include <linux/module.h>
21 #include <linux/platform_data/cros_ec_commands.h>
22 #include <linux/platform_data/cros_ec_proto.h>
23 #include <linux/platform_device.h>
24 #include <linux/printk.h>
25 #include <linux/reboot.h>
26 #include <linux/suspend.h>
27
28 #include "cros_ec.h"
29 #include "cros_ec_lpc_mec.h"
30
31 #define DRV_NAME "cros_ec_lpcs"
32 #define ACPI_DRV_NAME "GOOG0004"
33 #define FRMW_ACPI_DRV_NAME "FRMWC004"
34
35 /* True if ACPI device is present */
36 static bool cros_ec_lpc_acpi_device_found;
37
38 /*
39 * Indicates that lpc_driver_data.quirk_mmio_memory_base should
40 * be used as the base port for EC mapped memory.
41 */
42 #define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0)
43 /*
44 * Indicates that lpc_driver_data.quirk_acpi_id should be used to find
45 * the ACPI device.
46 */
47 #define CROS_EC_LPC_QUIRK_ACPI_ID BIT(1)
48 /*
49 * Indicates that lpc_driver_data.quirk_aml_mutex_name should be used
50 * to find an AML mutex to protect access to Microchip EC.
51 */
52 #define CROS_EC_LPC_QUIRK_AML_MUTEX BIT(2)
53
54 /**
55 * struct lpc_driver_data - driver data attached to a DMI device ID to indicate
56 * hardware quirks.
57 * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_*
58 * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used
59 * when quirk ...REMAP_MEMORY is set.)
60 * @quirk_acpi_id: An ACPI HID to be used to find the ACPI device.
61 * @quirk_aml_mutex_name: The name of an AML mutex to be used to protect access
62 * to Microchip EC.
63 */
64 struct lpc_driver_data {
65 u32 quirks;
66 u16 quirk_mmio_memory_base;
67 const char *quirk_acpi_id;
68 const char *quirk_aml_mutex_name;
69 };
70
71 /**
72 * struct cros_ec_lpc - LPC device-specific data
73 * @mmio_memory_base: The first I/O port addressing EC mapped memory.
74 */
75 struct cros_ec_lpc {
76 u16 mmio_memory_base;
77 };
78
79 /**
80 * struct lpc_driver_ops - LPC driver operations
81 * @read: Copy length bytes from EC address offset into buffer dest.
82 * Returns a negative error code on error, or the 8-bit checksum
83 * of all bytes read.
84 * @write: Copy length bytes from buffer msg into EC address offset.
85 * Returns a negative error code on error, or the 8-bit checksum
86 * of all bytes written.
87 */
88 struct lpc_driver_ops {
89 int (*read)(unsigned int offset, unsigned int length, u8 *dest);
90 int (*write)(unsigned int offset, unsigned int length, const u8 *msg);
91 };
92
93 static struct lpc_driver_ops cros_ec_lpc_ops = { };
94
95 /*
96 * A generic instance of the read function of struct lpc_driver_ops, used for
97 * the LPC EC.
98 */
cros_ec_lpc_read_bytes(unsigned int offset,unsigned int length,u8 * dest)99 static int cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length,
100 u8 *dest)
101 {
102 u8 sum = 0;
103 int i;
104
105 for (i = 0; i < length; ++i) {
106 dest[i] = inb(offset + i);
107 sum += dest[i];
108 }
109
110 /* Return checksum of all bytes read */
111 return sum;
112 }
113
114 /*
115 * A generic instance of the write function of struct lpc_driver_ops, used for
116 * the LPC EC.
117 */
cros_ec_lpc_write_bytes(unsigned int offset,unsigned int length,const u8 * msg)118 static int cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length,
119 const u8 *msg)
120 {
121 u8 sum = 0;
122 int i;
123
124 for (i = 0; i < length; ++i) {
125 outb(msg[i], offset + i);
126 sum += msg[i];
127 }
128
129 /* Return checksum of all bytes written */
130 return sum;
131 }
132
133 /*
134 * An instance of the read function of struct lpc_driver_ops, used for the
135 * MEC variant of LPC EC.
136 */
cros_ec_lpc_mec_read_bytes(unsigned int offset,unsigned int length,u8 * dest)137 static int cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length,
138 u8 *dest)
139 {
140 int in_range = cros_ec_lpc_mec_in_range(offset, length);
141
142 if (in_range < 0)
143 return in_range;
144
145 return in_range ?
146 cros_ec_lpc_io_bytes_mec(MEC_IO_READ,
147 offset - EC_HOST_CMD_REGION0,
148 length, dest) :
149 cros_ec_lpc_read_bytes(offset, length, dest);
150 }
151
152 /*
153 * An instance of the write function of struct lpc_driver_ops, used for the
154 * MEC variant of LPC EC.
155 */
cros_ec_lpc_mec_write_bytes(unsigned int offset,unsigned int length,const u8 * msg)156 static int cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length,
157 const u8 *msg)
158 {
159 int in_range = cros_ec_lpc_mec_in_range(offset, length);
160
161 if (in_range < 0)
162 return in_range;
163
164 return in_range ?
165 cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE,
166 offset - EC_HOST_CMD_REGION0,
167 length, (u8 *)msg) :
168 cros_ec_lpc_write_bytes(offset, length, msg);
169 }
170
ec_response_timed_out(void)171 static int ec_response_timed_out(void)
172 {
173 unsigned long one_second = jiffies + HZ;
174 u8 data;
175 int ret;
176
177 usleep_range(200, 300);
178 do {
179 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data);
180 if (ret < 0)
181 return ret;
182 if (!(data & EC_LPC_STATUS_BUSY_MASK))
183 return 0;
184 usleep_range(100, 200);
185 } while (time_before(jiffies, one_second));
186
187 return 1;
188 }
189
cros_ec_pkt_xfer_lpc(struct cros_ec_device * ec,struct cros_ec_command * msg)190 static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec,
191 struct cros_ec_command *msg)
192 {
193 struct ec_host_response response;
194 u8 sum;
195 int ret = 0;
196 u8 *dout;
197
198 ret = cros_ec_prepare_tx(ec, msg);
199 if (ret < 0)
200 goto done;
201
202 /* Write buffer */
203 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout);
204 if (ret < 0)
205 goto done;
206
207 /* Here we go */
208 sum = EC_COMMAND_PROTOCOL_3;
209 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum);
210 if (ret < 0)
211 goto done;
212
213 ret = ec_response_timed_out();
214 if (ret < 0)
215 goto done;
216 if (ret) {
217 dev_warn(ec->dev, "EC response timed out\n");
218 ret = -EIO;
219 goto done;
220 }
221
222 /* Check result */
223 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum);
224 if (ret < 0)
225 goto done;
226 msg->result = ret;
227 ret = cros_ec_check_result(ec, msg);
228 if (ret)
229 goto done;
230
231 /* Read back response */
232 dout = (u8 *)&response;
233 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response),
234 dout);
235 if (ret < 0)
236 goto done;
237 sum = ret;
238
239 msg->result = response.result;
240
241 if (response.data_len > msg->insize) {
242 dev_err(ec->dev,
243 "packet too long (%d bytes, expected %d)",
244 response.data_len, msg->insize);
245 ret = -EMSGSIZE;
246 goto done;
247 }
248
249 /* Read response and process checksum */
250 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET +
251 sizeof(response), response.data_len,
252 msg->data);
253 if (ret < 0)
254 goto done;
255 sum += ret;
256
257 if (sum) {
258 dev_err(ec->dev,
259 "bad packet checksum %02x\n",
260 response.checksum);
261 ret = -EBADMSG;
262 goto done;
263 }
264
265 /* Return actual amount of data received */
266 ret = response.data_len;
267 done:
268 return ret;
269 }
270
cros_ec_cmd_xfer_lpc(struct cros_ec_device * ec,struct cros_ec_command * msg)271 static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec,
272 struct cros_ec_command *msg)
273 {
274 struct ec_lpc_host_args args;
275 u8 sum;
276 int ret = 0;
277
278 if (msg->outsize > EC_PROTO2_MAX_PARAM_SIZE ||
279 msg->insize > EC_PROTO2_MAX_PARAM_SIZE) {
280 dev_err(ec->dev,
281 "invalid buffer sizes (out %d, in %d)\n",
282 msg->outsize, msg->insize);
283 return -EINVAL;
284 }
285
286 /* Now actually send the command to the EC and get the result */
287 args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
288 args.command_version = msg->version;
289 args.data_size = msg->outsize;
290
291 /* Initialize checksum */
292 sum = msg->command + args.flags + args.command_version + args.data_size;
293
294 /* Copy data and update checksum */
295 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize,
296 msg->data);
297 if (ret < 0)
298 goto done;
299 sum += ret;
300
301 /* Finalize checksum and write args */
302 args.checksum = sum;
303 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args),
304 (u8 *)&args);
305 if (ret < 0)
306 goto done;
307
308 /* Here we go */
309 sum = msg->command;
310 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum);
311 if (ret < 0)
312 goto done;
313
314 ret = ec_response_timed_out();
315 if (ret < 0)
316 goto done;
317 if (ret) {
318 dev_warn(ec->dev, "EC response timed out\n");
319 ret = -EIO;
320 goto done;
321 }
322
323 /* Check result */
324 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum);
325 if (ret < 0)
326 goto done;
327 msg->result = ret;
328 ret = cros_ec_check_result(ec, msg);
329 if (ret)
330 goto done;
331
332 /* Read back args */
333 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args);
334 if (ret < 0)
335 goto done;
336
337 if (args.data_size > msg->insize) {
338 dev_err(ec->dev,
339 "packet too long (%d bytes, expected %d)",
340 args.data_size, msg->insize);
341 ret = -ENOSPC;
342 goto done;
343 }
344
345 /* Start calculating response checksum */
346 sum = msg->command + args.flags + args.command_version + args.data_size;
347
348 /* Read response and update checksum */
349 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size,
350 msg->data);
351 if (ret < 0)
352 goto done;
353 sum += ret;
354
355 /* Verify checksum */
356 if (args.checksum != sum) {
357 dev_err(ec->dev,
358 "bad packet checksum, expected %02x, got %02x\n",
359 args.checksum, sum);
360 ret = -EBADMSG;
361 goto done;
362 }
363
364 /* Return actual amount of data received */
365 ret = args.data_size;
366 done:
367 return ret;
368 }
369
370 /* Returns num bytes read, or negative on error. Doesn't need locking. */
cros_ec_lpc_readmem(struct cros_ec_device * ec,unsigned int offset,unsigned int bytes,void * dest)371 static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset,
372 unsigned int bytes, void *dest)
373 {
374 struct cros_ec_lpc *ec_lpc = ec->priv;
375 int i = offset;
376 char *s = dest;
377 int cnt = 0;
378 int ret;
379
380 if (offset >= EC_MEMMAP_SIZE - bytes)
381 return -EINVAL;
382
383 /* fixed length */
384 if (bytes) {
385 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s);
386 if (ret < 0)
387 return ret;
388 return bytes;
389 }
390
391 /* string */
392 for (; i < EC_MEMMAP_SIZE; i++, s++) {
393 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s);
394 if (ret < 0)
395 return ret;
396 cnt++;
397 if (!*s)
398 break;
399 }
400
401 return cnt;
402 }
403
cros_ec_lpc_acpi_notify(acpi_handle device,u32 value,void * data)404 static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data)
405 {
406 static const char *env[] = { "ERROR=PANIC", NULL };
407 struct cros_ec_device *ec_dev = data;
408 bool ec_has_more_events;
409 int ret;
410
411 ec_dev->last_event_time = cros_ec_get_time_ns();
412
413 if (value == ACPI_NOTIFY_CROS_EC_PANIC) {
414 dev_emerg(ec_dev->dev, "CrOS EC Panic Reported. Shutdown is imminent!");
415 blocking_notifier_call_chain(&ec_dev->panic_notifier, 0, ec_dev);
416 kobject_uevent_env(&ec_dev->dev->kobj, KOBJ_CHANGE, (char **)env);
417 /* Begin orderly shutdown. EC will force reset after a short period. */
418 hw_protection_shutdown("CrOS EC Panic", -1);
419 /* Do not query for other events after a panic is reported */
420 return;
421 }
422
423 if (ec_dev->mkbp_event_supported)
424 do {
425 ret = cros_ec_get_next_event(ec_dev, NULL,
426 &ec_has_more_events);
427 if (ret > 0)
428 blocking_notifier_call_chain(
429 &ec_dev->event_notifier, 0,
430 ec_dev);
431 } while (ec_has_more_events);
432
433 if (value == ACPI_NOTIFY_DEVICE_WAKE)
434 pm_system_wakeup();
435 }
436
cros_ec_lpc_parse_device(acpi_handle handle,u32 level,void * context,void ** retval)437 static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level,
438 void *context, void **retval)
439 {
440 *(struct acpi_device **)context = acpi_fetch_acpi_dev(handle);
441 return AE_CTRL_TERMINATE;
442 }
443
cros_ec_lpc_get_device(const char * id)444 static struct acpi_device *cros_ec_lpc_get_device(const char *id)
445 {
446 struct acpi_device *adev = NULL;
447 acpi_status status = acpi_get_devices(id, cros_ec_lpc_parse_device,
448 &adev, NULL);
449 if (ACPI_FAILURE(status)) {
450 pr_warn(DRV_NAME ": Looking for %s failed\n", id);
451 return NULL;
452 }
453
454 return adev;
455 }
456
cros_ec_lpc_probe(struct platform_device * pdev)457 static int cros_ec_lpc_probe(struct platform_device *pdev)
458 {
459 struct device *dev = &pdev->dev;
460 struct acpi_device *adev;
461 acpi_status status;
462 struct cros_ec_device *ec_dev;
463 struct cros_ec_lpc *ec_lpc;
464 const struct lpc_driver_data *driver_data;
465 u8 buf[2] = {};
466 int irq, ret;
467 u32 quirks;
468
469 ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL);
470 if (!ec_lpc)
471 return -ENOMEM;
472
473 ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP;
474
475 driver_data = platform_get_drvdata(pdev);
476 if (!driver_data)
477 driver_data = acpi_device_get_match_data(dev);
478
479 if (driver_data) {
480 quirks = driver_data->quirks;
481
482 if (quirks)
483 dev_info(dev, "loaded with quirks %8.08x\n", quirks);
484
485 if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY)
486 ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base;
487
488 if (quirks & CROS_EC_LPC_QUIRK_ACPI_ID) {
489 adev = cros_ec_lpc_get_device(driver_data->quirk_acpi_id);
490 if (!adev) {
491 dev_err(dev, "failed to get ACPI device '%s'",
492 driver_data->quirk_acpi_id);
493 return -ENODEV;
494 }
495 ACPI_COMPANION_SET(dev, adev);
496 }
497
498 if (quirks & CROS_EC_LPC_QUIRK_AML_MUTEX) {
499 const char *name
500 = driver_data->quirk_aml_mutex_name;
501 ret = cros_ec_lpc_mec_acpi_mutex(ACPI_COMPANION(dev), name);
502 if (ret) {
503 dev_err(dev, "failed to get AML mutex '%s'", name);
504 return ret;
505 }
506 dev_info(dev, "got AML mutex '%s'", name);
507 }
508 }
509
510 /*
511 * The Framework Laptop (and possibly other non-ChromeOS devices)
512 * only exposes the eight I/O ports that are required for the Microchip EC.
513 * Requesting a larger reservation will fail.
514 */
515 if (!devm_request_region(dev, EC_HOST_CMD_REGION0,
516 EC_HOST_CMD_MEC_REGION_SIZE, dev_name(dev))) {
517 dev_err(dev, "couldn't reserve MEC region\n");
518 return -EBUSY;
519 }
520
521 cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0,
522 EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE);
523
524 /*
525 * Read the mapped ID twice, the first one is assuming the
526 * EC is a Microchip Embedded Controller (MEC) variant, if the
527 * protocol fails, fallback to the non MEC variant and try to
528 * read again the ID.
529 */
530 cros_ec_lpc_ops.read = cros_ec_lpc_mec_read_bytes;
531 cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes;
532 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf);
533 if (ret < 0)
534 return ret;
535 if (buf[0] != 'E' || buf[1] != 'C') {
536 if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE,
537 dev_name(dev))) {
538 dev_err(dev, "couldn't reserve memmap region\n");
539 return -EBUSY;
540 }
541
542 /* Re-assign read/write operations for the non MEC variant */
543 cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes;
544 cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes;
545 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2,
546 buf);
547 if (ret < 0)
548 return ret;
549 if (buf[0] != 'E' || buf[1] != 'C') {
550 dev_err(dev, "EC ID not detected\n");
551 return -ENODEV;
552 }
553
554 /* Reserve the remaining I/O ports required by the non-MEC protocol. */
555 if (!devm_request_region(dev, EC_HOST_CMD_REGION0 + EC_HOST_CMD_MEC_REGION_SIZE,
556 EC_HOST_CMD_REGION_SIZE - EC_HOST_CMD_MEC_REGION_SIZE,
557 dev_name(dev))) {
558 dev_err(dev, "couldn't reserve remainder of region0\n");
559 return -EBUSY;
560 }
561 if (!devm_request_region(dev, EC_HOST_CMD_REGION1,
562 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) {
563 dev_err(dev, "couldn't reserve region1\n");
564 return -EBUSY;
565 }
566 }
567
568 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
569 if (!ec_dev)
570 return -ENOMEM;
571
572 platform_set_drvdata(pdev, ec_dev);
573 ec_dev->dev = dev;
574 ec_dev->phys_name = dev_name(dev);
575 ec_dev->cmd_xfer = cros_ec_cmd_xfer_lpc;
576 ec_dev->pkt_xfer = cros_ec_pkt_xfer_lpc;
577 ec_dev->cmd_readmem = cros_ec_lpc_readmem;
578 ec_dev->din_size = sizeof(struct ec_host_response) +
579 sizeof(struct ec_response_get_protocol_info);
580 ec_dev->dout_size = sizeof(struct ec_host_request);
581 ec_dev->priv = ec_lpc;
582
583 /*
584 * Some boards do not have an IRQ allotted for cros_ec_lpc,
585 * which makes ENXIO an expected (and safe) scenario.
586 */
587 irq = platform_get_irq_optional(pdev, 0);
588 if (irq > 0)
589 ec_dev->irq = irq;
590 else if (irq != -ENXIO) {
591 dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq);
592 return irq;
593 }
594
595 ret = cros_ec_register(ec_dev);
596 if (ret) {
597 dev_err(dev, "couldn't register ec_dev (%d)\n", ret);
598 return ret;
599 }
600
601 /*
602 * Connect a notify handler to process MKBP messages if we have a
603 * companion ACPI device.
604 */
605 adev = ACPI_COMPANION(dev);
606 if (adev) {
607 status = acpi_install_notify_handler(adev->handle,
608 ACPI_ALL_NOTIFY,
609 cros_ec_lpc_acpi_notify,
610 ec_dev);
611 if (ACPI_FAILURE(status))
612 dev_warn(dev, "Failed to register notifier %08x\n",
613 status);
614 }
615
616 return 0;
617 }
618
cros_ec_lpc_remove(struct platform_device * pdev)619 static void cros_ec_lpc_remove(struct platform_device *pdev)
620 {
621 struct cros_ec_device *ec_dev = platform_get_drvdata(pdev);
622 struct acpi_device *adev;
623
624 adev = ACPI_COMPANION(&pdev->dev);
625 if (adev)
626 acpi_remove_notify_handler(adev->handle, ACPI_ALL_NOTIFY,
627 cros_ec_lpc_acpi_notify);
628
629 cros_ec_unregister(ec_dev);
630 }
631
632 static const struct lpc_driver_data framework_laptop_npcx_lpc_driver_data __initconst = {
633 .quirks = CROS_EC_LPC_QUIRK_REMAP_MEMORY,
634 .quirk_mmio_memory_base = 0xE00,
635 };
636
637 static const struct lpc_driver_data framework_laptop_mec_lpc_driver_data __initconst = {
638 .quirks = CROS_EC_LPC_QUIRK_ACPI_ID|CROS_EC_LPC_QUIRK_AML_MUTEX,
639 .quirk_acpi_id = "PNP0C09",
640 .quirk_aml_mutex_name = "ECMT",
641 };
642
643 static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = {
644 { ACPI_DRV_NAME, 0 },
645 { FRMW_ACPI_DRV_NAME, (kernel_ulong_t)&framework_laptop_npcx_lpc_driver_data },
646 { }
647 };
648 MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids);
649
650 static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = {
651 {
652 /*
653 * Today all Chromebooks/boxes ship with Google_* as version and
654 * coreboot as bios vendor. No other systems with this
655 * combination are known to date.
656 */
657 .matches = {
658 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
659 DMI_MATCH(DMI_BIOS_VERSION, "Google_"),
660 },
661 },
662 {
663 /*
664 * If the box is running custom coreboot firmware then the
665 * DMI BIOS version string will not be matched by "Google_",
666 * but the system vendor string will still be matched by
667 * "GOOGLE".
668 */
669 .matches = {
670 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
671 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
672 },
673 },
674 {
675 /* x86-link, the Chromebook Pixel. */
676 .matches = {
677 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
678 DMI_MATCH(DMI_PRODUCT_NAME, "Link"),
679 },
680 },
681 {
682 /* x86-samus, the Chromebook Pixel 2. */
683 .matches = {
684 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
685 DMI_MATCH(DMI_PRODUCT_NAME, "Samus"),
686 },
687 },
688 {
689 /* x86-peppy, the Acer C720 Chromebook. */
690 .matches = {
691 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
692 DMI_MATCH(DMI_PRODUCT_NAME, "Peppy"),
693 },
694 },
695 {
696 /* x86-glimmer, the Lenovo Thinkpad Yoga 11e. */
697 .matches = {
698 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
699 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"),
700 },
701 },
702 /* A small number of non-Chromebook/box machines also use the ChromeOS EC */
703 {
704 /* Framework Laptop (11th Gen Intel Core) */
705 .matches = {
706 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
707 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop"),
708 },
709 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data,
710 },
711 {
712 /* Framework Laptop (12th Gen Intel Core) */
713 .matches = {
714 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
715 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop (12th Gen Intel Core)"),
716 },
717 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data,
718 },
719 {
720 /* Framework Laptop (13th Gen Intel Core) */
721 .matches = {
722 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
723 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop (13th Gen Intel Core)"),
724 },
725 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data,
726 },
727 {
728 /*
729 * All remaining Framework Laptop models (13 AMD Ryzen, 16 AMD
730 * Ryzen, Intel Core Ultra)
731 */
732 .matches = {
733 DMI_MATCH(DMI_SYS_VENDOR, "Framework"),
734 DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"),
735 },
736 .driver_data = (void *)&framework_laptop_npcx_lpc_driver_data,
737 },
738 { /* sentinel */ }
739 };
740 MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table);
741
742 #ifdef CONFIG_PM_SLEEP
cros_ec_lpc_prepare(struct device * dev)743 static int cros_ec_lpc_prepare(struct device *dev)
744 {
745 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
746 return cros_ec_suspend_prepare(ec_dev);
747 }
748
cros_ec_lpc_complete(struct device * dev)749 static void cros_ec_lpc_complete(struct device *dev)
750 {
751 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
752 cros_ec_resume_complete(ec_dev);
753 }
754
cros_ec_lpc_suspend_late(struct device * dev)755 static int cros_ec_lpc_suspend_late(struct device *dev)
756 {
757 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
758
759 return cros_ec_suspend_late(ec_dev);
760 }
761
cros_ec_lpc_resume_early(struct device * dev)762 static int cros_ec_lpc_resume_early(struct device *dev)
763 {
764 struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
765
766 return cros_ec_resume_early(ec_dev);
767 }
768 #endif
769
770 static const struct dev_pm_ops cros_ec_lpc_pm_ops = {
771 #ifdef CONFIG_PM_SLEEP
772 .prepare = cros_ec_lpc_prepare,
773 .complete = cros_ec_lpc_complete,
774 #endif
775 SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend_late, cros_ec_lpc_resume_early)
776 };
777
778 static struct platform_driver cros_ec_lpc_driver = {
779 .driver = {
780 .name = DRV_NAME,
781 .acpi_match_table = cros_ec_lpc_acpi_device_ids,
782 .pm = &cros_ec_lpc_pm_ops,
783 /*
784 * ACPI child devices may probe before us, and they racily
785 * check our drvdata pointer. Force synchronous probe until
786 * those races are resolved.
787 */
788 .probe_type = PROBE_FORCE_SYNCHRONOUS,
789 },
790 .probe = cros_ec_lpc_probe,
791 .remove_new = cros_ec_lpc_remove,
792 };
793
794 static struct platform_device cros_ec_lpc_device = {
795 .name = DRV_NAME
796 };
797
cros_ec_lpc_init(void)798 static int __init cros_ec_lpc_init(void)
799 {
800 int ret;
801 const struct dmi_system_id *dmi_match;
802
803 cros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME) ||
804 !!cros_ec_lpc_get_device(FRMW_ACPI_DRV_NAME);
805
806 dmi_match = dmi_first_match(cros_ec_lpc_dmi_table);
807
808 if (!cros_ec_lpc_acpi_device_found && !dmi_match) {
809 pr_err(DRV_NAME ": unsupported system.\n");
810 return -ENODEV;
811 }
812
813 /* Register the driver */
814 ret = platform_driver_register(&cros_ec_lpc_driver);
815 if (ret) {
816 pr_err(DRV_NAME ": can't register driver: %d\n", ret);
817 return ret;
818 }
819
820 if (!cros_ec_lpc_acpi_device_found) {
821 /* Pass the DMI match's driver data down to the platform device */
822 platform_set_drvdata(&cros_ec_lpc_device, dmi_match->driver_data);
823
824 /* Register the device, and it'll get hooked up automatically */
825 ret = platform_device_register(&cros_ec_lpc_device);
826 if (ret) {
827 pr_err(DRV_NAME ": can't register device: %d\n", ret);
828 platform_driver_unregister(&cros_ec_lpc_driver);
829 }
830 }
831
832 return ret;
833 }
834
cros_ec_lpc_exit(void)835 static void __exit cros_ec_lpc_exit(void)
836 {
837 if (!cros_ec_lpc_acpi_device_found)
838 platform_device_unregister(&cros_ec_lpc_device);
839 platform_driver_unregister(&cros_ec_lpc_driver);
840 }
841
842 module_init(cros_ec_lpc_init);
843 module_exit(cros_ec_lpc_exit);
844
845 MODULE_LICENSE("GPL");
846 MODULE_DESCRIPTION("ChromeOS EC LPC driver");
847