1 // SPDX-License-Identifier: GPL-2.0-only OR Linux-OpenIB
2 /*
3 * Mellanox BlueField Performance Monitoring Counters driver
4 *
5 * This driver provides a sysfs interface for monitoring
6 * performance statistics in BlueField SoC.
7 *
8 * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/arm-smccc.h>
13 #include <linux/bitfield.h>
14 #include <linux/errno.h>
15 #include <linux/hwmon.h>
16 #include <linux/platform_device.h>
17 #include <linux/string.h>
18 #include <linux/string_helpers.h>
19 #include <uapi/linux/psci.h>
20
21 #define MLXBF_PMC_WRITE_REG_32 0x82000009
22 #define MLXBF_PMC_READ_REG_32 0x8200000A
23 #define MLXBF_PMC_WRITE_REG_64 0x8200000B
24 #define MLXBF_PMC_READ_REG_64 0x8200000C
25 #define MLXBF_PMC_SIP_SVC_UID 0x8200ff01
26 #define MLXBF_PMC_SIP_SVC_VERSION 0x8200ff03
27 #define MLXBF_PMC_SVC_REQ_MAJOR 0
28 #define MLXBF_PMC_SVC_MIN_MINOR 3
29
30 #define MLXBF_PMC_SMCCC_ACCESS_VIOLATION -4
31
32 #define MLXBF_PMC_EVENT_SET_BF1 0
33 #define MLXBF_PMC_EVENT_SET_BF2 1
34 #define MLXBF_PMC_EVENT_SET_BF3 2
35 #define MLXBF_PMC_EVENT_INFO_LEN 100
36
37 #define MLXBF_PMC_MAX_BLOCKS 30
38 #define MLXBF_PMC_MAX_ATTRS 70
39 #define MLXBF_PMC_INFO_SZ 4
40 #define MLXBF_PMC_REG_SIZE 8
41 #define MLXBF_PMC_L3C_REG_SIZE 4
42
43 #define MLXBF_PMC_TYPE_CRSPACE 2
44 #define MLXBF_PMC_TYPE_COUNTER 1
45 #define MLXBF_PMC_TYPE_REGISTER 0
46
47 #define MLXBF_PMC_PERFCTL 0
48 #define MLXBF_PMC_PERFEVT 1
49 #define MLXBF_PMC_PERFACC0 4
50
51 #define MLXBF_PMC_PERFMON_CONFIG_WR_R_B BIT(0)
52 #define MLXBF_PMC_PERFMON_CONFIG_STROBE BIT(1)
53 #define MLXBF_PMC_PERFMON_CONFIG_ADDR GENMASK_ULL(4, 2)
54 #define MLXBF_PMC_PERFMON_CONFIG_WDATA GENMASK_ULL(60, 5)
55
56 #define MLXBF_PMC_PERFCTL_FM0 GENMASK_ULL(18, 16)
57 #define MLXBF_PMC_PERFCTL_MS0 GENMASK_ULL(21, 20)
58 #define MLXBF_PMC_PERFCTL_ACCM0 GENMASK_ULL(26, 24)
59 #define MLXBF_PMC_PERFCTL_AD0 BIT(27)
60 #define MLXBF_PMC_PERFCTL_ETRIG0 GENMASK_ULL(29, 28)
61 #define MLXBF_PMC_PERFCTL_EB0 BIT(30)
62 #define MLXBF_PMC_PERFCTL_EN0 BIT(31)
63
64 #define MLXBF_PMC_PERFEVT_EVTSEL GENMASK_ULL(31, 24)
65
66 #define MLXBF_PMC_L3C_PERF_CNT_CFG 0x0
67 #define MLXBF_PMC_L3C_PERF_CNT_SEL 0x10
68 #define MLXBF_PMC_L3C_PERF_CNT_SEL_1 0x14
69 #define MLXBF_PMC_L3C_PERF_CNT_LOW 0x40
70 #define MLXBF_PMC_L3C_PERF_CNT_HIGH 0x60
71
72 #define MLXBF_PMC_L3C_PERF_CNT_CFG_EN BIT(0)
73 #define MLXBF_PMC_L3C_PERF_CNT_CFG_RST BIT(1)
74 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0 GENMASK(5, 0)
75 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1 GENMASK(13, 8)
76 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2 GENMASK(21, 16)
77 #define MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3 GENMASK(29, 24)
78
79 #define MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4 GENMASK(5, 0)
80
81 #define MLXBF_PMC_L3C_PERF_CNT_LOW_VAL GENMASK(31, 0)
82 #define MLXBF_PMC_L3C_PERF_CNT_HIGH_VAL GENMASK(24, 0)
83
84 #define MLXBF_PMC_CRSPACE_PERFMON_REG0 0x0
85 #define MLXBF_PMC_CRSPACE_PERFSEL_SZ 4
86 #define MLXBF_PMC_CRSPACE_PERFSEL0 GENMASK(23, 16)
87 #define MLXBF_PMC_CRSPACE_PERFSEL1 GENMASK(7, 0)
88 #define MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ 0x2
89 #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ)
90 #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30)
91 #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28)
92 #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc)
93
94 /**
95 * struct mlxbf_pmc_attribute - Structure to hold attribute and block info
96 * for each sysfs entry
97 * @dev_attr: Device attribute struct
98 * @index: index to identify counter number within a block
99 * @nr: block number to which the sysfs belongs
100 */
101 struct mlxbf_pmc_attribute {
102 struct device_attribute dev_attr;
103 unsigned int index;
104 unsigned int nr;
105 };
106
107 /**
108 * struct mlxbf_pmc_block_info - Structure to hold info for each HW block
109 *
110 * @mmio_base: The VA at which the PMC block is mapped
111 * @blk_size: Size of each mapped region
112 * @counters: Number of counters in the block
113 * @type: Type of counters in the block
114 * @attr_counter: Attributes for "counter" sysfs files
115 * @attr_event: Attributes for "event" sysfs files
116 * @attr_event_list: Attributes for "event_list" sysfs files
117 * @attr_enable: Attributes for "enable" sysfs files
118 * @block_attr: All attributes needed for the block
119 * @block_attr_grp: Attribute group for the block
120 */
121 struct mlxbf_pmc_block_info {
122 void __iomem *mmio_base;
123 size_t blk_size;
124 size_t counters;
125 unsigned int type;
126 struct mlxbf_pmc_attribute *attr_counter;
127 struct mlxbf_pmc_attribute *attr_event;
128 struct mlxbf_pmc_attribute attr_event_list;
129 struct mlxbf_pmc_attribute attr_enable;
130 struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS];
131 struct attribute_group block_attr_grp;
132 };
133
134 /**
135 * struct mlxbf_pmc_context - Structure to hold PMC context info
136 *
137 * @pdev: The kernel structure representing the device
138 * @total_blocks: Total number of blocks
139 * @tile_count: Number of tiles in the system
140 * @llt_enable: Info on enabled LLTs
141 * @mss_enable: Info on enabled MSSs
142 * @group_num: Group number assigned to each valid block
143 * @hwmon_dev: Hwmon device for bfperf
144 * @block_name: Block name
145 * @block: Block info
146 * @groups: Attribute groups from each block
147 * @svc_sreg_support: Whether SMCs are used to access performance registers
148 * @sreg_tbl_perf: Secure register access table number
149 * @event_set: Event set to use
150 */
151 struct mlxbf_pmc_context {
152 struct platform_device *pdev;
153 u32 total_blocks;
154 u32 tile_count;
155 u8 llt_enable;
156 u8 mss_enable;
157 u32 group_num;
158 struct device *hwmon_dev;
159 const char *block_name[MLXBF_PMC_MAX_BLOCKS];
160 struct mlxbf_pmc_block_info block[MLXBF_PMC_MAX_BLOCKS];
161 const struct attribute_group *groups[MLXBF_PMC_MAX_BLOCKS];
162 bool svc_sreg_support;
163 u32 sreg_tbl_perf;
164 unsigned int event_set;
165 };
166
167 /**
168 * struct mlxbf_pmc_events - Structure to hold supported events for each block
169 * @evt_num: Event number used to program counters
170 * @evt_name: Name of the event
171 */
172 struct mlxbf_pmc_events {
173 u32 evt_num;
174 char *evt_name;
175 };
176
177 static const struct mlxbf_pmc_events mlxbf_pmc_pcie_events[] = {
178 { 0x0, "IN_P_PKT_CNT" },
179 { 0x10, "IN_NP_PKT_CNT" },
180 { 0x18, "IN_C_PKT_CNT" },
181 { 0x20, "OUT_P_PKT_CNT" },
182 { 0x28, "OUT_NP_PKT_CNT" },
183 { 0x30, "OUT_C_PKT_CNT" },
184 { 0x38, "IN_P_BYTE_CNT" },
185 { 0x40, "IN_NP_BYTE_CNT" },
186 { 0x48, "IN_C_BYTE_CNT" },
187 { 0x50, "OUT_P_BYTE_CNT" },
188 { 0x58, "OUT_NP_BYTE_CNT" },
189 { 0x60, "OUT_C_BYTE_CNT" },
190 };
191
192 static const struct mlxbf_pmc_events mlxbf_pmc_smgen_events[] = {
193 { 0x0, "AW_REQ" },
194 { 0x1, "AW_BEATS" },
195 { 0x2, "AW_TRANS" },
196 { 0x3, "AW_RESP" },
197 { 0x4, "AW_STL" },
198 { 0x5, "AW_LAT" },
199 { 0x6, "AW_REQ_TBU" },
200 { 0x8, "AR_REQ" },
201 { 0x9, "AR_BEATS" },
202 { 0xa, "AR_TRANS" },
203 { 0xb, "AR_STL" },
204 { 0xc, "AR_LAT" },
205 { 0xd, "AR_REQ_TBU" },
206 { 0xe, "TBU_MISS" },
207 { 0xf, "TX_DAT_AF" },
208 { 0x10, "RX_DAT_AF" },
209 { 0x11, "RETRYQ_CRED" },
210 };
211
212 static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_1[] = {
213 { 0x0, "DISABLE" },
214 { 0xa0, "TPIO_DATA_BEAT" },
215 { 0xa1, "TDMA_DATA_BEAT" },
216 { 0xa2, "MAP_DATA_BEAT" },
217 { 0xa3, "TXMSG_DATA_BEAT" },
218 { 0xa4, "TPIO_DATA_PACKET" },
219 { 0xa5, "TDMA_DATA_PACKET" },
220 { 0xa6, "MAP_DATA_PACKET" },
221 { 0xa7, "TXMSG_DATA_PACKET" },
222 { 0xa8, "TDMA_RT_AF" },
223 { 0xa9, "TDMA_PBUF_MAC_AF" },
224 { 0xaa, "TRIO_MAP_WRQ_BUF_EMPTY" },
225 { 0xab, "TRIO_MAP_CPL_BUF_EMPTY" },
226 { 0xac, "TRIO_MAP_RDQ0_BUF_EMPTY" },
227 { 0xad, "TRIO_MAP_RDQ1_BUF_EMPTY" },
228 { 0xae, "TRIO_MAP_RDQ2_BUF_EMPTY" },
229 { 0xaf, "TRIO_MAP_RDQ3_BUF_EMPTY" },
230 { 0xb0, "TRIO_MAP_RDQ4_BUF_EMPTY" },
231 { 0xb1, "TRIO_MAP_RDQ5_BUF_EMPTY" },
232 { 0xb2, "TRIO_MAP_RDQ6_BUF_EMPTY" },
233 { 0xb3, "TRIO_MAP_RDQ7_BUF_EMPTY" },
234 };
235
236 static const struct mlxbf_pmc_events mlxbf_pmc_trio_events_2[] = {
237 { 0x0, "DISABLE" },
238 { 0xa0, "TPIO_DATA_BEAT" },
239 { 0xa1, "TDMA_DATA_BEAT" },
240 { 0xa2, "MAP_DATA_BEAT" },
241 { 0xa3, "TXMSG_DATA_BEAT" },
242 { 0xa4, "TPIO_DATA_PACKET" },
243 { 0xa5, "TDMA_DATA_PACKET" },
244 { 0xa6, "MAP_DATA_PACKET" },
245 { 0xa7, "TXMSG_DATA_PACKET" },
246 { 0xa8, "TDMA_RT_AF" },
247 { 0xa9, "TDMA_PBUF_MAC_AF" },
248 { 0xaa, "TRIO_MAP_WRQ_BUF_EMPTY" },
249 { 0xab, "TRIO_MAP_CPL_BUF_EMPTY" },
250 { 0xac, "TRIO_MAP_RDQ0_BUF_EMPTY" },
251 { 0xad, "TRIO_MAP_RDQ1_BUF_EMPTY" },
252 { 0xae, "TRIO_MAP_RDQ2_BUF_EMPTY" },
253 { 0xaf, "TRIO_MAP_RDQ3_BUF_EMPTY" },
254 { 0xb0, "TRIO_MAP_RDQ4_BUF_EMPTY" },
255 { 0xb1, "TRIO_MAP_RDQ5_BUF_EMPTY" },
256 { 0xb2, "TRIO_MAP_RDQ6_BUF_EMPTY" },
257 { 0xb3, "TRIO_MAP_RDQ7_BUF_EMPTY" },
258 { 0xb4, "TRIO_RING_TX_FLIT_CH0" },
259 { 0xb5, "TRIO_RING_TX_FLIT_CH1" },
260 { 0xb6, "TRIO_RING_TX_FLIT_CH2" },
261 { 0xb7, "TRIO_RING_TX_FLIT_CH3" },
262 { 0xb8, "TRIO_RING_TX_FLIT_CH4" },
263 { 0xb9, "TRIO_RING_RX_FLIT_CH0" },
264 { 0xba, "TRIO_RING_RX_FLIT_CH1" },
265 { 0xbb, "TRIO_RING_RX_FLIT_CH2" },
266 { 0xbc, "TRIO_RING_RX_FLIT_CH3" },
267 };
268
269 static const struct mlxbf_pmc_events mlxbf_pmc_ecc_events[] = {
270 { 0x0, "DISABLE" },
271 { 0x100, "ECC_SINGLE_ERROR_CNT" },
272 { 0x104, "ECC_DOUBLE_ERROR_CNT" },
273 { 0x114, "SERR_INJ" },
274 { 0x118, "DERR_INJ" },
275 { 0x124, "ECC_SINGLE_ERROR_0" },
276 { 0x164, "ECC_DOUBLE_ERROR_0" },
277 { 0x340, "DRAM_ECC_COUNT" },
278 { 0x344, "DRAM_ECC_INJECT" },
279 { 0x348, "DRAM_ECC_ERROR" },
280 };
281
282 static const struct mlxbf_pmc_events mlxbf_pmc_mss_events_1[] = {
283 { 0x0, "DISABLE" },
284 { 0xc0, "RXREQ_MSS" },
285 { 0xc1, "RXDAT_MSS" },
286 { 0xc2, "TXRSP_MSS" },
287 { 0xc3, "TXDAT_MSS" },
288 };
289
290 static const struct mlxbf_pmc_events mlxbf_pmc_mss_events_3[] = {
291 {0, "SKYLIB_CDN_TX_FLITS"},
292 {1, "SKYLIB_DDN_TX_FLITS"},
293 {2, "SKYLIB_NDN_TX_FLITS"},
294 {3, "SKYLIB_SDN_TX_FLITS"},
295 {4, "SKYLIB_UDN_TX_FLITS"},
296 {5, "SKYLIB_CDN_RX_FLITS"},
297 {6, "SKYLIB_DDN_RX_FLITS"},
298 {7, "SKYLIB_NDN_RX_FLITS"},
299 {8, "SKYLIB_SDN_RX_FLITS"},
300 {9, "SKYLIB_UDN_RX_FLITS"},
301 {10, "SKYLIB_CDN_TX_STALL"},
302 {11, "SKYLIB_DDN_TX_STALL"},
303 {12, "SKYLIB_NDN_TX_STALL"},
304 {13, "SKYLIB_SDN_TX_STALL"},
305 {14, "SKYLIB_UDN_TX_STALL"},
306 {15, "SKYLIB_CDN_RX_STALL"},
307 {16, "SKYLIB_DDN_RX_STALL"},
308 {17, "SKYLIB_NDN_RX_STALL"},
309 {18, "SKYLIB_SDN_RX_STALL"},
310 {19, "SKYLIB_UDN_RX_STALL"},
311 {20, "SKYLIB_CHI_REQ0_TX_FLITS"},
312 {21, "SKYLIB_CHI_DATA0_TX_FLITS"},
313 {22, "SKYLIB_CHI_RESP0_TX_FLITS"},
314 {23, "SKYLIB_CHI_SNP0_TX_FLITS"},
315 {24, "SKYLIB_CHI_REQ1_TX_FLITS"},
316 {25, "SKYLIB_CHI_DATA1_TX_FLITS"},
317 {26, "SKYLIB_CHI_RESP1_TX_FLITS"},
318 {27, "SKYLIB_CHI_SNP1_TX_FLITS"},
319 {28, "SKYLIB_CHI_REQ2_TX_FLITS"},
320 {29, "SKYLIB_CHI_DATA2_TX_FLITS"},
321 {30, "SKYLIB_CHI_RESP2_TX_FLITS"},
322 {31, "SKYLIB_CHI_SNP2_TX_FLITS"},
323 {32, "SKYLIB_CHI_REQ3_TX_FLITS"},
324 {33, "SKYLIB_CHI_DATA3_TX_FLITS"},
325 {34, "SKYLIB_CHI_RESP3_TX_FLITS"},
326 {35, "SKYLIB_CHI_SNP3_TX_FLITS"},
327 {36, "SKYLIB_TLP_REQ_TX_FLITS"},
328 {37, "SKYLIB_TLP_RESP_TX_FLITS"},
329 {38, "SKYLIB_TLP_META_TX_FLITS"},
330 {39, "SKYLIB_AXIS_DATA_TX_FLITS"},
331 {40, "SKYLIB_AXIS_CRED_TX_FLITS"},
332 {41, "SKYLIB_APB_TX_FLITS"},
333 {42, "SKYLIB_VW_TX_FLITS"},
334 {43, "SKYLIB_GGA_MSN_W_TX_FLITS"},
335 {44, "SKYLIB_GGA_MSN_N_TX_FLITS"},
336 {45, "SKYLIB_CR_REQ_TX_FLITS"},
337 {46, "SKYLIB_CR_RESP_TX_FLITS"},
338 {47, "SKYLIB_MSN_PRNF_TX_FLITS"},
339 {48, "SKYLIB_DBG_DATA_TX_FLITS"},
340 {49, "SKYLIB_DBG_CRED_TX_FLITS"},
341 {50, "SKYLIB_CHI_REQ0_RX_FLITS"},
342 {51, "SKYLIB_CHI_DATA0_RX_FLITS"},
343 {52, "SKYLIB_CHI_RESP0_RX_FLITS"},
344 {53, "SKYLIB_CHI_SNP0_RX_FLITS"},
345 {54, "SKYLIB_CHI_REQ1_RX_FLITS"},
346 {55, "SKYLIB_CHI_DATA1_RX_FLITS"},
347 {56, "SKYLIB_CHI_RESP1_RX_FLITS"},
348 {57, "SKYLIB_CHI_SNP1_RX_FLITS"},
349 {58, "SKYLIB_CHI_REQ2_RX_FLITS"},
350 {59, "SKYLIB_CHI_DATA2_RX_FLITS"},
351 {60, "SKYLIB_CHI_RESP2_RX_FLITS"},
352 {61, "SKYLIB_CHI_SNP2_RX_FLITS"},
353 {62, "SKYLIB_CHI_REQ3_RX_FLITS"},
354 {63, "SKYLIB_CHI_DATA3_RX_FLITS"},
355 {64, "SKYLIB_CHI_RESP3_RX_FLITS"},
356 {65, "SKYLIB_CHI_SNP3_RX_FLITS"},
357 {66, "SKYLIB_TLP_REQ_RX_FLITS"},
358 {67, "SKYLIB_TLP_RESP_RX_FLITS"},
359 {68, "SKYLIB_TLP_META_RX_FLITS"},
360 {69, "SKYLIB_AXIS_DATA_RX_FLITS"},
361 {70, "SKYLIB_AXIS_CRED_RX_FLITS"},
362 {71, "SKYLIB_APB_RX_FLITS"},
363 {72, "SKYLIB_VW_RX_FLITS"},
364 {73, "SKYLIB_GGA_MSN_W_RX_FLITS"},
365 {74, "SKYLIB_GGA_MSN_N_RX_FLITS"},
366 {75, "SKYLIB_CR_REQ_RX_FLITS"},
367 {76, "SKYLIB_CR_RESP_RX_FLITS"},
368 {77, "SKYLIB_MSN_PRNF_RX_FLITS"},
369 {78, "SKYLIB_DBG_DATA_RX_FLITS"},
370 {79, "SKYLIB_DBG_CRED_RX_FLITS"},
371 {80, "SKYLIB_CHI_REQ0_TX_STALL"},
372 {81, "SKYLIB_CHI_DATA0_TX_STALL"},
373 {82, "SKYLIB_CHI_RESP0_TX_STALL"},
374 {83, "SKYLIB_CHI_SNP0_TX_STALL"},
375 {84, "SKYLIB_CHI_REQ1_TX_STALL"},
376 {85, "SKYLIB_CHI_DATA1_TX_STALL"},
377 {86, "SKYLIB_CHI_RESP1_TX_STALL"},
378 {87, "SKYLIB_CHI_SNP1_TX_STALL"},
379 {88, "SKYLIB_CHI_REQ2_TX_STALL"},
380 {89, "SKYLIB_CHI_DATA2_TX_STALL"},
381 {90, "SKYLIB_CHI_RESP2_TX_STALL"},
382 {91, "SKYLIB_CHI_SNP2_TX_STALL"},
383 {92, "SKYLIB_CHI_REQ3_TX_STALL"},
384 {93, "SKYLIB_CHI_DATA3_TX_STALL"},
385 {94, "SKYLIB_CHI_RESP3_TX_STALL"},
386 {95, "SKYLIB_CHI_SNP3_TX_STALL"},
387 {96, "SKYLIB_TLP_REQ_TX_STALL"},
388 {97, "SKYLIB_TLP_RESP_TX_STALL"},
389 {98, "SKYLIB_TLP_META_TX_STALL"},
390 {99, "SKYLIB_AXIS_DATA_TX_STALL"},
391 {100, "SKYLIB_AXIS_CRED_TX_STALL"},
392 {101, "SKYLIB_APB_TX_STALL"},
393 {102, "SKYLIB_VW_TX_STALL"},
394 {103, "SKYLIB_GGA_MSN_W_TX_STALL"},
395 {104, "SKYLIB_GGA_MSN_N_TX_STALL"},
396 {105, "SKYLIB_CR_REQ_TX_STALL"},
397 {106, "SKYLIB_CR_RESP_TX_STALL"},
398 {107, "SKYLIB_MSN_PRNF_TX_STALL"},
399 {108, "SKYLIB_DBG_DATA_TX_STALL"},
400 {109, "SKYLIB_DBG_CRED_TX_STALL"},
401 {110, "SKYLIB_CHI_REQ0_RX_STALL"},
402 {111, "SKYLIB_CHI_DATA0_RX_STALL"},
403 {112, "SKYLIB_CHI_RESP0_RX_STALL"},
404 {113, "SKYLIB_CHI_SNP0_RX_STALL"},
405 {114, "SKYLIB_CHI_REQ1_RX_STALL"},
406 {115, "SKYLIB_CHI_DATA1_RX_STALL"},
407 {116, "SKYLIB_CHI_RESP1_RX_STALL"},
408 {117, "SKYLIB_CHI_SNP1_RX_STALL"},
409 {118, "SKYLIB_CHI_REQ2_RX_STALL"},
410 {119, "SKYLIB_CHI_DATA2_RX_STALL"},
411 {120, "SKYLIB_CHI_RESP2_RX_STALL"},
412 {121, "SKYLIB_CHI_SNP2_RX_STALL"},
413 {122, "SKYLIB_CHI_REQ3_RX_STALL"},
414 {123, "SKYLIB_CHI_DATA3_RX_STALL"},
415 {124, "SKYLIB_CHI_RESP3_RX_STALL"},
416 {125, "SKYLIB_CHI_SNP3_RX_STALL"},
417 {126, "SKYLIB_TLP_REQ_RX_STALL"},
418 {127, "SKYLIB_TLP_RESP_RX_STALL"},
419 {128, "SKYLIB_TLP_META_RX_STALL"},
420 {129, "SKYLIB_AXIS_DATA_RX_STALL"},
421 {130, "SKYLIB_AXIS_CRED_RX_STALL"},
422 {131, "SKYLIB_APB_RX_STALL"},
423 {132, "SKYLIB_VW_RX_STALL"},
424 {133, "SKYLIB_GGA_MSN_W_RX_STALL"},
425 {134, "SKYLIB_GGA_MSN_N_RX_STALL"},
426 {135, "SKYLIB_CR_REQ_RX_STALL"},
427 {136, "SKYLIB_CR_RESP_RX_STALL"},
428 {137, "SKYLIB_MSN_PRNF_RX_STALL"},
429 {138, "SKYLIB_DBG_DATA_RX_STALL"},
430 {139, "SKYLIB_DBG_CRED_RX_STALL"},
431 {140, "SKYLIB_CDN_LOOPBACK_FLITS"},
432 {141, "SKYLIB_DDN_LOOPBACK_FLITS"},
433 {142, "SKYLIB_NDN_LOOPBACK_FLITS"},
434 {143, "SKYLIB_SDN_LOOPBACK_FLITS"},
435 {144, "SKYLIB_UDN_LOOPBACK_FLITS"},
436 {145, "HISTOGRAM_HISTOGRAM_BIN0"},
437 {146, "HISTOGRAM_HISTOGRAM_BIN1"},
438 {147, "HISTOGRAM_HISTOGRAM_BIN2"},
439 {148, "HISTOGRAM_HISTOGRAM_BIN3"},
440 {149, "HISTOGRAM_HISTOGRAM_BIN4"},
441 {150, "HISTOGRAM_HISTOGRAM_BIN5"},
442 {151, "HISTOGRAM_HISTOGRAM_BIN6"},
443 {152, "HISTOGRAM_HISTOGRAM_BIN7"},
444 {153, "HISTOGRAM_HISTOGRAM_BIN8"},
445 {154, "HISTOGRAM_HISTOGRAM_BIN9"},
446 };
447
448 static const struct mlxbf_pmc_events mlxbf_pmc_hnf_events[] = {
449 { 0x0, "DISABLE" },
450 { 0x45, "HNF_REQUESTS" },
451 { 0x46, "HNF_REJECTS" },
452 { 0x47, "ALL_BUSY" },
453 { 0x48, "MAF_BUSY" },
454 { 0x49, "MAF_REQUESTS" },
455 { 0x4a, "RNF_REQUESTS" },
456 { 0x4b, "REQUEST_TYPE" },
457 { 0x4c, "MEMORY_READS" },
458 { 0x4d, "MEMORY_WRITES" },
459 { 0x4e, "VICTIM_WRITE" },
460 { 0x4f, "POC_FULL" },
461 { 0x50, "POC_FAIL" },
462 { 0x51, "POC_SUCCESS" },
463 { 0x52, "POC_WRITES" },
464 { 0x53, "POC_READS" },
465 { 0x54, "FORWARD" },
466 { 0x55, "RXREQ_HNF" },
467 { 0x56, "RXRSP_HNF" },
468 { 0x57, "RXDAT_HNF" },
469 { 0x58, "TXREQ_HNF" },
470 { 0x59, "TXRSP_HNF" },
471 { 0x5a, "TXDAT_HNF" },
472 { 0x5b, "TXSNP_HNF" },
473 { 0x5c, "INDEX_MATCH" },
474 { 0x5d, "A72_ACCESS" },
475 { 0x5e, "IO_ACCESS" },
476 { 0x5f, "TSO_WRITE" },
477 { 0x60, "TSO_CONFLICT" },
478 { 0x61, "DIR_HIT" },
479 { 0x62, "HNF_ACCEPTS" },
480 { 0x63, "REQ_BUF_EMPTY" },
481 { 0x64, "REQ_BUF_IDLE_MAF" },
482 { 0x65, "TSO_NOARB" },
483 { 0x66, "TSO_NOARB_CYCLES" },
484 { 0x67, "MSS_NO_CREDIT" },
485 { 0x68, "TXDAT_NO_LCRD" },
486 { 0x69, "TXSNP_NO_LCRD" },
487 { 0x6a, "TXRSP_NO_LCRD" },
488 { 0x6b, "TXREQ_NO_LCRD" },
489 { 0x6c, "TSO_CL_MATCH" },
490 { 0x6d, "MEMORY_READS_BYPASS" },
491 { 0x6e, "TSO_NOARB_TIMEOUT" },
492 { 0x6f, "ALLOCATE" },
493 { 0x70, "VICTIM" },
494 { 0x71, "A72_WRITE" },
495 { 0x72, "A72_READ" },
496 { 0x73, "IO_WRITE" },
497 { 0x74, "IO_READ" },
498 { 0x75, "TSO_REJECT" },
499 { 0x80, "TXREQ_RN" },
500 { 0x81, "TXRSP_RN" },
501 { 0x82, "TXDAT_RN" },
502 { 0x83, "RXSNP_RN" },
503 { 0x84, "RXRSP_RN" },
504 { 0x85, "RXDAT_RN" },
505 };
506
507 static const struct mlxbf_pmc_events mlxbf_pmc_hnfnet_events[] = {
508 { 0x0, "DISABLE" },
509 { 0x12, "CDN_REQ" },
510 { 0x13, "DDN_REQ" },
511 { 0x14, "NDN_REQ" },
512 { 0x15, "CDN_DIAG_N_OUT_OF_CRED" },
513 { 0x16, "CDN_DIAG_S_OUT_OF_CRED" },
514 { 0x17, "CDN_DIAG_E_OUT_OF_CRED" },
515 { 0x18, "CDN_DIAG_W_OUT_OF_CRED" },
516 { 0x19, "CDN_DIAG_C_OUT_OF_CRED" },
517 { 0x1a, "CDN_DIAG_N_EGRESS" },
518 { 0x1b, "CDN_DIAG_S_EGRESS" },
519 { 0x1c, "CDN_DIAG_E_EGRESS" },
520 { 0x1d, "CDN_DIAG_W_EGRESS" },
521 { 0x1e, "CDN_DIAG_C_EGRESS" },
522 { 0x1f, "CDN_DIAG_N_INGRESS" },
523 { 0x20, "CDN_DIAG_S_INGRESS" },
524 { 0x21, "CDN_DIAG_E_INGRESS" },
525 { 0x22, "CDN_DIAG_W_INGRESS" },
526 { 0x23, "CDN_DIAG_C_INGRESS" },
527 { 0x24, "CDN_DIAG_CORE_SENT" },
528 { 0x25, "DDN_DIAG_N_OUT_OF_CRED" },
529 { 0x26, "DDN_DIAG_S_OUT_OF_CRED" },
530 { 0x27, "DDN_DIAG_E_OUT_OF_CRED" },
531 { 0x28, "DDN_DIAG_W_OUT_OF_CRED" },
532 { 0x29, "DDN_DIAG_C_OUT_OF_CRED" },
533 { 0x2a, "DDN_DIAG_N_EGRESS" },
534 { 0x2b, "DDN_DIAG_S_EGRESS" },
535 { 0x2c, "DDN_DIAG_E_EGRESS" },
536 { 0x2d, "DDN_DIAG_W_EGRESS" },
537 { 0x2e, "DDN_DIAG_C_EGRESS" },
538 { 0x2f, "DDN_DIAG_N_INGRESS" },
539 { 0x30, "DDN_DIAG_S_INGRESS" },
540 { 0x31, "DDN_DIAG_E_INGRESS" },
541 { 0x32, "DDN_DIAG_W_INGRESS" },
542 { 0x33, "DDN_DIAG_C_INGRESS" },
543 { 0x34, "DDN_DIAG_CORE_SENT" },
544 { 0x35, "NDN_DIAG_N_OUT_OF_CRED" },
545 { 0x36, "NDN_DIAG_S_OUT_OF_CRED" },
546 { 0x37, "NDN_DIAG_E_OUT_OF_CRED" },
547 { 0x38, "NDN_DIAG_W_OUT_OF_CRED" },
548 { 0x39, "NDN_DIAG_C_OUT_OF_CRED" },
549 { 0x3a, "NDN_DIAG_N_EGRESS" },
550 { 0x3b, "NDN_DIAG_S_EGRESS" },
551 { 0x3c, "NDN_DIAG_E_EGRESS" },
552 { 0x3d, "NDN_DIAG_W_EGRESS" },
553 { 0x3e, "NDN_DIAG_C_EGRESS" },
554 { 0x3f, "NDN_DIAG_N_INGRESS" },
555 { 0x40, "NDN_DIAG_S_INGRESS" },
556 { 0x41, "NDN_DIAG_E_INGRESS" },
557 { 0x42, "NDN_DIAG_W_INGRESS" },
558 { 0x43, "NDN_DIAG_C_INGRESS" },
559 { 0x44, "NDN_DIAG_CORE_SENT" },
560 };
561
562 static const struct mlxbf_pmc_events mlxbf_pmc_l3c_events[] = {
563 { 0x00, "DISABLE" },
564 { 0x01, "CYCLES" },
565 { 0x02, "TOTAL_RD_REQ_IN" },
566 { 0x03, "TOTAL_WR_REQ_IN" },
567 { 0x04, "TOTAL_WR_DBID_ACK" },
568 { 0x05, "TOTAL_WR_DATA_IN" },
569 { 0x06, "TOTAL_WR_COMP" },
570 { 0x07, "TOTAL_RD_DATA_OUT" },
571 { 0x08, "TOTAL_CDN_REQ_IN_BANK0" },
572 { 0x09, "TOTAL_CDN_REQ_IN_BANK1" },
573 { 0x0a, "TOTAL_DDN_REQ_IN_BANK0" },
574 { 0x0b, "TOTAL_DDN_REQ_IN_BANK1" },
575 { 0x0c, "TOTAL_EMEM_RD_RES_IN_BANK0" },
576 { 0x0d, "TOTAL_EMEM_RD_RES_IN_BANK1" },
577 { 0x0e, "TOTAL_CACHE_RD_RES_IN_BANK0" },
578 { 0x0f, "TOTAL_CACHE_RD_RES_IN_BANK1" },
579 { 0x10, "TOTAL_EMEM_RD_REQ_BANK0" },
580 { 0x11, "TOTAL_EMEM_RD_REQ_BANK1" },
581 { 0x12, "TOTAL_EMEM_WR_REQ_BANK0" },
582 { 0x13, "TOTAL_EMEM_WR_REQ_BANK1" },
583 { 0x14, "TOTAL_RD_REQ_OUT" },
584 { 0x15, "TOTAL_WR_REQ_OUT" },
585 { 0x16, "TOTAL_RD_RES_IN" },
586 { 0x17, "HITS_BANK0" },
587 { 0x18, "HITS_BANK1" },
588 { 0x19, "MISSES_BANK0" },
589 { 0x1a, "MISSES_BANK1" },
590 { 0x1b, "ALLOCATIONS_BANK0" },
591 { 0x1c, "ALLOCATIONS_BANK1" },
592 { 0x1d, "EVICTIONS_BANK0" },
593 { 0x1e, "EVICTIONS_BANK1" },
594 { 0x1f, "DBID_REJECT" },
595 { 0x20, "WRDB_REJECT_BANK0" },
596 { 0x21, "WRDB_REJECT_BANK1" },
597 { 0x22, "CMDQ_REJECT_BANK0" },
598 { 0x23, "CMDQ_REJECT_BANK1" },
599 { 0x24, "COB_REJECT_BANK0" },
600 { 0x25, "COB_REJECT_BANK1" },
601 { 0x26, "TRB_REJECT_BANK0" },
602 { 0x27, "TRB_REJECT_BANK1" },
603 { 0x28, "TAG_REJECT_BANK0" },
604 { 0x29, "TAG_REJECT_BANK1" },
605 { 0x2a, "ANY_REJECT_BANK0" },
606 { 0x2b, "ANY_REJECT_BANK1" },
607 };
608
609 static const struct mlxbf_pmc_events mlxbf_pmc_llt_events[] = {
610 {0, "HNF0_CYCLES"},
611 {1, "HNF0_REQS_RECEIVED"},
612 {2, "HNF0_REQS_PROCESSED"},
613 {3, "HNF0_DIR_HIT"},
614 {4, "HNF0_DIR_MISS"},
615 {5, "HNF0_DIR_RD_ALLOC"},
616 {6, "HNF0_DIR_WR_ALLOC"},
617 {7, "HNF0_DIR_VICTIM"},
618 {8, "HNF0_CL_HAZARD"},
619 {9, "HNF0_ALL_HAZARD"},
620 {10, "HNF0_PIPE_STALLS"},
621 {11, "HNF0_MEM_READS"},
622 {12, "HNF0_MEM_WRITES"},
623 {13, "HNF0_MEM_ACCESS"},
624 {14, "HNF0_DCL_READ"},
625 {15, "HNF0_DCL_INVAL"},
626 {16, "HNF0_CHI_RXDAT"},
627 {17, "HNF0_CHI_RXRSP"},
628 {18, "HNF0_CHI_TXDAT"},
629 {19, "HNF0_CHI_TXRSP"},
630 {20, "HNF0_CHI_TXSNP"},
631 {21, "HNF0_DCT_SNP"},
632 {22, "HNF0_SNP_FWD_DATA"},
633 {23, "HNF0_SNP_FWD_RSP"},
634 {24, "HNF0_SNP_RSP"},
635 {25, "HNF0_EXCL_FULL"},
636 {26, "HNF0_EXCL_WRITE_F"},
637 {27, "HNF0_EXCL_WRITE_S"},
638 {28, "HNF0_EXCL_WRITE"},
639 {29, "HNF0_EXCL_READ"},
640 {30, "HNF0_REQ_BUF_EMPTY"},
641 {31, "HNF0_ALL_MAFS_BUSY"},
642 {32, "HNF0_TXDAT_NO_LCRD"},
643 {33, "HNF0_TXSNP_NO_LCRD"},
644 {34, "HNF0_TXRSP_NO_LCRD"},
645 {35, "HNF0_TXREQ_NO_LCRD"},
646 {36, "HNF0_WRITE"},
647 {37, "HNF0_READ"},
648 {38, "HNF0_ACCESS"},
649 {39, "HNF0_MAF_N_BUSY"},
650 {40, "HNF0_MAF_N_REQS"},
651 {41, "HNF0_SEL_OPCODE"},
652 {42, "HNF1_CYCLES"},
653 {43, "HNF1_REQS_RECEIVED"},
654 {44, "HNF1_REQS_PROCESSED"},
655 {45, "HNF1_DIR_HIT"},
656 {46, "HNF1_DIR_MISS"},
657 {47, "HNF1_DIR_RD_ALLOC"},
658 {48, "HNF1_DIR_WR_ALLOC"},
659 {49, "HNF1_DIR_VICTIM"},
660 {50, "HNF1_CL_HAZARD"},
661 {51, "HNF1_ALL_HAZARD"},
662 {52, "HNF1_PIPE_STALLS"},
663 {53, "HNF1_MEM_READS"},
664 {54, "HNF1_MEM_WRITES"},
665 {55, "HNF1_MEM_ACCESS"},
666 {56, "HNF1_DCL_READ"},
667 {57, "HNF1_DCL_INVAL"},
668 {58, "HNF1_CHI_RXDAT"},
669 {59, "HNF1_CHI_RXRSP"},
670 {60, "HNF1_CHI_TXDAT"},
671 {61, "HNF1_CHI_TXRSP"},
672 {62, "HNF1_CHI_TXSNP"},
673 {63, "HNF1_DCT_SNP"},
674 {64, "HNF1_SNP_FWD_DATA"},
675 {65, "HNF1_SNP_FWD_RSP"},
676 {66, "HNF1_SNP_RSP"},
677 {67, "HNF1_EXCL_FULL"},
678 {68, "HNF1_EXCL_WRITE_F"},
679 {69, "HNF1_EXCL_WRITE_S"},
680 {70, "HNF1_EXCL_WRITE"},
681 {71, "HNF1_EXCL_READ"},
682 {72, "HNF1_REQ_BUF_EMPTY"},
683 {73, "HNF1_ALL_MAFS_BUSY"},
684 {74, "HNF1_TXDAT_NO_LCRD"},
685 {75, "HNF1_TXSNP_NO_LCRD"},
686 {76, "HNF1_TXRSP_NO_LCRD"},
687 {77, "HNF1_TXREQ_NO_LCRD"},
688 {78, "HNF1_WRITE"},
689 {79, "HNF1_READ"},
690 {80, "HNF1_ACCESS"},
691 {81, "HNF1_MAF_N_BUSY"},
692 {82, "HNF1_MAF_N_REQS"},
693 {83, "HNF1_SEL_OPCODE"},
694 {84, "GDC_BANK0_RD_REQ"},
695 {85, "GDC_BANK0_WR_REQ"},
696 {86, "GDC_BANK0_ALLOCATE"},
697 {87, "GDC_BANK0_HIT"},
698 {88, "GDC_BANK0_MISS"},
699 {89, "GDC_BANK0_INVALIDATE"},
700 {90, "GDC_BANK0_EVICT"},
701 {91, "GDC_BANK0_RD_RESP"},
702 {92, "GDC_BANK0_WR_ACK"},
703 {93, "GDC_BANK0_SNOOP"},
704 {94, "GDC_BANK0_SNOOP_NORMAL"},
705 {95, "GDC_BANK0_SNOOP_FWD"},
706 {96, "GDC_BANK0_SNOOP_STASH"},
707 {97, "GDC_BANK0_SNOOP_STASH_INDPND_RD"},
708 {98, "GDC_BANK0_FOLLOWER"},
709 {99, "GDC_BANK0_FW"},
710 {100, "GDC_BANK0_HIT_DCL_BOTH"},
711 {101, "GDC_BANK0_HIT_DCL_PARTIAL"},
712 {102, "GDC_BANK0_EVICT_DCL"},
713 {103, "GDC_BANK0_G_RSE_PIPE_CACHE_DATA0"},
714 {104, "GDC_BANK0_G_RSE_PIPE_CACHE_DATA1"},
715 {105, "GDC_BANK0_ARB_STRB"},
716 {106, "GDC_BANK0_ARB_WAIT"},
717 {107, "GDC_BANK0_GGA_STRB"},
718 {108, "GDC_BANK0_GGA_WAIT"},
719 {109, "GDC_BANK0_FW_STRB"},
720 {110, "GDC_BANK0_FW_WAIT"},
721 {111, "GDC_BANK0_SNP_STRB"},
722 {112, "GDC_BANK0_SNP_WAIT"},
723 {113, "GDC_BANK0_MISS_INARB_STRB"},
724 {114, "GDC_BANK0_MISS_INARB_WAIT"},
725 {115, "GDC_BANK0_G_FIFO_FF_GGA_RSP_RD0"},
726 {116, "GDC_BANK0_G_FIFO_FF_GGA_RSP_RD1"},
727 {117, "GDC_BANK0_G_FIFO_FF_GGA_RSP_RD2"},
728 {118, "GDC_BANK0_G_FIFO_FF_GGA_RSP_RD3"},
729 {119, "GDC_BANK0_G_FIFO_FF_GGA_RSP_WR0"},
730 {120, "GDC_BANK0_G_FIFO_FF_GGA_RSP_WR1"},
731 {121, "GDC_BANK0_G_FIFO_FF_GGA_RSP_WR2"},
732 {122, "GDC_BANK0_G_FIFO_FF_GGA_RSP_WR3"},
733 {123, "GDC_BANK1_RD_REQ"},
734 {124, "GDC_BANK1_WR_REQ"},
735 {125, "GDC_BANK1_ALLOCATE"},
736 {126, "GDC_BANK1_HIT"},
737 {127, "GDC_BANK1_MISS"},
738 {128, "GDC_BANK1_INVALIDATE"},
739 {129, "GDC_BANK1_EVICT"},
740 {130, "GDC_BANK1_RD_RESP"},
741 {131, "GDC_BANK1_WR_ACK"},
742 {132, "GDC_BANK1_SNOOP"},
743 {133, "GDC_BANK1_SNOOP_NORMAL"},
744 {134, "GDC_BANK1_SNOOP_FWD"},
745 {135, "GDC_BANK1_SNOOP_STASH"},
746 {136, "GDC_BANK1_SNOOP_STASH_INDPND_RD"},
747 {137, "GDC_BANK1_FOLLOWER"},
748 {138, "GDC_BANK1_FW"},
749 {139, "GDC_BANK1_HIT_DCL_BOTH"},
750 {140, "GDC_BANK1_HIT_DCL_PARTIAL"},
751 {141, "GDC_BANK1_EVICT_DCL"},
752 {142, "GDC_BANK1_G_RSE_PIPE_CACHE_DATA0"},
753 {143, "GDC_BANK1_G_RSE_PIPE_CACHE_DATA1"},
754 {144, "GDC_BANK1_ARB_STRB"},
755 {145, "GDC_BANK1_ARB_WAIT"},
756 {146, "GDC_BANK1_GGA_STRB"},
757 {147, "GDC_BANK1_GGA_WAIT"},
758 {148, "GDC_BANK1_FW_STRB"},
759 {149, "GDC_BANK1_FW_WAIT"},
760 {150, "GDC_BANK1_SNP_STRB"},
761 {151, "GDC_BANK1_SNP_WAIT"},
762 {152, "GDC_BANK1_MISS_INARB_STRB"},
763 {153, "GDC_BANK1_MISS_INARB_WAIT"},
764 {154, "GDC_BANK1_G_FIFO_FF_GGA_RSP_RD0"},
765 {155, "GDC_BANK1_G_FIFO_FF_GGA_RSP_RD1"},
766 {156, "GDC_BANK1_G_FIFO_FF_GGA_RSP_RD2"},
767 {157, "GDC_BANK1_G_FIFO_FF_GGA_RSP_RD3"},
768 {158, "GDC_BANK1_G_FIFO_FF_GGA_RSP_WR0"},
769 {159, "GDC_BANK1_G_FIFO_FF_GGA_RSP_WR1"},
770 {160, "GDC_BANK1_G_FIFO_FF_GGA_RSP_WR2"},
771 {161, "GDC_BANK1_G_FIFO_FF_GGA_RSP_WR3"},
772 {162, "HISTOGRAM_HISTOGRAM_BIN0"},
773 {163, "HISTOGRAM_HISTOGRAM_BIN1"},
774 {164, "HISTOGRAM_HISTOGRAM_BIN2"},
775 {165, "HISTOGRAM_HISTOGRAM_BIN3"},
776 {166, "HISTOGRAM_HISTOGRAM_BIN4"},
777 {167, "HISTOGRAM_HISTOGRAM_BIN5"},
778 {168, "HISTOGRAM_HISTOGRAM_BIN6"},
779 {169, "HISTOGRAM_HISTOGRAM_BIN7"},
780 {170, "HISTOGRAM_HISTOGRAM_BIN8"},
781 {171, "HISTOGRAM_HISTOGRAM_BIN9"},
782 };
783
784 static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = {
785 {0, "GDC_MISS_MACHINE_RD_REQ"},
786 {1, "GDC_MISS_MACHINE_WR_REQ"},
787 {2, "GDC_MISS_MACHINE_SNP_REQ"},
788 {3, "GDC_MISS_MACHINE_EVICT_REQ"},
789 {4, "GDC_MISS_MACHINE_FW_REQ"},
790 {5, "GDC_MISS_MACHINE_RD_RESP"},
791 {6, "GDC_MISS_MACHINE_WR_RESP"},
792 {7, "GDC_MISS_MACHINE_SNP_STASH_DATAPULL_DROP"},
793 {8, "GDC_MISS_MACHINE_SNP_STASH_DATAPULL_DROP_TXDAT"},
794 {9, "GDC_MISS_MACHINE_CHI_TXREQ"},
795 {10, "GDC_MISS_MACHINE_CHI_RXRSP"},
796 {11, "GDC_MISS_MACHINE_CHI_TXDAT"},
797 {12, "GDC_MISS_MACHINE_CHI_RXDAT"},
798 {13, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC0_0"},
799 {14, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC0_1 "},
800 {15, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC0_2"},
801 {16, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC0_3 "},
802 {17, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC1_0 "},
803 {18, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC1_1 "},
804 {19, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC1_2 "},
805 {20, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC1_3 "},
806 {21, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE0_0"},
807 {22, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE0_1"},
808 {23, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE0_2"},
809 {24, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE0_3"},
810 {25, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE1_0 "},
811 {26, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE1_1"},
812 {27, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE1_2"},
813 {28, "GDC_MISS_MACHINE_G_FIFO_FF_EXEC_DONE1_3"},
814 {29, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_0"},
815 {30, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_1"},
816 {31, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_2"},
817 {32, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_3"},
818 {33, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_4"},
819 {34, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_5"},
820 {35, "GDC_MISS_MACHINE_GDC_LINK_LIST_FF_6"},
821 {36, "GDC_MISS_MACHINE_G_RSE_PIPE_TXREQ_0"},
822 {37, "GDC_MISS_MACHINE_G_RSE_PIPE_TXREQ_1"},
823 {38, "GDC_MISS_MACHINE_G_CREDIT_TXREQ_0"},
824 {39, "GDC_MISS_MACHINE_G_CREDIT_TXREQ_1"},
825 {40, "GDC_MISS_MACHINE_G_RSE_PIPE_TXDAT_0"},
826 {41, "GDC_MISS_MACHINE_G_RSE_PIPE_TXDAT_1"},
827 {42, "GDC_MISS_MACHINE_G_CREDIT_TXDAT_0"},
828 {43, "GDC_MISS_MACHINE_G_CREDIT_TXDAT_1"},
829 {44, "GDC_MISS_MACHINE_G_FIFO_FF_COMPACK_0"},
830 {45, "GDC_MISS_MACHINE_G_FIFO_FF_COMPACK_1"},
831 {46, "GDC_MISS_MACHINE_G_FIFO_FF_COMPACK_2"},
832 {47, "GDC_MISS_MACHINE_G_FIFO_FF_COMPACK_3"},
833 {48, "GDC_MISS_MACHINE_G_RSE_PIPE_TXRSP_0"},
834 {49, "GDC_MISS_MACHINE_G_RSE_PIPE_TXRSP_1"},
835 {50, "GDC_MISS_MACHINE_G_CREDIT_TXRSP_0"},
836 {51, "GDC_MISS_MACHINE_G_CREDIT_TXRSP_1"},
837 {52, "GDC_MISS_MACHINE_G_RSE_PIPE_INARB_0"},
838 {53, "GDC_MISS_MACHINE_G_RSE_PIPE_INARB_1"},
839 {54, "GDC_MISS_MACHINE_G_FIFO_FF_SNOOP_IN_0"},
840 {55, "GDC_MISS_MACHINE_G_FIFO_FF_SNOOP_IN_1"},
841 {56, "GDC_MISS_MACHINE_G_FIFO_FF_SNOOP_IN_2"},
842 {57, "GDC_MISS_MACHINE_G_FIFO_FF_SNOOP_IN_3"},
843 {58, "GDC_MISS_MACHINE_G_FIFO_FF_TXRSP_SNOOP_DATAPULL_0"},
844 {59, "GDC_MISS_MACHINE_G_FIFO_FF_TXRSP_SNOOP_DATAPULL_1"},
845 {60, "GDC_MISS_MACHINE_G_FIFO_FF_TXRSP_SNOOP_DATAPULL_2"},
846 {61, "GDC_MISS_MACHINE_G_FIFO_FF_TXRSP_SNOOP_DATAPULL_3"},
847 {62, "GDC_MISS_MACHINE_G_FIFO_FF_TXDAT_SNOOP_DATAPULL_4"},
848 {63, "GDC_MISS_MACHINE_G_FIFO_FF_TXDAT_SNOOP_DATAPULL_5"},
849 {64, "GDC_MISS_MACHINE_G_FIFO_FF_TXDAT_SNOOP_DATAPULL_6"},
850 {65, "GDC_MISS_MACHINE_G_FIFO_FF_TXDAT_SNOOP_DATAPULL_7"},
851 {66, "HISTOGRAM_HISTOGRAM_BIN0"},
852 {67, "HISTOGRAM_HISTOGRAM_BIN1"},
853 {68, "HISTOGRAM_HISTOGRAM_BIN2"},
854 {69, "HISTOGRAM_HISTOGRAM_BIN3"},
855 {70, "HISTOGRAM_HISTOGRAM_BIN4"},
856 {71, "HISTOGRAM_HISTOGRAM_BIN5"},
857 {72, "HISTOGRAM_HISTOGRAM_BIN6"},
858 {73, "HISTOGRAM_HISTOGRAM_BIN7"},
859 {74, "HISTOGRAM_HISTOGRAM_BIN8"},
860 {75, "HISTOGRAM_HISTOGRAM_BIN9"},
861 };
862
863 static struct mlxbf_pmc_context *pmc;
864
865 /* UUID used to probe ATF service. */
866 static const char *mlxbf_pmc_svc_uuid_str = "89c036b4-e7d7-11e6-8797-001aca00bfc4";
867
868 /* Calls an SMC to access a performance register */
mlxbf_pmc_secure_read(void __iomem * addr,u32 command,u64 * result)869 static int mlxbf_pmc_secure_read(void __iomem *addr, u32 command, u64 *result)
870 {
871 struct arm_smccc_res res;
872 int status, err = 0;
873
874 arm_smccc_smc(command, pmc->sreg_tbl_perf, (uintptr_t)addr, 0, 0, 0, 0,
875 0, &res);
876
877 status = res.a0;
878
879 switch (status) {
880 case PSCI_RET_NOT_SUPPORTED:
881 err = -EINVAL;
882 break;
883 case MLXBF_PMC_SMCCC_ACCESS_VIOLATION:
884 err = -EACCES;
885 break;
886 default:
887 *result = res.a1;
888 break;
889 }
890
891 return err;
892 }
893
894 /* Read from a performance counter */
mlxbf_pmc_read(void __iomem * addr,u32 command,u64 * result)895 static int mlxbf_pmc_read(void __iomem *addr, u32 command, u64 *result)
896 {
897 if (pmc->svc_sreg_support)
898 return mlxbf_pmc_secure_read(addr, command, result);
899
900 if (command == MLXBF_PMC_READ_REG_32)
901 *result = readl(addr);
902 else
903 *result = readq(addr);
904
905 return 0;
906 }
907
908 /* Convenience function for 32-bit reads */
mlxbf_pmc_readl(void __iomem * addr,u32 * result)909 static int mlxbf_pmc_readl(void __iomem *addr, u32 *result)
910 {
911 u64 read_out;
912 int status;
913
914 status = mlxbf_pmc_read(addr, MLXBF_PMC_READ_REG_32, &read_out);
915 if (status)
916 return status;
917 *result = (u32)read_out;
918
919 return 0;
920 }
921
922 /* Calls an SMC to access a performance register */
mlxbf_pmc_secure_write(void __iomem * addr,u32 command,u64 value)923 static int mlxbf_pmc_secure_write(void __iomem *addr, u32 command, u64 value)
924 {
925 struct arm_smccc_res res;
926 int status, err = 0;
927
928 arm_smccc_smc(command, pmc->sreg_tbl_perf, value, (uintptr_t)addr, 0, 0,
929 0, 0, &res);
930
931 status = res.a0;
932
933 switch (status) {
934 case PSCI_RET_NOT_SUPPORTED:
935 err = -EINVAL;
936 break;
937 case MLXBF_PMC_SMCCC_ACCESS_VIOLATION:
938 err = -EACCES;
939 break;
940 }
941
942 return err;
943 }
944
945 /* Write to a performance counter */
mlxbf_pmc_write(void __iomem * addr,int command,u64 value)946 static int mlxbf_pmc_write(void __iomem *addr, int command, u64 value)
947 {
948 if (pmc->svc_sreg_support)
949 return mlxbf_pmc_secure_write(addr, command, value);
950
951 if (command == MLXBF_PMC_WRITE_REG_32)
952 writel(value, addr);
953 else
954 writeq(value, addr);
955
956 return 0;
957 }
958
959 /* Check if the register offset is within the mapped region for the block */
mlxbf_pmc_valid_range(unsigned int blk_num,u32 offset)960 static bool mlxbf_pmc_valid_range(unsigned int blk_num, u32 offset)
961 {
962 if ((offset >= 0) && !(offset % MLXBF_PMC_REG_SIZE) &&
963 (offset + MLXBF_PMC_REG_SIZE <= pmc->block[blk_num].blk_size))
964 return true; /* inside the mapped PMC space */
965
966 return false;
967 }
968
969 /* Get the event list corresponding to a certain block */
mlxbf_pmc_event_list(const char * blk,size_t * psize)970 static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size_t *psize)
971 {
972 const struct mlxbf_pmc_events *events;
973 size_t size;
974
975 if (strstr(blk, "tilenet")) {
976 events = mlxbf_pmc_hnfnet_events;
977 size = ARRAY_SIZE(mlxbf_pmc_hnfnet_events);
978 } else if (strstr(blk, "tile")) {
979 events = mlxbf_pmc_hnf_events;
980 size = ARRAY_SIZE(mlxbf_pmc_hnf_events);
981 } else if (strstr(blk, "triogen")) {
982 events = mlxbf_pmc_smgen_events;
983 size = ARRAY_SIZE(mlxbf_pmc_smgen_events);
984 } else if (strstr(blk, "trio")) {
985 switch (pmc->event_set) {
986 case MLXBF_PMC_EVENT_SET_BF1:
987 events = mlxbf_pmc_trio_events_1;
988 size = ARRAY_SIZE(mlxbf_pmc_trio_events_1);
989 break;
990 case MLXBF_PMC_EVENT_SET_BF2:
991 events = mlxbf_pmc_trio_events_2;
992 size = ARRAY_SIZE(mlxbf_pmc_trio_events_2);
993 break;
994 default:
995 events = NULL;
996 size = 0;
997 break;
998 }
999 } else if (strstr(blk, "mss")) {
1000 switch (pmc->event_set) {
1001 case MLXBF_PMC_EVENT_SET_BF1:
1002 case MLXBF_PMC_EVENT_SET_BF2:
1003 events = mlxbf_pmc_mss_events_1;
1004 size = ARRAY_SIZE(mlxbf_pmc_mss_events_1);
1005 break;
1006 case MLXBF_PMC_EVENT_SET_BF3:
1007 events = mlxbf_pmc_mss_events_3;
1008 size = ARRAY_SIZE(mlxbf_pmc_mss_events_3);
1009 break;
1010 default:
1011 events = NULL;
1012 size = 0;
1013 break;
1014 }
1015 } else if (strstr(blk, "ecc")) {
1016 events = mlxbf_pmc_ecc_events;
1017 size = ARRAY_SIZE(mlxbf_pmc_ecc_events);
1018 } else if (strstr(blk, "pcie")) {
1019 events = mlxbf_pmc_pcie_events;
1020 size = ARRAY_SIZE(mlxbf_pmc_pcie_events);
1021 } else if (strstr(blk, "l3cache")) {
1022 events = mlxbf_pmc_l3c_events;
1023 size = ARRAY_SIZE(mlxbf_pmc_l3c_events);
1024 } else if (strstr(blk, "gic")) {
1025 events = mlxbf_pmc_smgen_events;
1026 size = ARRAY_SIZE(mlxbf_pmc_smgen_events);
1027 } else if (strstr(blk, "smmu")) {
1028 events = mlxbf_pmc_smgen_events;
1029 size = ARRAY_SIZE(mlxbf_pmc_smgen_events);
1030 } else if (strstr(blk, "llt_miss")) {
1031 events = mlxbf_pmc_llt_miss_events;
1032 size = ARRAY_SIZE(mlxbf_pmc_llt_miss_events);
1033 } else if (strstr(blk, "llt")) {
1034 events = mlxbf_pmc_llt_events;
1035 size = ARRAY_SIZE(mlxbf_pmc_llt_events);
1036 } else {
1037 events = NULL;
1038 size = 0;
1039 }
1040
1041 if (psize)
1042 *psize = size;
1043
1044 return events;
1045 }
1046
mlxbf_pmc_event_supported(const char * blk)1047 static bool mlxbf_pmc_event_supported(const char *blk)
1048 {
1049 return !!mlxbf_pmc_event_list(blk, NULL);
1050 }
1051
1052 /* Get the event number given the name */
mlxbf_pmc_get_event_num(const char * blk,const char * evt)1053 static int mlxbf_pmc_get_event_num(const char *blk, const char *evt)
1054 {
1055 const struct mlxbf_pmc_events *events;
1056 unsigned int i;
1057 size_t size;
1058
1059 events = mlxbf_pmc_event_list(blk, &size);
1060 if (!events)
1061 return -EINVAL;
1062
1063 for (i = 0; i < size; ++i) {
1064 if (!strcmp(evt, events[i].evt_name))
1065 return events[i].evt_num;
1066 }
1067
1068 return -ENODEV;
1069 }
1070
1071 /* Get the event name given the number */
mlxbf_pmc_get_event_name(const char * blk,u32 evt)1072 static char *mlxbf_pmc_get_event_name(const char *blk, u32 evt)
1073 {
1074 const struct mlxbf_pmc_events *events;
1075 unsigned int i;
1076 size_t size;
1077
1078 events = mlxbf_pmc_event_list(blk, &size);
1079 if (!events)
1080 return NULL;
1081
1082 for (i = 0; i < size; ++i) {
1083 if (evt == events[i].evt_num)
1084 return events[i].evt_name;
1085 }
1086
1087 return NULL;
1088 }
1089
1090 /* Method to enable/disable/reset l3cache counters */
mlxbf_pmc_config_l3_counters(unsigned int blk_num,bool enable,bool reset)1091 static int mlxbf_pmc_config_l3_counters(unsigned int blk_num, bool enable, bool reset)
1092 {
1093 u32 perfcnt_cfg = 0;
1094
1095 if (enable)
1096 perfcnt_cfg |= MLXBF_PMC_L3C_PERF_CNT_CFG_EN;
1097 if (reset)
1098 perfcnt_cfg |= MLXBF_PMC_L3C_PERF_CNT_CFG_RST;
1099
1100 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
1101 MLXBF_PMC_L3C_PERF_CNT_CFG,
1102 MLXBF_PMC_WRITE_REG_32, perfcnt_cfg);
1103 }
1104
1105 /* Method to handle l3cache counter programming */
mlxbf_pmc_program_l3_counter(unsigned int blk_num,u32 cnt_num,u32 evt)1106 static int mlxbf_pmc_program_l3_counter(unsigned int blk_num, u32 cnt_num, u32 evt)
1107 {
1108 u32 perfcnt_sel_1 = 0, perfcnt_sel = 0, *wordaddr;
1109 void __iomem *pmcaddr;
1110 int ret;
1111
1112 /* Disable all counters before programming them */
1113 if (mlxbf_pmc_config_l3_counters(blk_num, false, false))
1114 return -EINVAL;
1115
1116 /* Select appropriate register information */
1117 switch (cnt_num) {
1118 case 0 ... 3:
1119 pmcaddr = pmc->block[blk_num].mmio_base +
1120 MLXBF_PMC_L3C_PERF_CNT_SEL;
1121 wordaddr = &perfcnt_sel;
1122 break;
1123 case 4:
1124 pmcaddr = pmc->block[blk_num].mmio_base +
1125 MLXBF_PMC_L3C_PERF_CNT_SEL_1;
1126 wordaddr = &perfcnt_sel_1;
1127 break;
1128 default:
1129 return -EINVAL;
1130 }
1131
1132 ret = mlxbf_pmc_readl(pmcaddr, wordaddr);
1133 if (ret)
1134 return ret;
1135
1136 switch (cnt_num) {
1137 case 0:
1138 perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0;
1139 perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0,
1140 evt);
1141 break;
1142 case 1:
1143 perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1;
1144 perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1,
1145 evt);
1146 break;
1147 case 2:
1148 perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2;
1149 perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2,
1150 evt);
1151 break;
1152 case 3:
1153 perfcnt_sel &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3;
1154 perfcnt_sel |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3,
1155 evt);
1156 break;
1157 case 4:
1158 perfcnt_sel_1 &= ~MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4;
1159 perfcnt_sel_1 |= FIELD_PREP(MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4,
1160 evt);
1161 break;
1162 default:
1163 return -EINVAL;
1164 }
1165
1166 return mlxbf_pmc_write(pmcaddr, MLXBF_PMC_WRITE_REG_32, *wordaddr);
1167 }
1168
1169 /* Method to handle crspace counter programming */
mlxbf_pmc_program_crspace_counter(unsigned int blk_num,u32 cnt_num,u32 evt)1170 static int mlxbf_pmc_program_crspace_counter(unsigned int blk_num, u32 cnt_num, u32 evt)
1171 {
1172 void __iomem *addr;
1173 u32 word;
1174 int ret;
1175
1176 addr = pmc->block[blk_num].mmio_base +
1177 ((cnt_num / 2) * MLXBF_PMC_CRSPACE_PERFSEL_SZ);
1178 ret = mlxbf_pmc_readl(addr, &word);
1179 if (ret)
1180 return ret;
1181
1182 if (cnt_num % 2) {
1183 word &= ~MLXBF_PMC_CRSPACE_PERFSEL1;
1184 word |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFSEL1, evt);
1185 } else {
1186 word &= ~MLXBF_PMC_CRSPACE_PERFSEL0;
1187 word |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFSEL0, evt);
1188 }
1189
1190 return mlxbf_pmc_write(addr, MLXBF_PMC_WRITE_REG_32, word);
1191 }
1192
1193 /* Method to clear crspace counter value */
mlxbf_pmc_clear_crspace_counter(unsigned int blk_num,u32 cnt_num)1194 static int mlxbf_pmc_clear_crspace_counter(unsigned int blk_num, u32 cnt_num)
1195 {
1196 void __iomem *addr;
1197
1198 addr = pmc->block[blk_num].mmio_base +
1199 MLXBF_PMC_CRSPACE_PERFMON_VAL0(pmc->block[blk_num].counters) +
1200 (cnt_num * 4);
1201
1202 return mlxbf_pmc_write(addr, MLXBF_PMC_WRITE_REG_32, 0x0);
1203 }
1204
1205 /* Method to program a counter to monitor an event */
mlxbf_pmc_program_counter(unsigned int blk_num,u32 cnt_num,u32 evt,bool is_l3)1206 static int mlxbf_pmc_program_counter(unsigned int blk_num, u32 cnt_num, u32 evt, bool is_l3)
1207 {
1208 u64 perfctl, perfevt, perfmon_cfg;
1209
1210 if (cnt_num >= pmc->block[blk_num].counters)
1211 return -ENODEV;
1212
1213 if (is_l3)
1214 return mlxbf_pmc_program_l3_counter(blk_num, cnt_num, evt);
1215
1216 if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE)
1217 return mlxbf_pmc_program_crspace_counter(blk_num, cnt_num,
1218 evt);
1219
1220 /* Configure the counter */
1221 perfctl = FIELD_PREP(MLXBF_PMC_PERFCTL_EN0, 1);
1222 perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_EB0, 0);
1223 perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_ETRIG0, 1);
1224 perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_AD0, 0);
1225 perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_ACCM0, 0);
1226 perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_MS0, 0);
1227 perfctl |= FIELD_PREP(MLXBF_PMC_PERFCTL_FM0, 0);
1228
1229 perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WDATA, perfctl);
1230 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
1231 MLXBF_PMC_PERFCTL);
1232 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
1233 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 1);
1234
1235 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
1236 cnt_num * MLXBF_PMC_REG_SIZE,
1237 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
1238 return -EFAULT;
1239
1240 /* Select the event */
1241 perfevt = FIELD_PREP(MLXBF_PMC_PERFEVT_EVTSEL, evt);
1242
1243 perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WDATA, perfevt);
1244 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
1245 MLXBF_PMC_PERFEVT);
1246 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
1247 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 1);
1248
1249 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
1250 cnt_num * MLXBF_PMC_REG_SIZE,
1251 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
1252 return -EFAULT;
1253
1254 /* Clear the accumulator */
1255 perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
1256 MLXBF_PMC_PERFACC0);
1257 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
1258 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 1);
1259
1260 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
1261 cnt_num * MLXBF_PMC_REG_SIZE,
1262 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
1263 return -EFAULT;
1264
1265 return 0;
1266 }
1267
1268 /* Method to handle l3 counter reads */
mlxbf_pmc_read_l3_counter(unsigned int blk_num,u32 cnt_num,u64 * result)1269 static int mlxbf_pmc_read_l3_counter(unsigned int blk_num, u32 cnt_num, u64 *result)
1270 {
1271 u32 perfcnt_low = 0, perfcnt_high = 0;
1272 int status;
1273 u64 value;
1274
1275 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1276 MLXBF_PMC_L3C_PERF_CNT_LOW +
1277 cnt_num * MLXBF_PMC_L3C_REG_SIZE,
1278 &perfcnt_low);
1279
1280 if (status)
1281 return status;
1282
1283 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1284 MLXBF_PMC_L3C_PERF_CNT_HIGH +
1285 cnt_num * MLXBF_PMC_L3C_REG_SIZE,
1286 &perfcnt_high);
1287
1288 if (status)
1289 return status;
1290
1291 value = perfcnt_high;
1292 value = value << 32;
1293 value |= perfcnt_low;
1294 *result = value;
1295
1296 return 0;
1297 }
1298
1299 /* Method to handle crspace counter reads */
mlxbf_pmc_read_crspace_counter(unsigned int blk_num,u32 cnt_num,u64 * result)1300 static int mlxbf_pmc_read_crspace_counter(unsigned int blk_num, u32 cnt_num, u64 *result)
1301 {
1302 int status = 0;
1303 u32 value;
1304
1305 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1306 MLXBF_PMC_CRSPACE_PERFMON_VAL0(pmc->block[blk_num].counters) +
1307 (cnt_num * 4), &value);
1308 if (status)
1309 return status;
1310
1311 *result = value;
1312
1313 return 0;
1314 }
1315
1316 /* Method to read the counter value */
mlxbf_pmc_read_counter(unsigned int blk_num,u32 cnt_num,bool is_l3,u64 * result)1317 static int mlxbf_pmc_read_counter(unsigned int blk_num, u32 cnt_num, bool is_l3, u64 *result)
1318 {
1319 u32 perfcfg_offset, perfval_offset;
1320 u64 perfmon_cfg;
1321 int status;
1322
1323 if (cnt_num >= pmc->block[blk_num].counters)
1324 return -EINVAL;
1325
1326 if (is_l3)
1327 return mlxbf_pmc_read_l3_counter(blk_num, cnt_num, result);
1328
1329 if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE)
1330 return mlxbf_pmc_read_crspace_counter(blk_num, cnt_num, result);
1331
1332 perfcfg_offset = cnt_num * MLXBF_PMC_REG_SIZE;
1333 perfval_offset = perfcfg_offset +
1334 pmc->block[blk_num].counters * MLXBF_PMC_REG_SIZE;
1335
1336 /* Set counter in "read" mode */
1337 perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
1338 MLXBF_PMC_PERFACC0);
1339 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
1340 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 0);
1341
1342 status = mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,
1343 MLXBF_PMC_WRITE_REG_64, perfmon_cfg);
1344
1345 if (status)
1346 return status;
1347
1348 /* Get the counter value */
1349 return mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,
1350 MLXBF_PMC_READ_REG_64, result);
1351 }
1352
1353 /* Method to read L3 block event */
mlxbf_pmc_read_l3_event(unsigned int blk_num,u32 cnt_num,u64 * result)1354 static int mlxbf_pmc_read_l3_event(unsigned int blk_num, u32 cnt_num, u64 *result)
1355 {
1356 u32 perfcnt_sel = 0, perfcnt_sel_1 = 0, *wordaddr;
1357 void __iomem *pmcaddr;
1358 u64 evt;
1359
1360 /* Select appropriate register information */
1361 switch (cnt_num) {
1362 case 0 ... 3:
1363 pmcaddr = pmc->block[blk_num].mmio_base +
1364 MLXBF_PMC_L3C_PERF_CNT_SEL;
1365 wordaddr = &perfcnt_sel;
1366 break;
1367 case 4:
1368 pmcaddr = pmc->block[blk_num].mmio_base +
1369 MLXBF_PMC_L3C_PERF_CNT_SEL_1;
1370 wordaddr = &perfcnt_sel_1;
1371 break;
1372 default:
1373 return -EINVAL;
1374 }
1375
1376 if (mlxbf_pmc_readl(pmcaddr, wordaddr))
1377 return -EINVAL;
1378
1379 /* Read from appropriate register field for the counter */
1380 switch (cnt_num) {
1381 case 0:
1382 evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_0, perfcnt_sel);
1383 break;
1384 case 1:
1385 evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_1, perfcnt_sel);
1386 break;
1387 case 2:
1388 evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_2, perfcnt_sel);
1389 break;
1390 case 3:
1391 evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_CNT_3, perfcnt_sel);
1392 break;
1393 case 4:
1394 evt = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_SEL_1_CNT_4,
1395 perfcnt_sel_1);
1396 break;
1397 default:
1398 return -EINVAL;
1399 }
1400 *result = evt;
1401
1402 return 0;
1403 }
1404
1405 /* Method to read crspace block event */
mlxbf_pmc_read_crspace_event(unsigned int blk_num,u32 cnt_num,u64 * result)1406 static int mlxbf_pmc_read_crspace_event(unsigned int blk_num, u32 cnt_num, u64 *result)
1407 {
1408 u32 word, evt;
1409 void __iomem *addr;
1410 int ret;
1411
1412 addr = pmc->block[blk_num].mmio_base +
1413 ((cnt_num / 2) * MLXBF_PMC_CRSPACE_PERFSEL_SZ);
1414 ret = mlxbf_pmc_readl(addr, &word);
1415 if (ret)
1416 return ret;
1417
1418 if (cnt_num % 2)
1419 evt = FIELD_GET(MLXBF_PMC_CRSPACE_PERFSEL1, word);
1420 else
1421 evt = FIELD_GET(MLXBF_PMC_CRSPACE_PERFSEL0, word);
1422
1423 *result = evt;
1424
1425 return 0;
1426 }
1427
1428 /* Method to find the event currently being monitored by a counter */
mlxbf_pmc_read_event(unsigned int blk_num,u32 cnt_num,bool is_l3,u64 * result)1429 static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is_l3, u64 *result)
1430 {
1431 u32 perfcfg_offset, perfval_offset;
1432 u64 perfmon_cfg, perfevt;
1433
1434 if (cnt_num >= pmc->block[blk_num].counters)
1435 return -EINVAL;
1436
1437 if (is_l3)
1438 return mlxbf_pmc_read_l3_event(blk_num, cnt_num, result);
1439
1440 if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE)
1441 return mlxbf_pmc_read_crspace_event(blk_num, cnt_num, result);
1442
1443 perfcfg_offset = cnt_num * MLXBF_PMC_REG_SIZE;
1444 perfval_offset = perfcfg_offset +
1445 pmc->block[blk_num].counters * MLXBF_PMC_REG_SIZE;
1446
1447 /* Set counter in "read" mode */
1448 perfmon_cfg = FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_ADDR,
1449 MLXBF_PMC_PERFEVT);
1450 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_STROBE, 1);
1451 perfmon_cfg |= FIELD_PREP(MLXBF_PMC_PERFMON_CONFIG_WR_R_B, 0);
1452
1453 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,
1454 MLXBF_PMC_WRITE_REG_64, perfmon_cfg))
1455 return -EFAULT;
1456
1457 /* Get the event number */
1458 if (mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,
1459 MLXBF_PMC_READ_REG_64, &perfevt))
1460 return -EFAULT;
1461
1462 *result = FIELD_GET(MLXBF_PMC_PERFEVT_EVTSEL, perfevt);
1463
1464 return 0;
1465 }
1466
1467 /* Method to read a register */
mlxbf_pmc_read_reg(unsigned int blk_num,u32 offset,u64 * result)1468 static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result)
1469 {
1470 u32 ecc_out;
1471
1472 if (strstr(pmc->block_name[blk_num], "ecc")) {
1473 if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset,
1474 &ecc_out))
1475 return -EFAULT;
1476
1477 *result = ecc_out;
1478 return 0;
1479 }
1480
1481 if (mlxbf_pmc_valid_range(blk_num, offset))
1482 return mlxbf_pmc_read(pmc->block[blk_num].mmio_base + offset,
1483 MLXBF_PMC_READ_REG_64, result);
1484
1485 return -EINVAL;
1486 }
1487
1488 /* Method to write to a register */
mlxbf_pmc_write_reg(unsigned int blk_num,u32 offset,u64 data)1489 static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data)
1490 {
1491 if (strstr(pmc->block_name[blk_num], "ecc")) {
1492 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,
1493 MLXBF_PMC_WRITE_REG_32, data);
1494 }
1495
1496 if (mlxbf_pmc_valid_range(blk_num, offset))
1497 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,
1498 MLXBF_PMC_WRITE_REG_64, data);
1499
1500 return -EINVAL;
1501 }
1502
1503 /* Show function for "counter" sysfs files */
mlxbf_pmc_counter_show(struct device * dev,struct device_attribute * attr,char * buf)1504 static ssize_t mlxbf_pmc_counter_show(struct device *dev,
1505 struct device_attribute *attr, char *buf)
1506 {
1507 struct mlxbf_pmc_attribute *attr_counter = container_of(
1508 attr, struct mlxbf_pmc_attribute, dev_attr);
1509 unsigned int blk_num, cnt_num;
1510 bool is_l3 = false;
1511 int offset;
1512 u64 value;
1513
1514 blk_num = attr_counter->nr;
1515 cnt_num = attr_counter->index;
1516
1517 if (strstr(pmc->block_name[blk_num], "l3cache"))
1518 is_l3 = true;
1519
1520 if ((pmc->block[blk_num].type == MLXBF_PMC_TYPE_COUNTER) ||
1521 (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE)) {
1522 if (mlxbf_pmc_read_counter(blk_num, cnt_num, is_l3, &value))
1523 return -EINVAL;
1524 } else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_REGISTER) {
1525 offset = mlxbf_pmc_get_event_num(pmc->block_name[blk_num],
1526 attr->attr.name);
1527 if (offset < 0)
1528 return -EINVAL;
1529 if (mlxbf_pmc_read_reg(blk_num, offset, &value))
1530 return -EINVAL;
1531 } else
1532 return -EINVAL;
1533
1534 return sysfs_emit(buf, "0x%llx\n", value);
1535 }
1536
1537 /* Store function for "counter" sysfs files */
mlxbf_pmc_counter_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1538 static ssize_t mlxbf_pmc_counter_store(struct device *dev,
1539 struct device_attribute *attr,
1540 const char *buf, size_t count)
1541 {
1542 struct mlxbf_pmc_attribute *attr_counter = container_of(
1543 attr, struct mlxbf_pmc_attribute, dev_attr);
1544 unsigned int blk_num, cnt_num, data;
1545 bool is_l3 = false;
1546 u64 evt_num;
1547 int offset;
1548 int err;
1549
1550 blk_num = attr_counter->nr;
1551 cnt_num = attr_counter->index;
1552
1553 err = kstrtouint(buf, 0, &data);
1554 if (err < 0)
1555 return err;
1556
1557 /* Allow non-zero writes only to the ecc regs */
1558 if (!(strstr(pmc->block_name[blk_num], "ecc")) && data)
1559 return -EINVAL;
1560
1561 /* Do not allow writes to the L3C regs */
1562 if (strstr(pmc->block_name[blk_num], "l3cache"))
1563 return -EINVAL;
1564
1565 if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_COUNTER) {
1566 err = mlxbf_pmc_read_event(blk_num, cnt_num, is_l3, &evt_num);
1567 if (err)
1568 return err;
1569 err = mlxbf_pmc_program_counter(blk_num, cnt_num, evt_num,
1570 is_l3);
1571 if (err)
1572 return err;
1573 } else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_REGISTER) {
1574 offset = mlxbf_pmc_get_event_num(pmc->block_name[blk_num],
1575 attr->attr.name);
1576 if (offset < 0)
1577 return -EINVAL;
1578 err = mlxbf_pmc_write_reg(blk_num, offset, data);
1579 if (err)
1580 return err;
1581 } else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) {
1582 if (sscanf(attr->attr.name, "counter%u", &cnt_num) != 1)
1583 return -EINVAL;
1584 err = mlxbf_pmc_clear_crspace_counter(blk_num, cnt_num);
1585 } else
1586 return -EINVAL;
1587
1588 return count;
1589 }
1590
1591 /* Show function for "event" sysfs files */
mlxbf_pmc_event_show(struct device * dev,struct device_attribute * attr,char * buf)1592 static ssize_t mlxbf_pmc_event_show(struct device *dev,
1593 struct device_attribute *attr, char *buf)
1594 {
1595 struct mlxbf_pmc_attribute *attr_event = container_of(
1596 attr, struct mlxbf_pmc_attribute, dev_attr);
1597 unsigned int blk_num, cnt_num;
1598 bool is_l3 = false;
1599 char *evt_name;
1600 u64 evt_num;
1601 int err;
1602
1603 blk_num = attr_event->nr;
1604 cnt_num = attr_event->index;
1605
1606 if (strstr(pmc->block_name[blk_num], "l3cache"))
1607 is_l3 = true;
1608
1609 err = mlxbf_pmc_read_event(blk_num, cnt_num, is_l3, &evt_num);
1610 if (err)
1611 return sysfs_emit(buf, "No event being monitored\n");
1612
1613 evt_name = mlxbf_pmc_get_event_name(pmc->block_name[blk_num], evt_num);
1614 if (!evt_name)
1615 return -EINVAL;
1616
1617 return sysfs_emit(buf, "0x%llx: %s\n", evt_num, evt_name);
1618 }
1619
1620 /* Store function for "event" sysfs files */
mlxbf_pmc_event_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1621 static ssize_t mlxbf_pmc_event_store(struct device *dev,
1622 struct device_attribute *attr,
1623 const char *buf, size_t count)
1624 {
1625 struct mlxbf_pmc_attribute *attr_event = container_of(
1626 attr, struct mlxbf_pmc_attribute, dev_attr);
1627 unsigned int blk_num, cnt_num;
1628 bool is_l3 = false;
1629 char *evt_name;
1630 int evt_num;
1631 int err;
1632
1633 blk_num = attr_event->nr;
1634 cnt_num = attr_event->index;
1635
1636 if (isalpha(buf[0])) {
1637 /* Remove the trailing newline character if present */
1638 evt_name = kstrdup_and_replace(buf, '\n', '\0', GFP_KERNEL);
1639 if (!evt_name)
1640 return -ENOMEM;
1641
1642 evt_num = mlxbf_pmc_get_event_num(pmc->block_name[blk_num],
1643 evt_name);
1644 kfree(evt_name);
1645 if (evt_num < 0)
1646 return -EINVAL;
1647 } else {
1648 err = kstrtouint(buf, 0, &evt_num);
1649 if (err < 0)
1650 return err;
1651
1652 if (!mlxbf_pmc_get_event_name(pmc->block_name[blk_num], evt_num))
1653 return -EINVAL;
1654 }
1655
1656 if (strstr(pmc->block_name[blk_num], "l3cache"))
1657 is_l3 = true;
1658
1659 err = mlxbf_pmc_program_counter(blk_num, cnt_num, evt_num, is_l3);
1660 if (err)
1661 return err;
1662
1663 return count;
1664 }
1665
1666 /* Show function for "event_list" sysfs files */
mlxbf_pmc_event_list_show(struct device * dev,struct device_attribute * attr,char * buf)1667 static ssize_t mlxbf_pmc_event_list_show(struct device *dev,
1668 struct device_attribute *attr,
1669 char *buf)
1670 {
1671 struct mlxbf_pmc_attribute *attr_event_list = container_of(
1672 attr, struct mlxbf_pmc_attribute, dev_attr);
1673 const struct mlxbf_pmc_events *events;
1674 char e_info[MLXBF_PMC_EVENT_INFO_LEN];
1675 unsigned int blk_num, i, len = 0;
1676 size_t size;
1677 int ret = 0;
1678
1679 blk_num = attr_event_list->nr;
1680
1681 events = mlxbf_pmc_event_list(pmc->block_name[blk_num], &size);
1682 if (!events)
1683 return -EINVAL;
1684
1685 for (i = 0, buf[0] = '\0'; i < size; ++i) {
1686 len += snprintf(e_info, sizeof(e_info), "0x%x: %s\n",
1687 events[i].evt_num, events[i].evt_name);
1688 if (len >= PAGE_SIZE)
1689 break;
1690 strcat(buf, e_info);
1691 ret = len;
1692 }
1693
1694 return ret;
1695 }
1696
1697 /* Show function for "enable" sysfs files - only for l3cache & crspace */
mlxbf_pmc_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1698 static ssize_t mlxbf_pmc_enable_show(struct device *dev,
1699 struct device_attribute *attr, char *buf)
1700 {
1701 struct mlxbf_pmc_attribute *attr_enable = container_of(
1702 attr, struct mlxbf_pmc_attribute, dev_attr);
1703 unsigned int blk_num, value;
1704 u32 perfcnt_cfg, word;
1705
1706 blk_num = attr_enable->nr;
1707
1708 if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) {
1709 if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1710 MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
1711 &word))
1712 return -EINVAL;
1713
1714 value = FIELD_GET(MLXBF_PMC_CRSPACE_PERFMON_EN, word);
1715 } else {
1716 if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1717 MLXBF_PMC_L3C_PERF_CNT_CFG,
1718 &perfcnt_cfg))
1719 return -EINVAL;
1720
1721 value = FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_CFG_EN, perfcnt_cfg);
1722 }
1723
1724 return sysfs_emit(buf, "%u\n", value);
1725 }
1726
1727 /* Store function for "enable" sysfs files - only for l3cache & crspace */
mlxbf_pmc_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1728 static ssize_t mlxbf_pmc_enable_store(struct device *dev,
1729 struct device_attribute *attr,
1730 const char *buf, size_t count)
1731 {
1732 struct mlxbf_pmc_attribute *attr_enable = container_of(
1733 attr, struct mlxbf_pmc_attribute, dev_attr);
1734 unsigned int blk_num;
1735 u32 word;
1736 int err;
1737 bool en;
1738
1739 blk_num = attr_enable->nr;
1740
1741 err = kstrtobool(buf, &en);
1742 if (err < 0)
1743 return err;
1744
1745 if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) {
1746 err = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +
1747 MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
1748 &word);
1749 if (err)
1750 return -EINVAL;
1751
1752 word &= ~MLXBF_PMC_CRSPACE_PERFMON_EN;
1753 word |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_EN, en);
1754 if (en)
1755 word |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_CLR, 1);
1756
1757 mlxbf_pmc_write(pmc->block[blk_num].mmio_base +
1758 MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters),
1759 MLXBF_PMC_WRITE_REG_32, word);
1760 } else {
1761 err = mlxbf_pmc_config_l3_counters(blk_num, false, !!en);
1762 if (err)
1763 return err;
1764
1765 if (en) {
1766 err = mlxbf_pmc_config_l3_counters(blk_num, true, false);
1767 if (err)
1768 return err;
1769 }
1770 }
1771
1772 return count;
1773 }
1774
1775 /* Populate attributes for blocks with counters to monitor performance */
mlxbf_pmc_init_perftype_counter(struct device * dev,unsigned int blk_num)1776 static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_num)
1777 {
1778 struct mlxbf_pmc_attribute *attr;
1779 unsigned int i = 0, j = 0;
1780
1781 if (!mlxbf_pmc_event_supported(pmc->block_name[blk_num]))
1782 return -ENOENT;
1783
1784 /* "event_list" sysfs to list events supported by the block */
1785 attr = &pmc->block[blk_num].attr_event_list;
1786 sysfs_attr_init(&attr->dev_attr.attr);
1787 attr->dev_attr.attr.mode = 0444;
1788 attr->dev_attr.show = mlxbf_pmc_event_list_show;
1789 attr->nr = blk_num;
1790 attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, "event_list");
1791 if (!attr->dev_attr.attr.name)
1792 return -ENOMEM;
1793 pmc->block[blk_num].block_attr[i] = &attr->dev_attr.attr;
1794 attr = NULL;
1795
1796 /* "enable" sysfs to start/stop the counters. Only in L3C blocks */
1797 if (strstr(pmc->block_name[blk_num], "l3cache") ||
1798 ((pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE))) {
1799 attr = &pmc->block[blk_num].attr_enable;
1800 sysfs_attr_init(&attr->dev_attr.attr);
1801 attr->dev_attr.attr.mode = 0644;
1802 attr->dev_attr.show = mlxbf_pmc_enable_show;
1803 attr->dev_attr.store = mlxbf_pmc_enable_store;
1804 attr->nr = blk_num;
1805 attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
1806 "enable");
1807 if (!attr->dev_attr.attr.name)
1808 return -ENOMEM;
1809 pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
1810 attr = NULL;
1811 }
1812
1813 pmc->block[blk_num].attr_counter = devm_kcalloc(
1814 dev, pmc->block[blk_num].counters,
1815 sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
1816 if (!pmc->block[blk_num].attr_counter)
1817 return -ENOMEM;
1818
1819 pmc->block[blk_num].attr_event = devm_kcalloc(
1820 dev, pmc->block[blk_num].counters,
1821 sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
1822 if (!pmc->block[blk_num].attr_event)
1823 return -ENOMEM;
1824
1825 /* "eventX" and "counterX" sysfs to program and read counter values */
1826 for (j = 0; j < pmc->block[blk_num].counters; ++j) {
1827 attr = &pmc->block[blk_num].attr_counter[j];
1828 sysfs_attr_init(&attr->dev_attr.attr);
1829 attr->dev_attr.attr.mode = 0644;
1830 attr->dev_attr.show = mlxbf_pmc_counter_show;
1831 attr->dev_attr.store = mlxbf_pmc_counter_store;
1832 attr->index = j;
1833 attr->nr = blk_num;
1834 attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, "counter%u", j);
1835 if (!attr->dev_attr.attr.name)
1836 return -ENOMEM;
1837 pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
1838 attr = NULL;
1839
1840 attr = &pmc->block[blk_num].attr_event[j];
1841 sysfs_attr_init(&attr->dev_attr.attr);
1842 attr->dev_attr.attr.mode = 0644;
1843 attr->dev_attr.show = mlxbf_pmc_event_show;
1844 attr->dev_attr.store = mlxbf_pmc_event_store;
1845 attr->index = j;
1846 attr->nr = blk_num;
1847 attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, "event%u", j);
1848 if (!attr->dev_attr.attr.name)
1849 return -ENOMEM;
1850 pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr;
1851 attr = NULL;
1852 }
1853
1854 return 0;
1855 }
1856
1857 /* Populate attributes for blocks with registers to monitor performance */
mlxbf_pmc_init_perftype_reg(struct device * dev,unsigned int blk_num)1858 static int mlxbf_pmc_init_perftype_reg(struct device *dev, unsigned int blk_num)
1859 {
1860 const struct mlxbf_pmc_events *events;
1861 struct mlxbf_pmc_attribute *attr;
1862 unsigned int i = 0;
1863 size_t count = 0;
1864
1865 events = mlxbf_pmc_event_list(pmc->block_name[blk_num], &count);
1866 if (!events)
1867 return -ENOENT;
1868
1869 pmc->block[blk_num].attr_event = devm_kcalloc(
1870 dev, count, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);
1871 if (!pmc->block[blk_num].attr_event)
1872 return -ENOMEM;
1873
1874 while (count > 0) {
1875 --count;
1876 attr = &pmc->block[blk_num].attr_event[count];
1877 sysfs_attr_init(&attr->dev_attr.attr);
1878 attr->dev_attr.attr.mode = 0644;
1879 attr->dev_attr.show = mlxbf_pmc_counter_show;
1880 attr->dev_attr.store = mlxbf_pmc_counter_store;
1881 attr->nr = blk_num;
1882 attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL,
1883 events[count].evt_name);
1884 if (!attr->dev_attr.attr.name)
1885 return -ENOMEM;
1886 pmc->block[blk_num].block_attr[i] = &attr->dev_attr.attr;
1887 attr = NULL;
1888 i++;
1889 }
1890
1891 return 0;
1892 }
1893
1894 /* Helper to create the bfperf sysfs sub-directories and files */
mlxbf_pmc_create_groups(struct device * dev,unsigned int blk_num)1895 static int mlxbf_pmc_create_groups(struct device *dev, unsigned int blk_num)
1896 {
1897 int err;
1898
1899 /* Populate attributes based on counter type */
1900 if ((pmc->block[blk_num].type == MLXBF_PMC_TYPE_COUNTER) ||
1901 (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE))
1902 err = mlxbf_pmc_init_perftype_counter(dev, blk_num);
1903 else if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_REGISTER)
1904 err = mlxbf_pmc_init_perftype_reg(dev, blk_num);
1905 else
1906 err = -ENOENT;
1907
1908 if (err)
1909 return err;
1910
1911 /* Add a new attribute_group for the block */
1912 pmc->block[blk_num].block_attr_grp.attrs = pmc->block[blk_num].block_attr;
1913 pmc->block[blk_num].block_attr_grp.name = devm_kasprintf(
1914 dev, GFP_KERNEL, pmc->block_name[blk_num]);
1915 if (!pmc->block[blk_num].block_attr_grp.name)
1916 return -ENOMEM;
1917 pmc->groups[pmc->group_num] = &pmc->block[blk_num].block_attr_grp;
1918 pmc->group_num++;
1919
1920 return 0;
1921 }
1922
mlxbf_pmc_guid_match(const guid_t * guid,const struct arm_smccc_res * res)1923 static bool mlxbf_pmc_guid_match(const guid_t *guid,
1924 const struct arm_smccc_res *res)
1925 {
1926 guid_t id = GUID_INIT(res->a0, res->a1, res->a1 >> 16, res->a2,
1927 res->a2 >> 8, res->a2 >> 16, res->a2 >> 24,
1928 res->a3, res->a3 >> 8, res->a3 >> 16,
1929 res->a3 >> 24);
1930
1931 return guid_equal(guid, &id);
1932 }
1933
1934 /* Helper to map the Performance Counters from the varios blocks */
mlxbf_pmc_map_counters(struct device * dev)1935 static int mlxbf_pmc_map_counters(struct device *dev)
1936 {
1937 u64 info[MLXBF_PMC_INFO_SZ];
1938 unsigned int tile_num, i;
1939 int ret;
1940
1941 for (i = 0; i < pmc->total_blocks; ++i) {
1942 /* Create sysfs for tiles only if block number < tile_count */
1943 if (strstr(pmc->block_name[i], "tilenet")) {
1944 if (sscanf(pmc->block_name[i], "tilenet%u", &tile_num) != 1)
1945 continue;
1946
1947 if (tile_num >= pmc->tile_count)
1948 continue;
1949 } else if (strstr(pmc->block_name[i], "tile")) {
1950 if (sscanf(pmc->block_name[i], "tile%u", &tile_num) != 1)
1951 continue;
1952
1953 if (tile_num >= pmc->tile_count)
1954 continue;
1955 }
1956
1957 /* Create sysfs only for enabled MSS blocks */
1958 if (strstr(pmc->block_name[i], "mss") &&
1959 pmc->event_set == MLXBF_PMC_EVENT_SET_BF3) {
1960 unsigned int mss_num;
1961
1962 if (sscanf(pmc->block_name[i], "mss%u", &mss_num) != 1)
1963 continue;
1964
1965 if (!((pmc->mss_enable >> mss_num) & 0x1))
1966 continue;
1967 }
1968
1969 /* Create sysfs only for enabled LLT blocks */
1970 if (strstr(pmc->block_name[i], "llt_miss")) {
1971 unsigned int llt_num;
1972
1973 if (sscanf(pmc->block_name[i], "llt_miss%u", &llt_num) != 1)
1974 continue;
1975
1976 if (!((pmc->llt_enable >> llt_num) & 0x1))
1977 continue;
1978 } else if (strstr(pmc->block_name[i], "llt")) {
1979 unsigned int llt_num;
1980
1981 if (sscanf(pmc->block_name[i], "llt%u", &llt_num) != 1)
1982 continue;
1983
1984 if (!((pmc->llt_enable >> llt_num) & 0x1))
1985 continue;
1986 }
1987
1988 ret = device_property_read_u64_array(dev, pmc->block_name[i],
1989 info, MLXBF_PMC_INFO_SZ);
1990 if (ret)
1991 return ret;
1992
1993 /*
1994 * Do not remap if the proper SMC calls are supported,
1995 * since the SMC calls expect physical addresses.
1996 */
1997 if (pmc->svc_sreg_support)
1998 pmc->block[i].mmio_base = (void __iomem *)info[0];
1999 else
2000 pmc->block[i].mmio_base =
2001 devm_ioremap(dev, info[0], info[1]);
2002
2003 pmc->block[i].blk_size = info[1];
2004 pmc->block[i].counters = info[2];
2005 pmc->block[i].type = info[3];
2006
2007 if (!pmc->block[i].mmio_base)
2008 return -ENOMEM;
2009
2010 ret = mlxbf_pmc_create_groups(dev, i);
2011 if (ret == -ENOENT) {
2012 dev_warn(dev, "ignoring unsupported block: '%s'\n", pmc->block_name[i]);
2013 continue;
2014 }
2015 if (ret)
2016 return ret;
2017 }
2018
2019 return 0;
2020 }
2021
mlxbf_pmc_probe(struct platform_device * pdev)2022 static int mlxbf_pmc_probe(struct platform_device *pdev)
2023 {
2024 struct acpi_device *acpi_dev = ACPI_COMPANION(&pdev->dev);
2025 const char *hid = acpi_device_hid(acpi_dev);
2026 struct device *dev = &pdev->dev;
2027 struct arm_smccc_res res;
2028 guid_t guid;
2029 int ret;
2030
2031 /* Ensure we have the UUID we expect for this service. */
2032 arm_smccc_smc(MLXBF_PMC_SIP_SVC_UID, 0, 0, 0, 0, 0, 0, 0, &res);
2033 guid_parse(mlxbf_pmc_svc_uuid_str, &guid);
2034 if (!mlxbf_pmc_guid_match(&guid, &res))
2035 return -ENODEV;
2036
2037 pmc = devm_kzalloc(dev, sizeof(struct mlxbf_pmc_context), GFP_KERNEL);
2038 if (!pmc)
2039 return -ENOMEM;
2040
2041 /*
2042 * ACPI indicates whether we use SMCs to access registers or not.
2043 * If sreg_tbl_perf is not present, just assume we're not using SMCs.
2044 */
2045 ret = device_property_read_u32(dev, "sec_reg_block",
2046 &pmc->sreg_tbl_perf);
2047 if (ret) {
2048 pmc->svc_sreg_support = false;
2049 } else {
2050 /*
2051 * Check service version to see if we actually do support the
2052 * needed SMCs. If we have the calls we need, mark support for
2053 * them in the pmc struct.
2054 */
2055 arm_smccc_smc(MLXBF_PMC_SIP_SVC_VERSION, 0, 0, 0, 0, 0, 0, 0,
2056 &res);
2057 if (res.a0 == MLXBF_PMC_SVC_REQ_MAJOR &&
2058 res.a1 >= MLXBF_PMC_SVC_MIN_MINOR)
2059 pmc->svc_sreg_support = true;
2060 else
2061 return -EINVAL;
2062 }
2063
2064 if (!strcmp(hid, "MLNXBFD0"))
2065 pmc->event_set = MLXBF_PMC_EVENT_SET_BF1;
2066 else if (!strcmp(hid, "MLNXBFD1"))
2067 pmc->event_set = MLXBF_PMC_EVENT_SET_BF2;
2068 else if (!strcmp(hid, "MLNXBFD2"))
2069 pmc->event_set = MLXBF_PMC_EVENT_SET_BF3;
2070 else
2071 return -ENODEV;
2072
2073 ret = device_property_read_u32(dev, "block_num", &pmc->total_blocks);
2074 if (ret)
2075 return ret;
2076
2077 ret = device_property_read_string_array(dev, "block_name",
2078 pmc->block_name,
2079 pmc->total_blocks);
2080 if (ret != pmc->total_blocks)
2081 return -EFAULT;
2082
2083 if (device_property_read_u32(dev, "tile_num", &pmc->tile_count)) {
2084 if (device_property_read_u8(dev, "llt_enable", &pmc->llt_enable)) {
2085 dev_err(dev, "Number of tiles/LLTs undefined\n");
2086 return -EINVAL;
2087 }
2088 if (device_property_read_u8(dev, "mss_enable", &pmc->mss_enable)) {
2089 dev_err(dev, "Number of tiles/MSSs undefined\n");
2090 return -EINVAL;
2091 }
2092 }
2093
2094 pmc->pdev = pdev;
2095 pmc->group_num = 0;
2096
2097 ret = mlxbf_pmc_map_counters(dev);
2098 if (ret)
2099 return ret;
2100
2101 pmc->hwmon_dev = devm_hwmon_device_register_with_groups(
2102 dev, "bfperf", pmc, pmc->groups);
2103 if (IS_ERR(pmc->hwmon_dev))
2104 return PTR_ERR(pmc->hwmon_dev);
2105 platform_set_drvdata(pdev, pmc);
2106
2107 return 0;
2108 }
2109
2110 static const struct acpi_device_id mlxbf_pmc_acpi_ids[] = { { "MLNXBFD0", 0 },
2111 { "MLNXBFD1", 0 },
2112 { "MLNXBFD2", 0 },
2113 {}, };
2114
2115 MODULE_DEVICE_TABLE(acpi, mlxbf_pmc_acpi_ids);
2116 static struct platform_driver pmc_driver = {
2117 .driver = { .name = "mlxbf-pmc",
2118 .acpi_match_table = ACPI_PTR(mlxbf_pmc_acpi_ids), },
2119 .probe = mlxbf_pmc_probe,
2120 };
2121
2122 module_platform_driver(pmc_driver);
2123
2124 MODULE_AUTHOR("Shravan Kumar Ramani <sramani@mellanox.com>");
2125 MODULE_DESCRIPTION("Mellanox PMC driver");
2126 MODULE_LICENSE("Dual BSD/GPL");
2127