1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <asm/amd_nb.h>
14 #include <linux/acpi.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/limits.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/rtc.h>
26 #include <linux/serio.h>
27 #include <linux/suspend.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30
31 #include "pmc.h"
32
33 /* SMU communication registers */
34 #define AMD_PMC_REGISTER_RESPONSE 0x980
35 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
36
37 /* PMC Scratch Registers */
38 #define AMD_PMC_SCRATCH_REG_CZN 0x94
39 #define AMD_PMC_SCRATCH_REG_YC 0xD14
40 #define AMD_PMC_SCRATCH_REG_1AH 0xF14
41
42 /* STB Registers */
43 #define AMD_PMC_STB_PMI_0 0x03E30600
44 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
45 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
46 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
47 #define AMD_PMC_STB_DUMMY_PC 0xC6000007
48
49 /* STB S2D(Spill to DRAM) has different message port offset */
50 #define AMD_S2D_REGISTER_MESSAGE 0xA20
51 #define AMD_S2D_REGISTER_RESPONSE 0xA80
52 #define AMD_S2D_REGISTER_ARGUMENT 0xA88
53
54 /* STB Spill to DRAM Parameters */
55 #define S2D_TELEMETRY_BYTES_MAX 0x100000U
56 #define S2D_RSVD_RAM_SPACE 0x100000
57 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
58
59 /* STB Spill to DRAM Message Definition */
60 #define STB_FORCE_FLUSH_DATA 0xCF
61
62 /* Base address of SMU for mapping physical address to virtual address */
63 #define AMD_PMC_MAPPING_SIZE 0x01000
64 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
65 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
66 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
67 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
68 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
69
70 /* SMU Response Codes */
71 #define AMD_PMC_RESULT_OK 0x01
72 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
73 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
74 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
75 #define AMD_PMC_RESULT_FAILED 0xFF
76
77 /* FCH SSC Registers */
78 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
79 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
80 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
81 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
82 #define FCH_SSC_MAPPING_SIZE 0x800
83 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
84 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
85
86 /* SMU Message Definations */
87 #define SMU_MSG_GETSMUVERSION 0x02
88 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
89 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
90 #define SMU_MSG_LOG_START 0x06
91 #define SMU_MSG_LOG_RESET 0x07
92 #define SMU_MSG_LOG_DUMP_DATA 0x08
93 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
94
95 #define PMC_MSG_DELAY_MIN_US 50
96 #define RESPONSE_REGISTER_LOOP_MAX 20000
97
98 #define DELAY_MIN_US 2000
99 #define DELAY_MAX_US 3000
100 #define FIFO_SIZE 4096
101
102 enum amd_pmc_def {
103 MSG_TEST = 0x01,
104 MSG_OS_HINT_PCO,
105 MSG_OS_HINT_RN,
106 };
107
108 enum s2d_arg {
109 S2D_TELEMETRY_SIZE = 0x01,
110 S2D_PHYS_ADDR_LOW,
111 S2D_PHYS_ADDR_HIGH,
112 S2D_NUM_SAMPLES,
113 S2D_DRAM_SIZE,
114 };
115
116 struct amd_pmc_stb_v2_data {
117 size_t size;
118 u8 data[] __counted_by(size);
119 };
120
121 struct amd_pmc_bit_map {
122 const char *name;
123 u32 bit_mask;
124 };
125
126 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
127 {"DISPLAY", BIT(0)},
128 {"CPU", BIT(1)},
129 {"GFX", BIT(2)},
130 {"VDD", BIT(3)},
131 {"ACP", BIT(4)},
132 {"VCN", BIT(5)},
133 {"ISP", BIT(6)},
134 {"NBIO", BIT(7)},
135 {"DF", BIT(8)},
136 {"USB3_0", BIT(9)},
137 {"USB3_1", BIT(10)},
138 {"LAPIC", BIT(11)},
139 {"USB3_2", BIT(12)},
140 {"USB3_3", BIT(13)},
141 {"USB3_4", BIT(14)},
142 {"USB4_0", BIT(15)},
143 {"USB4_1", BIT(16)},
144 {"MPM", BIT(17)},
145 {"JPEG", BIT(18)},
146 {"IPU", BIT(19)},
147 {"UMSCH", BIT(20)},
148 {"VPE", BIT(21)},
149 {}
150 };
151
152 static bool enable_stb;
153 module_param(enable_stb, bool, 0644);
154 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
155
156 static bool disable_workarounds;
157 module_param(disable_workarounds, bool, 0644);
158 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
159
160 static bool dump_custom_stb;
161 module_param(dump_custom_stb, bool, 0644);
162 MODULE_PARM_DESC(dump_custom_stb, "Enable to dump full STB buffer");
163
164 static struct amd_pmc_dev pmc;
165 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
166 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
167 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
168
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)169 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
170 {
171 return ioread32(dev->regbase + reg_offset);
172 }
173
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)174 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
175 {
176 iowrite32(val, dev->regbase + reg_offset);
177 }
178
179 struct smu_metrics {
180 u32 table_version;
181 u32 hint_count;
182 u32 s0i3_last_entry_status;
183 u32 timein_s0i2;
184 u64 timeentering_s0i3_lastcapture;
185 u64 timeentering_s0i3_totaltime;
186 u64 timeto_resume_to_os_lastcapture;
187 u64 timeto_resume_to_os_totaltime;
188 u64 timein_s0i3_lastcapture;
189 u64 timein_s0i3_totaltime;
190 u64 timein_swdrips_lastcapture;
191 u64 timein_swdrips_totaltime;
192 u64 timecondition_notmet_lastcapture[32];
193 u64 timecondition_notmet_totaltime[32];
194 } __packed;
195
amd_pmc_stb_debugfs_open(struct inode * inode,struct file * filp)196 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
197 {
198 struct amd_pmc_dev *dev = filp->f_inode->i_private;
199 u32 size = FIFO_SIZE * sizeof(u32);
200 u32 *buf;
201 int rc;
202
203 buf = kzalloc(size, GFP_KERNEL);
204 if (!buf)
205 return -ENOMEM;
206
207 rc = amd_pmc_read_stb(dev, buf);
208 if (rc) {
209 kfree(buf);
210 return rc;
211 }
212
213 filp->private_data = buf;
214 return rc;
215 }
216
amd_pmc_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)217 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
218 loff_t *pos)
219 {
220 if (!filp->private_data)
221 return -EINVAL;
222
223 return simple_read_from_buffer(buf, size, pos, filp->private_data,
224 FIFO_SIZE * sizeof(u32));
225 }
226
amd_pmc_stb_debugfs_release(struct inode * inode,struct file * filp)227 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
228 {
229 kfree(filp->private_data);
230 return 0;
231 }
232
233 static const struct file_operations amd_pmc_stb_debugfs_fops = {
234 .owner = THIS_MODULE,
235 .open = amd_pmc_stb_debugfs_open,
236 .read = amd_pmc_stb_debugfs_read,
237 .release = amd_pmc_stb_debugfs_release,
238 };
239
240 /* Enhanced STB Firmware Reporting Mechanism */
amd_pmc_stb_handle_efr(struct file * filp)241 static int amd_pmc_stb_handle_efr(struct file *filp)
242 {
243 struct amd_pmc_dev *dev = filp->f_inode->i_private;
244 struct amd_pmc_stb_v2_data *stb_data_arr;
245 u32 fsize;
246
247 fsize = dev->dram_size - S2D_RSVD_RAM_SPACE;
248 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL);
249 if (!stb_data_arr)
250 return -ENOMEM;
251
252 stb_data_arr->size = fsize;
253 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize);
254 filp->private_data = stb_data_arr;
255
256 return 0;
257 }
258
amd_pmc_stb_debugfs_open_v2(struct inode * inode,struct file * filp)259 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
260 {
261 struct amd_pmc_dev *dev = filp->f_inode->i_private;
262 u32 fsize, num_samples, val, stb_rdptr_offset = 0;
263 struct amd_pmc_stb_v2_data *stb_data_arr;
264 int ret;
265
266 /* Write dummy postcode while reading the STB buffer */
267 ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
268 if (ret)
269 dev_err(dev->dev, "error writing to STB: %d\n", ret);
270
271 /* Spill to DRAM num_samples uses separate SMU message port */
272 dev->msg_port = 1;
273
274 ret = amd_pmc_send_cmd(dev, 0, &val, STB_FORCE_FLUSH_DATA, 1);
275 if (ret)
276 dev_dbg_once(dev->dev, "S2D force flush not supported: %d\n", ret);
277
278 /*
279 * We have a custom stb size and the PMFW is supposed to give
280 * the enhanced dram size. Note that we land here only for the
281 * platforms that support enhanced dram size reporting.
282 */
283 if (dump_custom_stb)
284 return amd_pmc_stb_handle_efr(filp);
285
286 /* Get the num_samples to calculate the last push location */
287 ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
288 /* Clear msg_port for other SMU operation */
289 dev->msg_port = 0;
290 if (ret) {
291 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
292 return ret;
293 }
294
295 fsize = min(num_samples, S2D_TELEMETRY_BYTES_MAX);
296 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL);
297 if (!stb_data_arr)
298 return -ENOMEM;
299
300 stb_data_arr->size = fsize;
301
302 /*
303 * Start capturing data from the last push location.
304 * This is for general cases, where the stb limits
305 * are meant for standard usage.
306 */
307 if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
308 /* First read oldest data starting 1 behind last write till end of ringbuffer */
309 stb_rdptr_offset = num_samples % S2D_TELEMETRY_BYTES_MAX;
310 fsize = S2D_TELEMETRY_BYTES_MAX - stb_rdptr_offset;
311
312 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr + stb_rdptr_offset, fsize);
313 /* Second copy the newer samples from offset 0 - last write */
314 memcpy_fromio(stb_data_arr->data + fsize, dev->stb_virt_addr, stb_rdptr_offset);
315 } else {
316 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize);
317 }
318
319 filp->private_data = stb_data_arr;
320
321 return 0;
322 }
323
amd_pmc_stb_debugfs_read_v2(struct file * filp,char __user * buf,size_t size,loff_t * pos)324 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
325 loff_t *pos)
326 {
327 struct amd_pmc_stb_v2_data *data = filp->private_data;
328
329 return simple_read_from_buffer(buf, size, pos, data->data, data->size);
330 }
331
amd_pmc_stb_debugfs_release_v2(struct inode * inode,struct file * filp)332 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
333 {
334 kfree(filp->private_data);
335 return 0;
336 }
337
338 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
339 .owner = THIS_MODULE,
340 .open = amd_pmc_stb_debugfs_open_v2,
341 .read = amd_pmc_stb_debugfs_read_v2,
342 .release = amd_pmc_stb_debugfs_release_v2,
343 };
344
amd_pmc_get_ip_info(struct amd_pmc_dev * dev)345 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
346 {
347 switch (dev->cpu_id) {
348 case AMD_CPU_ID_PCO:
349 case AMD_CPU_ID_RN:
350 case AMD_CPU_ID_YC:
351 case AMD_CPU_ID_CB:
352 dev->num_ips = 12;
353 dev->s2d_msg_id = 0xBE;
354 dev->smu_msg = 0x538;
355 break;
356 case AMD_CPU_ID_PS:
357 dev->num_ips = 21;
358 dev->s2d_msg_id = 0x85;
359 dev->smu_msg = 0x538;
360 break;
361 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
362 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
363 dev->num_ips = 22;
364 dev->s2d_msg_id = 0xDE;
365 dev->smu_msg = 0x938;
366 break;
367 }
368 }
369
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)370 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
371 {
372 if (dev->cpu_id == AMD_CPU_ID_PCO) {
373 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
374 return -EINVAL;
375 }
376
377 /* Get Active devices list from SMU */
378 if (!dev->active_ips)
379 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
380
381 /* Get dram address */
382 if (!dev->smu_virt_addr) {
383 u32 phys_addr_low, phys_addr_hi;
384 u64 smu_phys_addr;
385
386 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
387 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
388 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
389
390 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
391 sizeof(struct smu_metrics));
392 if (!dev->smu_virt_addr)
393 return -ENOMEM;
394 }
395
396 memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics));
397
398 /* Start the logging */
399 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
400 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
401
402 return 0;
403 }
404
get_metrics_table(struct amd_pmc_dev * pdev,struct smu_metrics * table)405 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
406 {
407 if (!pdev->smu_virt_addr) {
408 int ret = amd_pmc_setup_smu_logging(pdev);
409
410 if (ret)
411 return ret;
412 }
413
414 if (pdev->cpu_id == AMD_CPU_ID_PCO)
415 return -ENODEV;
416 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
417 return 0;
418 }
419
amd_pmc_validate_deepest(struct amd_pmc_dev * pdev)420 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
421 {
422 struct smu_metrics table;
423
424 if (get_metrics_table(pdev, &table))
425 return;
426
427 if (!table.s0i3_last_entry_status)
428 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
429 pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
430 table.timein_s0i3_lastcapture : 0);
431 }
432
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)433 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
434 {
435 int rc;
436 u32 val;
437
438 if (dev->cpu_id == AMD_CPU_ID_PCO)
439 return -ENODEV;
440
441 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
442 if (rc)
443 return rc;
444
445 dev->smu_program = (val >> 24) & GENMASK(7, 0);
446 dev->major = (val >> 16) & GENMASK(7, 0);
447 dev->minor = (val >> 8) & GENMASK(7, 0);
448 dev->rev = (val >> 0) & GENMASK(7, 0);
449
450 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
451 dev->smu_program, dev->major, dev->minor, dev->rev);
452
453 return 0;
454 }
455
smu_fw_version_show(struct device * d,struct device_attribute * attr,char * buf)456 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
457 char *buf)
458 {
459 struct amd_pmc_dev *dev = dev_get_drvdata(d);
460
461 if (!dev->major) {
462 int rc = amd_pmc_get_smu_version(dev);
463
464 if (rc)
465 return rc;
466 }
467 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
468 }
469
smu_program_show(struct device * d,struct device_attribute * attr,char * buf)470 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
471 char *buf)
472 {
473 struct amd_pmc_dev *dev = dev_get_drvdata(d);
474
475 if (!dev->major) {
476 int rc = amd_pmc_get_smu_version(dev);
477
478 if (rc)
479 return rc;
480 }
481 return sysfs_emit(buf, "%u\n", dev->smu_program);
482 }
483
484 static DEVICE_ATTR_RO(smu_fw_version);
485 static DEVICE_ATTR_RO(smu_program);
486
pmc_attr_is_visible(struct kobject * kobj,struct attribute * attr,int idx)487 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
488 {
489 struct device *dev = kobj_to_dev(kobj);
490 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
491
492 if (pdev->cpu_id == AMD_CPU_ID_PCO)
493 return 0;
494 return 0444;
495 }
496
497 static struct attribute *pmc_attrs[] = {
498 &dev_attr_smu_fw_version.attr,
499 &dev_attr_smu_program.attr,
500 NULL,
501 };
502
503 static struct attribute_group pmc_attr_group = {
504 .attrs = pmc_attrs,
505 .is_visible = pmc_attr_is_visible,
506 };
507
508 static const struct attribute_group *pmc_groups[] = {
509 &pmc_attr_group,
510 NULL,
511 };
512
smu_fw_info_show(struct seq_file * s,void * unused)513 static int smu_fw_info_show(struct seq_file *s, void *unused)
514 {
515 struct amd_pmc_dev *dev = s->private;
516 struct smu_metrics table;
517 int idx;
518
519 if (get_metrics_table(dev, &table))
520 return -EINVAL;
521
522 seq_puts(s, "\n=== SMU Statistics ===\n");
523 seq_printf(s, "Table Version: %d\n", table.table_version);
524 seq_printf(s, "Hint Count: %d\n", table.hint_count);
525 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
526 "Unknown/Fail");
527 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
528 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
529 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
530 table.timeto_resume_to_os_lastcapture);
531
532 seq_puts(s, "\n=== Active time (in us) ===\n");
533 for (idx = 0 ; idx < dev->num_ips ; idx++) {
534 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
535 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
536 table.timecondition_notmet_lastcapture[idx]);
537 }
538
539 return 0;
540 }
541 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
542
s0ix_stats_show(struct seq_file * s,void * unused)543 static int s0ix_stats_show(struct seq_file *s, void *unused)
544 {
545 struct amd_pmc_dev *dev = s->private;
546 u64 entry_time, exit_time, residency;
547
548 /* Use FCH registers to get the S0ix stats */
549 if (!dev->fch_virt_addr) {
550 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
551 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
552 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
553
554 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
555 if (!dev->fch_virt_addr)
556 return -ENOMEM;
557 }
558
559 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
560 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
561
562 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
563 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
564
565 /* It's in 48MHz. We need to convert it */
566 residency = exit_time - entry_time;
567 do_div(residency, 48);
568
569 seq_puts(s, "=== S0ix statistics ===\n");
570 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
571 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
572 seq_printf(s, "Residency Time: %lld\n", residency);
573
574 return 0;
575 }
576 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
577
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)578 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
579 struct seq_file *s)
580 {
581 u32 val;
582 int rc;
583
584 switch (pdev->cpu_id) {
585 case AMD_CPU_ID_CZN:
586 /* we haven't yet read SMU version */
587 if (!pdev->major) {
588 rc = amd_pmc_get_smu_version(pdev);
589 if (rc)
590 return rc;
591 }
592 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
593 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
594 else
595 return -EINVAL;
596 break;
597 case AMD_CPU_ID_YC:
598 case AMD_CPU_ID_CB:
599 case AMD_CPU_ID_PS:
600 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
601 break;
602 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
603 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
604 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
605 break;
606 default:
607 return -EINVAL;
608 }
609
610 if (dev)
611 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
612
613 if (s)
614 seq_printf(s, "SMU idlemask : 0x%x\n", val);
615
616 return 0;
617 }
618
amd_pmc_idlemask_show(struct seq_file * s,void * unused)619 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
620 {
621 return amd_pmc_idlemask_read(s->private, NULL, s);
622 }
623 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
624
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)625 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
626 {
627 debugfs_remove_recursive(dev->dbgfs_dir);
628 }
629
amd_pmc_is_stb_supported(struct amd_pmc_dev * dev)630 static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev)
631 {
632 switch (dev->cpu_id) {
633 case AMD_CPU_ID_YC:
634 case AMD_CPU_ID_CB:
635 case AMD_CPU_ID_PS:
636 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
637 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
638 return true;
639 default:
640 return false;
641 }
642 }
643
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)644 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
645 {
646 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
647 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
648 &smu_fw_info_fops);
649 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
650 &s0ix_stats_fops);
651 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
652 &amd_pmc_idlemask_fops);
653 /* Enable STB only when the module_param is set */
654 if (enable_stb) {
655 if (amd_pmc_is_stb_supported(dev))
656 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
657 &amd_pmc_stb_debugfs_fops_v2);
658 else
659 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
660 &amd_pmc_stb_debugfs_fops);
661 }
662 }
663
amd_pmc_dump_registers(struct amd_pmc_dev * dev)664 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
665 {
666 u32 value, message, argument, response;
667
668 if (dev->msg_port) {
669 message = AMD_S2D_REGISTER_MESSAGE;
670 argument = AMD_S2D_REGISTER_ARGUMENT;
671 response = AMD_S2D_REGISTER_RESPONSE;
672 } else {
673 message = dev->smu_msg;
674 argument = AMD_PMC_REGISTER_ARGUMENT;
675 response = AMD_PMC_REGISTER_RESPONSE;
676 }
677
678 value = amd_pmc_reg_read(dev, response);
679 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
680
681 value = amd_pmc_reg_read(dev, argument);
682 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
683
684 value = amd_pmc_reg_read(dev, message);
685 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
686 }
687
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)688 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
689 {
690 int rc;
691 u32 val, message, argument, response;
692
693 mutex_lock(&dev->lock);
694
695 if (dev->msg_port) {
696 message = AMD_S2D_REGISTER_MESSAGE;
697 argument = AMD_S2D_REGISTER_ARGUMENT;
698 response = AMD_S2D_REGISTER_RESPONSE;
699 } else {
700 message = dev->smu_msg;
701 argument = AMD_PMC_REGISTER_ARGUMENT;
702 response = AMD_PMC_REGISTER_RESPONSE;
703 }
704
705 /* Wait until we get a valid response */
706 rc = readx_poll_timeout(ioread32, dev->regbase + response,
707 val, val != 0, PMC_MSG_DELAY_MIN_US,
708 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
709 if (rc) {
710 dev_err(dev->dev, "failed to talk to SMU\n");
711 goto out_unlock;
712 }
713
714 /* Write zero to response register */
715 amd_pmc_reg_write(dev, response, 0);
716
717 /* Write argument into response register */
718 amd_pmc_reg_write(dev, argument, arg);
719
720 /* Write message ID to message ID register */
721 amd_pmc_reg_write(dev, message, msg);
722
723 /* Wait until we get a valid response */
724 rc = readx_poll_timeout(ioread32, dev->regbase + response,
725 val, val != 0, PMC_MSG_DELAY_MIN_US,
726 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
727 if (rc) {
728 dev_err(dev->dev, "SMU response timed out\n");
729 goto out_unlock;
730 }
731
732 switch (val) {
733 case AMD_PMC_RESULT_OK:
734 if (ret) {
735 /* PMFW may take longer time to return back the data */
736 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
737 *data = amd_pmc_reg_read(dev, argument);
738 }
739 break;
740 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
741 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
742 rc = -EBUSY;
743 goto out_unlock;
744 case AMD_PMC_RESULT_CMD_UNKNOWN:
745 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
746 rc = -EINVAL;
747 goto out_unlock;
748 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
749 case AMD_PMC_RESULT_FAILED:
750 default:
751 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
752 rc = -EIO;
753 goto out_unlock;
754 }
755
756 out_unlock:
757 mutex_unlock(&dev->lock);
758 amd_pmc_dump_registers(dev);
759 return rc;
760 }
761
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)762 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
763 {
764 switch (dev->cpu_id) {
765 case AMD_CPU_ID_PCO:
766 return MSG_OS_HINT_PCO;
767 case AMD_CPU_ID_RN:
768 case AMD_CPU_ID_YC:
769 case AMD_CPU_ID_CB:
770 case AMD_CPU_ID_PS:
771 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
772 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
773 return MSG_OS_HINT_RN;
774 }
775 return -EINVAL;
776 }
777
amd_pmc_wa_irq1(struct amd_pmc_dev * pdev)778 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
779 {
780 struct device *d;
781 int rc;
782
783 /* cezanne platform firmware has a fix in 64.66.0 */
784 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
785 if (!pdev->major) {
786 rc = amd_pmc_get_smu_version(pdev);
787 if (rc)
788 return rc;
789 }
790
791 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
792 return 0;
793 }
794
795 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
796 if (!d)
797 return 0;
798 if (device_may_wakeup(d)) {
799 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
800 disable_irq_wake(1);
801 device_set_wakeup_enable(d, false);
802 }
803 put_device(d);
804
805 return 0;
806 }
807
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)808 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
809 {
810 struct rtc_device *rtc_device;
811 time64_t then, now, duration;
812 struct rtc_wkalrm alarm;
813 struct rtc_time tm;
814 int rc;
815
816 /* we haven't yet read SMU version */
817 if (!pdev->major) {
818 rc = amd_pmc_get_smu_version(pdev);
819 if (rc)
820 return rc;
821 }
822
823 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
824 return 0;
825
826 rtc_device = rtc_class_open("rtc0");
827 if (!rtc_device)
828 return 0;
829 rc = rtc_read_alarm(rtc_device, &alarm);
830 if (rc)
831 return rc;
832 if (!alarm.enabled) {
833 dev_dbg(pdev->dev, "alarm not enabled\n");
834 return 0;
835 }
836 rc = rtc_read_time(rtc_device, &tm);
837 if (rc)
838 return rc;
839 then = rtc_tm_to_time64(&alarm.time);
840 now = rtc_tm_to_time64(&tm);
841 duration = then-now;
842
843 /* in the past */
844 if (then < now)
845 return 0;
846
847 /* will be stored in upper 16 bits of s0i3 hint argument,
848 * so timer wakeup from s0i3 is limited to ~18 hours or less
849 */
850 if (duration <= 4 || duration > U16_MAX)
851 return -EINVAL;
852
853 *arg |= (duration << 16);
854 rc = rtc_alarm_irq_enable(rtc_device, 0);
855 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
856
857 return rc;
858 }
859
amd_pmc_s2idle_prepare(void)860 static void amd_pmc_s2idle_prepare(void)
861 {
862 struct amd_pmc_dev *pdev = &pmc;
863 int rc;
864 u8 msg;
865 u32 arg = 1;
866
867 /* Reset and Start SMU logging - to monitor the s0i3 stats */
868 amd_pmc_setup_smu_logging(pdev);
869
870 /* Activate CZN specific platform bug workarounds */
871 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
872 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
873 if (rc) {
874 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
875 return;
876 }
877 }
878
879 msg = amd_pmc_get_os_hint(pdev);
880 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
881 if (rc) {
882 dev_err(pdev->dev, "suspend failed: %d\n", rc);
883 return;
884 }
885
886 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
887 if (rc)
888 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
889 }
890
amd_pmc_s2idle_check(void)891 static void amd_pmc_s2idle_check(void)
892 {
893 struct amd_pmc_dev *pdev = &pmc;
894 struct smu_metrics table;
895 int rc;
896
897 /* Avoid triggering OVP */
898 if (!get_metrics_table(pdev, &table) && table.s0i3_last_entry_status)
899 msleep(2500);
900
901 /* Dump the IdleMask before we add to the STB */
902 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
903
904 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
905 if (rc)
906 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
907 }
908
amd_pmc_dump_data(struct amd_pmc_dev * pdev)909 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
910 {
911 if (pdev->cpu_id == AMD_CPU_ID_PCO)
912 return -ENODEV;
913
914 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
915 }
916
amd_pmc_s2idle_restore(void)917 static void amd_pmc_s2idle_restore(void)
918 {
919 struct amd_pmc_dev *pdev = &pmc;
920 int rc;
921 u8 msg;
922
923 msg = amd_pmc_get_os_hint(pdev);
924 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
925 if (rc)
926 dev_err(pdev->dev, "resume failed: %d\n", rc);
927
928 /* Let SMU know that we are looking for stats */
929 amd_pmc_dump_data(pdev);
930
931 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
932 if (rc)
933 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
934
935 /* Notify on failed entry */
936 amd_pmc_validate_deepest(pdev);
937
938 amd_pmc_process_restore_quirks(pdev);
939 }
940
941 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
942 .prepare = amd_pmc_s2idle_prepare,
943 .check = amd_pmc_s2idle_check,
944 .restore = amd_pmc_s2idle_restore,
945 };
946
amd_pmc_suspend_handler(struct device * dev)947 static int amd_pmc_suspend_handler(struct device *dev)
948 {
949 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
950
951 /*
952 * Must be called only from the same set of dev_pm_ops handlers
953 * as i8042_pm_suspend() is called: currently just from .suspend.
954 */
955 if (pdev->disable_8042_wakeup && !disable_workarounds) {
956 int rc = amd_pmc_wa_irq1(pdev);
957
958 if (rc) {
959 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
960 return rc;
961 }
962 }
963
964 return 0;
965 }
966
967 static const struct dev_pm_ops amd_pmc_pm = {
968 .suspend = amd_pmc_suspend_handler,
969 };
970
971 static const struct pci_device_id pmc_pci_ids[] = {
972 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
973 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
974 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
975 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
976 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
977 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
978 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
979 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
980 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
981 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
982 { }
983 };
984
amd_pmc_s2d_init(struct amd_pmc_dev * dev)985 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
986 {
987 u32 phys_addr_low, phys_addr_hi;
988 u64 stb_phys_addr;
989 u32 size = 0;
990 int ret;
991
992 /* Spill to DRAM feature uses separate SMU message port */
993 dev->msg_port = 1;
994
995 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
996 if (size != S2D_TELEMETRY_BYTES_MAX)
997 return -EIO;
998
999 /* Get DRAM size */
1000 ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
1001 if (ret || !dev->dram_size)
1002 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
1003
1004 /* Get STB DRAM address */
1005 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
1006 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
1007
1008 if (!phys_addr_hi && !phys_addr_low) {
1009 dev_err(dev->dev, "STB is not enabled on the system; disable enable_stb or contact system vendor\n");
1010 return -EINVAL;
1011 }
1012
1013 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
1014
1015 /* Clear msg_port for other SMU operation */
1016 dev->msg_port = 0;
1017
1018 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
1019 if (!dev->stb_virt_addr)
1020 return -ENOMEM;
1021
1022 return 0;
1023 }
1024
amd_pmc_write_stb(struct amd_pmc_dev * dev,u32 data)1025 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
1026 {
1027 int err;
1028
1029 err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
1030 if (err) {
1031 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
1032 return pcibios_err_to_errno(err);
1033 }
1034
1035 return 0;
1036 }
1037
amd_pmc_read_stb(struct amd_pmc_dev * dev,u32 * buf)1038 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
1039 {
1040 int i, err;
1041
1042 for (i = 0; i < FIFO_SIZE; i++) {
1043 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
1044 if (err) {
1045 dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
1046 return pcibios_err_to_errno(err);
1047 }
1048 }
1049
1050 return 0;
1051 }
1052
amd_pmc_probe(struct platform_device * pdev)1053 static int amd_pmc_probe(struct platform_device *pdev)
1054 {
1055 struct amd_pmc_dev *dev = &pmc;
1056 struct pci_dev *rdev;
1057 u32 base_addr_lo, base_addr_hi;
1058 u64 base_addr;
1059 int err;
1060 u32 val;
1061
1062 dev->dev = &pdev->dev;
1063
1064 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
1065 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
1066 err = -ENODEV;
1067 goto err_pci_dev_put;
1068 }
1069
1070 dev->cpu_id = rdev->device;
1071
1072 if (dev->cpu_id == AMD_CPU_ID_SP) {
1073 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
1074 err = -ENODEV;
1075 goto err_pci_dev_put;
1076 }
1077
1078 dev->rdev = rdev;
1079 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
1080 if (err) {
1081 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
1082 err = pcibios_err_to_errno(err);
1083 goto err_pci_dev_put;
1084 }
1085
1086 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
1087
1088 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
1089 if (err) {
1090 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
1091 err = pcibios_err_to_errno(err);
1092 goto err_pci_dev_put;
1093 }
1094
1095 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
1096 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
1097
1098 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
1099 AMD_PMC_MAPPING_SIZE);
1100 if (!dev->regbase) {
1101 err = -ENOMEM;
1102 goto err_pci_dev_put;
1103 }
1104
1105 mutex_init(&dev->lock);
1106
1107 /* Get num of IP blocks within the SoC */
1108 amd_pmc_get_ip_info(dev);
1109
1110 if (enable_stb && amd_pmc_is_stb_supported(dev)) {
1111 err = amd_pmc_s2d_init(dev);
1112 if (err)
1113 goto err_pci_dev_put;
1114 }
1115
1116 platform_set_drvdata(pdev, dev);
1117 if (IS_ENABLED(CONFIG_SUSPEND)) {
1118 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1119 if (err)
1120 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1121 if (!disable_workarounds)
1122 amd_pmc_quirks_init(dev);
1123 }
1124
1125 amd_pmc_dbgfs_register(dev);
1126 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
1127 amd_mp2_stb_init(dev);
1128 pm_report_max_hw_sleep(U64_MAX);
1129 return 0;
1130
1131 err_pci_dev_put:
1132 pci_dev_put(rdev);
1133 return err;
1134 }
1135
amd_pmc_remove(struct platform_device * pdev)1136 static void amd_pmc_remove(struct platform_device *pdev)
1137 {
1138 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1139
1140 if (IS_ENABLED(CONFIG_SUSPEND))
1141 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1142 amd_pmc_dbgfs_unregister(dev);
1143 pci_dev_put(dev->rdev);
1144 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
1145 amd_mp2_stb_deinit(dev);
1146 mutex_destroy(&dev->lock);
1147 }
1148
1149 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1150 {"AMDI0005", 0},
1151 {"AMDI0006", 0},
1152 {"AMDI0007", 0},
1153 {"AMDI0008", 0},
1154 {"AMDI0009", 0},
1155 {"AMDI000A", 0},
1156 {"AMDI000B", 0},
1157 {"AMD0004", 0},
1158 {"AMD0005", 0},
1159 { }
1160 };
1161 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1162
1163 static struct platform_driver amd_pmc_driver = {
1164 .driver = {
1165 .name = "amd_pmc",
1166 .acpi_match_table = amd_pmc_acpi_ids,
1167 .dev_groups = pmc_groups,
1168 .pm = pm_sleep_ptr(&amd_pmc_pm),
1169 },
1170 .probe = amd_pmc_probe,
1171 .remove_new = amd_pmc_remove,
1172 };
1173 module_platform_driver(amd_pmc_driver);
1174
1175 MODULE_LICENSE("GPL v2");
1176 MODULE_DESCRIPTION("AMD PMC Driver");
1177