1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Common code for Intel Running Average Power Limit (RAPL) support.
4 * Copyright (c) 2019, Intel Corporation.
5 */
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/bitmap.h>
9 #include <linux/cleanup.h>
10 #include <linux/cpu.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/intel_rapl.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/log2.h>
17 #include <linux/module.h>
18 #include <linux/nospec.h>
19 #include <linux/perf_event.h>
20 #include <linux/platform_device.h>
21 #include <linux/powercap.h>
22 #include <linux/processor.h>
23 #include <linux/slab.h>
24 #include <linux/suspend.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27
28 #include <asm/cpu_device_id.h>
29 #include <asm/intel-family.h>
30 #include <asm/iosf_mbi.h>
31
32 /* bitmasks for RAPL MSRs, used by primitive access functions */
33 #define ENERGY_STATUS_MASK 0xffffffff
34
35 #define POWER_LIMIT1_MASK 0x7FFF
36 #define POWER_LIMIT1_ENABLE BIT(15)
37 #define POWER_LIMIT1_CLAMP BIT(16)
38
39 #define POWER_LIMIT2_MASK (0x7FFFULL<<32)
40 #define POWER_LIMIT2_ENABLE BIT_ULL(47)
41 #define POWER_LIMIT2_CLAMP BIT_ULL(48)
42 #define POWER_HIGH_LOCK BIT_ULL(63)
43 #define POWER_LOW_LOCK BIT(31)
44
45 #define POWER_LIMIT4_MASK 0x1FFF
46
47 #define TIME_WINDOW1_MASK (0x7FULL<<17)
48 #define TIME_WINDOW2_MASK (0x7FULL<<49)
49
50 #define POWER_UNIT_OFFSET 0
51 #define POWER_UNIT_MASK 0x0F
52
53 #define ENERGY_UNIT_OFFSET 0x08
54 #define ENERGY_UNIT_MASK 0x1F00
55
56 #define TIME_UNIT_OFFSET 0x10
57 #define TIME_UNIT_MASK 0xF0000
58
59 #define POWER_INFO_MAX_MASK (0x7fffULL<<32)
60 #define POWER_INFO_MIN_MASK (0x7fffULL<<16)
61 #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
62 #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
63
64 #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
65 #define PP_POLICY_MASK 0x1F
66
67 /*
68 * SPR has different layout for Psys Domain PowerLimit registers.
69 * There are 17 bits of PL1 and PL2 instead of 15 bits.
70 * The Enable bits and TimeWindow bits are also shifted as a result.
71 */
72 #define PSYS_POWER_LIMIT1_MASK 0x1FFFF
73 #define PSYS_POWER_LIMIT1_ENABLE BIT(17)
74
75 #define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
76 #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
77
78 #define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
79 #define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
80
81 /* bitmasks for RAPL TPMI, used by primitive access functions */
82 #define TPMI_POWER_LIMIT_MASK 0x3FFFF
83 #define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
84 #define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
85 #define TPMI_INFO_SPEC_MASK 0x3FFFF
86 #define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
87 #define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
88 #define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54)
89
90 /* Non HW constants */
91 #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
92 #define RAPL_PRIMITIVE_DUMMY BIT(2)
93
94 #define TIME_WINDOW_MAX_MSEC 40000
95 #define TIME_WINDOW_MIN_MSEC 250
96 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
97 enum unit_type {
98 ARBITRARY_UNIT, /* no translation */
99 POWER_UNIT,
100 ENERGY_UNIT,
101 TIME_UNIT,
102 };
103
104 /* per domain data, some are optional */
105 #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
106
107 #define DOMAIN_STATE_INACTIVE BIT(0)
108 #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
109
110 static const char *pl_names[NR_POWER_LIMITS] = {
111 [POWER_LIMIT1] = "long_term",
112 [POWER_LIMIT2] = "short_term",
113 [POWER_LIMIT4] = "peak_power",
114 };
115
116 enum pl_prims {
117 PL_ENABLE,
118 PL_CLAMP,
119 PL_LIMIT,
120 PL_TIME_WINDOW,
121 PL_MAX_POWER,
122 PL_LOCK,
123 };
124
is_pl_valid(struct rapl_domain * rd,int pl)125 static bool is_pl_valid(struct rapl_domain *rd, int pl)
126 {
127 if (pl < POWER_LIMIT1 || pl > POWER_LIMIT4)
128 return false;
129 return rd->rpl[pl].name ? true : false;
130 }
131
get_pl_lock_prim(struct rapl_domain * rd,int pl)132 static int get_pl_lock_prim(struct rapl_domain *rd, int pl)
133 {
134 if (rd->rp->priv->type == RAPL_IF_TPMI) {
135 if (pl == POWER_LIMIT1)
136 return PL1_LOCK;
137 if (pl == POWER_LIMIT2)
138 return PL2_LOCK;
139 if (pl == POWER_LIMIT4)
140 return PL4_LOCK;
141 }
142
143 /* MSR/MMIO Interface doesn't have Lock bit for PL4 */
144 if (pl == POWER_LIMIT4)
145 return -EINVAL;
146
147 /*
148 * Power Limit register that supports two power limits has a different
149 * bit position for the Lock bit.
150 */
151 if (rd->rp->priv->limits[rd->id] & BIT(POWER_LIMIT2))
152 return FW_HIGH_LOCK;
153 return FW_LOCK;
154 }
155
get_pl_prim(struct rapl_domain * rd,int pl,enum pl_prims prim)156 static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim)
157 {
158 switch (pl) {
159 case POWER_LIMIT1:
160 if (prim == PL_ENABLE)
161 return PL1_ENABLE;
162 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI)
163 return PL1_CLAMP;
164 if (prim == PL_LIMIT)
165 return POWER_LIMIT1;
166 if (prim == PL_TIME_WINDOW)
167 return TIME_WINDOW1;
168 if (prim == PL_MAX_POWER)
169 return THERMAL_SPEC_POWER;
170 if (prim == PL_LOCK)
171 return get_pl_lock_prim(rd, pl);
172 return -EINVAL;
173 case POWER_LIMIT2:
174 if (prim == PL_ENABLE)
175 return PL2_ENABLE;
176 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI)
177 return PL2_CLAMP;
178 if (prim == PL_LIMIT)
179 return POWER_LIMIT2;
180 if (prim == PL_TIME_WINDOW)
181 return TIME_WINDOW2;
182 if (prim == PL_MAX_POWER)
183 return MAX_POWER;
184 if (prim == PL_LOCK)
185 return get_pl_lock_prim(rd, pl);
186 return -EINVAL;
187 case POWER_LIMIT4:
188 if (prim == PL_LIMIT)
189 return POWER_LIMIT4;
190 if (prim == PL_ENABLE)
191 return PL4_ENABLE;
192 /* PL4 would be around two times PL2, use same prim as PL2. */
193 if (prim == PL_MAX_POWER)
194 return MAX_POWER;
195 if (prim == PL_LOCK)
196 return get_pl_lock_prim(rd, pl);
197 return -EINVAL;
198 default:
199 return -EINVAL;
200 }
201 }
202
203 #define power_zone_to_rapl_domain(_zone) \
204 container_of(_zone, struct rapl_domain, power_zone)
205
206 struct rapl_defaults {
207 u8 floor_freq_reg_addr;
208 int (*check_unit)(struct rapl_domain *rd);
209 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
210 u64 (*compute_time_window)(struct rapl_domain *rd, u64 val,
211 bool to_raw);
212 unsigned int dram_domain_energy_unit;
213 unsigned int psys_domain_energy_unit;
214 bool spr_psys_bits;
215 };
216 static struct rapl_defaults *defaults_msr;
217 static const struct rapl_defaults defaults_tpmi;
218
get_defaults(struct rapl_package * rp)219 static struct rapl_defaults *get_defaults(struct rapl_package *rp)
220 {
221 return rp->priv->defaults;
222 }
223
224 /* Sideband MBI registers */
225 #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
226 #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
227
228 #define PACKAGE_PLN_INT_SAVED BIT(0)
229 #define MAX_PRIM_NAME (32)
230
231 /* per domain data. used to describe individual knobs such that access function
232 * can be consolidated into one instead of many inline functions.
233 */
234 struct rapl_primitive_info {
235 const char *name;
236 u64 mask;
237 int shift;
238 enum rapl_domain_reg_id id;
239 enum unit_type unit;
240 u32 flag;
241 };
242
243 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
244 .name = #p, \
245 .mask = m, \
246 .shift = s, \
247 .id = i, \
248 .unit = u, \
249 .flag = f \
250 }
251
252 static void rapl_init_domains(struct rapl_package *rp);
253 static int rapl_read_data_raw(struct rapl_domain *rd,
254 enum rapl_primitives prim,
255 bool xlate, u64 *data);
256 static int rapl_write_data_raw(struct rapl_domain *rd,
257 enum rapl_primitives prim,
258 unsigned long long value);
259 static int rapl_read_pl_data(struct rapl_domain *rd, int pl,
260 enum pl_prims pl_prim,
261 bool xlate, u64 *data);
262 static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
263 enum pl_prims pl_prim,
264 unsigned long long value);
265 static u64 rapl_unit_xlate(struct rapl_domain *rd,
266 enum unit_type type, u64 value, int to_raw);
267 static void package_power_limit_irq_save(struct rapl_package *rp);
268
269 static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
270
271 static const char *const rapl_domain_names[] = {
272 "package",
273 "core",
274 "uncore",
275 "dram",
276 "psys",
277 };
278
get_energy_counter(struct powercap_zone * power_zone,u64 * energy_raw)279 static int get_energy_counter(struct powercap_zone *power_zone,
280 u64 *energy_raw)
281 {
282 struct rapl_domain *rd;
283 u64 energy_now;
284
285 /* prevent CPU hotplug, make sure the RAPL domain does not go
286 * away while reading the counter.
287 */
288 cpus_read_lock();
289 rd = power_zone_to_rapl_domain(power_zone);
290
291 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
292 *energy_raw = energy_now;
293 cpus_read_unlock();
294
295 return 0;
296 }
297 cpus_read_unlock();
298
299 return -EIO;
300 }
301
get_max_energy_counter(struct powercap_zone * pcd_dev,u64 * energy)302 static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
303 {
304 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
305
306 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
307 return 0;
308 }
309
release_zone(struct powercap_zone * power_zone)310 static int release_zone(struct powercap_zone *power_zone)
311 {
312 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
313 struct rapl_package *rp = rd->rp;
314
315 /* package zone is the last zone of a package, we can free
316 * memory here since all children has been unregistered.
317 */
318 if (rd->id == RAPL_DOMAIN_PACKAGE) {
319 kfree(rd);
320 rp->domains = NULL;
321 }
322
323 return 0;
324
325 }
326
find_nr_power_limit(struct rapl_domain * rd)327 static int find_nr_power_limit(struct rapl_domain *rd)
328 {
329 int i, nr_pl = 0;
330
331 for (i = 0; i < NR_POWER_LIMITS; i++) {
332 if (is_pl_valid(rd, i))
333 nr_pl++;
334 }
335
336 return nr_pl;
337 }
338
set_domain_enable(struct powercap_zone * power_zone,bool mode)339 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
340 {
341 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
342 struct rapl_defaults *defaults = get_defaults(rd->rp);
343 u64 val;
344 int ret;
345
346 cpus_read_lock();
347 ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode);
348 if (ret)
349 goto end;
350
351 ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, false, &val);
352 if (ret)
353 goto end;
354
355 if (mode != val) {
356 pr_debug("%s cannot be %s\n", power_zone->name,
357 str_enabled_disabled(mode));
358 goto end;
359 }
360
361 if (defaults->set_floor_freq)
362 defaults->set_floor_freq(rd, mode);
363
364 end:
365 cpus_read_unlock();
366
367 return ret;
368 }
369
get_domain_enable(struct powercap_zone * power_zone,bool * mode)370 static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
371 {
372 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
373 u64 val;
374 int ret;
375
376 if (rd->rpl[POWER_LIMIT1].locked) {
377 *mode = false;
378 return 0;
379 }
380 cpus_read_lock();
381 ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, true, &val);
382 if (!ret)
383 *mode = val;
384 cpus_read_unlock();
385
386 return ret;
387 }
388
389 /* per RAPL domain ops, in the order of rapl_domain_type */
390 static const struct powercap_zone_ops zone_ops[] = {
391 /* RAPL_DOMAIN_PACKAGE */
392 {
393 .get_energy_uj = get_energy_counter,
394 .get_max_energy_range_uj = get_max_energy_counter,
395 .release = release_zone,
396 .set_enable = set_domain_enable,
397 .get_enable = get_domain_enable,
398 },
399 /* RAPL_DOMAIN_PP0 */
400 {
401 .get_energy_uj = get_energy_counter,
402 .get_max_energy_range_uj = get_max_energy_counter,
403 .release = release_zone,
404 .set_enable = set_domain_enable,
405 .get_enable = get_domain_enable,
406 },
407 /* RAPL_DOMAIN_PP1 */
408 {
409 .get_energy_uj = get_energy_counter,
410 .get_max_energy_range_uj = get_max_energy_counter,
411 .release = release_zone,
412 .set_enable = set_domain_enable,
413 .get_enable = get_domain_enable,
414 },
415 /* RAPL_DOMAIN_DRAM */
416 {
417 .get_energy_uj = get_energy_counter,
418 .get_max_energy_range_uj = get_max_energy_counter,
419 .release = release_zone,
420 .set_enable = set_domain_enable,
421 .get_enable = get_domain_enable,
422 },
423 /* RAPL_DOMAIN_PLATFORM */
424 {
425 .get_energy_uj = get_energy_counter,
426 .get_max_energy_range_uj = get_max_energy_counter,
427 .release = release_zone,
428 .set_enable = set_domain_enable,
429 .get_enable = get_domain_enable,
430 },
431 };
432
433 /*
434 * Constraint index used by powercap can be different than power limit (PL)
435 * index in that some PLs maybe missing due to non-existent MSRs. So we
436 * need to convert here by finding the valid PLs only (name populated).
437 */
contraint_to_pl(struct rapl_domain * rd,int cid)438 static int contraint_to_pl(struct rapl_domain *rd, int cid)
439 {
440 int i, j;
441
442 for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) {
443 if (is_pl_valid(rd, i) && j++ == cid) {
444 pr_debug("%s: index %d\n", __func__, i);
445 return i;
446 }
447 }
448 pr_err("Cannot find matching power limit for constraint %d\n", cid);
449
450 return -EINVAL;
451 }
452
set_power_limit(struct powercap_zone * power_zone,int cid,u64 power_limit)453 static int set_power_limit(struct powercap_zone *power_zone, int cid,
454 u64 power_limit)
455 {
456 struct rapl_domain *rd;
457 struct rapl_package *rp;
458 int ret = 0;
459 int id;
460
461 cpus_read_lock();
462 rd = power_zone_to_rapl_domain(power_zone);
463 id = contraint_to_pl(rd, cid);
464 rp = rd->rp;
465
466 ret = rapl_write_pl_data(rd, id, PL_LIMIT, power_limit);
467 if (!ret)
468 package_power_limit_irq_save(rp);
469 cpus_read_unlock();
470 return ret;
471 }
472
get_current_power_limit(struct powercap_zone * power_zone,int cid,u64 * data)473 static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
474 u64 *data)
475 {
476 struct rapl_domain *rd;
477 u64 val;
478 int ret = 0;
479 int id;
480
481 cpus_read_lock();
482 rd = power_zone_to_rapl_domain(power_zone);
483 id = contraint_to_pl(rd, cid);
484
485 ret = rapl_read_pl_data(rd, id, PL_LIMIT, true, &val);
486 if (!ret)
487 *data = val;
488
489 cpus_read_unlock();
490
491 return ret;
492 }
493
set_time_window(struct powercap_zone * power_zone,int cid,u64 window)494 static int set_time_window(struct powercap_zone *power_zone, int cid,
495 u64 window)
496 {
497 struct rapl_domain *rd;
498 int ret = 0;
499 int id;
500
501 cpus_read_lock();
502 rd = power_zone_to_rapl_domain(power_zone);
503 id = contraint_to_pl(rd, cid);
504
505 ret = rapl_write_pl_data(rd, id, PL_TIME_WINDOW, window);
506
507 cpus_read_unlock();
508 return ret;
509 }
510
get_time_window(struct powercap_zone * power_zone,int cid,u64 * data)511 static int get_time_window(struct powercap_zone *power_zone, int cid,
512 u64 *data)
513 {
514 struct rapl_domain *rd;
515 u64 val;
516 int ret = 0;
517 int id;
518
519 cpus_read_lock();
520 rd = power_zone_to_rapl_domain(power_zone);
521 id = contraint_to_pl(rd, cid);
522
523 ret = rapl_read_pl_data(rd, id, PL_TIME_WINDOW, true, &val);
524 if (!ret)
525 *data = val;
526
527 cpus_read_unlock();
528
529 return ret;
530 }
531
get_constraint_name(struct powercap_zone * power_zone,int cid)532 static const char *get_constraint_name(struct powercap_zone *power_zone,
533 int cid)
534 {
535 struct rapl_domain *rd;
536 int id;
537
538 rd = power_zone_to_rapl_domain(power_zone);
539 id = contraint_to_pl(rd, cid);
540 if (id >= 0)
541 return rd->rpl[id].name;
542
543 return NULL;
544 }
545
get_max_power(struct powercap_zone * power_zone,int cid,u64 * data)546 static int get_max_power(struct powercap_zone *power_zone, int cid, u64 *data)
547 {
548 struct rapl_domain *rd;
549 u64 val;
550 int ret = 0;
551 int id;
552
553 cpus_read_lock();
554 rd = power_zone_to_rapl_domain(power_zone);
555 id = contraint_to_pl(rd, cid);
556
557 ret = rapl_read_pl_data(rd, id, PL_MAX_POWER, true, &val);
558 if (!ret)
559 *data = val;
560
561 /* As a generalization rule, PL4 would be around two times PL2. */
562 if (id == POWER_LIMIT4)
563 *data = *data * 2;
564
565 cpus_read_unlock();
566
567 return ret;
568 }
569
570 static const struct powercap_zone_constraint_ops constraint_ops = {
571 .set_power_limit_uw = set_power_limit,
572 .get_power_limit_uw = get_current_power_limit,
573 .set_time_window_us = set_time_window,
574 .get_time_window_us = get_time_window,
575 .get_max_power_uw = get_max_power,
576 .get_name = get_constraint_name,
577 };
578
579 /* Return the id used for read_raw/write_raw callback */
get_rid(struct rapl_package * rp)580 static int get_rid(struct rapl_package *rp)
581 {
582 return rp->lead_cpu >= 0 ? rp->lead_cpu : rp->id;
583 }
584
585 /* called after domain detection and package level data are set */
rapl_init_domains(struct rapl_package * rp)586 static void rapl_init_domains(struct rapl_package *rp)
587 {
588 enum rapl_domain_type i;
589 enum rapl_domain_reg_id j;
590 struct rapl_domain *rd = rp->domains;
591
592 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
593 unsigned int mask = rp->domain_map & (1 << i);
594 int t;
595
596 if (!mask)
597 continue;
598
599 rd->rp = rp;
600
601 if (i == RAPL_DOMAIN_PLATFORM && rp->id > 0) {
602 snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "psys-%d",
603 rp->lead_cpu >= 0 ? topology_physical_package_id(rp->lead_cpu) :
604 rp->id);
605 } else {
606 snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "%s",
607 rapl_domain_names[i]);
608 }
609
610 rd->id = i;
611
612 /* PL1 is supported by default */
613 rp->priv->limits[i] |= BIT(POWER_LIMIT1);
614
615 for (t = POWER_LIMIT1; t < NR_POWER_LIMITS; t++) {
616 if (rp->priv->limits[i] & BIT(t))
617 rd->rpl[t].name = pl_names[t];
618 }
619
620 for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++)
621 rd->regs[j] = rp->priv->regs[i][j];
622
623 rd++;
624 }
625 }
626
rapl_unit_xlate(struct rapl_domain * rd,enum unit_type type,u64 value,int to_raw)627 static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
628 u64 value, int to_raw)
629 {
630 u64 units = 1;
631 struct rapl_defaults *defaults = get_defaults(rd->rp);
632 u64 scale = 1;
633
634 switch (type) {
635 case POWER_UNIT:
636 units = rd->power_unit;
637 break;
638 case ENERGY_UNIT:
639 scale = ENERGY_UNIT_SCALE;
640 units = rd->energy_unit;
641 break;
642 case TIME_UNIT:
643 return defaults->compute_time_window(rd, value, to_raw);
644 case ARBITRARY_UNIT:
645 default:
646 return value;
647 }
648
649 if (to_raw)
650 return div64_u64(value, units) * scale;
651
652 value *= units;
653
654 return div64_u64(value, scale);
655 }
656
657 /* RAPL primitives for MSR and MMIO I/F */
658 static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
659 /* name, mask, shift, msr index, unit divisor */
660 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
661 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
662 [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
663 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
664 [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
665 RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
666 [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
667 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
668 [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
669 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
670 [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
671 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
672 [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
673 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
674 [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
675 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
676 [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
677 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
678 [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
679 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
680 [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
681 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
682 [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
683 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
684 [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
685 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
686 [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
687 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
688 [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
689 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
690 [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
691 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
692 [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
693 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
694 [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
695 RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
696 [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
697 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
698 [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32,
699 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
700 [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17,
701 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
702 [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49,
703 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
704 [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19,
705 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
706 [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51,
707 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
708 /* non-hardware */
709 [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
710 RAPL_PRIMITIVE_DERIVED),
711 };
712
713 /* RAPL primitives for TPMI I/F */
714 static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = {
715 /* name, mask, shift, msr index, unit divisor */
716 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
717 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
718 [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0,
719 RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0),
720 [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0,
721 RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
722 [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
723 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
724 [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63,
725 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
726 [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63,
727 RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
728 [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63,
729 RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
730 [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
731 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
732 [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
733 RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
734 [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
735 RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
736 [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18,
737 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
738 [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18,
739 RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0),
740 [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0,
741 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
742 [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36,
743 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
744 [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18,
745 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
746 [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 54,
747 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
748 [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
749 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
750 /* non-hardware */
751 [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0,
752 POWER_UNIT, RAPL_PRIMITIVE_DERIVED),
753 };
754
get_rpi(struct rapl_package * rp,int prim)755 static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim)
756 {
757 struct rapl_primitive_info *rpi = rp->priv->rpi;
758
759 if (prim < 0 || prim >= NR_RAPL_PRIMITIVES || !rpi)
760 return NULL;
761
762 return &rpi[prim];
763 }
764
rapl_config(struct rapl_package * rp)765 static int rapl_config(struct rapl_package *rp)
766 {
767 switch (rp->priv->type) {
768 /* MMIO I/F shares the same register layout as MSR registers */
769 case RAPL_IF_MMIO:
770 case RAPL_IF_MSR:
771 rp->priv->defaults = (void *)defaults_msr;
772 rp->priv->rpi = (void *)rpi_msr;
773 break;
774 case RAPL_IF_TPMI:
775 rp->priv->defaults = (void *)&defaults_tpmi;
776 rp->priv->rpi = (void *)rpi_tpmi;
777 break;
778 default:
779 return -EINVAL;
780 }
781
782 /* defaults_msr can be NULL on unsupported platforms */
783 if (!rp->priv->defaults || !rp->priv->rpi)
784 return -ENODEV;
785
786 return 0;
787 }
788
789 static enum rapl_primitives
prim_fixups(struct rapl_domain * rd,enum rapl_primitives prim)790 prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim)
791 {
792 struct rapl_defaults *defaults = get_defaults(rd->rp);
793
794 if (!defaults->spr_psys_bits)
795 return prim;
796
797 if (rd->id != RAPL_DOMAIN_PLATFORM)
798 return prim;
799
800 switch (prim) {
801 case POWER_LIMIT1:
802 return PSYS_POWER_LIMIT1;
803 case POWER_LIMIT2:
804 return PSYS_POWER_LIMIT2;
805 case PL1_ENABLE:
806 return PSYS_PL1_ENABLE;
807 case PL2_ENABLE:
808 return PSYS_PL2_ENABLE;
809 case TIME_WINDOW1:
810 return PSYS_TIME_WINDOW1;
811 case TIME_WINDOW2:
812 return PSYS_TIME_WINDOW2;
813 default:
814 return prim;
815 }
816 }
817
818 /* Read primitive data based on its related struct rapl_primitive_info.
819 * if xlate flag is set, return translated data based on data units, i.e.
820 * time, energy, and power.
821 * RAPL MSRs are non-architectual and are laid out not consistently across
822 * domains. Here we use primitive info to allow writing consolidated access
823 * functions.
824 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
825 * is pre-assigned based on RAPL unit MSRs read at init time.
826 * 63-------------------------- 31--------------------------- 0
827 * | xxxxx (mask) |
828 * | |<- shift ----------------|
829 * 63-------------------------- 31--------------------------- 0
830 */
rapl_read_data_raw(struct rapl_domain * rd,enum rapl_primitives prim,bool xlate,u64 * data)831 static int rapl_read_data_raw(struct rapl_domain *rd,
832 enum rapl_primitives prim, bool xlate, u64 *data)
833 {
834 u64 value;
835 enum rapl_primitives prim_fixed = prim_fixups(rd, prim);
836 struct rapl_primitive_info *rpi = get_rpi(rd->rp, prim_fixed);
837 struct reg_action ra;
838
839 if (!rpi || !rpi->name || rpi->flag & RAPL_PRIMITIVE_DUMMY)
840 return -EINVAL;
841
842 ra.reg = rd->regs[rpi->id];
843 if (!ra.reg.val)
844 return -EINVAL;
845
846 /* non-hardware data are collected by the polling thread */
847 if (rpi->flag & RAPL_PRIMITIVE_DERIVED) {
848 *data = rd->rdd.primitives[prim];
849 return 0;
850 }
851
852 ra.mask = rpi->mask;
853
854 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
855 pr_debug("failed to read reg 0x%llx for %s:%s\n", ra.reg.val, rd->rp->name, rd->name);
856 return -EIO;
857 }
858
859 value = ra.value >> rpi->shift;
860
861 if (xlate)
862 *data = rapl_unit_xlate(rd, rpi->unit, value, 0);
863 else
864 *data = value;
865
866 return 0;
867 }
868
869 /* Similar use of primitive info in the read counterpart */
rapl_write_data_raw(struct rapl_domain * rd,enum rapl_primitives prim,unsigned long long value)870 static int rapl_write_data_raw(struct rapl_domain *rd,
871 enum rapl_primitives prim,
872 unsigned long long value)
873 {
874 enum rapl_primitives prim_fixed = prim_fixups(rd, prim);
875 struct rapl_primitive_info *rpi = get_rpi(rd->rp, prim_fixed);
876 u64 bits;
877 struct reg_action ra;
878 int ret;
879
880 if (!rpi || !rpi->name || rpi->flag & RAPL_PRIMITIVE_DUMMY)
881 return -EINVAL;
882
883 bits = rapl_unit_xlate(rd, rpi->unit, value, 1);
884 bits <<= rpi->shift;
885 bits &= rpi->mask;
886
887 memset(&ra, 0, sizeof(ra));
888
889 ra.reg = rd->regs[rpi->id];
890 ra.mask = rpi->mask;
891 ra.value = bits;
892
893 ret = rd->rp->priv->write_raw(get_rid(rd->rp), &ra);
894
895 return ret;
896 }
897
rapl_read_pl_data(struct rapl_domain * rd,int pl,enum pl_prims pl_prim,bool xlate,u64 * data)898 static int rapl_read_pl_data(struct rapl_domain *rd, int pl,
899 enum pl_prims pl_prim, bool xlate, u64 *data)
900 {
901 enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim);
902
903 if (!is_pl_valid(rd, pl))
904 return -EINVAL;
905
906 return rapl_read_data_raw(rd, prim, xlate, data);
907 }
908
rapl_write_pl_data(struct rapl_domain * rd,int pl,enum pl_prims pl_prim,unsigned long long value)909 static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
910 enum pl_prims pl_prim,
911 unsigned long long value)
912 {
913 enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim);
914
915 if (!is_pl_valid(rd, pl))
916 return -EINVAL;
917
918 if (rd->rpl[pl].locked) {
919 pr_debug("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name, pl_names[pl]);
920 return -EACCES;
921 }
922
923 return rapl_write_data_raw(rd, prim, value);
924 }
925 /*
926 * Raw RAPL data stored in MSRs are in certain scales. We need to
927 * convert them into standard units based on the units reported in
928 * the RAPL unit MSRs. This is specific to CPUs as the method to
929 * calculate units differ on different CPUs.
930 * We convert the units to below format based on CPUs.
931 * i.e.
932 * energy unit: picoJoules : Represented in picoJoules by default
933 * power unit : microWatts : Represented in milliWatts by default
934 * time unit : microseconds: Represented in seconds by default
935 */
rapl_check_unit_core(struct rapl_domain * rd)936 static int rapl_check_unit_core(struct rapl_domain *rd)
937 {
938 struct reg_action ra;
939 u32 value;
940
941 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
942 ra.mask = ~0;
943 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
944 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
945 ra.reg.val, rd->rp->name, rd->name);
946 return -ENODEV;
947 }
948
949 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
950 rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
951
952 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
953 rd->power_unit = 1000000 / (1 << value);
954
955 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
956 rd->time_unit = 1000000 / (1 << value);
957
958 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
959 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
960
961 return 0;
962 }
963
rapl_check_unit_atom(struct rapl_domain * rd)964 static int rapl_check_unit_atom(struct rapl_domain *rd)
965 {
966 struct reg_action ra;
967 u32 value;
968
969 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
970 ra.mask = ~0;
971 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
972 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
973 ra.reg.val, rd->rp->name, rd->name);
974 return -ENODEV;
975 }
976
977 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
978 rd->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
979
980 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
981 rd->power_unit = (1 << value) * 1000;
982
983 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
984 rd->time_unit = 1000000 / (1 << value);
985
986 pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n",
987 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
988
989 return 0;
990 }
991
power_limit_irq_save_cpu(void * info)992 static void power_limit_irq_save_cpu(void *info)
993 {
994 u32 l, h = 0;
995 struct rapl_package *rp = (struct rapl_package *)info;
996
997 /* save the state of PLN irq mask bit before disabling it */
998 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
999 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
1000 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
1001 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
1002 }
1003 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
1004 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
1005 }
1006
1007 /* REVISIT:
1008 * When package power limit is set artificially low by RAPL, LVT
1009 * thermal interrupt for package power limit should be ignored
1010 * since we are not really exceeding the real limit. The intention
1011 * is to avoid excessive interrupts while we are trying to save power.
1012 * A useful feature might be routing the package_power_limit interrupt
1013 * to userspace via eventfd. once we have a usecase, this is simple
1014 * to do by adding an atomic notifier.
1015 */
1016
package_power_limit_irq_save(struct rapl_package * rp)1017 static void package_power_limit_irq_save(struct rapl_package *rp)
1018 {
1019 if (rp->lead_cpu < 0)
1020 return;
1021
1022 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
1023 return;
1024
1025 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
1026 }
1027
1028 /*
1029 * Restore per package power limit interrupt enable state. Called from cpu
1030 * hotplug code on package removal.
1031 */
package_power_limit_irq_restore(struct rapl_package * rp)1032 static void package_power_limit_irq_restore(struct rapl_package *rp)
1033 {
1034 u32 l, h;
1035
1036 if (rp->lead_cpu < 0)
1037 return;
1038
1039 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
1040 return;
1041
1042 /* irq enable state not saved, nothing to restore */
1043 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
1044 return;
1045
1046 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
1047
1048 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
1049 l |= PACKAGE_THERM_INT_PLN_ENABLE;
1050 else
1051 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
1052
1053 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
1054 }
1055
set_floor_freq_default(struct rapl_domain * rd,bool mode)1056 static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
1057 {
1058 int i;
1059
1060 /* always enable clamp such that p-state can go below OS requested
1061 * range. power capping priority over guranteed frequency.
1062 */
1063 rapl_write_pl_data(rd, POWER_LIMIT1, PL_CLAMP, mode);
1064
1065 for (i = POWER_LIMIT2; i < NR_POWER_LIMITS; i++) {
1066 rapl_write_pl_data(rd, i, PL_ENABLE, mode);
1067 rapl_write_pl_data(rd, i, PL_CLAMP, mode);
1068 }
1069 }
1070
set_floor_freq_atom(struct rapl_domain * rd,bool enable)1071 static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
1072 {
1073 static u32 power_ctrl_orig_val;
1074 struct rapl_defaults *defaults = get_defaults(rd->rp);
1075 u32 mdata;
1076
1077 if (!defaults->floor_freq_reg_addr) {
1078 pr_err("Invalid floor frequency config register\n");
1079 return;
1080 }
1081
1082 if (!power_ctrl_orig_val)
1083 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
1084 defaults->floor_freq_reg_addr,
1085 &power_ctrl_orig_val);
1086 mdata = power_ctrl_orig_val;
1087 if (enable) {
1088 mdata &= ~(0x7f << 8);
1089 mdata |= 1 << 8;
1090 }
1091 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
1092 defaults->floor_freq_reg_addr, mdata);
1093 }
1094
rapl_compute_time_window_core(struct rapl_domain * rd,u64 value,bool to_raw)1095 static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value,
1096 bool to_raw)
1097 {
1098 u64 f, y; /* fraction and exp. used for time unit */
1099
1100 /*
1101 * Special processing based on 2^Y*(1+F/4), refer
1102 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
1103 */
1104 if (!to_raw) {
1105 f = (value & 0x60) >> 5;
1106 y = value & 0x1f;
1107 value = (1 << y) * (4 + f) * rd->time_unit / 4;
1108 } else {
1109 if (value < rd->time_unit)
1110 return 0;
1111
1112 do_div(value, rd->time_unit);
1113 y = ilog2(value);
1114
1115 /*
1116 * The target hardware field is 7 bits wide, so return all ones
1117 * if the exponent is too large.
1118 */
1119 if (y > 0x1f)
1120 return 0x7f;
1121
1122 f = div64_u64(4 * (value - (1ULL << y)), 1ULL << y);
1123 value = (y & 0x1f) | ((f & 0x3) << 5);
1124 }
1125 return value;
1126 }
1127
rapl_compute_time_window_atom(struct rapl_domain * rd,u64 value,bool to_raw)1128 static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
1129 bool to_raw)
1130 {
1131 /*
1132 * Atom time unit encoding is straight forward val * time_unit,
1133 * where time_unit is default to 1 sec. Never 0.
1134 */
1135 if (!to_raw)
1136 return (value) ? value * rd->time_unit : rd->time_unit;
1137
1138 value = div64_u64(value, rd->time_unit);
1139
1140 return value;
1141 }
1142
1143 /* TPMI Unit register has different layout */
1144 #define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
1145 #define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
1146 #define TPMI_ENERGY_UNIT_OFFSET 0x06
1147 #define TPMI_ENERGY_UNIT_MASK 0x7C0
1148 #define TPMI_TIME_UNIT_OFFSET 0x0C
1149 #define TPMI_TIME_UNIT_MASK 0xF000
1150
rapl_check_unit_tpmi(struct rapl_domain * rd)1151 static int rapl_check_unit_tpmi(struct rapl_domain *rd)
1152 {
1153 struct reg_action ra;
1154 u32 value;
1155
1156 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
1157 ra.mask = ~0;
1158 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) {
1159 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
1160 ra.reg.val, rd->rp->name, rd->name);
1161 return -ENODEV;
1162 }
1163
1164 value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET;
1165 rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
1166
1167 value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET;
1168 rd->power_unit = 1000000 / (1 << value);
1169
1170 value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET;
1171 rd->time_unit = 1000000 / (1 << value);
1172
1173 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
1174 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
1175
1176 return 0;
1177 }
1178
1179 static const struct rapl_defaults defaults_tpmi = {
1180 .check_unit = rapl_check_unit_tpmi,
1181 /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */
1182 .set_floor_freq = set_floor_freq_default,
1183 .compute_time_window = rapl_compute_time_window_core,
1184 };
1185
1186 static const struct rapl_defaults rapl_defaults_core = {
1187 .floor_freq_reg_addr = 0,
1188 .check_unit = rapl_check_unit_core,
1189 .set_floor_freq = set_floor_freq_default,
1190 .compute_time_window = rapl_compute_time_window_core,
1191 };
1192
1193 static const struct rapl_defaults rapl_defaults_hsw_server = {
1194 .check_unit = rapl_check_unit_core,
1195 .set_floor_freq = set_floor_freq_default,
1196 .compute_time_window = rapl_compute_time_window_core,
1197 .dram_domain_energy_unit = 15300,
1198 };
1199
1200 static const struct rapl_defaults rapl_defaults_spr_server = {
1201 .check_unit = rapl_check_unit_core,
1202 .set_floor_freq = set_floor_freq_default,
1203 .compute_time_window = rapl_compute_time_window_core,
1204 .psys_domain_energy_unit = 1000000000,
1205 .spr_psys_bits = true,
1206 };
1207
1208 static const struct rapl_defaults rapl_defaults_byt = {
1209 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1210 .check_unit = rapl_check_unit_atom,
1211 .set_floor_freq = set_floor_freq_atom,
1212 .compute_time_window = rapl_compute_time_window_atom,
1213 };
1214
1215 static const struct rapl_defaults rapl_defaults_tng = {
1216 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
1217 .check_unit = rapl_check_unit_atom,
1218 .set_floor_freq = set_floor_freq_atom,
1219 .compute_time_window = rapl_compute_time_window_atom,
1220 };
1221
1222 static const struct rapl_defaults rapl_defaults_ann = {
1223 .floor_freq_reg_addr = 0,
1224 .check_unit = rapl_check_unit_atom,
1225 .set_floor_freq = NULL,
1226 .compute_time_window = rapl_compute_time_window_atom,
1227 };
1228
1229 static const struct rapl_defaults rapl_defaults_cht = {
1230 .floor_freq_reg_addr = 0,
1231 .check_unit = rapl_check_unit_atom,
1232 .set_floor_freq = NULL,
1233 .compute_time_window = rapl_compute_time_window_atom,
1234 };
1235
1236 static const struct rapl_defaults rapl_defaults_amd = {
1237 .check_unit = rapl_check_unit_core,
1238 };
1239
1240 static const struct x86_cpu_id rapl_ids[] __initconst = {
1241 X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
1242 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
1243
1244 X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
1245 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
1246
1247 X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
1248 X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
1249 X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
1250 X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
1251
1252 X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
1253 X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
1254 X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
1255 X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
1256
1257 X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
1258 X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
1259 X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
1260 X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
1261 X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
1262 X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
1263 X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
1264 X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
1265 X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
1266 X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
1267 X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
1268 X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
1269 X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
1270 X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
1271 X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
1272 X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
1273 X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
1274 X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
1275 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
1276 X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
1277 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
1278 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
1279 X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
1280 X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
1281 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
1282 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
1283 X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
1284 X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
1285 X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
1286 X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
1287 X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
1288
1289 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
1290 X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
1291 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
1292 X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID, &rapl_defaults_ann),
1293 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
1294 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
1295 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
1296 X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
1297 X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
1298 X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
1299
1300 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
1301 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
1302
1303 X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
1304 X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
1305 X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
1306 X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
1307 {}
1308 };
1309 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1310
1311 /* Read once for all raw primitive data for domains */
rapl_update_domain_data(struct rapl_package * rp)1312 static void rapl_update_domain_data(struct rapl_package *rp)
1313 {
1314 int dmn, prim;
1315 u64 val;
1316
1317 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1318 pr_debug("update %s domain %s data\n", rp->name,
1319 rp->domains[dmn].name);
1320 /* exclude non-raw primitives */
1321 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
1322 struct rapl_primitive_info *rpi = get_rpi(rp, prim);
1323
1324 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1325 rpi->unit, &val))
1326 rp->domains[dmn].rdd.primitives[prim] = val;
1327 }
1328 }
1329
1330 }
1331
rapl_package_register_powercap(struct rapl_package * rp)1332 static int rapl_package_register_powercap(struct rapl_package *rp)
1333 {
1334 struct rapl_domain *rd;
1335 struct powercap_zone *power_zone = NULL;
1336 int nr_pl, ret;
1337
1338 /* Update the domain data of the new package */
1339 rapl_update_domain_data(rp);
1340
1341 /* first we register package domain as the parent zone */
1342 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1343 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1344 nr_pl = find_nr_power_limit(rd);
1345 pr_debug("register package domain %s\n", rp->name);
1346 power_zone = powercap_register_zone(&rd->power_zone,
1347 rp->priv->control_type, rp->name,
1348 NULL, &zone_ops[rd->id], nr_pl,
1349 &constraint_ops);
1350 if (IS_ERR(power_zone)) {
1351 pr_debug("failed to register power zone %s\n",
1352 rp->name);
1353 return PTR_ERR(power_zone);
1354 }
1355 /* track parent zone in per package/socket data */
1356 rp->power_zone = power_zone;
1357 /* done, only one package domain per socket */
1358 break;
1359 }
1360 }
1361 if (!power_zone) {
1362 pr_err("no package domain found, unknown topology!\n");
1363 return -ENODEV;
1364 }
1365 /* now register domains as children of the socket/package */
1366 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1367 struct powercap_zone *parent = rp->power_zone;
1368
1369 if (rd->id == RAPL_DOMAIN_PACKAGE)
1370 continue;
1371 if (rd->id == RAPL_DOMAIN_PLATFORM)
1372 parent = NULL;
1373 /* number of power limits per domain varies */
1374 nr_pl = find_nr_power_limit(rd);
1375 power_zone = powercap_register_zone(&rd->power_zone,
1376 rp->priv->control_type,
1377 rd->name, parent,
1378 &zone_ops[rd->id], nr_pl,
1379 &constraint_ops);
1380
1381 if (IS_ERR(power_zone)) {
1382 pr_debug("failed to register power_zone, %s:%s\n",
1383 rp->name, rd->name);
1384 ret = PTR_ERR(power_zone);
1385 goto err_cleanup;
1386 }
1387 }
1388 return 0;
1389
1390 err_cleanup:
1391 /*
1392 * Clean up previously initialized domains within the package if we
1393 * failed after the first domain setup.
1394 */
1395 while (--rd >= rp->domains) {
1396 pr_debug("unregister %s domain %s\n", rp->name, rd->name);
1397 powercap_unregister_zone(rp->priv->control_type,
1398 &rd->power_zone);
1399 }
1400
1401 return ret;
1402 }
1403
rapl_check_domain(int domain,struct rapl_package * rp)1404 static int rapl_check_domain(int domain, struct rapl_package *rp)
1405 {
1406 struct reg_action ra;
1407
1408 switch (domain) {
1409 case RAPL_DOMAIN_PACKAGE:
1410 case RAPL_DOMAIN_PP0:
1411 case RAPL_DOMAIN_PP1:
1412 case RAPL_DOMAIN_DRAM:
1413 case RAPL_DOMAIN_PLATFORM:
1414 ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS];
1415 break;
1416 default:
1417 pr_err("invalid domain id %d\n", domain);
1418 return -EINVAL;
1419 }
1420 /* make sure domain counters are available and contains non-zero
1421 * values, otherwise skip it.
1422 */
1423
1424 ra.mask = ENERGY_STATUS_MASK;
1425 if (rp->priv->read_raw(get_rid(rp), &ra) || !ra.value)
1426 return -ENODEV;
1427
1428 return 0;
1429 }
1430
1431 /*
1432 * Get per domain energy/power/time unit.
1433 * RAPL Interfaces without per domain unit register will use the package
1434 * scope unit register to set per domain units.
1435 */
rapl_get_domain_unit(struct rapl_domain * rd)1436 static int rapl_get_domain_unit(struct rapl_domain *rd)
1437 {
1438 struct rapl_defaults *defaults = get_defaults(rd->rp);
1439 int ret;
1440
1441 if (!rd->regs[RAPL_DOMAIN_REG_UNIT].val) {
1442 if (!rd->rp->priv->reg_unit.val) {
1443 pr_err("No valid Unit register found\n");
1444 return -ENODEV;
1445 }
1446 rd->regs[RAPL_DOMAIN_REG_UNIT] = rd->rp->priv->reg_unit;
1447 }
1448
1449 if (!defaults->check_unit) {
1450 pr_err("missing .check_unit() callback\n");
1451 return -ENODEV;
1452 }
1453
1454 ret = defaults->check_unit(rd);
1455 if (ret)
1456 return ret;
1457
1458 if (rd->id == RAPL_DOMAIN_DRAM && defaults->dram_domain_energy_unit)
1459 rd->energy_unit = defaults->dram_domain_energy_unit;
1460 if (rd->id == RAPL_DOMAIN_PLATFORM && defaults->psys_domain_energy_unit)
1461 rd->energy_unit = defaults->psys_domain_energy_unit;
1462 return 0;
1463 }
1464
1465 /*
1466 * Check if power limits are available. Two cases when they are not available:
1467 * 1. Locked by BIOS, in this case we still provide read-only access so that
1468 * users can see what limit is set by the BIOS.
1469 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not
1470 * exist at all. In this case, we do not show the constraints in powercap.
1471 *
1472 * Called after domains are detected and initialized.
1473 */
rapl_detect_powerlimit(struct rapl_domain * rd)1474 static void rapl_detect_powerlimit(struct rapl_domain *rd)
1475 {
1476 u64 val64;
1477 int i;
1478
1479 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
1480 if (!rapl_read_pl_data(rd, i, PL_LOCK, false, &val64)) {
1481 if (val64) {
1482 rd->rpl[i].locked = true;
1483 pr_info("%s:%s:%s locked by BIOS\n",
1484 rd->rp->name, rd->name, pl_names[i]);
1485 }
1486 }
1487
1488 if (rapl_read_pl_data(rd, i, PL_LIMIT, false, &val64))
1489 rd->rpl[i].name = NULL;
1490 }
1491 }
1492
1493 /* Detect active and valid domains for the given CPU, caller must
1494 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1495 */
rapl_detect_domains(struct rapl_package * rp)1496 static int rapl_detect_domains(struct rapl_package *rp)
1497 {
1498 struct rapl_domain *rd;
1499 int i;
1500
1501 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1502 /* use physical package id to read counters */
1503 if (!rapl_check_domain(i, rp)) {
1504 rp->domain_map |= 1 << i;
1505 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1506 }
1507 }
1508 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1509 if (!rp->nr_domains) {
1510 pr_debug("no valid rapl domains found in %s\n", rp->name);
1511 return -ENODEV;
1512 }
1513 pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name);
1514
1515 rp->domains = kcalloc(rp->nr_domains, sizeof(struct rapl_domain),
1516 GFP_KERNEL);
1517 if (!rp->domains)
1518 return -ENOMEM;
1519
1520 rapl_init_domains(rp);
1521
1522 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1523 rapl_get_domain_unit(rd);
1524 rapl_detect_powerlimit(rd);
1525 }
1526
1527 return 0;
1528 }
1529
1530 #ifdef CONFIG_PERF_EVENTS
1531
1532 /*
1533 * Support for RAPL PMU
1534 *
1535 * Register a PMU if any of the registered RAPL Packages have the requirement
1536 * of exposing its energy counters via Perf PMU.
1537 *
1538 * PMU Name:
1539 * power
1540 *
1541 * Events:
1542 * Name Event id RAPL Domain
1543 * energy_cores 0x01 RAPL_DOMAIN_PP0
1544 * energy_pkg 0x02 RAPL_DOMAIN_PACKAGE
1545 * energy_ram 0x03 RAPL_DOMAIN_DRAM
1546 * energy_gpu 0x04 RAPL_DOMAIN_PP1
1547 * energy_psys 0x05 RAPL_DOMAIN_PLATFORM
1548 *
1549 * Unit:
1550 * Joules
1551 *
1552 * Scale:
1553 * 2.3283064365386962890625e-10
1554 * The same RAPL domain in different RAPL Packages may have different
1555 * energy units. Use 2.3283064365386962890625e-10 (2^-32) Joules as
1556 * the fixed unit for all energy counters, and covert each hardware
1557 * counter increase to N times of PMU event counter increases.
1558 *
1559 * This is fully compatible with the current MSR RAPL PMU. This means that
1560 * userspace programs like turbostat can use the same code to handle RAPL Perf
1561 * PMU, no matter what RAPL Interface driver (MSR/TPMI, etc) is running
1562 * underlying on the platform.
1563 *
1564 * Note that RAPL Packages can be probed/removed dynamically, and the events
1565 * supported by each TPMI RAPL device can be different. Thus the RAPL PMU
1566 * support is done on demand, which means
1567 * 1. PMU is registered only if it is needed by a RAPL Package. PMU events for
1568 * unsupported counters are not exposed.
1569 * 2. PMU is unregistered and registered when a new RAPL Package is probed and
1570 * supports new counters that are not supported by current PMU.
1571 * 3. PMU is unregistered when all registered RAPL Packages don't need PMU.
1572 */
1573
1574 struct rapl_pmu {
1575 struct pmu pmu; /* Perf PMU structure */
1576 u64 timer_ms; /* Maximum expiration time to avoid counter overflow */
1577 unsigned long domain_map; /* Events supported by current registered PMU */
1578 bool registered; /* Whether the PMU has been registered or not */
1579 };
1580
1581 static struct rapl_pmu rapl_pmu;
1582
1583 /* PMU helpers */
1584
get_pmu_cpu(struct rapl_package * rp)1585 static int get_pmu_cpu(struct rapl_package *rp)
1586 {
1587 int cpu;
1588
1589 if (!rp->has_pmu)
1590 return nr_cpu_ids;
1591
1592 /* Only TPMI RAPL is supported for now */
1593 if (rp->priv->type != RAPL_IF_TPMI)
1594 return nr_cpu_ids;
1595
1596 /* TPMI RAPL uses any CPU in the package for PMU */
1597 for_each_online_cpu(cpu)
1598 if (topology_physical_package_id(cpu) == rp->id)
1599 return cpu;
1600
1601 return nr_cpu_ids;
1602 }
1603
is_rp_pmu_cpu(struct rapl_package * rp,int cpu)1604 static bool is_rp_pmu_cpu(struct rapl_package *rp, int cpu)
1605 {
1606 if (!rp->has_pmu)
1607 return false;
1608
1609 /* Only TPMI RAPL is supported for now */
1610 if (rp->priv->type != RAPL_IF_TPMI)
1611 return false;
1612
1613 /* TPMI RAPL uses any CPU in the package for PMU */
1614 return topology_physical_package_id(cpu) == rp->id;
1615 }
1616
event_to_pmu_data(struct perf_event * event)1617 static struct rapl_package_pmu_data *event_to_pmu_data(struct perf_event *event)
1618 {
1619 struct rapl_package *rp = event->pmu_private;
1620
1621 return &rp->pmu_data;
1622 }
1623
1624 /* PMU event callbacks */
1625
event_read_counter(struct perf_event * event)1626 static u64 event_read_counter(struct perf_event *event)
1627 {
1628 struct rapl_package *rp = event->pmu_private;
1629 u64 val;
1630 int ret;
1631
1632 /* Return 0 for unsupported events */
1633 if (event->hw.idx < 0)
1634 return 0;
1635
1636 ret = rapl_read_data_raw(&rp->domains[event->hw.idx], ENERGY_COUNTER, false, &val);
1637
1638 /* Return 0 for failed read */
1639 if (ret)
1640 return 0;
1641
1642 return val;
1643 }
1644
__rapl_pmu_event_start(struct perf_event * event)1645 static void __rapl_pmu_event_start(struct perf_event *event)
1646 {
1647 struct rapl_package_pmu_data *data = event_to_pmu_data(event);
1648
1649 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1650 return;
1651
1652 event->hw.state = 0;
1653
1654 list_add_tail(&event->active_entry, &data->active_list);
1655
1656 local64_set(&event->hw.prev_count, event_read_counter(event));
1657 if (++data->n_active == 1)
1658 hrtimer_start(&data->hrtimer, data->timer_interval,
1659 HRTIMER_MODE_REL_PINNED);
1660 }
1661
rapl_pmu_event_start(struct perf_event * event,int mode)1662 static void rapl_pmu_event_start(struct perf_event *event, int mode)
1663 {
1664 struct rapl_package_pmu_data *data = event_to_pmu_data(event);
1665 unsigned long flags;
1666
1667 raw_spin_lock_irqsave(&data->lock, flags);
1668 __rapl_pmu_event_start(event);
1669 raw_spin_unlock_irqrestore(&data->lock, flags);
1670 }
1671
rapl_event_update(struct perf_event * event)1672 static u64 rapl_event_update(struct perf_event *event)
1673 {
1674 struct hw_perf_event *hwc = &event->hw;
1675 struct rapl_package_pmu_data *data = event_to_pmu_data(event);
1676 u64 prev_raw_count, new_raw_count;
1677 s64 delta, sdelta;
1678
1679 /*
1680 * Follow the generic code to drain hwc->prev_count.
1681 * The loop is not expected to run for multiple times.
1682 */
1683 prev_raw_count = local64_read(&hwc->prev_count);
1684 do {
1685 new_raw_count = event_read_counter(event);
1686 } while (!local64_try_cmpxchg(&hwc->prev_count,
1687 &prev_raw_count, new_raw_count));
1688
1689
1690 /*
1691 * Now we have the new raw value and have updated the prev
1692 * timestamp already. We can now calculate the elapsed delta
1693 * (event-)time and add that to the generic event.
1694 */
1695 delta = new_raw_count - prev_raw_count;
1696
1697 /*
1698 * Scale delta to smallest unit (2^-32)
1699 * users must then scale back: count * 1/(1e9*2^32) to get Joules
1700 * or use ldexp(count, -32).
1701 * Watts = Joules/Time delta
1702 */
1703 sdelta = delta * data->scale[event->hw.flags];
1704
1705 local64_add(sdelta, &event->count);
1706
1707 return new_raw_count;
1708 }
1709
rapl_pmu_event_stop(struct perf_event * event,int mode)1710 static void rapl_pmu_event_stop(struct perf_event *event, int mode)
1711 {
1712 struct rapl_package_pmu_data *data = event_to_pmu_data(event);
1713 struct hw_perf_event *hwc = &event->hw;
1714 unsigned long flags;
1715
1716 raw_spin_lock_irqsave(&data->lock, flags);
1717
1718 /* Mark event as deactivated and stopped */
1719 if (!(hwc->state & PERF_HES_STOPPED)) {
1720 WARN_ON_ONCE(data->n_active <= 0);
1721 if (--data->n_active == 0)
1722 hrtimer_cancel(&data->hrtimer);
1723
1724 list_del(&event->active_entry);
1725
1726 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1727 hwc->state |= PERF_HES_STOPPED;
1728 }
1729
1730 /* Check if update of sw counter is necessary */
1731 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1732 /*
1733 * Drain the remaining delta count out of a event
1734 * that we are disabling:
1735 */
1736 rapl_event_update(event);
1737 hwc->state |= PERF_HES_UPTODATE;
1738 }
1739
1740 raw_spin_unlock_irqrestore(&data->lock, flags);
1741 }
1742
rapl_pmu_event_add(struct perf_event * event,int mode)1743 static int rapl_pmu_event_add(struct perf_event *event, int mode)
1744 {
1745 struct rapl_package_pmu_data *data = event_to_pmu_data(event);
1746 struct hw_perf_event *hwc = &event->hw;
1747 unsigned long flags;
1748
1749 raw_spin_lock_irqsave(&data->lock, flags);
1750
1751 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1752
1753 if (mode & PERF_EF_START)
1754 __rapl_pmu_event_start(event);
1755
1756 raw_spin_unlock_irqrestore(&data->lock, flags);
1757
1758 return 0;
1759 }
1760
rapl_pmu_event_del(struct perf_event * event,int flags)1761 static void rapl_pmu_event_del(struct perf_event *event, int flags)
1762 {
1763 rapl_pmu_event_stop(event, PERF_EF_UPDATE);
1764 }
1765
1766 /* RAPL PMU event ids, same as shown in sysfs */
1767 enum perf_rapl_events {
1768 PERF_RAPL_PP0 = 1, /* all cores */
1769 PERF_RAPL_PKG, /* entire package */
1770 PERF_RAPL_RAM, /* DRAM */
1771 PERF_RAPL_PP1, /* gpu */
1772 PERF_RAPL_PSYS, /* psys */
1773 PERF_RAPL_MAX
1774 };
1775 #define RAPL_EVENT_MASK GENMASK(7, 0)
1776
1777 static const int event_to_domain[PERF_RAPL_MAX] = {
1778 [PERF_RAPL_PP0] = RAPL_DOMAIN_PP0,
1779 [PERF_RAPL_PKG] = RAPL_DOMAIN_PACKAGE,
1780 [PERF_RAPL_RAM] = RAPL_DOMAIN_DRAM,
1781 [PERF_RAPL_PP1] = RAPL_DOMAIN_PP1,
1782 [PERF_RAPL_PSYS] = RAPL_DOMAIN_PLATFORM,
1783 };
1784
rapl_pmu_event_init(struct perf_event * event)1785 static int rapl_pmu_event_init(struct perf_event *event)
1786 {
1787 struct rapl_package *pos, *rp = NULL;
1788 u64 cfg = event->attr.config & RAPL_EVENT_MASK;
1789 int domain, idx;
1790
1791 /* Only look at RAPL events */
1792 if (event->attr.type != event->pmu->type)
1793 return -ENOENT;
1794
1795 /* Check for supported events only */
1796 if (!cfg || cfg >= PERF_RAPL_MAX)
1797 return -EINVAL;
1798
1799 if (event->cpu < 0)
1800 return -EINVAL;
1801
1802 /* Find out which Package the event belongs to */
1803 list_for_each_entry(pos, &rapl_packages, plist) {
1804 if (is_rp_pmu_cpu(pos, event->cpu)) {
1805 rp = pos;
1806 break;
1807 }
1808 }
1809 if (!rp)
1810 return -ENODEV;
1811
1812 /* Find out which RAPL Domain the event belongs to */
1813 domain = event_to_domain[cfg];
1814
1815 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
1816 event->pmu_private = rp; /* Which package */
1817 event->hw.flags = domain; /* Which domain */
1818
1819 event->hw.idx = -1;
1820 /* Find out the index in rp->domains[] to get domain pointer */
1821 for (idx = 0; idx < rp->nr_domains; idx++) {
1822 if (rp->domains[idx].id == domain) {
1823 event->hw.idx = idx;
1824 break;
1825 }
1826 }
1827
1828 return 0;
1829 }
1830
rapl_pmu_event_read(struct perf_event * event)1831 static void rapl_pmu_event_read(struct perf_event *event)
1832 {
1833 rapl_event_update(event);
1834 }
1835
rapl_hrtimer_handle(struct hrtimer * hrtimer)1836 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer)
1837 {
1838 struct rapl_package_pmu_data *data =
1839 container_of(hrtimer, struct rapl_package_pmu_data, hrtimer);
1840 struct perf_event *event;
1841 unsigned long flags;
1842
1843 if (!data->n_active)
1844 return HRTIMER_NORESTART;
1845
1846 raw_spin_lock_irqsave(&data->lock, flags);
1847
1848 list_for_each_entry(event, &data->active_list, active_entry)
1849 rapl_event_update(event);
1850
1851 raw_spin_unlock_irqrestore(&data->lock, flags);
1852
1853 hrtimer_forward_now(hrtimer, data->timer_interval);
1854
1855 return HRTIMER_RESTART;
1856 }
1857
1858 /* PMU sysfs attributes */
1859
1860 /*
1861 * There are no default events, but we need to create "events" group (with
1862 * empty attrs) before updating it with detected events.
1863 */
1864 static struct attribute *attrs_empty[] = {
1865 NULL,
1866 };
1867
1868 static struct attribute_group pmu_events_group = {
1869 .name = "events",
1870 .attrs = attrs_empty,
1871 };
1872
cpumask_show(struct device * dev,struct device_attribute * attr,char * buf)1873 static ssize_t cpumask_show(struct device *dev,
1874 struct device_attribute *attr, char *buf)
1875 {
1876 struct rapl_package *rp;
1877 cpumask_var_t cpu_mask;
1878 int cpu;
1879 int ret;
1880
1881 if (!alloc_cpumask_var(&cpu_mask, GFP_KERNEL))
1882 return -ENOMEM;
1883
1884 cpus_read_lock();
1885
1886 cpumask_clear(cpu_mask);
1887
1888 /* Choose a cpu for each RAPL Package */
1889 list_for_each_entry(rp, &rapl_packages, plist) {
1890 cpu = get_pmu_cpu(rp);
1891 if (cpu < nr_cpu_ids)
1892 cpumask_set_cpu(cpu, cpu_mask);
1893 }
1894 cpus_read_unlock();
1895
1896 ret = cpumap_print_to_pagebuf(true, buf, cpu_mask);
1897
1898 free_cpumask_var(cpu_mask);
1899
1900 return ret;
1901 }
1902
1903 static DEVICE_ATTR_RO(cpumask);
1904
1905 static struct attribute *pmu_cpumask_attrs[] = {
1906 &dev_attr_cpumask.attr,
1907 NULL
1908 };
1909
1910 static struct attribute_group pmu_cpumask_group = {
1911 .attrs = pmu_cpumask_attrs,
1912 };
1913
1914 PMU_FORMAT_ATTR(event, "config:0-7");
1915 static struct attribute *pmu_format_attr[] = {
1916 &format_attr_event.attr,
1917 NULL
1918 };
1919
1920 static struct attribute_group pmu_format_group = {
1921 .name = "format",
1922 .attrs = pmu_format_attr,
1923 };
1924
1925 static const struct attribute_group *pmu_attr_groups[] = {
1926 &pmu_events_group,
1927 &pmu_cpumask_group,
1928 &pmu_format_group,
1929 NULL
1930 };
1931
1932 #define RAPL_EVENT_ATTR_STR(_name, v, str) \
1933 static struct perf_pmu_events_attr event_attr_##v = { \
1934 .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \
1935 .event_str = str, \
1936 }
1937
1938 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
1939 RAPL_EVENT_ATTR_STR(energy-pkg, rapl_pkg, "event=0x02");
1940 RAPL_EVENT_ATTR_STR(energy-ram, rapl_ram, "event=0x03");
1941 RAPL_EVENT_ATTR_STR(energy-gpu, rapl_gpu, "event=0x04");
1942 RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05");
1943
1944 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_unit_cores, "Joules");
1945 RAPL_EVENT_ATTR_STR(energy-pkg.unit, rapl_unit_pkg, "Joules");
1946 RAPL_EVENT_ATTR_STR(energy-ram.unit, rapl_unit_ram, "Joules");
1947 RAPL_EVENT_ATTR_STR(energy-gpu.unit, rapl_unit_gpu, "Joules");
1948 RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_unit_psys, "Joules");
1949
1950 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_scale_cores, "2.3283064365386962890625e-10");
1951 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_scale_pkg, "2.3283064365386962890625e-10");
1952 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_scale_ram, "2.3283064365386962890625e-10");
1953 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_scale_gpu, "2.3283064365386962890625e-10");
1954 RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_scale_psys, "2.3283064365386962890625e-10");
1955
1956 #define RAPL_EVENT_GROUP(_name, domain) \
1957 static struct attribute *pmu_attr_##_name[] = { \
1958 &event_attr_rapl_##_name.attr.attr, \
1959 &event_attr_rapl_unit_##_name.attr.attr, \
1960 &event_attr_rapl_scale_##_name.attr.attr, \
1961 NULL \
1962 }; \
1963 static umode_t is_visible_##_name(struct kobject *kobj, struct attribute *attr, int event) \
1964 { \
1965 return rapl_pmu.domain_map & BIT(domain) ? attr->mode : 0; \
1966 } \
1967 static struct attribute_group pmu_group_##_name = { \
1968 .name = "events", \
1969 .attrs = pmu_attr_##_name, \
1970 .is_visible = is_visible_##_name, \
1971 }
1972
1973 RAPL_EVENT_GROUP(cores, RAPL_DOMAIN_PP0);
1974 RAPL_EVENT_GROUP(pkg, RAPL_DOMAIN_PACKAGE);
1975 RAPL_EVENT_GROUP(ram, RAPL_DOMAIN_DRAM);
1976 RAPL_EVENT_GROUP(gpu, RAPL_DOMAIN_PP1);
1977 RAPL_EVENT_GROUP(psys, RAPL_DOMAIN_PLATFORM);
1978
1979 static const struct attribute_group *pmu_attr_update[] = {
1980 &pmu_group_cores,
1981 &pmu_group_pkg,
1982 &pmu_group_ram,
1983 &pmu_group_gpu,
1984 &pmu_group_psys,
1985 NULL
1986 };
1987
rapl_pmu_update(struct rapl_package * rp)1988 static int rapl_pmu_update(struct rapl_package *rp)
1989 {
1990 int ret = 0;
1991
1992 /* Return if PMU already covers all events supported by current RAPL Package */
1993 if (rapl_pmu.registered && !(rp->domain_map & (~rapl_pmu.domain_map)))
1994 goto end;
1995
1996 /* Unregister previous registered PMU */
1997 if (rapl_pmu.registered)
1998 perf_pmu_unregister(&rapl_pmu.pmu);
1999
2000 rapl_pmu.registered = false;
2001 rapl_pmu.domain_map |= rp->domain_map;
2002
2003 memset(&rapl_pmu.pmu, 0, sizeof(struct pmu));
2004 rapl_pmu.pmu.attr_groups = pmu_attr_groups;
2005 rapl_pmu.pmu.attr_update = pmu_attr_update;
2006 rapl_pmu.pmu.task_ctx_nr = perf_invalid_context;
2007 rapl_pmu.pmu.event_init = rapl_pmu_event_init;
2008 rapl_pmu.pmu.add = rapl_pmu_event_add;
2009 rapl_pmu.pmu.del = rapl_pmu_event_del;
2010 rapl_pmu.pmu.start = rapl_pmu_event_start;
2011 rapl_pmu.pmu.stop = rapl_pmu_event_stop;
2012 rapl_pmu.pmu.read = rapl_pmu_event_read;
2013 rapl_pmu.pmu.module = THIS_MODULE;
2014 rapl_pmu.pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT;
2015 ret = perf_pmu_register(&rapl_pmu.pmu, "power", -1);
2016 if (ret) {
2017 pr_info("Failed to register PMU\n");
2018 return ret;
2019 }
2020
2021 rapl_pmu.registered = true;
2022 end:
2023 rp->has_pmu = true;
2024 return ret;
2025 }
2026
rapl_package_add_pmu(struct rapl_package * rp)2027 int rapl_package_add_pmu(struct rapl_package *rp)
2028 {
2029 struct rapl_package_pmu_data *data = &rp->pmu_data;
2030 int idx;
2031
2032 if (rp->has_pmu)
2033 return -EEXIST;
2034
2035 guard(cpus_read_lock)();
2036
2037 for (idx = 0; idx < rp->nr_domains; idx++) {
2038 struct rapl_domain *rd = &rp->domains[idx];
2039 int domain = rd->id;
2040 u64 val;
2041
2042 if (!test_bit(domain, &rp->domain_map))
2043 continue;
2044
2045 /*
2046 * The RAPL PMU granularity is 2^-32 Joules
2047 * data->scale[]: times of 2^-32 Joules for each ENERGY COUNTER increase
2048 */
2049 val = rd->energy_unit * (1ULL << 32);
2050 do_div(val, ENERGY_UNIT_SCALE * 1000000);
2051 data->scale[domain] = val;
2052
2053 if (!rapl_pmu.timer_ms) {
2054 struct rapl_primitive_info *rpi = get_rpi(rp, ENERGY_COUNTER);
2055
2056 /*
2057 * Calculate the timer rate:
2058 * Use reference of 200W for scaling the timeout to avoid counter
2059 * overflows.
2060 *
2061 * max_count = rpi->mask >> rpi->shift + 1
2062 * max_energy_pj = max_count * rd->energy_unit
2063 * max_time_sec = (max_energy_pj / 1000000000) / 200w
2064 *
2065 * rapl_pmu.timer_ms = max_time_sec * 1000 / 2
2066 */
2067 val = (rpi->mask >> rpi->shift) + 1;
2068 val *= rd->energy_unit;
2069 do_div(val, 1000000 * 200 * 2);
2070 rapl_pmu.timer_ms = val;
2071
2072 pr_debug("%llu ms overflow timer\n", rapl_pmu.timer_ms);
2073 }
2074
2075 pr_debug("Domain %s: hw unit %lld * 2^-32 Joules\n", rd->name, data->scale[domain]);
2076 }
2077
2078 /* Initialize per package PMU data */
2079 raw_spin_lock_init(&data->lock);
2080 INIT_LIST_HEAD(&data->active_list);
2081 data->timer_interval = ms_to_ktime(rapl_pmu.timer_ms);
2082 hrtimer_init(&data->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2083 data->hrtimer.function = rapl_hrtimer_handle;
2084
2085 return rapl_pmu_update(rp);
2086 }
2087 EXPORT_SYMBOL_GPL(rapl_package_add_pmu);
2088
rapl_package_remove_pmu(struct rapl_package * rp)2089 void rapl_package_remove_pmu(struct rapl_package *rp)
2090 {
2091 struct rapl_package *pos;
2092
2093 if (!rp->has_pmu)
2094 return;
2095
2096 guard(cpus_read_lock)();
2097
2098 list_for_each_entry(pos, &rapl_packages, plist) {
2099 /* PMU is still needed */
2100 if (pos->has_pmu && pos != rp)
2101 return;
2102 }
2103
2104 perf_pmu_unregister(&rapl_pmu.pmu);
2105 memset(&rapl_pmu, 0, sizeof(struct rapl_pmu));
2106 }
2107 EXPORT_SYMBOL_GPL(rapl_package_remove_pmu);
2108 #endif
2109
2110 /* called from CPU hotplug notifier, hotplug lock held */
rapl_remove_package_cpuslocked(struct rapl_package * rp)2111 void rapl_remove_package_cpuslocked(struct rapl_package *rp)
2112 {
2113 struct rapl_domain *rd, *rd_package = NULL;
2114
2115 package_power_limit_irq_restore(rp);
2116
2117 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
2118 int i;
2119
2120 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
2121 rapl_write_pl_data(rd, i, PL_ENABLE, 0);
2122 rapl_write_pl_data(rd, i, PL_CLAMP, 0);
2123 }
2124
2125 if (rd->id == RAPL_DOMAIN_PACKAGE) {
2126 rd_package = rd;
2127 continue;
2128 }
2129 pr_debug("remove package, undo power limit on %s: %s\n",
2130 rp->name, rd->name);
2131 powercap_unregister_zone(rp->priv->control_type,
2132 &rd->power_zone);
2133 }
2134 /* do parent zone last */
2135 powercap_unregister_zone(rp->priv->control_type,
2136 &rd_package->power_zone);
2137 list_del(&rp->plist);
2138 kfree(rp);
2139 }
2140 EXPORT_SYMBOL_GPL(rapl_remove_package_cpuslocked);
2141
rapl_remove_package(struct rapl_package * rp)2142 void rapl_remove_package(struct rapl_package *rp)
2143 {
2144 guard(cpus_read_lock)();
2145 rapl_remove_package_cpuslocked(rp);
2146 }
2147 EXPORT_SYMBOL_GPL(rapl_remove_package);
2148
2149 /*
2150 * RAPL Package energy counter scope:
2151 * 1. AMD/HYGON platforms use per-PKG package energy counter
2152 * 2. For Intel platforms
2153 * 2.1 CLX-AP platform has per-DIE package energy counter
2154 * 2.2 Other platforms that uses MSR RAPL are single die systems so the
2155 * package energy counter can be considered as per-PKG/per-DIE,
2156 * here it is considered as per-DIE.
2157 * 2.3 New platforms that use TPMI RAPL doesn't care about the
2158 * scope because they are not MSR/CPU based.
2159 */
2160 #define rapl_msrs_are_pkg_scope() \
2161 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || \
2162 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
2163
2164 /* caller to ensure CPU hotplug lock is held */
rapl_find_package_domain_cpuslocked(int id,struct rapl_if_priv * priv,bool id_is_cpu)2165 struct rapl_package *rapl_find_package_domain_cpuslocked(int id, struct rapl_if_priv *priv,
2166 bool id_is_cpu)
2167 {
2168 struct rapl_package *rp;
2169 int uid;
2170
2171 if (id_is_cpu) {
2172 uid = rapl_msrs_are_pkg_scope() ?
2173 topology_physical_package_id(id) : topology_logical_die_id(id);
2174 if (uid < 0) {
2175 pr_err("topology_logical_(package/die)_id() returned a negative value");
2176 return NULL;
2177 }
2178 }
2179 else
2180 uid = id;
2181
2182 list_for_each_entry(rp, &rapl_packages, plist) {
2183 if (rp->id == uid
2184 && rp->priv->control_type == priv->control_type)
2185 return rp;
2186 }
2187
2188 return NULL;
2189 }
2190 EXPORT_SYMBOL_GPL(rapl_find_package_domain_cpuslocked);
2191
rapl_find_package_domain(int id,struct rapl_if_priv * priv,bool id_is_cpu)2192 struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu)
2193 {
2194 guard(cpus_read_lock)();
2195 return rapl_find_package_domain_cpuslocked(id, priv, id_is_cpu);
2196 }
2197 EXPORT_SYMBOL_GPL(rapl_find_package_domain);
2198
2199 /* called from CPU hotplug notifier, hotplug lock held */
rapl_add_package_cpuslocked(int id,struct rapl_if_priv * priv,bool id_is_cpu)2200 struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *priv, bool id_is_cpu)
2201 {
2202 struct rapl_package *rp;
2203 int ret;
2204
2205 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
2206 if (!rp)
2207 return ERR_PTR(-ENOMEM);
2208
2209 if (id_is_cpu) {
2210 rp->id = rapl_msrs_are_pkg_scope() ?
2211 topology_physical_package_id(id) : topology_logical_die_id(id);
2212 if ((int)(rp->id) < 0) {
2213 pr_err("topology_logical_(package/die)_id() returned a negative value");
2214 return ERR_PTR(-EINVAL);
2215 }
2216 rp->lead_cpu = id;
2217 if (!rapl_msrs_are_pkg_scope() && topology_max_dies_per_package() > 1)
2218 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d-die-%d",
2219 topology_physical_package_id(id), topology_die_id(id));
2220 else
2221 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d",
2222 topology_physical_package_id(id));
2223 } else {
2224 rp->id = id;
2225 rp->lead_cpu = -1;
2226 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", id);
2227 }
2228
2229 rp->priv = priv;
2230 ret = rapl_config(rp);
2231 if (ret)
2232 goto err_free_package;
2233
2234 /* check if the package contains valid domains */
2235 if (rapl_detect_domains(rp)) {
2236 ret = -ENODEV;
2237 goto err_free_package;
2238 }
2239 ret = rapl_package_register_powercap(rp);
2240 if (!ret) {
2241 INIT_LIST_HEAD(&rp->plist);
2242 list_add(&rp->plist, &rapl_packages);
2243 return rp;
2244 }
2245
2246 err_free_package:
2247 kfree(rp->domains);
2248 kfree(rp);
2249 return ERR_PTR(ret);
2250 }
2251 EXPORT_SYMBOL_GPL(rapl_add_package_cpuslocked);
2252
rapl_add_package(int id,struct rapl_if_priv * priv,bool id_is_cpu)2253 struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu)
2254 {
2255 guard(cpus_read_lock)();
2256 return rapl_add_package_cpuslocked(id, priv, id_is_cpu);
2257 }
2258 EXPORT_SYMBOL_GPL(rapl_add_package);
2259
power_limit_state_save(void)2260 static void power_limit_state_save(void)
2261 {
2262 struct rapl_package *rp;
2263 struct rapl_domain *rd;
2264 int ret, i;
2265
2266 cpus_read_lock();
2267 list_for_each_entry(rp, &rapl_packages, plist) {
2268 if (!rp->power_zone)
2269 continue;
2270 rd = power_zone_to_rapl_domain(rp->power_zone);
2271 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
2272 ret = rapl_read_pl_data(rd, i, PL_LIMIT, true,
2273 &rd->rpl[i].last_power_limit);
2274 if (ret)
2275 rd->rpl[i].last_power_limit = 0;
2276 }
2277 }
2278 cpus_read_unlock();
2279 }
2280
power_limit_state_restore(void)2281 static void power_limit_state_restore(void)
2282 {
2283 struct rapl_package *rp;
2284 struct rapl_domain *rd;
2285 int i;
2286
2287 cpus_read_lock();
2288 list_for_each_entry(rp, &rapl_packages, plist) {
2289 if (!rp->power_zone)
2290 continue;
2291 rd = power_zone_to_rapl_domain(rp->power_zone);
2292 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
2293 if (rd->rpl[i].last_power_limit)
2294 rapl_write_pl_data(rd, i, PL_LIMIT,
2295 rd->rpl[i].last_power_limit);
2296 }
2297 cpus_read_unlock();
2298 }
2299
rapl_pm_callback(struct notifier_block * nb,unsigned long mode,void * _unused)2300 static int rapl_pm_callback(struct notifier_block *nb,
2301 unsigned long mode, void *_unused)
2302 {
2303 switch (mode) {
2304 case PM_SUSPEND_PREPARE:
2305 power_limit_state_save();
2306 break;
2307 case PM_POST_SUSPEND:
2308 power_limit_state_restore();
2309 break;
2310 }
2311 return NOTIFY_OK;
2312 }
2313
2314 static struct notifier_block rapl_pm_notifier = {
2315 .notifier_call = rapl_pm_callback,
2316 };
2317
2318 static struct platform_device *rapl_msr_platdev;
2319
rapl_init(void)2320 static int __init rapl_init(void)
2321 {
2322 const struct x86_cpu_id *id;
2323 int ret;
2324
2325 id = x86_match_cpu(rapl_ids);
2326 if (id) {
2327 defaults_msr = (struct rapl_defaults *)id->driver_data;
2328
2329 rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0);
2330 if (!rapl_msr_platdev)
2331 return -ENOMEM;
2332
2333 ret = platform_device_add(rapl_msr_platdev);
2334 if (ret) {
2335 platform_device_put(rapl_msr_platdev);
2336 return ret;
2337 }
2338 }
2339
2340 ret = register_pm_notifier(&rapl_pm_notifier);
2341 if (ret && rapl_msr_platdev) {
2342 platform_device_del(rapl_msr_platdev);
2343 platform_device_put(rapl_msr_platdev);
2344 }
2345
2346 return ret;
2347 }
2348
rapl_exit(void)2349 static void __exit rapl_exit(void)
2350 {
2351 platform_device_unregister(rapl_msr_platdev);
2352 unregister_pm_notifier(&rapl_pm_notifier);
2353 }
2354
2355 fs_initcall(rapl_init);
2356 module_exit(rapl_exit);
2357
2358 MODULE_DESCRIPTION("Intel Runtime Average Power Limit (RAPL) common code");
2359 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
2360 MODULE_LICENSE("GPL v2");
2361