1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
39
40 static struct class timecard_class = {
41 .name = "timecard",
42 };
43
44 struct ocp_reg {
45 u32 ctrl;
46 u32 status;
47 u32 select;
48 u32 version;
49 u32 time_ns;
50 u32 time_sec;
51 u32 __pad0[2];
52 u32 adjust_ns;
53 u32 adjust_sec;
54 u32 __pad1[2];
55 u32 offset_ns;
56 u32 offset_window_ns;
57 u32 __pad2[2];
58 u32 drift_ns;
59 u32 drift_window_ns;
60 u32 __pad3[6];
61 u32 servo_offset_p;
62 u32 servo_offset_i;
63 u32 servo_drift_p;
64 u32 servo_drift_i;
65 u32 status_offset;
66 u32 status_drift;
67 };
68
69 struct ptp_ocp_servo_conf {
70 u32 servo_offset_p;
71 u32 servo_offset_i;
72 u32 servo_drift_p;
73 u32 servo_drift_i;
74 };
75
76 #define OCP_CTRL_ENABLE BIT(0)
77 #define OCP_CTRL_ADJUST_TIME BIT(1)
78 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
79 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
80 #define OCP_CTRL_ADJUST_SERVO BIT(8)
81 #define OCP_CTRL_READ_TIME_REQ BIT(30)
82 #define OCP_CTRL_READ_TIME_DONE BIT(31)
83
84 #define OCP_STATUS_IN_SYNC BIT(0)
85 #define OCP_STATUS_IN_HOLDOVER BIT(1)
86
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
89
90 struct tod_reg {
91 u32 ctrl;
92 u32 status;
93 u32 uart_polarity;
94 u32 version;
95 u32 adj_sec;
96 u32 __pad0[3];
97 u32 uart_baud;
98 u32 __pad1[3];
99 u32 utc_status;
100 u32 leap;
101 };
102
103 #define TOD_CTRL_PROTOCOL BIT(28)
104 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
105 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
108 #define TOD_CTRL_GNSS_SHIFT 24
109
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
111 #define TOD_STATUS_UTC_VALID BIT(8)
112 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
113 #define TOD_STATUS_LEAP_VALID BIT(16)
114
115 struct ts_reg {
116 u32 enable;
117 u32 error;
118 u32 polarity;
119 u32 version;
120 u32 __pad0[4];
121 u32 cable_delay;
122 u32 __pad1[3];
123 u32 intr;
124 u32 intr_mask;
125 u32 event_count;
126 u32 __pad2[1];
127 u32 ts_count;
128 u32 time_ns;
129 u32 time_sec;
130 u32 data_width;
131 u32 data;
132 };
133
134 struct pps_reg {
135 u32 ctrl;
136 u32 status;
137 u32 __pad0[6];
138 u32 cable_delay;
139 };
140
141 #define PPS_STATUS_FILTER_ERR BIT(0)
142 #define PPS_STATUS_SUPERV_ERR BIT(1)
143
144 struct img_reg {
145 u32 version;
146 };
147
148 struct gpio_reg {
149 u32 gpio1;
150 u32 __pad0;
151 u32 gpio2;
152 u32 __pad1;
153 };
154
155 struct irig_master_reg {
156 u32 ctrl;
157 u32 status;
158 u32 __pad0;
159 u32 version;
160 u32 adj_sec;
161 u32 mode_ctrl;
162 };
163
164 #define IRIG_M_CTRL_ENABLE BIT(0)
165
166 struct irig_slave_reg {
167 u32 ctrl;
168 u32 status;
169 u32 __pad0;
170 u32 version;
171 u32 adj_sec;
172 u32 mode_ctrl;
173 };
174
175 #define IRIG_S_CTRL_ENABLE BIT(0)
176
177 struct dcf_master_reg {
178 u32 ctrl;
179 u32 status;
180 u32 __pad0;
181 u32 version;
182 u32 adj_sec;
183 };
184
185 #define DCF_M_CTRL_ENABLE BIT(0)
186
187 struct dcf_slave_reg {
188 u32 ctrl;
189 u32 status;
190 u32 __pad0;
191 u32 version;
192 u32 adj_sec;
193 };
194
195 #define DCF_S_CTRL_ENABLE BIT(0)
196
197 struct signal_reg {
198 u32 enable;
199 u32 status;
200 u32 polarity;
201 u32 version;
202 u32 __pad0[4];
203 u32 cable_delay;
204 u32 __pad1[3];
205 u32 intr;
206 u32 intr_mask;
207 u32 __pad2[2];
208 u32 start_ns;
209 u32 start_sec;
210 u32 pulse_ns;
211 u32 pulse_sec;
212 u32 period_ns;
213 u32 period_sec;
214 u32 repeat_count;
215 };
216
217 struct frequency_reg {
218 u32 ctrl;
219 u32 status;
220 };
221
222 struct board_config_reg {
223 u32 mro50_serial_activate;
224 };
225
226 #define FREQ_STATUS_VALID BIT(31)
227 #define FREQ_STATUS_ERROR BIT(30)
228 #define FREQ_STATUS_OVERRUN BIT(29)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
230
231 struct ptp_ocp_flash_info {
232 const char *name;
233 int pci_offset;
234 int data_size;
235 void *data;
236 };
237
238 struct ptp_ocp_firmware_header {
239 char magic[4];
240 __be16 pci_vendor_id;
241 __be16 pci_device_id;
242 __be32 image_size;
243 __be16 hw_revision;
244 __be16 crc;
245 };
246
247 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
248
249 struct ptp_ocp_i2c_info {
250 const char *name;
251 unsigned long fixed_rate;
252 size_t data_size;
253 void *data;
254 };
255
256 struct ptp_ocp_ext_info {
257 int index;
258 irqreturn_t (*irq_fcn)(int irq, void *priv);
259 int (*enable)(void *priv, u32 req, bool enable);
260 };
261
262 struct ptp_ocp_ext_src {
263 void __iomem *mem;
264 struct ptp_ocp *bp;
265 struct ptp_ocp_ext_info *info;
266 int irq_vec;
267 };
268
269 enum ptp_ocp_sma_mode {
270 SMA_MODE_IN,
271 SMA_MODE_OUT,
272 };
273
274 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
275 DPLL_PIN_FREQUENCY_1PPS,
276 DPLL_PIN_FREQUENCY_10MHZ,
277 DPLL_PIN_FREQUENCY_IRIG_B,
278 DPLL_PIN_FREQUENCY_DCF77,
279 };
280
281 struct ptp_ocp_sma_connector {
282 enum ptp_ocp_sma_mode mode;
283 bool fixed_fcn;
284 bool fixed_dir;
285 bool disabled;
286 u8 default_fcn;
287 struct dpll_pin *dpll_pin;
288 struct dpll_pin_properties dpll_prop;
289 };
290
291 struct ocp_attr_group {
292 u64 cap;
293 const struct attribute_group *group;
294 };
295
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
299
300 struct ptp_ocp_signal {
301 ktime_t period;
302 ktime_t pulse;
303 ktime_t phase;
304 ktime_t start;
305 int duty;
306 bool polarity;
307 bool running;
308 };
309
310 struct ptp_ocp_serial_port {
311 int line;
312 int baud;
313 };
314
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
318 #define OCP_SIGNAL_NUM 4
319 #define OCP_FREQ_NUM 4
320
321 enum {
322 PORT_GNSS,
323 PORT_GNSS2,
324 PORT_MAC, /* miniature atomic clock */
325 PORT_NMEA,
326
327 __PORT_COUNT,
328 };
329
330 struct ptp_ocp {
331 struct pci_dev *pdev;
332 struct device dev;
333 spinlock_t lock;
334 struct ocp_reg __iomem *reg;
335 struct tod_reg __iomem *tod;
336 struct pps_reg __iomem *pps_to_ext;
337 struct pps_reg __iomem *pps_to_clk;
338 struct board_config_reg __iomem *board_config;
339 struct gpio_reg __iomem *pps_select;
340 struct gpio_reg __iomem *sma_map1;
341 struct gpio_reg __iomem *sma_map2;
342 struct irig_master_reg __iomem *irig_out;
343 struct irig_slave_reg __iomem *irig_in;
344 struct dcf_master_reg __iomem *dcf_out;
345 struct dcf_slave_reg __iomem *dcf_in;
346 struct tod_reg __iomem *nmea_out;
347 struct frequency_reg __iomem *freq_in[OCP_FREQ_NUM];
348 struct ptp_ocp_ext_src *signal_out[OCP_SIGNAL_NUM];
349 struct ptp_ocp_ext_src *pps;
350 struct ptp_ocp_ext_src *ts0;
351 struct ptp_ocp_ext_src *ts1;
352 struct ptp_ocp_ext_src *ts2;
353 struct ptp_ocp_ext_src *ts3;
354 struct ptp_ocp_ext_src *ts4;
355 struct ocp_art_gpio_reg __iomem *art_sma;
356 struct img_reg __iomem *image;
357 struct ptp_clock *ptp;
358 struct ptp_clock_info ptp_info;
359 struct platform_device *i2c_ctrl;
360 struct platform_device *spi_flash;
361 struct clk_hw *i2c_clk;
362 struct timer_list watchdog;
363 const struct attribute_group **attr_group;
364 const struct ptp_ocp_eeprom_map *eeprom_map;
365 struct dentry *debug_root;
366 bool sync;
367 time64_t gnss_lost;
368 struct delayed_work sync_work;
369 int id;
370 int n_irqs;
371 struct ptp_ocp_serial_port port[__PORT_COUNT];
372 bool fw_loader;
373 u8 fw_tag;
374 u16 fw_version;
375 u8 board_id[OCP_BOARD_ID_LEN];
376 u8 serial[OCP_SERIAL_LEN];
377 bool has_eeprom_data;
378 u32 pps_req_map;
379 int flash_start;
380 u32 utc_tai_offset;
381 u32 ts_window_adjust;
382 u64 fw_cap;
383 struct ptp_ocp_signal signal[OCP_SIGNAL_NUM];
384 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
385 const struct ocp_sma_op *sma_op;
386 struct dpll_device *dpll;
387 int signals_nr;
388 int freq_in_nr;
389 };
390
391 #define OCP_REQ_TIMESTAMP BIT(0)
392 #define OCP_REQ_PPS BIT(1)
393
394 struct ocp_resource {
395 unsigned long offset;
396 int size;
397 int irq_vec;
398 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
399 void *extra;
400 unsigned long bp_offset;
401 const char * const name;
402 };
403
404 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
405 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
406 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
407 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
408 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
409 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
410 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
411 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
412 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
413 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
414 struct ptp_perout_request *req);
415 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
416 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
417
418 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
419
420 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
421
422 static const struct ocp_attr_group fb_timecard_groups[];
423
424 static const struct ocp_attr_group art_timecard_groups[];
425
426 static const struct ocp_attr_group adva_timecard_groups[];
427
428 struct ptp_ocp_eeprom_map {
429 u16 off;
430 u16 len;
431 u32 bp_offset;
432 const void * const tag;
433 };
434
435 #define EEPROM_ENTRY(addr, member) \
436 .off = addr, \
437 .len = sizeof_field(struct ptp_ocp, member), \
438 .bp_offset = offsetof(struct ptp_ocp, member)
439
440 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
441 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
442 })
443
444 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
445 { EEPROM_ENTRY(0x43, board_id) },
446 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
447 { }
448 };
449
450 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
451 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
452 { EEPROM_ENTRY(0x200 + 0x63, serial) },
453 { }
454 };
455
456 #define bp_assign_entry(bp, res, val) ({ \
457 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
458 *(typeof(val) *)addr = val; \
459 })
460
461 #define OCP_RES_LOCATION(member) \
462 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
463
464 #define OCP_MEM_RESOURCE(member) \
465 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
466
467 #define OCP_SERIAL_RESOURCE(member) \
468 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
469
470 #define OCP_I2C_RESOURCE(member) \
471 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
472
473 #define OCP_SPI_RESOURCE(member) \
474 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
475
476 #define OCP_EXT_RESOURCE(member) \
477 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
478
479 /* This is the MSI vector mapping used.
480 * 0: PPS (TS5)
481 * 1: TS0
482 * 2: TS1
483 * 3: GNSS1
484 * 4: GNSS2
485 * 5: MAC
486 * 6: TS2
487 * 7: I2C controller
488 * 8: HWICAP (notused)
489 * 9: SPI Flash
490 * 10: NMEA
491 * 11: Signal Generator 1
492 * 12: Signal Generator 2
493 * 13: Signal Generator 3
494 * 14: Signal Generator 4
495 * 15: TS3
496 * 16: TS4
497 --
498 * 8: Orolia TS1
499 * 10: Orolia TS2
500 * 11: Orolia TS0 (GNSS)
501 * 12: Orolia PPS
502 * 14: Orolia TS3
503 * 15: Orolia TS4
504 */
505
506 static struct ocp_resource ocp_fb_resource[] = {
507 {
508 OCP_MEM_RESOURCE(reg),
509 .offset = 0x01000000, .size = 0x10000,
510 },
511 {
512 OCP_EXT_RESOURCE(ts0),
513 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
514 .extra = &(struct ptp_ocp_ext_info) {
515 .index = 0,
516 .irq_fcn = ptp_ocp_ts_irq,
517 .enable = ptp_ocp_ts_enable,
518 },
519 },
520 {
521 OCP_EXT_RESOURCE(ts1),
522 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
523 .extra = &(struct ptp_ocp_ext_info) {
524 .index = 1,
525 .irq_fcn = ptp_ocp_ts_irq,
526 .enable = ptp_ocp_ts_enable,
527 },
528 },
529 {
530 OCP_EXT_RESOURCE(ts2),
531 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
532 .extra = &(struct ptp_ocp_ext_info) {
533 .index = 2,
534 .irq_fcn = ptp_ocp_ts_irq,
535 .enable = ptp_ocp_ts_enable,
536 },
537 },
538 {
539 OCP_EXT_RESOURCE(ts3),
540 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
541 .extra = &(struct ptp_ocp_ext_info) {
542 .index = 3,
543 .irq_fcn = ptp_ocp_ts_irq,
544 .enable = ptp_ocp_ts_enable,
545 },
546 },
547 {
548 OCP_EXT_RESOURCE(ts4),
549 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
550 .extra = &(struct ptp_ocp_ext_info) {
551 .index = 4,
552 .irq_fcn = ptp_ocp_ts_irq,
553 .enable = ptp_ocp_ts_enable,
554 },
555 },
556 /* Timestamp for PHC and/or PPS generator */
557 {
558 OCP_EXT_RESOURCE(pps),
559 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
560 .extra = &(struct ptp_ocp_ext_info) {
561 .index = 5,
562 .irq_fcn = ptp_ocp_ts_irq,
563 .enable = ptp_ocp_ts_enable,
564 },
565 },
566 {
567 OCP_EXT_RESOURCE(signal_out[0]),
568 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
569 .extra = &(struct ptp_ocp_ext_info) {
570 .index = 1,
571 .irq_fcn = ptp_ocp_signal_irq,
572 .enable = ptp_ocp_signal_enable,
573 },
574 },
575 {
576 OCP_EXT_RESOURCE(signal_out[1]),
577 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
578 .extra = &(struct ptp_ocp_ext_info) {
579 .index = 2,
580 .irq_fcn = ptp_ocp_signal_irq,
581 .enable = ptp_ocp_signal_enable,
582 },
583 },
584 {
585 OCP_EXT_RESOURCE(signal_out[2]),
586 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
587 .extra = &(struct ptp_ocp_ext_info) {
588 .index = 3,
589 .irq_fcn = ptp_ocp_signal_irq,
590 .enable = ptp_ocp_signal_enable,
591 },
592 },
593 {
594 OCP_EXT_RESOURCE(signal_out[3]),
595 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
596 .extra = &(struct ptp_ocp_ext_info) {
597 .index = 4,
598 .irq_fcn = ptp_ocp_signal_irq,
599 .enable = ptp_ocp_signal_enable,
600 },
601 },
602 {
603 OCP_MEM_RESOURCE(pps_to_ext),
604 .offset = 0x01030000, .size = 0x10000,
605 },
606 {
607 OCP_MEM_RESOURCE(pps_to_clk),
608 .offset = 0x01040000, .size = 0x10000,
609 },
610 {
611 OCP_MEM_RESOURCE(tod),
612 .offset = 0x01050000, .size = 0x10000,
613 },
614 {
615 OCP_MEM_RESOURCE(irig_in),
616 .offset = 0x01070000, .size = 0x10000,
617 },
618 {
619 OCP_MEM_RESOURCE(irig_out),
620 .offset = 0x01080000, .size = 0x10000,
621 },
622 {
623 OCP_MEM_RESOURCE(dcf_in),
624 .offset = 0x01090000, .size = 0x10000,
625 },
626 {
627 OCP_MEM_RESOURCE(dcf_out),
628 .offset = 0x010A0000, .size = 0x10000,
629 },
630 {
631 OCP_MEM_RESOURCE(nmea_out),
632 .offset = 0x010B0000, .size = 0x10000,
633 },
634 {
635 OCP_MEM_RESOURCE(image),
636 .offset = 0x00020000, .size = 0x1000,
637 },
638 {
639 OCP_MEM_RESOURCE(pps_select),
640 .offset = 0x00130000, .size = 0x1000,
641 },
642 {
643 OCP_MEM_RESOURCE(sma_map1),
644 .offset = 0x00140000, .size = 0x1000,
645 },
646 {
647 OCP_MEM_RESOURCE(sma_map2),
648 .offset = 0x00220000, .size = 0x1000,
649 },
650 {
651 OCP_I2C_RESOURCE(i2c_ctrl),
652 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
653 .extra = &(struct ptp_ocp_i2c_info) {
654 .name = "xiic-i2c",
655 .fixed_rate = 50000000,
656 .data_size = sizeof(struct xiic_i2c_platform_data),
657 .data = &(struct xiic_i2c_platform_data) {
658 .num_devices = 2,
659 .devices = (struct i2c_board_info[]) {
660 { I2C_BOARD_INFO("24c02", 0x50) },
661 { I2C_BOARD_INFO("24mac402", 0x58),
662 .platform_data = "mac" },
663 },
664 },
665 },
666 },
667 {
668 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
669 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
670 .extra = &(struct ptp_ocp_serial_port) {
671 .baud = 115200,
672 },
673 },
674 {
675 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
676 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
677 .extra = &(struct ptp_ocp_serial_port) {
678 .baud = 115200,
679 },
680 },
681 {
682 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
683 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
684 .extra = &(struct ptp_ocp_serial_port) {
685 .baud = 57600,
686 },
687 },
688 {
689 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
690 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
691 },
692 {
693 OCP_SPI_RESOURCE(spi_flash),
694 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
695 .extra = &(struct ptp_ocp_flash_info) {
696 .name = "xilinx_spi", .pci_offset = 0,
697 .data_size = sizeof(struct xspi_platform_data),
698 .data = &(struct xspi_platform_data) {
699 .num_chipselect = 1,
700 .bits_per_word = 8,
701 .num_devices = 1,
702 .force_irq = true,
703 .devices = &(struct spi_board_info) {
704 .modalias = "spi-nor",
705 },
706 },
707 },
708 },
709 {
710 OCP_MEM_RESOURCE(freq_in[0]),
711 .offset = 0x01200000, .size = 0x10000,
712 },
713 {
714 OCP_MEM_RESOURCE(freq_in[1]),
715 .offset = 0x01210000, .size = 0x10000,
716 },
717 {
718 OCP_MEM_RESOURCE(freq_in[2]),
719 .offset = 0x01220000, .size = 0x10000,
720 },
721 {
722 OCP_MEM_RESOURCE(freq_in[3]),
723 .offset = 0x01230000, .size = 0x10000,
724 },
725 {
726 .setup = ptp_ocp_fb_board_init,
727 .extra = &(struct ptp_ocp_servo_conf) {
728 .servo_offset_p = 0x2000,
729 .servo_offset_i = 0x1000,
730 .servo_drift_p = 0,
731 .servo_drift_i = 0,
732 },
733 },
734 { }
735 };
736
737 #define OCP_ART_CONFIG_SIZE 144
738 #define OCP_ART_TEMP_TABLE_SIZE 368
739
740 struct ocp_art_gpio_reg {
741 struct {
742 u32 gpio;
743 u32 __pad[3];
744 } map[4];
745 };
746
747 static struct ocp_resource ocp_art_resource[] = {
748 {
749 OCP_MEM_RESOURCE(reg),
750 .offset = 0x01000000, .size = 0x10000,
751 },
752 {
753 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
754 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
755 .extra = &(struct ptp_ocp_serial_port) {
756 .baud = 115200,
757 },
758 },
759 {
760 OCP_MEM_RESOURCE(art_sma),
761 .offset = 0x003C0000, .size = 0x1000,
762 },
763 /* Timestamp associated with GNSS1 receiver PPS */
764 {
765 OCP_EXT_RESOURCE(ts0),
766 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
767 .extra = &(struct ptp_ocp_ext_info) {
768 .index = 0,
769 .irq_fcn = ptp_ocp_ts_irq,
770 .enable = ptp_ocp_ts_enable,
771 },
772 },
773 {
774 OCP_EXT_RESOURCE(ts1),
775 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
776 .extra = &(struct ptp_ocp_ext_info) {
777 .index = 1,
778 .irq_fcn = ptp_ocp_ts_irq,
779 .enable = ptp_ocp_ts_enable,
780 },
781 },
782 {
783 OCP_EXT_RESOURCE(ts2),
784 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
785 .extra = &(struct ptp_ocp_ext_info) {
786 .index = 2,
787 .irq_fcn = ptp_ocp_ts_irq,
788 .enable = ptp_ocp_ts_enable,
789 },
790 },
791 {
792 OCP_EXT_RESOURCE(ts3),
793 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
794 .extra = &(struct ptp_ocp_ext_info) {
795 .index = 3,
796 .irq_fcn = ptp_ocp_ts_irq,
797 .enable = ptp_ocp_ts_enable,
798 },
799 },
800 {
801 OCP_EXT_RESOURCE(ts4),
802 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
803 .extra = &(struct ptp_ocp_ext_info) {
804 .index = 4,
805 .irq_fcn = ptp_ocp_ts_irq,
806 .enable = ptp_ocp_ts_enable,
807 },
808 },
809 /* Timestamp associated with Internal PPS of the card */
810 {
811 OCP_EXT_RESOURCE(pps),
812 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
813 .extra = &(struct ptp_ocp_ext_info) {
814 .index = 5,
815 .irq_fcn = ptp_ocp_ts_irq,
816 .enable = ptp_ocp_ts_enable,
817 },
818 },
819 {
820 OCP_SPI_RESOURCE(spi_flash),
821 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
822 .extra = &(struct ptp_ocp_flash_info) {
823 .name = "spi_altera", .pci_offset = 0,
824 .data_size = sizeof(struct altera_spi_platform_data),
825 .data = &(struct altera_spi_platform_data) {
826 .num_chipselect = 1,
827 .num_devices = 1,
828 .devices = &(struct spi_board_info) {
829 .modalias = "spi-nor",
830 },
831 },
832 },
833 },
834 {
835 OCP_I2C_RESOURCE(i2c_ctrl),
836 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
837 .extra = &(struct ptp_ocp_i2c_info) {
838 .name = "ocores-i2c",
839 .fixed_rate = 400000,
840 .data_size = sizeof(struct ocores_i2c_platform_data),
841 .data = &(struct ocores_i2c_platform_data) {
842 .clock_khz = 125000,
843 .bus_khz = 400,
844 .num_devices = 1,
845 .devices = &(struct i2c_board_info) {
846 I2C_BOARD_INFO("24c08", 0x50),
847 },
848 },
849 },
850 },
851 {
852 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
853 .offset = 0x00190000, .irq_vec = 7,
854 .extra = &(struct ptp_ocp_serial_port) {
855 .baud = 9600,
856 },
857 },
858 {
859 OCP_MEM_RESOURCE(board_config),
860 .offset = 0x210000, .size = 0x1000,
861 },
862 {
863 .setup = ptp_ocp_art_board_init,
864 .extra = &(struct ptp_ocp_servo_conf) {
865 .servo_offset_p = 0x2000,
866 .servo_offset_i = 0x1000,
867 .servo_drift_p = 0,
868 .servo_drift_i = 0,
869 },
870 },
871 { }
872 };
873
874 static struct ocp_resource ocp_adva_resource[] = {
875 {
876 OCP_MEM_RESOURCE(reg),
877 .offset = 0x01000000, .size = 0x10000,
878 },
879 {
880 OCP_EXT_RESOURCE(ts0),
881 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
882 .extra = &(struct ptp_ocp_ext_info) {
883 .index = 0,
884 .irq_fcn = ptp_ocp_ts_irq,
885 .enable = ptp_ocp_ts_enable,
886 },
887 },
888 {
889 OCP_EXT_RESOURCE(ts1),
890 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
891 .extra = &(struct ptp_ocp_ext_info) {
892 .index = 1,
893 .irq_fcn = ptp_ocp_ts_irq,
894 .enable = ptp_ocp_ts_enable,
895 },
896 },
897 {
898 OCP_EXT_RESOURCE(ts2),
899 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
900 .extra = &(struct ptp_ocp_ext_info) {
901 .index = 2,
902 .irq_fcn = ptp_ocp_ts_irq,
903 .enable = ptp_ocp_ts_enable,
904 },
905 },
906 /* Timestamp for PHC and/or PPS generator */
907 {
908 OCP_EXT_RESOURCE(pps),
909 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
910 .extra = &(struct ptp_ocp_ext_info) {
911 .index = 5,
912 .irq_fcn = ptp_ocp_ts_irq,
913 .enable = ptp_ocp_ts_enable,
914 },
915 },
916 {
917 OCP_EXT_RESOURCE(signal_out[0]),
918 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
919 .extra = &(struct ptp_ocp_ext_info) {
920 .index = 1,
921 .irq_fcn = ptp_ocp_signal_irq,
922 .enable = ptp_ocp_signal_enable,
923 },
924 },
925 {
926 OCP_EXT_RESOURCE(signal_out[1]),
927 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
928 .extra = &(struct ptp_ocp_ext_info) {
929 .index = 2,
930 .irq_fcn = ptp_ocp_signal_irq,
931 .enable = ptp_ocp_signal_enable,
932 },
933 },
934 {
935 OCP_MEM_RESOURCE(pps_to_ext),
936 .offset = 0x01030000, .size = 0x10000,
937 },
938 {
939 OCP_MEM_RESOURCE(pps_to_clk),
940 .offset = 0x01040000, .size = 0x10000,
941 },
942 {
943 OCP_MEM_RESOURCE(tod),
944 .offset = 0x01050000, .size = 0x10000,
945 },
946 {
947 OCP_MEM_RESOURCE(image),
948 .offset = 0x00020000, .size = 0x1000,
949 },
950 {
951 OCP_MEM_RESOURCE(pps_select),
952 .offset = 0x00130000, .size = 0x1000,
953 },
954 {
955 OCP_MEM_RESOURCE(sma_map1),
956 .offset = 0x00140000, .size = 0x1000,
957 },
958 {
959 OCP_MEM_RESOURCE(sma_map2),
960 .offset = 0x00220000, .size = 0x1000,
961 },
962 {
963 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
964 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
965 .extra = &(struct ptp_ocp_serial_port) {
966 .baud = 9600,
967 },
968 },
969 {
970 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
971 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
972 .extra = &(struct ptp_ocp_serial_port) {
973 .baud = 115200,
974 },
975 },
976 {
977 OCP_MEM_RESOURCE(freq_in[0]),
978 .offset = 0x01200000, .size = 0x10000,
979 },
980 {
981 OCP_MEM_RESOURCE(freq_in[1]),
982 .offset = 0x01210000, .size = 0x10000,
983 },
984 {
985 OCP_SPI_RESOURCE(spi_flash),
986 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
987 .extra = &(struct ptp_ocp_flash_info) {
988 .name = "spi_altera", .pci_offset = 0,
989 .data_size = sizeof(struct altera_spi_platform_data),
990 .data = &(struct altera_spi_platform_data) {
991 .num_chipselect = 1,
992 .num_devices = 1,
993 .devices = &(struct spi_board_info) {
994 .modalias = "spi-nor",
995 },
996 },
997 },
998 },
999 {
1000 OCP_I2C_RESOURCE(i2c_ctrl),
1001 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
1002 .extra = &(struct ptp_ocp_i2c_info) {
1003 .name = "ocores-i2c",
1004 .fixed_rate = 50000000,
1005 .data_size = sizeof(struct ocores_i2c_platform_data),
1006 .data = &(struct ocores_i2c_platform_data) {
1007 .clock_khz = 50000,
1008 .bus_khz = 100,
1009 .reg_io_width = 4, // 32-bit/4-byte
1010 .reg_shift = 2, // 32-bit addressing
1011 .num_devices = 2,
1012 .devices = (struct i2c_board_info[]) {
1013 { I2C_BOARD_INFO("24c02", 0x50) },
1014 { I2C_BOARD_INFO("24mac402", 0x58),
1015 .platform_data = "mac" },
1016 },
1017 },
1018 },
1019 },
1020 {
1021 .setup = ptp_ocp_adva_board_init,
1022 .extra = &(struct ptp_ocp_servo_conf) {
1023 .servo_offset_p = 0xc000,
1024 .servo_offset_i = 0x1000,
1025 .servo_drift_p = 0,
1026 .servo_drift_i = 0,
1027 },
1028 },
1029 { }
1030 };
1031
1032 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1033 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
1034 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1035 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1036 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1037 { }
1038 };
1039 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1040
1041 static DEFINE_MUTEX(ptp_ocp_lock);
1042 static DEFINE_IDR(ptp_ocp_idr);
1043
1044 struct ocp_selector {
1045 const char *name;
1046 int value;
1047 u64 frequency;
1048 };
1049
1050 static const struct ocp_selector ptp_ocp_clock[] = {
1051 { .name = "NONE", .value = 0 },
1052 { .name = "TOD", .value = 1 },
1053 { .name = "IRIG", .value = 2 },
1054 { .name = "PPS", .value = 3 },
1055 { .name = "PTP", .value = 4 },
1056 { .name = "RTC", .value = 5 },
1057 { .name = "DCF", .value = 6 },
1058 { .name = "REGS", .value = 0xfe },
1059 { .name = "EXT", .value = 0xff },
1060 { }
1061 };
1062
1063 #define SMA_DISABLE BIT(16)
1064 #define SMA_ENABLE BIT(15)
1065 #define SMA_SELECT_MASK GENMASK(14, 0)
1066
1067 static const struct ocp_selector ptp_ocp_sma_in[] = {
1068 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1069 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1070 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1071 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1072 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1073 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1074 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1075 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1076 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1077 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1078 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1079 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1080 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1081 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1082 { }
1083 };
1084
1085 static const struct ocp_selector ptp_ocp_sma_out[] = {
1086 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1087 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1088 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1089 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1090 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1091 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1092 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1093 { .name = "GEN1", .value = 0x0040 },
1094 { .name = "GEN2", .value = 0x0080 },
1095 { .name = "GEN3", .value = 0x0100 },
1096 { .name = "GEN4", .value = 0x0200 },
1097 { .name = "GND", .value = 0x2000 },
1098 { .name = "VCC", .value = 0x4000 },
1099 { }
1100 };
1101
1102 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1103 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1104 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1105 { }
1106 };
1107
1108 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1109 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1110 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1111 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1112 { }
1113 };
1114
1115 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1116 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1117 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1118 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1119 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1120 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1121 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1122 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1123 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1124 { }
1125 };
1126
1127 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1128 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1129 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1130 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1131 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1132 { .name = "GEN1", .value = 0x0040 },
1133 { .name = "GEN2", .value = 0x0080 },
1134 { .name = "GND", .value = 0x2000 },
1135 { .name = "VCC", .value = 0x4000 },
1136 { }
1137 };
1138
1139 struct ocp_sma_op {
1140 const struct ocp_selector *tbl[2];
1141 void (*init)(struct ptp_ocp *bp);
1142 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1143 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1144 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1145 };
1146
1147 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)1148 ptp_ocp_sma_init(struct ptp_ocp *bp)
1149 {
1150 return bp->sma_op->init(bp);
1151 }
1152
1153 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)1154 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1155 {
1156 return bp->sma_op->get(bp, sma_nr);
1157 }
1158
1159 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)1160 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1161 {
1162 return bp->sma_op->set_inputs(bp, sma_nr, val);
1163 }
1164
1165 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)1166 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1167 {
1168 return bp->sma_op->set_output(bp, sma_nr, val);
1169 }
1170
1171 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)1172 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1173 {
1174 int i;
1175
1176 for (i = 0; tbl[i].name; i++)
1177 if (tbl[i].value == val)
1178 return tbl[i].name;
1179 return NULL;
1180 }
1181
1182 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)1183 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1184 {
1185 const char *select;
1186 int i;
1187
1188 for (i = 0; tbl[i].name; i++) {
1189 select = tbl[i].name;
1190 if (!strncasecmp(name, select, strlen(select)))
1191 return tbl[i].value;
1192 }
1193 return -EINVAL;
1194 }
1195
1196 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)1197 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1198 {
1199 ssize_t count;
1200 int i;
1201
1202 count = 0;
1203 for (i = 0; tbl[i].name; i++)
1204 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1205 if (count)
1206 count--;
1207 count += sysfs_emit_at(buf, count, "\n");
1208 return count;
1209 }
1210
1211 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1212 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1213 struct ptp_system_timestamp *sts)
1214 {
1215 u32 ctrl, time_sec, time_ns;
1216 int i;
1217
1218 ptp_read_system_prets(sts);
1219
1220 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1221 iowrite32(ctrl, &bp->reg->ctrl);
1222
1223 for (i = 0; i < 100; i++) {
1224 ctrl = ioread32(&bp->reg->ctrl);
1225 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1226 break;
1227 }
1228 ptp_read_system_postts(sts);
1229
1230 if (sts && bp->ts_window_adjust) {
1231 s64 ns = timespec64_to_ns(&sts->post_ts);
1232
1233 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1234 }
1235
1236 time_ns = ioread32(&bp->reg->time_ns);
1237 time_sec = ioread32(&bp->reg->time_sec);
1238
1239 ts->tv_sec = time_sec;
1240 ts->tv_nsec = time_ns;
1241
1242 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1243 }
1244
1245 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1246 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1247 struct ptp_system_timestamp *sts)
1248 {
1249 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1250 unsigned long flags;
1251 int err;
1252
1253 spin_lock_irqsave(&bp->lock, flags);
1254 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1255 spin_unlock_irqrestore(&bp->lock, flags);
1256
1257 return err;
1258 }
1259
1260 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1261 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1262 {
1263 u32 ctrl, time_sec, time_ns;
1264 u32 select;
1265
1266 time_ns = ts->tv_nsec;
1267 time_sec = ts->tv_sec;
1268
1269 select = ioread32(&bp->reg->select);
1270 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1271
1272 iowrite32(time_ns, &bp->reg->adjust_ns);
1273 iowrite32(time_sec, &bp->reg->adjust_sec);
1274
1275 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1276 iowrite32(ctrl, &bp->reg->ctrl);
1277
1278 /* restore clock selection */
1279 iowrite32(select >> 16, &bp->reg->select);
1280 }
1281
1282 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1283 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1284 {
1285 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1286 unsigned long flags;
1287
1288 spin_lock_irqsave(&bp->lock, flags);
1289 __ptp_ocp_settime_locked(bp, ts);
1290 spin_unlock_irqrestore(&bp->lock, flags);
1291
1292 return 0;
1293 }
1294
1295 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1296 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1297 {
1298 u32 select, ctrl;
1299
1300 select = ioread32(&bp->reg->select);
1301 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1302
1303 iowrite32(adj_val, &bp->reg->offset_ns);
1304 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1305
1306 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1307 iowrite32(ctrl, &bp->reg->ctrl);
1308
1309 /* restore clock selection */
1310 iowrite32(select >> 16, &bp->reg->select);
1311 }
1312
1313 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1314 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1315 {
1316 struct timespec64 ts;
1317 unsigned long flags;
1318 int err;
1319
1320 spin_lock_irqsave(&bp->lock, flags);
1321 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1322 if (likely(!err)) {
1323 set_normalized_timespec64(&ts, ts.tv_sec,
1324 ts.tv_nsec + delta_ns);
1325 __ptp_ocp_settime_locked(bp, &ts);
1326 }
1327 spin_unlock_irqrestore(&bp->lock, flags);
1328 }
1329
1330 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1331 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1332 {
1333 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1334 unsigned long flags;
1335 u32 adj_ns, sign;
1336
1337 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1338 ptp_ocp_adjtime_coarse(bp, delta_ns);
1339 return 0;
1340 }
1341
1342 sign = delta_ns < 0 ? BIT(31) : 0;
1343 adj_ns = sign ? -delta_ns : delta_ns;
1344
1345 spin_lock_irqsave(&bp->lock, flags);
1346 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1347 spin_unlock_irqrestore(&bp->lock, flags);
1348
1349 return 0;
1350 }
1351
1352 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1353 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1354 {
1355 if (scaled_ppm == 0)
1356 return 0;
1357
1358 return -EOPNOTSUPP;
1359 }
1360
1361 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1362 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1363 {
1364 return 0;
1365 }
1366
1367 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1368 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1369 {
1370 return -EOPNOTSUPP;
1371 }
1372
1373 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1374 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1375 int on)
1376 {
1377 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1378 struct ptp_ocp_ext_src *ext = NULL;
1379 u32 req;
1380 int err;
1381
1382 switch (rq->type) {
1383 case PTP_CLK_REQ_EXTTS:
1384 req = OCP_REQ_TIMESTAMP;
1385 switch (rq->extts.index) {
1386 case 0:
1387 ext = bp->ts0;
1388 break;
1389 case 1:
1390 ext = bp->ts1;
1391 break;
1392 case 2:
1393 ext = bp->ts2;
1394 break;
1395 case 3:
1396 ext = bp->ts3;
1397 break;
1398 case 4:
1399 ext = bp->ts4;
1400 break;
1401 case 5:
1402 ext = bp->pps;
1403 break;
1404 }
1405 break;
1406 case PTP_CLK_REQ_PPS:
1407 req = OCP_REQ_PPS;
1408 ext = bp->pps;
1409 break;
1410 case PTP_CLK_REQ_PEROUT:
1411 switch (rq->perout.index) {
1412 case 0:
1413 /* This is a request for 1PPS on an output SMA.
1414 * Allow, but assume manual configuration.
1415 */
1416 if (on && (rq->perout.period.sec != 1 ||
1417 rq->perout.period.nsec != 0))
1418 return -EINVAL;
1419 return 0;
1420 case 1:
1421 case 2:
1422 case 3:
1423 case 4:
1424 req = rq->perout.index - 1;
1425 ext = bp->signal_out[req];
1426 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1427 if (err)
1428 return err;
1429 break;
1430 }
1431 break;
1432 default:
1433 return -EOPNOTSUPP;
1434 }
1435
1436 err = -ENXIO;
1437 if (ext)
1438 err = ext->info->enable(ext, req, on);
1439
1440 return err;
1441 }
1442
1443 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1444 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1445 enum ptp_pin_function func, unsigned chan)
1446 {
1447 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1448 char buf[16];
1449
1450 switch (func) {
1451 case PTP_PF_NONE:
1452 snprintf(buf, sizeof(buf), "IN: None");
1453 break;
1454 case PTP_PF_EXTTS:
1455 /* Allow timestamps, but require sysfs configuration. */
1456 return 0;
1457 case PTP_PF_PEROUT:
1458 /* channel 0 is 1PPS from PHC.
1459 * channels 1..4 are the frequency generators.
1460 */
1461 if (chan)
1462 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1463 else
1464 snprintf(buf, sizeof(buf), "OUT: PHC");
1465 break;
1466 default:
1467 return -EOPNOTSUPP;
1468 }
1469
1470 return ptp_ocp_sma_store(bp, buf, pin + 1);
1471 }
1472
1473 static const struct ptp_clock_info ptp_ocp_clock_info = {
1474 .owner = THIS_MODULE,
1475 .name = KBUILD_MODNAME,
1476 .max_adj = 100000000,
1477 .gettimex64 = ptp_ocp_gettimex,
1478 .settime64 = ptp_ocp_settime,
1479 .adjtime = ptp_ocp_adjtime,
1480 .adjfine = ptp_ocp_null_adjfine,
1481 .adjphase = ptp_ocp_null_adjphase,
1482 .getmaxphase = ptp_ocp_null_getmaxphase,
1483 .enable = ptp_ocp_enable,
1484 .verify = ptp_ocp_verify,
1485 .pps = true,
1486 .n_ext_ts = 6,
1487 .n_per_out = 5,
1488 };
1489
1490 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1491 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1492 {
1493 u32 ctrl, select;
1494
1495 select = ioread32(&bp->reg->select);
1496 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1497
1498 iowrite32(0, &bp->reg->drift_ns);
1499
1500 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1501 iowrite32(ctrl, &bp->reg->ctrl);
1502
1503 /* restore clock selection */
1504 iowrite32(select >> 16, &bp->reg->select);
1505 }
1506
1507 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1508 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1509 {
1510 unsigned long flags;
1511
1512 spin_lock_irqsave(&bp->lock, flags);
1513
1514 bp->utc_tai_offset = val;
1515
1516 if (bp->irig_out)
1517 iowrite32(val, &bp->irig_out->adj_sec);
1518 if (bp->dcf_out)
1519 iowrite32(val, &bp->dcf_out->adj_sec);
1520 if (bp->nmea_out)
1521 iowrite32(val, &bp->nmea_out->adj_sec);
1522
1523 spin_unlock_irqrestore(&bp->lock, flags);
1524 }
1525
1526 static void
ptp_ocp_watchdog(struct timer_list * t)1527 ptp_ocp_watchdog(struct timer_list *t)
1528 {
1529 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1530 unsigned long flags;
1531 u32 status, utc_offset;
1532
1533 status = ioread32(&bp->pps_to_clk->status);
1534
1535 if (status & PPS_STATUS_SUPERV_ERR) {
1536 iowrite32(status, &bp->pps_to_clk->status);
1537 if (!bp->gnss_lost) {
1538 spin_lock_irqsave(&bp->lock, flags);
1539 __ptp_ocp_clear_drift_locked(bp);
1540 spin_unlock_irqrestore(&bp->lock, flags);
1541 bp->gnss_lost = ktime_get_real_seconds();
1542 }
1543
1544 } else if (bp->gnss_lost) {
1545 bp->gnss_lost = 0;
1546 }
1547
1548 /* if GNSS provides correct data we can rely on
1549 * it to get leap second information
1550 */
1551 if (bp->tod) {
1552 status = ioread32(&bp->tod->utc_status);
1553 utc_offset = status & TOD_STATUS_UTC_MASK;
1554 if (status & TOD_STATUS_UTC_VALID &&
1555 utc_offset != bp->utc_tai_offset)
1556 ptp_ocp_utc_distribute(bp, utc_offset);
1557 }
1558
1559 mod_timer(&bp->watchdog, jiffies + HZ);
1560 }
1561
1562 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1563 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1564 {
1565 ktime_t start, end, delay = U64_MAX;
1566 u32 ctrl;
1567 int i;
1568
1569 for (i = 0; i < 3; i++) {
1570 ctrl = ioread32(&bp->reg->ctrl);
1571 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1572
1573 iowrite32(ctrl, &bp->reg->ctrl);
1574
1575 start = ktime_get_raw_ns();
1576
1577 ctrl = ioread32(&bp->reg->ctrl);
1578
1579 end = ktime_get_raw_ns();
1580
1581 delay = min(delay, end - start);
1582 }
1583 bp->ts_window_adjust = (delay >> 5) * 3;
1584 }
1585
1586 static int
ptp_ocp_init_clock(struct ptp_ocp * bp,struct ptp_ocp_servo_conf * servo_conf)1587 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1588 {
1589 struct timespec64 ts;
1590 u32 ctrl;
1591
1592 ctrl = OCP_CTRL_ENABLE;
1593 iowrite32(ctrl, &bp->reg->ctrl);
1594
1595 /* servo configuration */
1596 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1597 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1598 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1599 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1600
1601 /* latch servo values */
1602 ctrl |= OCP_CTRL_ADJUST_SERVO;
1603 iowrite32(ctrl, &bp->reg->ctrl);
1604
1605 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1606 dev_err(&bp->pdev->dev, "clock not enabled\n");
1607 return -ENODEV;
1608 }
1609
1610 ptp_ocp_estimate_pci_timing(bp);
1611
1612 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1613 if (!bp->sync) {
1614 ktime_get_clocktai_ts64(&ts);
1615 ptp_ocp_settime(&bp->ptp_info, &ts);
1616 }
1617
1618 /* If there is a clock supervisor, then enable the watchdog */
1619 if (bp->pps_to_clk) {
1620 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1621 mod_timer(&bp->watchdog, jiffies + HZ);
1622 }
1623
1624 return 0;
1625 }
1626
1627 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1628 ptp_ocp_tod_init(struct ptp_ocp *bp)
1629 {
1630 u32 ctrl, reg;
1631
1632 ctrl = ioread32(&bp->tod->ctrl);
1633 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1634 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1635 iowrite32(ctrl, &bp->tod->ctrl);
1636
1637 reg = ioread32(&bp->tod->utc_status);
1638 if (reg & TOD_STATUS_UTC_VALID)
1639 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1640 }
1641
1642 static const char *
ptp_ocp_tod_proto_name(const int idx)1643 ptp_ocp_tod_proto_name(const int idx)
1644 {
1645 static const char * const proto_name[] = {
1646 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1647 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1648 };
1649 return proto_name[idx];
1650 }
1651
1652 static const char *
ptp_ocp_tod_gnss_name(int idx)1653 ptp_ocp_tod_gnss_name(int idx)
1654 {
1655 static const char * const gnss_name[] = {
1656 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1657 "Unknown"
1658 };
1659 if (idx >= ARRAY_SIZE(gnss_name))
1660 idx = ARRAY_SIZE(gnss_name) - 1;
1661 return gnss_name[idx];
1662 }
1663
1664 static const char *
ptp_ocp_tty_port_name(int idx)1665 ptp_ocp_tty_port_name(int idx)
1666 {
1667 static const char * const tty_name[] = {
1668 "GNSS", "GNSS2", "MAC", "NMEA"
1669 };
1670 return tty_name[idx];
1671 }
1672
1673 struct ptp_ocp_nvmem_match_info {
1674 struct ptp_ocp *bp;
1675 const void * const tag;
1676 };
1677
1678 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1679 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1680 {
1681 const struct ptp_ocp_nvmem_match_info *info = data;
1682
1683 dev = dev->parent;
1684 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1685 return 0;
1686
1687 while ((dev = dev->parent))
1688 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1689 return info->bp == dev_get_drvdata(dev);
1690 return 0;
1691 }
1692
1693 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1694 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1695 {
1696 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1697
1698 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1699 }
1700
1701 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1702 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1703 {
1704 if (!IS_ERR_OR_NULL(*nvmemp))
1705 nvmem_device_put(*nvmemp);
1706 *nvmemp = NULL;
1707 }
1708
1709 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1710 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1711 {
1712 const struct ptp_ocp_eeprom_map *map;
1713 struct nvmem_device *nvmem;
1714 const void *tag;
1715 int ret;
1716
1717 if (!bp->i2c_ctrl)
1718 return;
1719
1720 tag = NULL;
1721 nvmem = NULL;
1722
1723 for (map = bp->eeprom_map; map->len; map++) {
1724 if (map->tag != tag) {
1725 tag = map->tag;
1726 ptp_ocp_nvmem_device_put(&nvmem);
1727 }
1728 if (!nvmem) {
1729 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1730 if (IS_ERR(nvmem)) {
1731 ret = PTR_ERR(nvmem);
1732 goto fail;
1733 }
1734 }
1735 ret = nvmem_device_read(nvmem, map->off, map->len,
1736 BP_MAP_ENTRY_ADDR(bp, map));
1737 if (ret != map->len)
1738 goto fail;
1739 }
1740
1741 bp->has_eeprom_data = true;
1742
1743 out:
1744 ptp_ocp_nvmem_device_put(&nvmem);
1745 return;
1746
1747 fail:
1748 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1749 goto out;
1750 }
1751
1752 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1753 ptp_ocp_find_flash(struct ptp_ocp *bp)
1754 {
1755 struct device *dev, *last;
1756
1757 last = NULL;
1758 dev = &bp->spi_flash->dev;
1759
1760 while ((dev = device_find_any_child(dev))) {
1761 if (!strcmp("mtd", dev_bus_name(dev)))
1762 break;
1763 put_device(last);
1764 last = dev;
1765 }
1766 put_device(last);
1767
1768 return dev;
1769 }
1770
1771 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1772 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1773 const u8 **data, size_t *size)
1774 {
1775 struct ptp_ocp *bp = devlink_priv(devlink);
1776 const struct ptp_ocp_firmware_header *hdr;
1777 size_t offset, length;
1778 u16 crc;
1779
1780 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1781 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1782 devlink_flash_update_status_notify(devlink,
1783 "No firmware header found, cancel firmware upgrade",
1784 NULL, 0, 0);
1785 return -EINVAL;
1786 }
1787
1788 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1789 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1790 devlink_flash_update_status_notify(devlink,
1791 "Firmware image compatibility check failed",
1792 NULL, 0, 0);
1793 return -EINVAL;
1794 }
1795
1796 offset = sizeof(*hdr);
1797 length = be32_to_cpu(hdr->image_size);
1798 if (length != (fw->size - offset)) {
1799 devlink_flash_update_status_notify(devlink,
1800 "Firmware image size check failed",
1801 NULL, 0, 0);
1802 return -EINVAL;
1803 }
1804
1805 crc = crc16(0xffff, &fw->data[offset], length);
1806 if (be16_to_cpu(hdr->crc) != crc) {
1807 devlink_flash_update_status_notify(devlink,
1808 "Firmware image CRC check failed",
1809 NULL, 0, 0);
1810 return -EINVAL;
1811 }
1812
1813 *data = &fw->data[offset];
1814 *size = length;
1815
1816 return 0;
1817 }
1818
1819 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1820 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1821 const struct firmware *fw)
1822 {
1823 struct mtd_info *mtd = dev_get_drvdata(dev);
1824 struct ptp_ocp *bp = devlink_priv(devlink);
1825 size_t off, len, size, resid, wrote;
1826 struct erase_info erase;
1827 size_t base, blksz;
1828 const u8 *data;
1829 int err;
1830
1831 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1832 if (err)
1833 goto out;
1834
1835 off = 0;
1836 base = bp->flash_start;
1837 blksz = 4096;
1838 resid = size;
1839
1840 while (resid) {
1841 devlink_flash_update_status_notify(devlink, "Flashing",
1842 NULL, off, size);
1843
1844 len = min_t(size_t, resid, blksz);
1845 erase.addr = base + off;
1846 erase.len = blksz;
1847
1848 err = mtd_erase(mtd, &erase);
1849 if (err)
1850 goto out;
1851
1852 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1853 if (err)
1854 goto out;
1855
1856 off += blksz;
1857 resid -= len;
1858 }
1859 out:
1860 return err;
1861 }
1862
1863 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1864 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1865 struct devlink_flash_update_params *params,
1866 struct netlink_ext_ack *extack)
1867 {
1868 struct ptp_ocp *bp = devlink_priv(devlink);
1869 struct device *dev;
1870 const char *msg;
1871 int err;
1872
1873 dev = ptp_ocp_find_flash(bp);
1874 if (!dev) {
1875 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1876 return -ENODEV;
1877 }
1878
1879 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1880 NULL, 0, 0);
1881
1882 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1883
1884 msg = err ? "Flash error" : "Flash complete";
1885 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1886
1887 put_device(dev);
1888 return err;
1889 }
1890
1891 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1892 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1893 struct netlink_ext_ack *extack)
1894 {
1895 struct ptp_ocp *bp = devlink_priv(devlink);
1896 const char *fw_image;
1897 char buf[32];
1898 int err;
1899
1900 fw_image = bp->fw_loader ? "loader" : "fw";
1901 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1902 err = devlink_info_version_running_put(req, fw_image, buf);
1903 if (err)
1904 return err;
1905
1906 if (!bp->has_eeprom_data) {
1907 ptp_ocp_read_eeprom(bp);
1908 if (!bp->has_eeprom_data)
1909 return 0;
1910 }
1911
1912 sprintf(buf, "%pM", bp->serial);
1913 err = devlink_info_serial_number_put(req, buf);
1914 if (err)
1915 return err;
1916
1917 err = devlink_info_version_fixed_put(req,
1918 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1919 bp->board_id);
1920 if (err)
1921 return err;
1922
1923 return 0;
1924 }
1925
1926 static const struct devlink_ops ptp_ocp_devlink_ops = {
1927 .flash_update = ptp_ocp_devlink_flash_update,
1928 .info_get = ptp_ocp_devlink_info_get,
1929 };
1930
1931 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1932 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1933 {
1934 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1935
1936 return devm_ioremap_resource(&bp->pdev->dev, &res);
1937 }
1938
1939 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1940 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1941 {
1942 resource_size_t start;
1943
1944 start = pci_resource_start(bp->pdev, 0) + r->offset;
1945 return __ptp_ocp_get_mem(bp, start, r->size);
1946 }
1947
1948 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1949 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1950 {
1951 struct ptp_ocp_flash_info *info;
1952 struct pci_dev *pdev = bp->pdev;
1953 struct platform_device *p;
1954 struct resource res[2];
1955 resource_size_t start;
1956 int id;
1957
1958 start = pci_resource_start(pdev, 0) + r->offset;
1959 res[0] = DEFINE_RES_MEM(start, r->size);
1960 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1961
1962 info = r->extra;
1963 id = pci_dev_id(pdev) << 1;
1964 id += info->pci_offset;
1965
1966 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1967 res, ARRAY_SIZE(res), info->data,
1968 info->data_size);
1969 if (IS_ERR(p))
1970 return PTR_ERR(p);
1971
1972 bp_assign_entry(bp, r, p);
1973
1974 return 0;
1975 }
1976
1977 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1978 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1979 {
1980 struct ptp_ocp_i2c_info *info;
1981 struct resource res[2];
1982 resource_size_t start;
1983
1984 info = r->extra;
1985 start = pci_resource_start(pdev, 0) + r->offset;
1986 res[0] = DEFINE_RES_MEM(start, r->size);
1987 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1988
1989 return platform_device_register_resndata(&pdev->dev, info->name,
1990 id, res, ARRAY_SIZE(res),
1991 info->data, info->data_size);
1992 }
1993
1994 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1995 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1996 {
1997 struct pci_dev *pdev = bp->pdev;
1998 struct ptp_ocp_i2c_info *info;
1999 struct platform_device *p;
2000 struct clk_hw *clk;
2001 char buf[32];
2002 int id;
2003
2004 info = r->extra;
2005 id = pci_dev_id(bp->pdev);
2006
2007 sprintf(buf, "AXI.%d", id);
2008 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2009 info->fixed_rate);
2010 if (IS_ERR(clk))
2011 return PTR_ERR(clk);
2012 bp->i2c_clk = clk;
2013
2014 sprintf(buf, "%s.%d", info->name, id);
2015 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2016 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2017 if (IS_ERR(p))
2018 return PTR_ERR(p);
2019
2020 bp_assign_entry(bp, r, p);
2021
2022 return 0;
2023 }
2024
2025 /* The expectation is that this is triggered only on error. */
2026 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)2027 ptp_ocp_signal_irq(int irq, void *priv)
2028 {
2029 struct ptp_ocp_ext_src *ext = priv;
2030 struct signal_reg __iomem *reg = ext->mem;
2031 struct ptp_ocp *bp = ext->bp;
2032 u32 enable, status;
2033 int gen;
2034
2035 gen = ext->info->index - 1;
2036
2037 enable = ioread32(®->enable);
2038 status = ioread32(®->status);
2039
2040 /* disable generator on error */
2041 if (status || !enable) {
2042 iowrite32(0, ®->intr_mask);
2043 iowrite32(0, ®->enable);
2044 bp->signal[gen].running = false;
2045 }
2046
2047 iowrite32(0, ®->intr); /* ack interrupt */
2048
2049 return IRQ_HANDLED;
2050 }
2051
2052 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)2053 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2054 {
2055 struct ptp_system_timestamp sts;
2056 struct timespec64 ts;
2057 ktime_t start_ns;
2058 int err;
2059
2060 if (!s->period)
2061 return 0;
2062
2063 if (!s->pulse)
2064 s->pulse = ktime_divns(s->period * s->duty, 100);
2065
2066 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2067 if (err)
2068 return err;
2069
2070 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2071 if (!s->start) {
2072 /* roundup() does not work on 32-bit systems */
2073 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2074 s->start *= s->period;
2075 s->start = ktime_add(s->start, s->phase);
2076 }
2077
2078 if (s->duty < 1 || s->duty > 99)
2079 return -EINVAL;
2080
2081 if (s->pulse < 1 || s->pulse > s->period)
2082 return -EINVAL;
2083
2084 if (s->start < start_ns)
2085 return -EINVAL;
2086
2087 bp->signal[gen] = *s;
2088
2089 return 0;
2090 }
2091
2092 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)2093 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2094 struct ptp_perout_request *req)
2095 {
2096 struct ptp_ocp_signal s = { };
2097
2098 s.polarity = bp->signal[gen].polarity;
2099 s.period = ktime_set(req->period.sec, req->period.nsec);
2100 if (!s.period)
2101 return 0;
2102
2103 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2104 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2105 s.duty = ktime_divns(s.pulse * 100, s.period);
2106 }
2107
2108 if (req->flags & PTP_PEROUT_PHASE)
2109 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2110 else
2111 s.start = ktime_set(req->start.sec, req->start.nsec);
2112
2113 return ptp_ocp_signal_set(bp, gen, &s);
2114 }
2115
2116 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)2117 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2118 {
2119 struct ptp_ocp_ext_src *ext = priv;
2120 struct signal_reg __iomem *reg = ext->mem;
2121 struct ptp_ocp *bp = ext->bp;
2122 struct timespec64 ts;
2123 int gen;
2124
2125 gen = ext->info->index - 1;
2126
2127 iowrite32(0, ®->intr_mask);
2128 iowrite32(0, ®->enable);
2129 bp->signal[gen].running = false;
2130 if (!enable)
2131 return 0;
2132
2133 ts = ktime_to_timespec64(bp->signal[gen].start);
2134 iowrite32(ts.tv_sec, ®->start_sec);
2135 iowrite32(ts.tv_nsec, ®->start_ns);
2136
2137 ts = ktime_to_timespec64(bp->signal[gen].period);
2138 iowrite32(ts.tv_sec, ®->period_sec);
2139 iowrite32(ts.tv_nsec, ®->period_ns);
2140
2141 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2142 iowrite32(ts.tv_sec, ®->pulse_sec);
2143 iowrite32(ts.tv_nsec, ®->pulse_ns);
2144
2145 iowrite32(bp->signal[gen].polarity, ®->polarity);
2146 iowrite32(0, ®->repeat_count);
2147
2148 iowrite32(0, ®->intr); /* clear interrupt state */
2149 iowrite32(1, ®->intr_mask); /* enable interrupt */
2150 iowrite32(3, ®->enable); /* valid & enable */
2151
2152 bp->signal[gen].running = true;
2153
2154 return 0;
2155 }
2156
2157 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)2158 ptp_ocp_ts_irq(int irq, void *priv)
2159 {
2160 struct ptp_ocp_ext_src *ext = priv;
2161 struct ts_reg __iomem *reg = ext->mem;
2162 struct ptp_clock_event ev;
2163 u32 sec, nsec;
2164
2165 if (ext == ext->bp->pps) {
2166 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2167 ev.type = PTP_CLOCK_PPS;
2168 ptp_clock_event(ext->bp->ptp, &ev);
2169 }
2170
2171 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2172 goto out;
2173 }
2174
2175 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2176 sec = ioread32(®->time_sec);
2177 nsec = ioread32(®->time_ns);
2178
2179 ev.type = PTP_CLOCK_EXTTS;
2180 ev.index = ext->info->index;
2181 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2182
2183 ptp_clock_event(ext->bp->ptp, &ev);
2184
2185 out:
2186 iowrite32(1, ®->intr); /* write 1 to ack */
2187
2188 return IRQ_HANDLED;
2189 }
2190
2191 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)2192 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2193 {
2194 struct ptp_ocp_ext_src *ext = priv;
2195 struct ts_reg __iomem *reg = ext->mem;
2196 struct ptp_ocp *bp = ext->bp;
2197
2198 if (ext == bp->pps) {
2199 u32 old_map = bp->pps_req_map;
2200
2201 if (enable)
2202 bp->pps_req_map |= req;
2203 else
2204 bp->pps_req_map &= ~req;
2205
2206 /* if no state change, just return */
2207 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2208 return 0;
2209 }
2210
2211 if (enable) {
2212 iowrite32(1, ®->enable);
2213 iowrite32(1, ®->intr_mask);
2214 iowrite32(1, ®->intr);
2215 } else {
2216 iowrite32(0, ®->intr_mask);
2217 iowrite32(0, ®->enable);
2218 }
2219
2220 return 0;
2221 }
2222
2223 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)2224 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2225 {
2226 ext->info->enable(ext, ~0, false);
2227 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2228 kfree(ext);
2229 }
2230
2231 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2232 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2233 {
2234 struct pci_dev *pdev = bp->pdev;
2235 struct ptp_ocp_ext_src *ext;
2236 int err;
2237
2238 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2239 if (!ext)
2240 return -ENOMEM;
2241
2242 ext->mem = ptp_ocp_get_mem(bp, r);
2243 if (IS_ERR(ext->mem)) {
2244 err = PTR_ERR(ext->mem);
2245 goto out;
2246 }
2247
2248 ext->bp = bp;
2249 ext->info = r->extra;
2250 ext->irq_vec = r->irq_vec;
2251
2252 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2253 ext, "ocp%d.%s", bp->id, r->name);
2254 if (err) {
2255 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2256 goto out;
2257 }
2258
2259 bp_assign_entry(bp, r, ext);
2260
2261 return 0;
2262
2263 out:
2264 kfree(ext);
2265 return err;
2266 }
2267
2268 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2269 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2270 {
2271 struct pci_dev *pdev = bp->pdev;
2272 struct uart_8250_port uart;
2273
2274 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2275 * the serial port device claim and release the pci resource.
2276 */
2277 memset(&uart, 0, sizeof(uart));
2278 uart.port.dev = &pdev->dev;
2279 uart.port.iotype = UPIO_MEM;
2280 uart.port.regshift = 2;
2281 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2282 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2283 uart.port.uartclk = 50000000;
2284 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2285 uart.port.type = PORT_16550A;
2286
2287 return serial8250_register_8250_port(&uart);
2288 }
2289
2290 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2291 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2292 {
2293 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2294 struct ptp_ocp_serial_port port = {};
2295
2296 port.line = ptp_ocp_serial_line(bp, r);
2297 if (port.line < 0)
2298 return port.line;
2299
2300 if (p)
2301 port.baud = p->baud;
2302
2303 bp_assign_entry(bp, r, port);
2304
2305 return 0;
2306 }
2307
2308 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2309 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2310 {
2311 void __iomem *mem;
2312
2313 mem = ptp_ocp_get_mem(bp, r);
2314 if (IS_ERR(mem))
2315 return PTR_ERR(mem);
2316
2317 bp_assign_entry(bp, r, mem);
2318
2319 return 0;
2320 }
2321
2322 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2323 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2324 {
2325 if (!bp->nmea_out)
2326 return;
2327
2328 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2329 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2330 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2331 }
2332
2333 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2334 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2335 {
2336 u32 val;
2337
2338 iowrite32(0, ®->enable); /* disable */
2339
2340 val = ioread32(®->polarity);
2341 s->polarity = val ? true : false;
2342 s->duty = 50;
2343 }
2344
2345 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2346 ptp_ocp_signal_init(struct ptp_ocp *bp)
2347 {
2348 int i;
2349
2350 for (i = 0; i < 4; i++)
2351 if (bp->signal_out[i])
2352 _ptp_ocp_signal_init(&bp->signal[i],
2353 bp->signal_out[i]->mem);
2354 }
2355
2356 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2357 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2358 {
2359 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2360 kfree(bp->attr_group);
2361 }
2362
2363 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2364 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2365 const struct ocp_attr_group *attr_tbl)
2366 {
2367 int count, i;
2368 int err;
2369
2370 count = 0;
2371 for (i = 0; attr_tbl[i].cap; i++)
2372 if (attr_tbl[i].cap & bp->fw_cap)
2373 count++;
2374
2375 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2376 GFP_KERNEL);
2377 if (!bp->attr_group)
2378 return -ENOMEM;
2379
2380 count = 0;
2381 for (i = 0; attr_tbl[i].cap; i++)
2382 if (attr_tbl[i].cap & bp->fw_cap)
2383 bp->attr_group[count++] = attr_tbl[i].group;
2384
2385 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2386 if (err)
2387 bp->attr_group[0] = NULL;
2388
2389 return err;
2390 }
2391
2392 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2393 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2394 {
2395 u32 ctrl;
2396 bool on;
2397
2398 ctrl = ioread32(reg);
2399 on = ctrl & bit;
2400 if (on ^ enable) {
2401 ctrl &= ~bit;
2402 ctrl |= enable ? bit : 0;
2403 iowrite32(ctrl, reg);
2404 }
2405 }
2406
2407 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2408 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2409 {
2410 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2411 IRIG_M_CTRL_ENABLE, enable);
2412 }
2413
2414 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2415 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2416 {
2417 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2418 IRIG_S_CTRL_ENABLE, enable);
2419 }
2420
2421 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2422 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2423 {
2424 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2425 DCF_M_CTRL_ENABLE, enable);
2426 }
2427
2428 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2429 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2430 {
2431 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2432 DCF_S_CTRL_ENABLE, enable);
2433 }
2434
2435 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2436 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2437 {
2438 ptp_ocp_irig_out(bp, val & 0x00100010);
2439 ptp_ocp_dcf_out(bp, val & 0x00200020);
2440 }
2441
2442 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2443 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2444 {
2445 ptp_ocp_irig_in(bp, val & 0x00100010);
2446 ptp_ocp_dcf_in(bp, val & 0x00200020);
2447 }
2448
2449 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2450 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2451 {
2452 u32 __iomem *gpio;
2453 u32 shift;
2454
2455 if (bp->sma[sma_nr - 1].fixed_fcn)
2456 return (sma_nr - 1) & 1;
2457
2458 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2459 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2460 else
2461 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2462 shift = sma_nr & 1 ? 0 : 16;
2463
2464 return (ioread32(gpio) >> shift) & 0xffff;
2465 }
2466
2467 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2468 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2469 {
2470 u32 reg, mask, shift;
2471 unsigned long flags;
2472 u32 __iomem *gpio;
2473
2474 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2475 shift = sma_nr & 1 ? 0 : 16;
2476
2477 mask = 0xffff << (16 - shift);
2478
2479 spin_lock_irqsave(&bp->lock, flags);
2480
2481 reg = ioread32(gpio);
2482 reg = (reg & mask) | (val << shift);
2483
2484 __handle_signal_outputs(bp, reg);
2485
2486 iowrite32(reg, gpio);
2487
2488 spin_unlock_irqrestore(&bp->lock, flags);
2489
2490 return 0;
2491 }
2492
2493 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2494 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2495 {
2496 u32 reg, mask, shift;
2497 unsigned long flags;
2498 u32 __iomem *gpio;
2499
2500 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2501 shift = sma_nr & 1 ? 0 : 16;
2502
2503 mask = 0xffff << (16 - shift);
2504
2505 spin_lock_irqsave(&bp->lock, flags);
2506
2507 reg = ioread32(gpio);
2508 reg = (reg & mask) | (val << shift);
2509
2510 __handle_signal_inputs(bp, reg);
2511
2512 iowrite32(reg, gpio);
2513
2514 spin_unlock_irqrestore(&bp->lock, flags);
2515
2516 return 0;
2517 }
2518
2519 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2520 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2521 {
2522 struct dpll_pin_properties prop = {
2523 .board_label = NULL,
2524 .type = DPLL_PIN_TYPE_EXT,
2525 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2526 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2527 .freq_supported = ptp_ocp_sma_freq,
2528
2529 };
2530 u32 reg;
2531 int i;
2532
2533 /* defaults */
2534 for (i = 0; i < OCP_SMA_NUM; i++) {
2535 bp->sma[i].default_fcn = i & 1;
2536 bp->sma[i].dpll_prop = prop;
2537 bp->sma[i].dpll_prop.board_label =
2538 bp->ptp_info.pin_config[i].name;
2539 }
2540 bp->sma[0].mode = SMA_MODE_IN;
2541 bp->sma[1].mode = SMA_MODE_IN;
2542 bp->sma[2].mode = SMA_MODE_OUT;
2543 bp->sma[3].mode = SMA_MODE_OUT;
2544 /* If no SMA1 map, the pin functions and directions are fixed. */
2545 if (!bp->sma_map1) {
2546 for (i = 0; i < OCP_SMA_NUM; i++) {
2547 bp->sma[i].fixed_fcn = true;
2548 bp->sma[i].fixed_dir = true;
2549 bp->sma[1].dpll_prop.capabilities &=
2550 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2551 }
2552 return;
2553 }
2554
2555 /* If SMA2 GPIO output map is all 1, it is not present.
2556 * This indicates the firmware has fixed direction SMA pins.
2557 */
2558 reg = ioread32(&bp->sma_map2->gpio2);
2559 if (reg == 0xffffffff) {
2560 for (i = 0; i < OCP_SMA_NUM; i++)
2561 bp->sma[i].fixed_dir = true;
2562 } else {
2563 reg = ioread32(&bp->sma_map1->gpio1);
2564 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2565 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2566
2567 reg = ioread32(&bp->sma_map1->gpio2);
2568 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2569 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2570 }
2571 }
2572
2573 static const struct ocp_sma_op ocp_fb_sma_op = {
2574 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2575 .init = ptp_ocp_sma_fb_init,
2576 .get = ptp_ocp_sma_fb_get,
2577 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2578 .set_output = ptp_ocp_sma_fb_set_output,
2579 };
2580
2581 static int
ptp_ocp_sma_adva_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2582 ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2583 {
2584 u32 reg, mask, shift;
2585 unsigned long flags;
2586 u32 __iomem *gpio;
2587
2588 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2589 shift = sma_nr & 1 ? 0 : 16;
2590
2591 mask = 0xffff << (16 - shift);
2592
2593 spin_lock_irqsave(&bp->lock, flags);
2594
2595 reg = ioread32(gpio);
2596 reg = (reg & mask) | (val << shift);
2597
2598 iowrite32(reg, gpio);
2599
2600 spin_unlock_irqrestore(&bp->lock, flags);
2601
2602 return 0;
2603 }
2604
2605 static int
ptp_ocp_sma_adva_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2606 ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2607 {
2608 u32 reg, mask, shift;
2609 unsigned long flags;
2610 u32 __iomem *gpio;
2611
2612 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2613 shift = sma_nr & 1 ? 0 : 16;
2614
2615 mask = 0xffff << (16 - shift);
2616
2617 spin_lock_irqsave(&bp->lock, flags);
2618
2619 reg = ioread32(gpio);
2620 reg = (reg & mask) | (val << shift);
2621
2622 iowrite32(reg, gpio);
2623
2624 spin_unlock_irqrestore(&bp->lock, flags);
2625
2626 return 0;
2627 }
2628
2629 static const struct ocp_sma_op ocp_adva_sma_op = {
2630 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2631 .init = ptp_ocp_sma_fb_init,
2632 .get = ptp_ocp_sma_fb_get,
2633 .set_inputs = ptp_ocp_sma_adva_set_inputs,
2634 .set_output = ptp_ocp_sma_adva_set_output,
2635 };
2636
2637 static int
ptp_ocp_set_pins(struct ptp_ocp * bp)2638 ptp_ocp_set_pins(struct ptp_ocp *bp)
2639 {
2640 struct ptp_pin_desc *config;
2641 int i;
2642
2643 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2644 if (!config)
2645 return -ENOMEM;
2646
2647 for (i = 0; i < 4; i++) {
2648 sprintf(config[i].name, "sma%d", i + 1);
2649 config[i].index = i;
2650 }
2651
2652 bp->ptp_info.n_pins = 4;
2653 bp->ptp_info.pin_config = config;
2654
2655 return 0;
2656 }
2657
2658 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2659 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2660 {
2661 u64 cap = OCP_CAP_BASIC;
2662 u32 version;
2663
2664 version = ioread32(&bp->image->version);
2665
2666 /* if lower 16 bits are empty, this is the fw loader. */
2667 if ((version & 0xffff) == 0) {
2668 version = version >> 16;
2669 bp->fw_loader = true;
2670 }
2671
2672 bp->fw_tag = version >> 15;
2673 bp->fw_version = version & 0x7fff;
2674
2675 if (bp->fw_tag) {
2676 /* FPGA firmware */
2677 if (version >= 5)
2678 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2679 } else {
2680 /* SOM firmware */
2681 if (version >= 19)
2682 cap |= OCP_CAP_SIGNAL;
2683 if (version >= 20)
2684 cap |= OCP_CAP_FREQ;
2685 }
2686
2687 bp->fw_cap = cap;
2688 }
2689
2690 /* FB specific board initializers; last "resource" registered. */
2691 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2692 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2693 {
2694 int err;
2695
2696 bp->flash_start = 1024 * 4096;
2697 bp->eeprom_map = fb_eeprom_map;
2698 bp->fw_version = ioread32(&bp->image->version);
2699 bp->sma_op = &ocp_fb_sma_op;
2700 bp->signals_nr = 4;
2701 bp->freq_in_nr = 4;
2702
2703 ptp_ocp_fb_set_version(bp);
2704
2705 ptp_ocp_tod_init(bp);
2706 ptp_ocp_nmea_out_init(bp);
2707 ptp_ocp_signal_init(bp);
2708
2709 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2710 if (err)
2711 return err;
2712
2713 err = ptp_ocp_set_pins(bp);
2714 if (err)
2715 return err;
2716 ptp_ocp_sma_init(bp);
2717
2718 return ptp_ocp_init_clock(bp, r->extra);
2719 }
2720
2721 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2722 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2723 {
2724 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2725
2726 if (!allow)
2727 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2728 r->irq_vec, r->name);
2729 return allow;
2730 }
2731
2732 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2733 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2734 {
2735 struct ocp_resource *r, *table;
2736 int err = 0;
2737
2738 table = (struct ocp_resource *)driver_data;
2739 for (r = table; r->setup; r++) {
2740 if (!ptp_ocp_allow_irq(bp, r))
2741 continue;
2742 err = r->setup(bp, r);
2743 if (err) {
2744 dev_err(&bp->pdev->dev,
2745 "Could not register %s: err %d\n",
2746 r->name, err);
2747 break;
2748 }
2749 }
2750 return err;
2751 }
2752
2753 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)2754 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2755 {
2756 struct dpll_pin_properties prop = {
2757 .board_label = NULL,
2758 .type = DPLL_PIN_TYPE_EXT,
2759 .capabilities = 0,
2760 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2761 .freq_supported = ptp_ocp_sma_freq,
2762
2763 };
2764 u32 reg;
2765 int i;
2766
2767 /* defaults */
2768 bp->sma[0].mode = SMA_MODE_IN;
2769 bp->sma[1].mode = SMA_MODE_IN;
2770 bp->sma[2].mode = SMA_MODE_OUT;
2771 bp->sma[3].mode = SMA_MODE_OUT;
2772
2773 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2774 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2775 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2776 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2777
2778 for (i = 0; i < OCP_SMA_NUM; i++) {
2779 /* If no SMA map, the pin functions and directions are fixed. */
2780 bp->sma[i].dpll_prop = prop;
2781 bp->sma[i].dpll_prop.board_label =
2782 bp->ptp_info.pin_config[i].name;
2783 if (!bp->art_sma) {
2784 bp->sma[i].fixed_fcn = true;
2785 bp->sma[i].fixed_dir = true;
2786 continue;
2787 }
2788 reg = ioread32(&bp->art_sma->map[i].gpio);
2789
2790 switch (reg & 0xff) {
2791 case 0:
2792 bp->sma[i].fixed_fcn = true;
2793 bp->sma[i].fixed_dir = true;
2794 break;
2795 case 1:
2796 case 8:
2797 bp->sma[i].mode = SMA_MODE_IN;
2798 bp->sma[i].dpll_prop.capabilities =
2799 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2800 break;
2801 default:
2802 bp->sma[i].mode = SMA_MODE_OUT;
2803 bp->sma[i].dpll_prop.capabilities =
2804 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2805 break;
2806 }
2807 }
2808 }
2809
2810 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)2811 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2812 {
2813 if (bp->sma[sma_nr - 1].fixed_fcn)
2814 return bp->sma[sma_nr - 1].default_fcn;
2815
2816 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2817 }
2818
2819 /* note: store 0 is considered invalid. */
2820 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)2821 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2822 {
2823 unsigned long flags;
2824 u32 __iomem *gpio;
2825 int err = 0;
2826 u32 reg;
2827
2828 val &= SMA_SELECT_MASK;
2829 if (hweight32(val) > 1)
2830 return -EINVAL;
2831
2832 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2833
2834 spin_lock_irqsave(&bp->lock, flags);
2835 reg = ioread32(gpio);
2836 if (((reg >> 16) & val) == 0) {
2837 err = -EOPNOTSUPP;
2838 } else {
2839 reg = (reg & 0xff00) | (val & 0xff);
2840 iowrite32(reg, gpio);
2841 }
2842 spin_unlock_irqrestore(&bp->lock, flags);
2843
2844 return err;
2845 }
2846
2847 static const struct ocp_sma_op ocp_art_sma_op = {
2848 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2849 .init = ptp_ocp_art_sma_init,
2850 .get = ptp_ocp_art_sma_get,
2851 .set_inputs = ptp_ocp_art_sma_set,
2852 .set_output = ptp_ocp_art_sma_set,
2853 };
2854
2855 /* ART specific board initializers; last "resource" registered. */
2856 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2857 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2858 {
2859 int err;
2860
2861 bp->flash_start = 0x1000000;
2862 bp->eeprom_map = art_eeprom_map;
2863 bp->fw_cap = OCP_CAP_BASIC;
2864 bp->fw_version = ioread32(&bp->reg->version);
2865 bp->fw_tag = 2;
2866 bp->sma_op = &ocp_art_sma_op;
2867 bp->signals_nr = 4;
2868 bp->freq_in_nr = 4;
2869
2870 /* Enable MAC serial port during initialisation */
2871 iowrite32(1, &bp->board_config->mro50_serial_activate);
2872
2873 err = ptp_ocp_set_pins(bp);
2874 if (err)
2875 return err;
2876 ptp_ocp_sma_init(bp);
2877
2878 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2879 if (err)
2880 return err;
2881
2882 return ptp_ocp_init_clock(bp, r->extra);
2883 }
2884
2885 /* ADVA specific board initializers; last "resource" registered. */
2886 static int
ptp_ocp_adva_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2887 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2888 {
2889 int err;
2890 u32 version;
2891
2892 bp->flash_start = 0xA00000;
2893 bp->eeprom_map = fb_eeprom_map;
2894 bp->sma_op = &ocp_adva_sma_op;
2895 bp->signals_nr = 2;
2896 bp->freq_in_nr = 2;
2897
2898 version = ioread32(&bp->image->version);
2899 /* if lower 16 bits are empty, this is the fw loader. */
2900 if ((version & 0xffff) == 0) {
2901 version = version >> 16;
2902 bp->fw_loader = true;
2903 }
2904 bp->fw_tag = 3;
2905 bp->fw_version = version & 0xffff;
2906 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2907
2908 ptp_ocp_tod_init(bp);
2909 ptp_ocp_nmea_out_init(bp);
2910 ptp_ocp_signal_init(bp);
2911
2912 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2913 if (err)
2914 return err;
2915
2916 err = ptp_ocp_set_pins(bp);
2917 if (err)
2918 return err;
2919 ptp_ocp_sma_init(bp);
2920
2921 return ptp_ocp_init_clock(bp, r->extra);
2922 }
2923
2924 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2925 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2926 int def_val)
2927 {
2928 const char *name;
2929 ssize_t count;
2930
2931 count = sysfs_emit(buf, "OUT: ");
2932 name = ptp_ocp_select_name_from_val(tbl, val);
2933 if (!name)
2934 name = ptp_ocp_select_name_from_val(tbl, def_val);
2935 count += sysfs_emit_at(buf, count, "%s\n", name);
2936 return count;
2937 }
2938
2939 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2940 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2941 int def_val)
2942 {
2943 const char *name;
2944 ssize_t count;
2945 int i;
2946
2947 count = sysfs_emit(buf, "IN: ");
2948 for (i = 0; tbl[i].name; i++) {
2949 if (val & tbl[i].value) {
2950 name = tbl[i].name;
2951 count += sysfs_emit_at(buf, count, "%s ", name);
2952 }
2953 }
2954 if (!val && def_val >= 0) {
2955 name = ptp_ocp_select_name_from_val(tbl, def_val);
2956 count += sysfs_emit_at(buf, count, "%s ", name);
2957 }
2958 if (count)
2959 count--;
2960 count += sysfs_emit_at(buf, count, "\n");
2961 return count;
2962 }
2963
2964 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2965 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2966 enum ptp_ocp_sma_mode *mode)
2967 {
2968 int idx, count, dir;
2969 char **argv;
2970 int ret;
2971
2972 argv = argv_split(GFP_KERNEL, buf, &count);
2973 if (!argv)
2974 return -ENOMEM;
2975
2976 ret = -EINVAL;
2977 if (!count)
2978 goto out;
2979
2980 idx = 0;
2981 dir = *mode == SMA_MODE_IN ? 0 : 1;
2982 if (!strcasecmp("IN:", argv[0])) {
2983 dir = 0;
2984 idx++;
2985 }
2986 if (!strcasecmp("OUT:", argv[0])) {
2987 dir = 1;
2988 idx++;
2989 }
2990 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2991
2992 ret = 0;
2993 for (; idx < count; idx++)
2994 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2995 if (ret < 0)
2996 ret = -EINVAL;
2997
2998 out:
2999 argv_free(argv);
3000 return ret;
3001 }
3002
3003 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)3004 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
3005 int default_in_val, int default_out_val)
3006 {
3007 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3008 const struct ocp_selector * const *tbl;
3009 u32 val;
3010
3011 tbl = bp->sma_op->tbl;
3012 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
3013
3014 if (sma->mode == SMA_MODE_IN) {
3015 if (sma->disabled)
3016 val = SMA_DISABLE;
3017 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
3018 }
3019
3020 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
3021 }
3022
3023 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)3024 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
3025 {
3026 struct ptp_ocp *bp = dev_get_drvdata(dev);
3027
3028 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
3029 }
3030
3031 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)3032 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
3033 {
3034 struct ptp_ocp *bp = dev_get_drvdata(dev);
3035
3036 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
3037 }
3038
3039 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)3040 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
3041 {
3042 struct ptp_ocp *bp = dev_get_drvdata(dev);
3043
3044 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
3045 }
3046
3047 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)3048 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
3049 {
3050 struct ptp_ocp *bp = dev_get_drvdata(dev);
3051
3052 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
3053 }
3054
3055 static int
ptp_ocp_sma_store_val(struct ptp_ocp * bp,int val,enum ptp_ocp_sma_mode mode,int sma_nr)3056 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3057 {
3058 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3059
3060 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3061 return -EOPNOTSUPP;
3062
3063 if (sma->fixed_fcn) {
3064 if (val != sma->default_fcn)
3065 return -EOPNOTSUPP;
3066 return 0;
3067 }
3068
3069 sma->disabled = !!(val & SMA_DISABLE);
3070
3071 if (mode != sma->mode) {
3072 if (mode == SMA_MODE_IN)
3073 ptp_ocp_sma_set_output(bp, sma_nr, 0);
3074 else
3075 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3076 sma->mode = mode;
3077 }
3078
3079 if (!sma->fixed_dir)
3080 val |= SMA_ENABLE; /* add enable bit */
3081
3082 if (sma->disabled)
3083 val = 0;
3084
3085 if (mode == SMA_MODE_IN)
3086 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3087 else
3088 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3089
3090 return val;
3091 }
3092
3093 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)3094 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3095 {
3096 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3097 enum ptp_ocp_sma_mode mode;
3098 int val;
3099
3100 mode = sma->mode;
3101 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3102 if (val < 0)
3103 return val;
3104 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3105 }
3106
3107 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3108 sma1_store(struct device *dev, struct device_attribute *attr,
3109 const char *buf, size_t count)
3110 {
3111 struct ptp_ocp *bp = dev_get_drvdata(dev);
3112 int err;
3113
3114 err = ptp_ocp_sma_store(bp, buf, 1);
3115 return err ? err : count;
3116 }
3117
3118 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3119 sma2_store(struct device *dev, struct device_attribute *attr,
3120 const char *buf, size_t count)
3121 {
3122 struct ptp_ocp *bp = dev_get_drvdata(dev);
3123 int err;
3124
3125 err = ptp_ocp_sma_store(bp, buf, 2);
3126 return err ? err : count;
3127 }
3128
3129 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3130 sma3_store(struct device *dev, struct device_attribute *attr,
3131 const char *buf, size_t count)
3132 {
3133 struct ptp_ocp *bp = dev_get_drvdata(dev);
3134 int err;
3135
3136 err = ptp_ocp_sma_store(bp, buf, 3);
3137 return err ? err : count;
3138 }
3139
3140 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3141 sma4_store(struct device *dev, struct device_attribute *attr,
3142 const char *buf, size_t count)
3143 {
3144 struct ptp_ocp *bp = dev_get_drvdata(dev);
3145 int err;
3146
3147 err = ptp_ocp_sma_store(bp, buf, 4);
3148 return err ? err : count;
3149 }
3150 static DEVICE_ATTR_RW(sma1);
3151 static DEVICE_ATTR_RW(sma2);
3152 static DEVICE_ATTR_RW(sma3);
3153 static DEVICE_ATTR_RW(sma4);
3154
3155 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)3156 available_sma_inputs_show(struct device *dev,
3157 struct device_attribute *attr, char *buf)
3158 {
3159 struct ptp_ocp *bp = dev_get_drvdata(dev);
3160
3161 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3162 }
3163 static DEVICE_ATTR_RO(available_sma_inputs);
3164
3165 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)3166 available_sma_outputs_show(struct device *dev,
3167 struct device_attribute *attr, char *buf)
3168 {
3169 struct ptp_ocp *bp = dev_get_drvdata(dev);
3170
3171 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3172 }
3173 static DEVICE_ATTR_RO(available_sma_outputs);
3174
3175 #define EXT_ATTR_RO(_group, _name, _val) \
3176 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3177 { __ATTR_RO(_name), (void *)_val }
3178 #define EXT_ATTR_RW(_group, _name, _val) \
3179 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3180 { __ATTR_RW(_name), (void *)_val }
3181 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3182
3183 /* period [duty [phase [polarity]]] */
3184 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3185 signal_store(struct device *dev, struct device_attribute *attr,
3186 const char *buf, size_t count)
3187 {
3188 struct dev_ext_attribute *ea = to_ext_attr(attr);
3189 struct ptp_ocp *bp = dev_get_drvdata(dev);
3190 struct ptp_ocp_signal s = { };
3191 int gen = (uintptr_t)ea->var;
3192 int argc, err;
3193 char **argv;
3194
3195 argv = argv_split(GFP_KERNEL, buf, &argc);
3196 if (!argv)
3197 return -ENOMEM;
3198
3199 err = -EINVAL;
3200 s.duty = bp->signal[gen].duty;
3201 s.phase = bp->signal[gen].phase;
3202 s.period = bp->signal[gen].period;
3203 s.polarity = bp->signal[gen].polarity;
3204
3205 switch (argc) {
3206 case 4:
3207 argc--;
3208 err = kstrtobool(argv[argc], &s.polarity);
3209 if (err)
3210 goto out;
3211 fallthrough;
3212 case 3:
3213 argc--;
3214 err = kstrtou64(argv[argc], 0, &s.phase);
3215 if (err)
3216 goto out;
3217 fallthrough;
3218 case 2:
3219 argc--;
3220 err = kstrtoint(argv[argc], 0, &s.duty);
3221 if (err)
3222 goto out;
3223 fallthrough;
3224 case 1:
3225 argc--;
3226 err = kstrtou64(argv[argc], 0, &s.period);
3227 if (err)
3228 goto out;
3229 break;
3230 default:
3231 goto out;
3232 }
3233
3234 err = ptp_ocp_signal_set(bp, gen, &s);
3235 if (err)
3236 goto out;
3237
3238 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3239
3240 out:
3241 argv_free(argv);
3242 return err ? err : count;
3243 }
3244
3245 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)3246 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3247 {
3248 struct dev_ext_attribute *ea = to_ext_attr(attr);
3249 struct ptp_ocp *bp = dev_get_drvdata(dev);
3250 struct ptp_ocp_signal *signal;
3251 struct timespec64 ts;
3252 ssize_t count;
3253 int i;
3254
3255 i = (uintptr_t)ea->var;
3256 signal = &bp->signal[i];
3257
3258 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
3259 signal->duty, signal->phase, signal->polarity);
3260
3261 ts = ktime_to_timespec64(signal->start);
3262 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
3263
3264 return count;
3265 }
3266 static EXT_ATTR_RW(signal, signal, 0);
3267 static EXT_ATTR_RW(signal, signal, 1);
3268 static EXT_ATTR_RW(signal, signal, 2);
3269 static EXT_ATTR_RW(signal, signal, 3);
3270
3271 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)3272 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3273 {
3274 struct dev_ext_attribute *ea = to_ext_attr(attr);
3275 struct ptp_ocp *bp = dev_get_drvdata(dev);
3276 int i = (uintptr_t)ea->var;
3277
3278 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3279 }
3280 static EXT_ATTR_RO(signal, duty, 0);
3281 static EXT_ATTR_RO(signal, duty, 1);
3282 static EXT_ATTR_RO(signal, duty, 2);
3283 static EXT_ATTR_RO(signal, duty, 3);
3284
3285 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)3286 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3287 {
3288 struct dev_ext_attribute *ea = to_ext_attr(attr);
3289 struct ptp_ocp *bp = dev_get_drvdata(dev);
3290 int i = (uintptr_t)ea->var;
3291
3292 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3293 }
3294 static EXT_ATTR_RO(signal, period, 0);
3295 static EXT_ATTR_RO(signal, period, 1);
3296 static EXT_ATTR_RO(signal, period, 2);
3297 static EXT_ATTR_RO(signal, period, 3);
3298
3299 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)3300 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3301 {
3302 struct dev_ext_attribute *ea = to_ext_attr(attr);
3303 struct ptp_ocp *bp = dev_get_drvdata(dev);
3304 int i = (uintptr_t)ea->var;
3305
3306 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3307 }
3308 static EXT_ATTR_RO(signal, phase, 0);
3309 static EXT_ATTR_RO(signal, phase, 1);
3310 static EXT_ATTR_RO(signal, phase, 2);
3311 static EXT_ATTR_RO(signal, phase, 3);
3312
3313 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)3314 polarity_show(struct device *dev, struct device_attribute *attr,
3315 char *buf)
3316 {
3317 struct dev_ext_attribute *ea = to_ext_attr(attr);
3318 struct ptp_ocp *bp = dev_get_drvdata(dev);
3319 int i = (uintptr_t)ea->var;
3320
3321 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3322 }
3323 static EXT_ATTR_RO(signal, polarity, 0);
3324 static EXT_ATTR_RO(signal, polarity, 1);
3325 static EXT_ATTR_RO(signal, polarity, 2);
3326 static EXT_ATTR_RO(signal, polarity, 3);
3327
3328 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)3329 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3330 {
3331 struct dev_ext_attribute *ea = to_ext_attr(attr);
3332 struct ptp_ocp *bp = dev_get_drvdata(dev);
3333 int i = (uintptr_t)ea->var;
3334
3335 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3336 }
3337 static EXT_ATTR_RO(signal, running, 0);
3338 static EXT_ATTR_RO(signal, running, 1);
3339 static EXT_ATTR_RO(signal, running, 2);
3340 static EXT_ATTR_RO(signal, running, 3);
3341
3342 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)3343 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3344 {
3345 struct dev_ext_attribute *ea = to_ext_attr(attr);
3346 struct ptp_ocp *bp = dev_get_drvdata(dev);
3347 int i = (uintptr_t)ea->var;
3348 struct timespec64 ts;
3349
3350 ts = ktime_to_timespec64(bp->signal[i].start);
3351 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3352 }
3353 static EXT_ATTR_RO(signal, start, 0);
3354 static EXT_ATTR_RO(signal, start, 1);
3355 static EXT_ATTR_RO(signal, start, 2);
3356 static EXT_ATTR_RO(signal, start, 3);
3357
3358 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3359 seconds_store(struct device *dev, struct device_attribute *attr,
3360 const char *buf, size_t count)
3361 {
3362 struct dev_ext_attribute *ea = to_ext_attr(attr);
3363 struct ptp_ocp *bp = dev_get_drvdata(dev);
3364 int idx = (uintptr_t)ea->var;
3365 u32 val;
3366 int err;
3367
3368 err = kstrtou32(buf, 0, &val);
3369 if (err)
3370 return err;
3371 if (val > 0xff)
3372 return -EINVAL;
3373
3374 if (val)
3375 val = (val << 8) | 0x1;
3376
3377 iowrite32(val, &bp->freq_in[idx]->ctrl);
3378
3379 return count;
3380 }
3381
3382 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3383 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3384 {
3385 struct dev_ext_attribute *ea = to_ext_attr(attr);
3386 struct ptp_ocp *bp = dev_get_drvdata(dev);
3387 int idx = (uintptr_t)ea->var;
3388 u32 val;
3389
3390 val = ioread32(&bp->freq_in[idx]->ctrl);
3391 if (val & 1)
3392 val = (val >> 8) & 0xff;
3393 else
3394 val = 0;
3395
3396 return sysfs_emit(buf, "%u\n", val);
3397 }
3398 static EXT_ATTR_RW(freq, seconds, 0);
3399 static EXT_ATTR_RW(freq, seconds, 1);
3400 static EXT_ATTR_RW(freq, seconds, 2);
3401 static EXT_ATTR_RW(freq, seconds, 3);
3402
3403 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3404 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3405 {
3406 struct dev_ext_attribute *ea = to_ext_attr(attr);
3407 struct ptp_ocp *bp = dev_get_drvdata(dev);
3408 int idx = (uintptr_t)ea->var;
3409 u32 val;
3410
3411 val = ioread32(&bp->freq_in[idx]->status);
3412 if (val & FREQ_STATUS_ERROR)
3413 return sysfs_emit(buf, "error\n");
3414 if (val & FREQ_STATUS_OVERRUN)
3415 return sysfs_emit(buf, "overrun\n");
3416 if (val & FREQ_STATUS_VALID)
3417 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3418 return 0;
3419 }
3420 static EXT_ATTR_RO(freq, frequency, 0);
3421 static EXT_ATTR_RO(freq, frequency, 1);
3422 static EXT_ATTR_RO(freq, frequency, 2);
3423 static EXT_ATTR_RO(freq, frequency, 3);
3424
3425 static ssize_t
ptp_ocp_tty_show(struct device * dev,struct device_attribute * attr,char * buf)3426 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3427 {
3428 struct dev_ext_attribute *ea = to_ext_attr(attr);
3429 struct ptp_ocp *bp = dev_get_drvdata(dev);
3430
3431 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3432 }
3433
3434 static umode_t
ptp_ocp_timecard_tty_is_visible(struct kobject * kobj,struct attribute * attr,int n)3435 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3436 {
3437 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3438 struct ptp_ocp_serial_port *port;
3439 struct device_attribute *dattr;
3440 struct dev_ext_attribute *ea;
3441
3442 if (strncmp(attr->name, "tty", 3))
3443 return attr->mode;
3444
3445 dattr = container_of(attr, struct device_attribute, attr);
3446 ea = container_of(dattr, struct dev_ext_attribute, attr);
3447 port = &bp->port[(uintptr_t)ea->var];
3448 return port->line == -1 ? 0 : 0444;
3449 }
3450
3451 #define EXT_TTY_ATTR_RO(_name, _val) \
3452 struct dev_ext_attribute dev_attr_tty##_name = \
3453 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3454
3455 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3456 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3457 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3458 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3459 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3460 &dev_attr_ttyGNSS.attr.attr,
3461 &dev_attr_ttyGNSS2.attr.attr,
3462 &dev_attr_ttyMAC.attr.attr,
3463 &dev_attr_ttyNMEA.attr.attr,
3464 NULL,
3465 };
3466
3467 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3468 .name = "tty",
3469 .attrs = ptp_ocp_timecard_tty_attrs,
3470 .is_visible = ptp_ocp_timecard_tty_is_visible,
3471 };
3472
3473 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3474 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3475 {
3476 struct ptp_ocp *bp = dev_get_drvdata(dev);
3477
3478 if (!bp->has_eeprom_data)
3479 ptp_ocp_read_eeprom(bp);
3480
3481 return sysfs_emit(buf, "%pM\n", bp->serial);
3482 }
3483 static DEVICE_ATTR_RO(serialnum);
3484
3485 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3486 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3487 {
3488 struct ptp_ocp *bp = dev_get_drvdata(dev);
3489 ssize_t ret;
3490
3491 if (bp->gnss_lost)
3492 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3493 else
3494 ret = sysfs_emit(buf, "SYNC\n");
3495
3496 return ret;
3497 }
3498 static DEVICE_ATTR_RO(gnss_sync);
3499
3500 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3501 utc_tai_offset_show(struct device *dev,
3502 struct device_attribute *attr, char *buf)
3503 {
3504 struct ptp_ocp *bp = dev_get_drvdata(dev);
3505
3506 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3507 }
3508
3509 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3510 utc_tai_offset_store(struct device *dev,
3511 struct device_attribute *attr,
3512 const char *buf, size_t count)
3513 {
3514 struct ptp_ocp *bp = dev_get_drvdata(dev);
3515 int err;
3516 u32 val;
3517
3518 err = kstrtou32(buf, 0, &val);
3519 if (err)
3520 return err;
3521
3522 ptp_ocp_utc_distribute(bp, val);
3523
3524 return count;
3525 }
3526 static DEVICE_ATTR_RW(utc_tai_offset);
3527
3528 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3529 ts_window_adjust_show(struct device *dev,
3530 struct device_attribute *attr, char *buf)
3531 {
3532 struct ptp_ocp *bp = dev_get_drvdata(dev);
3533
3534 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3535 }
3536
3537 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3538 ts_window_adjust_store(struct device *dev,
3539 struct device_attribute *attr,
3540 const char *buf, size_t count)
3541 {
3542 struct ptp_ocp *bp = dev_get_drvdata(dev);
3543 int err;
3544 u32 val;
3545
3546 err = kstrtou32(buf, 0, &val);
3547 if (err)
3548 return err;
3549
3550 bp->ts_window_adjust = val;
3551
3552 return count;
3553 }
3554 static DEVICE_ATTR_RW(ts_window_adjust);
3555
3556 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3557 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3558 {
3559 struct ptp_ocp *bp = dev_get_drvdata(dev);
3560 u32 val;
3561
3562 val = ioread32(&bp->irig_out->ctrl);
3563 val = (val >> 16) & 0x07;
3564 return sysfs_emit(buf, "%d\n", val);
3565 }
3566
3567 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3568 irig_b_mode_store(struct device *dev,
3569 struct device_attribute *attr,
3570 const char *buf, size_t count)
3571 {
3572 struct ptp_ocp *bp = dev_get_drvdata(dev);
3573 unsigned long flags;
3574 int err;
3575 u32 reg;
3576 u8 val;
3577
3578 err = kstrtou8(buf, 0, &val);
3579 if (err)
3580 return err;
3581 if (val > 7)
3582 return -EINVAL;
3583
3584 reg = ((val & 0x7) << 16);
3585
3586 spin_lock_irqsave(&bp->lock, flags);
3587 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3588 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3589 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3590 spin_unlock_irqrestore(&bp->lock, flags);
3591
3592 return count;
3593 }
3594 static DEVICE_ATTR_RW(irig_b_mode);
3595
3596 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3597 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3598 {
3599 struct ptp_ocp *bp = dev_get_drvdata(dev);
3600 const char *p;
3601 u32 select;
3602
3603 select = ioread32(&bp->reg->select);
3604 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3605
3606 return sysfs_emit(buf, "%s\n", p);
3607 }
3608
3609 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3610 clock_source_store(struct device *dev, struct device_attribute *attr,
3611 const char *buf, size_t count)
3612 {
3613 struct ptp_ocp *bp = dev_get_drvdata(dev);
3614 unsigned long flags;
3615 int val;
3616
3617 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3618 if (val < 0)
3619 return val;
3620
3621 spin_lock_irqsave(&bp->lock, flags);
3622 iowrite32(val, &bp->reg->select);
3623 spin_unlock_irqrestore(&bp->lock, flags);
3624
3625 return count;
3626 }
3627 static DEVICE_ATTR_RW(clock_source);
3628
3629 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3630 available_clock_sources_show(struct device *dev,
3631 struct device_attribute *attr, char *buf)
3632 {
3633 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3634 }
3635 static DEVICE_ATTR_RO(available_clock_sources);
3636
3637 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3638 clock_status_drift_show(struct device *dev,
3639 struct device_attribute *attr, char *buf)
3640 {
3641 struct ptp_ocp *bp = dev_get_drvdata(dev);
3642 u32 val;
3643 int res;
3644
3645 val = ioread32(&bp->reg->status_drift);
3646 res = (val & ~INT_MAX) ? -1 : 1;
3647 res *= (val & INT_MAX);
3648 return sysfs_emit(buf, "%d\n", res);
3649 }
3650 static DEVICE_ATTR_RO(clock_status_drift);
3651
3652 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3653 clock_status_offset_show(struct device *dev,
3654 struct device_attribute *attr, char *buf)
3655 {
3656 struct ptp_ocp *bp = dev_get_drvdata(dev);
3657 u32 val;
3658 int res;
3659
3660 val = ioread32(&bp->reg->status_offset);
3661 res = (val & ~INT_MAX) ? -1 : 1;
3662 res *= (val & INT_MAX);
3663 return sysfs_emit(buf, "%d\n", res);
3664 }
3665 static DEVICE_ATTR_RO(clock_status_offset);
3666
3667 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3668 tod_correction_show(struct device *dev,
3669 struct device_attribute *attr, char *buf)
3670 {
3671 struct ptp_ocp *bp = dev_get_drvdata(dev);
3672 u32 val;
3673 int res;
3674
3675 val = ioread32(&bp->tod->adj_sec);
3676 res = (val & ~INT_MAX) ? -1 : 1;
3677 res *= (val & INT_MAX);
3678 return sysfs_emit(buf, "%d\n", res);
3679 }
3680
3681 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3682 tod_correction_store(struct device *dev, struct device_attribute *attr,
3683 const char *buf, size_t count)
3684 {
3685 struct ptp_ocp *bp = dev_get_drvdata(dev);
3686 unsigned long flags;
3687 int err, res;
3688 u32 val = 0;
3689
3690 err = kstrtos32(buf, 0, &res);
3691 if (err)
3692 return err;
3693 if (res < 0) {
3694 res *= -1;
3695 val |= BIT(31);
3696 }
3697 val |= res;
3698
3699 spin_lock_irqsave(&bp->lock, flags);
3700 iowrite32(val, &bp->tod->adj_sec);
3701 spin_unlock_irqrestore(&bp->lock, flags);
3702
3703 return count;
3704 }
3705 static DEVICE_ATTR_RW(tod_correction);
3706
3707 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3708 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3709 &dev_attr_signal##_nr##_signal.attr.attr, \
3710 &dev_attr_signal##_nr##_duty.attr.attr, \
3711 &dev_attr_signal##_nr##_phase.attr.attr, \
3712 &dev_attr_signal##_nr##_period.attr.attr, \
3713 &dev_attr_signal##_nr##_polarity.attr.attr, \
3714 &dev_attr_signal##_nr##_running.attr.attr, \
3715 &dev_attr_signal##_nr##_start.attr.attr, \
3716 NULL, \
3717 }
3718
3719 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3720 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3721 static const struct attribute_group \
3722 fb_timecard_signal##_nr##_group = { \
3723 .name = #_name, \
3724 .attrs = fb_timecard_signal##_nr##_attrs, \
3725 }
3726
3727 DEVICE_SIGNAL_GROUP(gen1, 0);
3728 DEVICE_SIGNAL_GROUP(gen2, 1);
3729 DEVICE_SIGNAL_GROUP(gen3, 2);
3730 DEVICE_SIGNAL_GROUP(gen4, 3);
3731
3732 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3733 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3734 &dev_attr_freq##_nr##_seconds.attr.attr, \
3735 &dev_attr_freq##_nr##_frequency.attr.attr, \
3736 NULL, \
3737 }
3738
3739 #define DEVICE_FREQ_GROUP(_name, _nr) \
3740 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3741 static const struct attribute_group \
3742 fb_timecard_freq##_nr##_group = { \
3743 .name = #_name, \
3744 .attrs = fb_timecard_freq##_nr##_attrs, \
3745 }
3746
3747 DEVICE_FREQ_GROUP(freq1, 0);
3748 DEVICE_FREQ_GROUP(freq2, 1);
3749 DEVICE_FREQ_GROUP(freq3, 2);
3750 DEVICE_FREQ_GROUP(freq4, 3);
3751
3752 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3753 disciplining_config_read(struct file *filp, struct kobject *kobj,
3754 struct bin_attribute *bin_attr, char *buf,
3755 loff_t off, size_t count)
3756 {
3757 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3758 size_t size = OCP_ART_CONFIG_SIZE;
3759 struct nvmem_device *nvmem;
3760 ssize_t err;
3761
3762 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3763 if (IS_ERR(nvmem))
3764 return PTR_ERR(nvmem);
3765
3766 if (off > size) {
3767 err = 0;
3768 goto out;
3769 }
3770
3771 if (off + count > size)
3772 count = size - off;
3773
3774 // the configuration is in the very beginning of the EEPROM
3775 err = nvmem_device_read(nvmem, off, count, buf);
3776 if (err != count) {
3777 err = -EFAULT;
3778 goto out;
3779 }
3780
3781 out:
3782 ptp_ocp_nvmem_device_put(&nvmem);
3783
3784 return err;
3785 }
3786
3787 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3788 disciplining_config_write(struct file *filp, struct kobject *kobj,
3789 struct bin_attribute *bin_attr, char *buf,
3790 loff_t off, size_t count)
3791 {
3792 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3793 struct nvmem_device *nvmem;
3794 ssize_t err;
3795
3796 /* Allow write of the whole area only */
3797 if (off || count != OCP_ART_CONFIG_SIZE)
3798 return -EFAULT;
3799
3800 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3801 if (IS_ERR(nvmem))
3802 return PTR_ERR(nvmem);
3803
3804 err = nvmem_device_write(nvmem, 0x00, count, buf);
3805 if (err != count)
3806 err = -EFAULT;
3807
3808 ptp_ocp_nvmem_device_put(&nvmem);
3809
3810 return err;
3811 }
3812 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3813
3814 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3815 temperature_table_read(struct file *filp, struct kobject *kobj,
3816 struct bin_attribute *bin_attr, char *buf,
3817 loff_t off, size_t count)
3818 {
3819 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3820 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3821 struct nvmem_device *nvmem;
3822 ssize_t err;
3823
3824 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3825 if (IS_ERR(nvmem))
3826 return PTR_ERR(nvmem);
3827
3828 if (off > size) {
3829 err = 0;
3830 goto out;
3831 }
3832
3833 if (off + count > size)
3834 count = size - off;
3835
3836 // the configuration is in the very beginning of the EEPROM
3837 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3838 if (err != count) {
3839 err = -EFAULT;
3840 goto out;
3841 }
3842
3843 out:
3844 ptp_ocp_nvmem_device_put(&nvmem);
3845
3846 return err;
3847 }
3848
3849 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3850 temperature_table_write(struct file *filp, struct kobject *kobj,
3851 struct bin_attribute *bin_attr, char *buf,
3852 loff_t off, size_t count)
3853 {
3854 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3855 struct nvmem_device *nvmem;
3856 ssize_t err;
3857
3858 /* Allow write of the whole area only */
3859 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3860 return -EFAULT;
3861
3862 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3863 if (IS_ERR(nvmem))
3864 return PTR_ERR(nvmem);
3865
3866 err = nvmem_device_write(nvmem, 0x90, count, buf);
3867 if (err != count)
3868 err = -EFAULT;
3869
3870 ptp_ocp_nvmem_device_put(&nvmem);
3871
3872 return err;
3873 }
3874 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3875
3876 static struct attribute *fb_timecard_attrs[] = {
3877 &dev_attr_serialnum.attr,
3878 &dev_attr_gnss_sync.attr,
3879 &dev_attr_clock_source.attr,
3880 &dev_attr_available_clock_sources.attr,
3881 &dev_attr_sma1.attr,
3882 &dev_attr_sma2.attr,
3883 &dev_attr_sma3.attr,
3884 &dev_attr_sma4.attr,
3885 &dev_attr_available_sma_inputs.attr,
3886 &dev_attr_available_sma_outputs.attr,
3887 &dev_attr_clock_status_drift.attr,
3888 &dev_attr_clock_status_offset.attr,
3889 &dev_attr_irig_b_mode.attr,
3890 &dev_attr_utc_tai_offset.attr,
3891 &dev_attr_ts_window_adjust.attr,
3892 &dev_attr_tod_correction.attr,
3893 NULL,
3894 };
3895
3896 static const struct attribute_group fb_timecard_group = {
3897 .attrs = fb_timecard_attrs,
3898 };
3899
3900 static const struct ocp_attr_group fb_timecard_groups[] = {
3901 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3902 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3903 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3904 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3905 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3906 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3907 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3908 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3909 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3910 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3911 { },
3912 };
3913
3914 static struct attribute *art_timecard_attrs[] = {
3915 &dev_attr_serialnum.attr,
3916 &dev_attr_clock_source.attr,
3917 &dev_attr_available_clock_sources.attr,
3918 &dev_attr_utc_tai_offset.attr,
3919 &dev_attr_ts_window_adjust.attr,
3920 &dev_attr_sma1.attr,
3921 &dev_attr_sma2.attr,
3922 &dev_attr_sma3.attr,
3923 &dev_attr_sma4.attr,
3924 &dev_attr_available_sma_inputs.attr,
3925 &dev_attr_available_sma_outputs.attr,
3926 NULL,
3927 };
3928
3929 static struct bin_attribute *bin_art_timecard_attrs[] = {
3930 &bin_attr_disciplining_config,
3931 &bin_attr_temperature_table,
3932 NULL,
3933 };
3934
3935 static const struct attribute_group art_timecard_group = {
3936 .attrs = art_timecard_attrs,
3937 .bin_attrs = bin_art_timecard_attrs,
3938 };
3939
3940 static const struct ocp_attr_group art_timecard_groups[] = {
3941 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3942 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3943 { },
3944 };
3945
3946 static struct attribute *adva_timecard_attrs[] = {
3947 &dev_attr_serialnum.attr,
3948 &dev_attr_gnss_sync.attr,
3949 &dev_attr_clock_source.attr,
3950 &dev_attr_available_clock_sources.attr,
3951 &dev_attr_sma1.attr,
3952 &dev_attr_sma2.attr,
3953 &dev_attr_sma3.attr,
3954 &dev_attr_sma4.attr,
3955 &dev_attr_available_sma_inputs.attr,
3956 &dev_attr_available_sma_outputs.attr,
3957 &dev_attr_clock_status_drift.attr,
3958 &dev_attr_clock_status_offset.attr,
3959 &dev_attr_ts_window_adjust.attr,
3960 &dev_attr_tod_correction.attr,
3961 NULL,
3962 };
3963
3964 static const struct attribute_group adva_timecard_group = {
3965 .attrs = adva_timecard_attrs,
3966 };
3967
3968 static const struct ocp_attr_group adva_timecard_groups[] = {
3969 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3970 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3971 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3972 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3973 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3974 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3975 { },
3976 };
3977
3978 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3979 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3980 const char *def)
3981 {
3982 int i;
3983
3984 for (i = 0; i < 4; i++) {
3985 if (bp->sma[i].mode != SMA_MODE_IN)
3986 continue;
3987 if (map[i][0] & (1 << bit)) {
3988 sprintf(buf, "sma%d", i + 1);
3989 return;
3990 }
3991 }
3992 if (!def)
3993 def = "----";
3994 strcpy(buf, def);
3995 }
3996
3997 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)3998 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3999 {
4000 char *ans = buf;
4001 int i;
4002
4003 strcpy(ans, "----");
4004 for (i = 0; i < 4; i++) {
4005 if (bp->sma[i].mode != SMA_MODE_OUT)
4006 continue;
4007 if (map[i][1] & (1 << bit))
4008 ans += sprintf(ans, "sma%d ", i + 1);
4009 }
4010 }
4011
4012 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)4013 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
4014 {
4015 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
4016 struct ptp_ocp_signal *signal = &bp->signal[nr];
4017 char label[16];
4018 bool on;
4019 u32 val;
4020
4021 if (!signal)
4022 return;
4023
4024 on = signal->running;
4025 sprintf(label, "GEN%d", nr + 1);
4026 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
4027 label, on ? " ON" : "OFF",
4028 signal->period, signal->duty, signal->phase,
4029 signal->polarity);
4030
4031 val = ioread32(®->enable);
4032 seq_printf(s, " [%x", val);
4033 val = ioread32(®->status);
4034 seq_printf(s, " %x]", val);
4035
4036 seq_printf(s, " start:%llu\n", signal->start);
4037 }
4038
4039 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)4040 _frequency_summary_show(struct seq_file *s, int nr,
4041 struct frequency_reg __iomem *reg)
4042 {
4043 char label[16];
4044 bool on;
4045 u32 val;
4046
4047 if (!reg)
4048 return;
4049
4050 sprintf(label, "FREQ%d", nr + 1);
4051 val = ioread32(®->ctrl);
4052 on = val & 1;
4053 val = (val >> 8) & 0xff;
4054 seq_printf(s, "%7s: %s, sec:%u",
4055 label,
4056 on ? " ON" : "OFF",
4057 val);
4058
4059 val = ioread32(®->status);
4060 if (val & FREQ_STATUS_ERROR)
4061 seq_printf(s, ", error");
4062 if (val & FREQ_STATUS_OVERRUN)
4063 seq_printf(s, ", overrun");
4064 if (val & FREQ_STATUS_VALID)
4065 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
4066 seq_printf(s, " reg:%x\n", val);
4067 }
4068
4069 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)4070 ptp_ocp_summary_show(struct seq_file *s, void *data)
4071 {
4072 struct device *dev = s->private;
4073 struct ptp_system_timestamp sts;
4074 struct ts_reg __iomem *ts_reg;
4075 char *buf, *src, *mac_src;
4076 struct timespec64 ts;
4077 struct ptp_ocp *bp;
4078 u16 sma_val[4][2];
4079 u32 ctrl, val;
4080 bool on, map;
4081 int i;
4082
4083 buf = (char *)__get_free_page(GFP_KERNEL);
4084 if (!buf)
4085 return -ENOMEM;
4086
4087 bp = dev_get_drvdata(dev);
4088
4089 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
4090 for (i = 0; i < __PORT_COUNT; i++) {
4091 if (bp->port[i].line != -1)
4092 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
4093 bp->port[i].line);
4094 }
4095
4096 memset(sma_val, 0xff, sizeof(sma_val));
4097 if (bp->sma_map1) {
4098 u32 reg;
4099
4100 reg = ioread32(&bp->sma_map1->gpio1);
4101 sma_val[0][0] = reg & 0xffff;
4102 sma_val[1][0] = reg >> 16;
4103
4104 reg = ioread32(&bp->sma_map1->gpio2);
4105 sma_val[2][1] = reg & 0xffff;
4106 sma_val[3][1] = reg >> 16;
4107
4108 reg = ioread32(&bp->sma_map2->gpio1);
4109 sma_val[2][0] = reg & 0xffff;
4110 sma_val[3][0] = reg >> 16;
4111
4112 reg = ioread32(&bp->sma_map2->gpio2);
4113 sma_val[0][1] = reg & 0xffff;
4114 sma_val[1][1] = reg >> 16;
4115 }
4116
4117 sma1_show(dev, NULL, buf);
4118 seq_printf(s, " sma1: %04x,%04x %s",
4119 sma_val[0][0], sma_val[0][1], buf);
4120
4121 sma2_show(dev, NULL, buf);
4122 seq_printf(s, " sma2: %04x,%04x %s",
4123 sma_val[1][0], sma_val[1][1], buf);
4124
4125 sma3_show(dev, NULL, buf);
4126 seq_printf(s, " sma3: %04x,%04x %s",
4127 sma_val[2][0], sma_val[2][1], buf);
4128
4129 sma4_show(dev, NULL, buf);
4130 seq_printf(s, " sma4: %04x,%04x %s",
4131 sma_val[3][0], sma_val[3][1], buf);
4132
4133 if (bp->ts0) {
4134 ts_reg = bp->ts0->mem;
4135 on = ioread32(&ts_reg->enable);
4136 src = "GNSS1";
4137 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4138 on ? " ON" : "OFF", src);
4139 }
4140
4141 if (bp->ts1) {
4142 ts_reg = bp->ts1->mem;
4143 on = ioread32(&ts_reg->enable);
4144 gpio_input_map(buf, bp, sma_val, 2, NULL);
4145 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4146 on ? " ON" : "OFF", buf);
4147 }
4148
4149 if (bp->ts2) {
4150 ts_reg = bp->ts2->mem;
4151 on = ioread32(&ts_reg->enable);
4152 gpio_input_map(buf, bp, sma_val, 3, NULL);
4153 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4154 on ? " ON" : "OFF", buf);
4155 }
4156
4157 if (bp->ts3) {
4158 ts_reg = bp->ts3->mem;
4159 on = ioread32(&ts_reg->enable);
4160 gpio_input_map(buf, bp, sma_val, 6, NULL);
4161 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4162 on ? " ON" : "OFF", buf);
4163 }
4164
4165 if (bp->ts4) {
4166 ts_reg = bp->ts4->mem;
4167 on = ioread32(&ts_reg->enable);
4168 gpio_input_map(buf, bp, sma_val, 7, NULL);
4169 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4170 on ? " ON" : "OFF", buf);
4171 }
4172
4173 if (bp->pps) {
4174 ts_reg = bp->pps->mem;
4175 src = "PHC";
4176 on = ioread32(&ts_reg->enable);
4177 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4178 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4179 on && map ? " ON" : "OFF", src);
4180
4181 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4182 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4183 on && map ? " ON" : "OFF", src);
4184 }
4185
4186 if (bp->fw_cap & OCP_CAP_SIGNAL)
4187 for (i = 0; i < bp->signals_nr; i++)
4188 _signal_summary_show(s, bp, i);
4189
4190 if (bp->fw_cap & OCP_CAP_FREQ)
4191 for (i = 0; i < bp->freq_in_nr; i++)
4192 _frequency_summary_show(s, i, bp->freq_in[i]);
4193
4194 if (bp->irig_out) {
4195 ctrl = ioread32(&bp->irig_out->ctrl);
4196 on = ctrl & IRIG_M_CTRL_ENABLE;
4197 val = ioread32(&bp->irig_out->status);
4198 gpio_output_map(buf, bp, sma_val, 4);
4199 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4200 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4201 }
4202
4203 if (bp->irig_in) {
4204 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4205 val = ioread32(&bp->irig_in->status);
4206 gpio_input_map(buf, bp, sma_val, 4, NULL);
4207 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4208 on ? " ON" : "OFF", val, buf);
4209 }
4210
4211 if (bp->dcf_out) {
4212 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4213 val = ioread32(&bp->dcf_out->status);
4214 gpio_output_map(buf, bp, sma_val, 5);
4215 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4216 on ? " ON" : "OFF", val, buf);
4217 }
4218
4219 if (bp->dcf_in) {
4220 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4221 val = ioread32(&bp->dcf_in->status);
4222 gpio_input_map(buf, bp, sma_val, 5, NULL);
4223 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4224 on ? " ON" : "OFF", val, buf);
4225 }
4226
4227 if (bp->nmea_out) {
4228 on = ioread32(&bp->nmea_out->ctrl) & 1;
4229 val = ioread32(&bp->nmea_out->status);
4230 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4231 on ? " ON" : "OFF", val);
4232 }
4233
4234 /* compute src for PPS1, used below. */
4235 if (bp->pps_select) {
4236 val = ioread32(&bp->pps_select->gpio1);
4237 src = &buf[80];
4238 mac_src = "GNSS1";
4239 if (val & 0x01) {
4240 gpio_input_map(src, bp, sma_val, 0, NULL);
4241 mac_src = src;
4242 } else if (val & 0x02) {
4243 src = "MAC";
4244 } else if (val & 0x04) {
4245 src = "GNSS1";
4246 } else {
4247 src = "----";
4248 mac_src = src;
4249 }
4250 } else {
4251 src = "?";
4252 mac_src = src;
4253 }
4254 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4255
4256 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4257 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4258
4259 /* assumes automatic switchover/selection */
4260 val = ioread32(&bp->reg->select);
4261 switch (val >> 16) {
4262 case 0:
4263 sprintf(buf, "----");
4264 break;
4265 case 2:
4266 sprintf(buf, "IRIG");
4267 break;
4268 case 3:
4269 sprintf(buf, "%s via PPS1", src);
4270 break;
4271 case 6:
4272 sprintf(buf, "DCF");
4273 break;
4274 default:
4275 strcpy(buf, "unknown");
4276 break;
4277 }
4278 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4279 bp->sync ? "sync" : "unsynced");
4280
4281 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4282 struct timespec64 sys_ts;
4283 s64 pre_ns, post_ns, ns;
4284
4285 pre_ns = timespec64_to_ns(&sts.pre_ts);
4286 post_ns = timespec64_to_ns(&sts.post_ts);
4287 ns = (pre_ns + post_ns) / 2;
4288 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4289 sys_ts = ns_to_timespec64(ns);
4290
4291 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
4292 ts.tv_sec, ts.tv_nsec, &ts);
4293 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
4294 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
4295 bp->utc_tai_offset);
4296 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4297 timespec64_to_ns(&ts) - ns,
4298 post_ns - pre_ns);
4299 }
4300
4301 free_page((unsigned long)buf);
4302 return 0;
4303 }
4304 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4305
4306 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)4307 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4308 {
4309 struct device *dev = s->private;
4310 struct ptp_ocp *bp;
4311 u32 val;
4312 int idx;
4313
4314 bp = dev_get_drvdata(dev);
4315
4316 val = ioread32(&bp->tod->ctrl);
4317 if (!(val & TOD_CTRL_ENABLE)) {
4318 seq_printf(s, "TOD Slave disabled\n");
4319 return 0;
4320 }
4321 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4322
4323 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4324 idx += (val >> 16) & 3;
4325 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4326
4327 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4328 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4329
4330 val = ioread32(&bp->tod->version);
4331 seq_printf(s, "TOD Version %d.%d.%d\n",
4332 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4333
4334 val = ioread32(&bp->tod->status);
4335 seq_printf(s, "Status register: 0x%08X\n", val);
4336
4337 val = ioread32(&bp->tod->adj_sec);
4338 idx = (val & ~INT_MAX) ? -1 : 1;
4339 idx *= (val & INT_MAX);
4340 seq_printf(s, "Correction seconds: %d\n", idx);
4341
4342 val = ioread32(&bp->tod->utc_status);
4343 seq_printf(s, "UTC status register: 0x%08X\n", val);
4344 seq_printf(s, "UTC offset: %ld valid:%d\n",
4345 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4346 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4347 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4348 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4349
4350 val = ioread32(&bp->tod->leap);
4351 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4352
4353 return 0;
4354 }
4355 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4356
4357 static struct dentry *ptp_ocp_debugfs_root;
4358
4359 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)4360 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4361 {
4362 struct dentry *d;
4363
4364 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4365 bp->debug_root = d;
4366 debugfs_create_file("summary", 0444, bp->debug_root,
4367 &bp->dev, &ptp_ocp_summary_fops);
4368 if (bp->tod)
4369 debugfs_create_file("tod_status", 0444, bp->debug_root,
4370 &bp->dev, &ptp_ocp_tod_status_fops);
4371 }
4372
4373 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)4374 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4375 {
4376 debugfs_remove_recursive(bp->debug_root);
4377 }
4378
4379 static void
ptp_ocp_debugfs_init(void)4380 ptp_ocp_debugfs_init(void)
4381 {
4382 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4383 }
4384
4385 static void
ptp_ocp_debugfs_fini(void)4386 ptp_ocp_debugfs_fini(void)
4387 {
4388 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4389 }
4390
4391 static void
ptp_ocp_dev_release(struct device * dev)4392 ptp_ocp_dev_release(struct device *dev)
4393 {
4394 struct ptp_ocp *bp = dev_get_drvdata(dev);
4395
4396 mutex_lock(&ptp_ocp_lock);
4397 idr_remove(&ptp_ocp_idr, bp->id);
4398 mutex_unlock(&ptp_ocp_lock);
4399 }
4400
4401 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)4402 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4403 {
4404 int i, err;
4405
4406 mutex_lock(&ptp_ocp_lock);
4407 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4408 mutex_unlock(&ptp_ocp_lock);
4409 if (err < 0) {
4410 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4411 return err;
4412 }
4413 bp->id = err;
4414
4415 bp->ptp_info = ptp_ocp_clock_info;
4416 spin_lock_init(&bp->lock);
4417
4418 for (i = 0; i < __PORT_COUNT; i++)
4419 bp->port[i].line = -1;
4420
4421 bp->pdev = pdev;
4422
4423 device_initialize(&bp->dev);
4424 dev_set_name(&bp->dev, "ocp%d", bp->id);
4425 bp->dev.class = &timecard_class;
4426 bp->dev.parent = &pdev->dev;
4427 bp->dev.release = ptp_ocp_dev_release;
4428 dev_set_drvdata(&bp->dev, bp);
4429
4430 err = device_add(&bp->dev);
4431 if (err) {
4432 dev_err(&bp->dev, "device add failed: %d\n", err);
4433 goto out;
4434 }
4435
4436 pci_set_drvdata(pdev, bp);
4437
4438 return 0;
4439
4440 out:
4441 put_device(&bp->dev);
4442 return err;
4443 }
4444
4445 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4446 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4447 {
4448 struct device *dev = &bp->dev;
4449
4450 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4451 dev_err(dev, "%s symlink failed\n", link);
4452 }
4453
4454 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4455 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4456 {
4457 struct device *dev, *child;
4458
4459 dev = &bp->pdev->dev;
4460
4461 child = device_find_child_by_name(dev, name);
4462 if (!child) {
4463 dev_err(dev, "Could not find device %s\n", name);
4464 return;
4465 }
4466
4467 ptp_ocp_symlink(bp, child, link);
4468 put_device(child);
4469 }
4470
4471 static int
ptp_ocp_complete(struct ptp_ocp * bp)4472 ptp_ocp_complete(struct ptp_ocp *bp)
4473 {
4474 struct pps_device *pps;
4475 char buf[32];
4476
4477 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4478 ptp_ocp_link_child(bp, buf, "ptp");
4479
4480 pps = pps_lookup_dev(bp->ptp);
4481 if (pps)
4482 ptp_ocp_symlink(bp, &pps->dev, "pps");
4483
4484 ptp_ocp_debugfs_add_device(bp);
4485
4486 return 0;
4487 }
4488
4489 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4490 ptp_ocp_phc_info(struct ptp_ocp *bp)
4491 {
4492 struct timespec64 ts;
4493 u32 version, select;
4494
4495 version = ioread32(&bp->reg->version);
4496 select = ioread32(&bp->reg->select);
4497 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4498 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4499 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4500 ptp_clock_index(bp->ptp));
4501
4502 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4503 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4504 ts.tv_sec, ts.tv_nsec,
4505 bp->sync ? "in-sync" : "UNSYNCED");
4506 }
4507
4508 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4509 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4510 {
4511 if (port != -1)
4512 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4513 }
4514
4515 static void
ptp_ocp_info(struct ptp_ocp * bp)4516 ptp_ocp_info(struct ptp_ocp *bp)
4517 {
4518 static int nmea_baud[] = {
4519 1200, 2400, 4800, 9600, 19200, 38400,
4520 57600, 115200, 230400, 460800, 921600,
4521 1000000, 2000000
4522 };
4523 struct device *dev = &bp->pdev->dev;
4524 u32 reg;
4525 int i;
4526
4527 ptp_ocp_phc_info(bp);
4528
4529 for (i = 0; i < __PORT_COUNT; i++) {
4530 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
4531 bp->port[PORT_NMEA].baud = -1;
4532
4533 reg = ioread32(&bp->nmea_out->uart_baud);
4534 if (reg < ARRAY_SIZE(nmea_baud))
4535 bp->port[PORT_NMEA].baud = nmea_baud[reg];
4536 }
4537 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
4538 bp->port[i].baud);
4539 }
4540 }
4541
4542 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4543 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4544 {
4545 struct device *dev = &bp->dev;
4546
4547 sysfs_remove_link(&dev->kobj, "ptp");
4548 sysfs_remove_link(&dev->kobj, "pps");
4549 }
4550
4551 static void
ptp_ocp_detach(struct ptp_ocp * bp)4552 ptp_ocp_detach(struct ptp_ocp *bp)
4553 {
4554 int i;
4555
4556 ptp_ocp_debugfs_remove_device(bp);
4557 ptp_ocp_detach_sysfs(bp);
4558 ptp_ocp_attr_group_del(bp);
4559 if (timer_pending(&bp->watchdog))
4560 del_timer_sync(&bp->watchdog);
4561 if (bp->ts0)
4562 ptp_ocp_unregister_ext(bp->ts0);
4563 if (bp->ts1)
4564 ptp_ocp_unregister_ext(bp->ts1);
4565 if (bp->ts2)
4566 ptp_ocp_unregister_ext(bp->ts2);
4567 if (bp->ts3)
4568 ptp_ocp_unregister_ext(bp->ts3);
4569 if (bp->ts4)
4570 ptp_ocp_unregister_ext(bp->ts4);
4571 if (bp->pps)
4572 ptp_ocp_unregister_ext(bp->pps);
4573 for (i = 0; i < 4; i++)
4574 if (bp->signal_out[i])
4575 ptp_ocp_unregister_ext(bp->signal_out[i]);
4576 for (i = 0; i < __PORT_COUNT; i++)
4577 if (bp->port[i].line != -1)
4578 serial8250_unregister_port(bp->port[i].line);
4579 platform_device_unregister(bp->spi_flash);
4580 platform_device_unregister(bp->i2c_ctrl);
4581 if (bp->i2c_clk)
4582 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4583 if (bp->n_irqs)
4584 pci_free_irq_vectors(bp->pdev);
4585 if (bp->ptp)
4586 ptp_clock_unregister(bp->ptp);
4587 kfree(bp->ptp_info.pin_config);
4588 device_unregister(&bp->dev);
4589 }
4590
4591 static int
ptp_ocp_dpll_lock_status_get(const struct dpll_device * dpll,void * priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)4592 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4593 enum dpll_lock_status *status,
4594 enum dpll_lock_status_error *status_error,
4595 struct netlink_ext_ack *extack)
4596 {
4597 struct ptp_ocp *bp = priv;
4598
4599 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4600
4601 return 0;
4602 }
4603
ptp_ocp_dpll_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)4604 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4605 const struct dpll_device *dpll, void *priv,
4606 enum dpll_pin_state *state,
4607 struct netlink_ext_ack *extack)
4608 {
4609 struct ptp_ocp *bp = priv;
4610 int idx;
4611
4612 if (bp->pps_select) {
4613 idx = ioread32(&bp->pps_select->gpio1);
4614 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4615 DPLL_PIN_STATE_SELECTABLE;
4616 return 0;
4617 }
4618 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4619 return -EINVAL;
4620 }
4621
ptp_ocp_dpll_mode_get(const struct dpll_device * dpll,void * priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)4622 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4623 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4624 {
4625 *mode = DPLL_MODE_AUTOMATIC;
4626 return 0;
4627 }
4628
ptp_ocp_dpll_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)4629 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4630 void *pin_priv,
4631 const struct dpll_device *dpll,
4632 void *priv,
4633 enum dpll_pin_direction *direction,
4634 struct netlink_ext_ack *extack)
4635 {
4636 struct ptp_ocp_sma_connector *sma = pin_priv;
4637
4638 *direction = sma->mode == SMA_MODE_IN ?
4639 DPLL_PIN_DIRECTION_INPUT :
4640 DPLL_PIN_DIRECTION_OUTPUT;
4641 return 0;
4642 }
4643
ptp_ocp_dpll_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack)4644 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4645 void *pin_priv,
4646 const struct dpll_device *dpll,
4647 void *dpll_priv,
4648 enum dpll_pin_direction direction,
4649 struct netlink_ext_ack *extack)
4650 {
4651 struct ptp_ocp_sma_connector *sma = pin_priv;
4652 struct ptp_ocp *bp = dpll_priv;
4653 enum ptp_ocp_sma_mode mode;
4654 int sma_nr = (sma - bp->sma);
4655
4656 if (sma->fixed_dir)
4657 return -EOPNOTSUPP;
4658 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4659 SMA_MODE_IN : SMA_MODE_OUT;
4660 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
4661 }
4662
ptp_ocp_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)4663 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4664 void *pin_priv,
4665 const struct dpll_device *dpll,
4666 void *dpll_priv, u64 frequency,
4667 struct netlink_ext_ack *extack)
4668 {
4669 struct ptp_ocp_sma_connector *sma = pin_priv;
4670 struct ptp_ocp *bp = dpll_priv;
4671 const struct ocp_selector *tbl;
4672 int sma_nr = (sma - bp->sma);
4673 int i;
4674
4675 if (sma->fixed_fcn)
4676 return -EOPNOTSUPP;
4677
4678 tbl = bp->sma_op->tbl[sma->mode];
4679 for (i = 0; tbl[i].name; i++)
4680 if (tbl[i].frequency == frequency)
4681 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
4682 return -EINVAL;
4683 }
4684
ptp_ocp_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)4685 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4686 void *pin_priv,
4687 const struct dpll_device *dpll,
4688 void *dpll_priv, u64 *frequency,
4689 struct netlink_ext_ack *extack)
4690 {
4691 struct ptp_ocp_sma_connector *sma = pin_priv;
4692 struct ptp_ocp *bp = dpll_priv;
4693 const struct ocp_selector *tbl;
4694 int sma_nr = (sma - bp->sma);
4695 u32 val;
4696 int i;
4697
4698 val = bp->sma_op->get(bp, sma_nr + 1);
4699 tbl = bp->sma_op->tbl[sma->mode];
4700 for (i = 0; tbl[i].name; i++)
4701 if (val == tbl[i].value) {
4702 *frequency = tbl[i].frequency;
4703 return 0;
4704 }
4705
4706 return -EINVAL;
4707 }
4708
4709 static const struct dpll_device_ops dpll_ops = {
4710 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4711 .mode_get = ptp_ocp_dpll_mode_get,
4712 };
4713
4714 static const struct dpll_pin_ops dpll_pins_ops = {
4715 .frequency_get = ptp_ocp_dpll_frequency_get,
4716 .frequency_set = ptp_ocp_dpll_frequency_set,
4717 .direction_get = ptp_ocp_dpll_direction_get,
4718 .direction_set = ptp_ocp_dpll_direction_set,
4719 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4720 };
4721
4722 static void
ptp_ocp_sync_work(struct work_struct * work)4723 ptp_ocp_sync_work(struct work_struct *work)
4724 {
4725 struct ptp_ocp *bp;
4726 bool sync;
4727
4728 bp = container_of(work, struct ptp_ocp, sync_work.work);
4729 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4730
4731 if (bp->sync != sync)
4732 dpll_device_change_ntf(bp->dpll);
4733
4734 bp->sync = sync;
4735
4736 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4737 }
4738
4739 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)4740 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4741 {
4742 struct devlink *devlink;
4743 struct ptp_ocp *bp;
4744 int err, i;
4745 u64 clkid;
4746
4747 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4748 if (!devlink) {
4749 dev_err(&pdev->dev, "devlink_alloc failed\n");
4750 return -ENOMEM;
4751 }
4752
4753 err = pci_enable_device(pdev);
4754 if (err) {
4755 dev_err(&pdev->dev, "pci_enable_device\n");
4756 goto out_free;
4757 }
4758
4759 bp = devlink_priv(devlink);
4760 err = ptp_ocp_device_init(bp, pdev);
4761 if (err)
4762 goto out_disable;
4763
4764 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4765
4766 /* compat mode.
4767 * Older FPGA firmware only returns 2 irq's.
4768 * allow this - if not all of the IRQ's are returned, skip the
4769 * extra devices and just register the clock.
4770 */
4771 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4772 if (err < 0) {
4773 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4774 goto out;
4775 }
4776 bp->n_irqs = err;
4777 pci_set_master(pdev);
4778
4779 err = ptp_ocp_register_resources(bp, id->driver_data);
4780 if (err)
4781 goto out;
4782
4783 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4784 if (IS_ERR(bp->ptp)) {
4785 err = PTR_ERR(bp->ptp);
4786 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4787 bp->ptp = NULL;
4788 goto out;
4789 }
4790
4791 err = ptp_ocp_complete(bp);
4792 if (err)
4793 goto out;
4794
4795 ptp_ocp_info(bp);
4796 devlink_register(devlink);
4797
4798 clkid = pci_get_dsn(pdev);
4799 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
4800 if (IS_ERR(bp->dpll)) {
4801 err = PTR_ERR(bp->dpll);
4802 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4803 goto out;
4804 }
4805
4806 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4807 if (err)
4808 goto out;
4809
4810 for (i = 0; i < OCP_SMA_NUM; i++) {
4811 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
4812 if (IS_ERR(bp->sma[i].dpll_pin)) {
4813 err = PTR_ERR(bp->sma[i].dpll_pin);
4814 goto out_dpll;
4815 }
4816
4817 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4818 &bp->sma[i]);
4819 if (err) {
4820 dpll_pin_put(bp->sma[i].dpll_pin);
4821 goto out_dpll;
4822 }
4823 }
4824 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4825
4826 return 0;
4827 out_dpll:
4828 while (i) {
4829 --i;
4830 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4831 dpll_pin_put(bp->sma[i].dpll_pin);
4832 }
4833 dpll_device_put(bp->dpll);
4834 out:
4835 ptp_ocp_detach(bp);
4836 out_disable:
4837 pci_disable_device(pdev);
4838 out_free:
4839 devlink_free(devlink);
4840 return err;
4841 }
4842
4843 static void
ptp_ocp_remove(struct pci_dev * pdev)4844 ptp_ocp_remove(struct pci_dev *pdev)
4845 {
4846 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4847 struct devlink *devlink = priv_to_devlink(bp);
4848 int i;
4849
4850 cancel_delayed_work_sync(&bp->sync_work);
4851 for (i = 0; i < OCP_SMA_NUM; i++) {
4852 if (bp->sma[i].dpll_pin) {
4853 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4854 dpll_pin_put(bp->sma[i].dpll_pin);
4855 }
4856 }
4857 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4858 dpll_device_put(bp->dpll);
4859 devlink_unregister(devlink);
4860 ptp_ocp_detach(bp);
4861 pci_disable_device(pdev);
4862
4863 devlink_free(devlink);
4864 }
4865
4866 static struct pci_driver ptp_ocp_driver = {
4867 .name = KBUILD_MODNAME,
4868 .id_table = ptp_ocp_pcidev_id,
4869 .probe = ptp_ocp_probe,
4870 .remove = ptp_ocp_remove,
4871 };
4872
4873 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)4874 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4875 unsigned long action, void *data)
4876 {
4877 struct device *dev, *child = data;
4878 struct ptp_ocp *bp;
4879 bool add;
4880
4881 switch (action) {
4882 case BUS_NOTIFY_ADD_DEVICE:
4883 case BUS_NOTIFY_DEL_DEVICE:
4884 add = action == BUS_NOTIFY_ADD_DEVICE;
4885 break;
4886 default:
4887 return 0;
4888 }
4889
4890 if (!i2c_verify_adapter(child))
4891 return 0;
4892
4893 dev = child;
4894 while ((dev = dev->parent))
4895 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4896 goto found;
4897 return 0;
4898
4899 found:
4900 bp = dev_get_drvdata(dev);
4901 if (add)
4902 ptp_ocp_symlink(bp, child, "i2c");
4903 else
4904 sysfs_remove_link(&bp->dev.kobj, "i2c");
4905
4906 return 0;
4907 }
4908
4909 static struct notifier_block ptp_ocp_i2c_notifier = {
4910 .notifier_call = ptp_ocp_i2c_notifier_call,
4911 };
4912
4913 static int __init
ptp_ocp_init(void)4914 ptp_ocp_init(void)
4915 {
4916 const char *what;
4917 int err;
4918
4919 ptp_ocp_debugfs_init();
4920
4921 what = "timecard class";
4922 err = class_register(&timecard_class);
4923 if (err)
4924 goto out;
4925
4926 what = "i2c notifier";
4927 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4928 if (err)
4929 goto out_notifier;
4930
4931 what = "ptp_ocp driver";
4932 err = pci_register_driver(&ptp_ocp_driver);
4933 if (err)
4934 goto out_register;
4935
4936 return 0;
4937
4938 out_register:
4939 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4940 out_notifier:
4941 class_unregister(&timecard_class);
4942 out:
4943 ptp_ocp_debugfs_fini();
4944 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4945 return err;
4946 }
4947
4948 static void __exit
ptp_ocp_fini(void)4949 ptp_ocp_fini(void)
4950 {
4951 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4952 pci_unregister_driver(&ptp_ocp_driver);
4953 class_unregister(&timecard_class);
4954 ptp_ocp_debugfs_fini();
4955 }
4956
4957 module_init(ptp_ocp_init);
4958 module_exit(ptp_ocp_fini);
4959
4960 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4961 MODULE_LICENSE("GPL v2");
4962