1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * simple driver for PWM (Pulse Width Modulator) controller
4 *
5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
6 *
7 * Limitations:
8 * - When disabled the output is driven to 0 independent of the configured
9 * polarity.
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bitops.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/pwm.h>
23 #include <linux/slab.h>
24
25 #define MX3_PWMCR 0x00 /* PWM Control Register */
26 #define MX3_PWMSR 0x04 /* PWM Status Register */
27 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
28 #define MX3_PWMPR 0x10 /* PWM Period Register */
29 #define MX3_PWMCNR 0x14 /* PWM Counter Register */
30
31 #define MX3_PWMCR_FWM GENMASK(27, 26)
32 #define MX3_PWMCR_STOPEN BIT(25)
33 #define MX3_PWMCR_DOZEN BIT(24)
34 #define MX3_PWMCR_WAITEN BIT(23)
35 #define MX3_PWMCR_DBGEN BIT(22)
36 #define MX3_PWMCR_BCTR BIT(21)
37 #define MX3_PWMCR_HCTR BIT(20)
38
39 #define MX3_PWMCR_POUTC GENMASK(19, 18)
40 #define MX3_PWMCR_POUTC_NORMAL 0
41 #define MX3_PWMCR_POUTC_INVERTED 1
42 #define MX3_PWMCR_POUTC_OFF 2
43
44 #define MX3_PWMCR_CLKSRC GENMASK(17, 16)
45 #define MX3_PWMCR_CLKSRC_OFF 0
46 #define MX3_PWMCR_CLKSRC_IPG 1
47 #define MX3_PWMCR_CLKSRC_IPG_HIGH 2
48 #define MX3_PWMCR_CLKSRC_IPG_32K 3
49
50 #define MX3_PWMCR_PRESCALER GENMASK(15, 4)
51
52 #define MX3_PWMCR_SWR BIT(3)
53
54 #define MX3_PWMCR_REPEAT GENMASK(2, 1)
55 #define MX3_PWMCR_REPEAT_1X 0
56 #define MX3_PWMCR_REPEAT_2X 1
57 #define MX3_PWMCR_REPEAT_4X 2
58 #define MX3_PWMCR_REPEAT_8X 3
59
60 #define MX3_PWMCR_EN BIT(0)
61
62 #define MX3_PWMSR_FWE BIT(6)
63 #define MX3_PWMSR_CMP BIT(5)
64 #define MX3_PWMSR_ROV BIT(4)
65 #define MX3_PWMSR_FE BIT(3)
66
67 #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
68 #define MX3_PWMSR_FIFOAV_EMPTY 0
69 #define MX3_PWMSR_FIFOAV_1WORD 1
70 #define MX3_PWMSR_FIFOAV_2WORDS 2
71 #define MX3_PWMSR_FIFOAV_3WORDS 3
72 #define MX3_PWMSR_FIFOAV_4WORDS 4
73
74 #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
75 #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
76 (x)) + 1)
77
78 #define MX3_PWM_SWR_LOOP 5
79
80 /* PWMPR register value of 0xffff has the same effect as 0xfffe */
81 #define MX3_PWMPR_MAX 0xfffe
82
83 struct pwm_imx27_chip {
84 struct clk *clk_ipg;
85 struct clk *clk_per;
86 void __iomem *mmio_base;
87
88 /*
89 * The driver cannot read the current duty cycle from the hardware if
90 * the hardware is disabled. Cache the last programmed duty cycle
91 * value to return in that case.
92 */
93 unsigned int duty_cycle;
94 };
95
to_pwm_imx27_chip(struct pwm_chip * chip)96 static inline struct pwm_imx27_chip *to_pwm_imx27_chip(struct pwm_chip *chip)
97 {
98 return pwmchip_get_drvdata(chip);
99 }
100
pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip * imx)101 static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
102 {
103 int ret;
104
105 ret = clk_prepare_enable(imx->clk_ipg);
106 if (ret)
107 return ret;
108
109 ret = clk_prepare_enable(imx->clk_per);
110 if (ret) {
111 clk_disable_unprepare(imx->clk_ipg);
112 return ret;
113 }
114
115 return 0;
116 }
117
pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip * imx)118 static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
119 {
120 clk_disable_unprepare(imx->clk_per);
121 clk_disable_unprepare(imx->clk_ipg);
122 }
123
pwm_imx27_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)124 static int pwm_imx27_get_state(struct pwm_chip *chip,
125 struct pwm_device *pwm, struct pwm_state *state)
126 {
127 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
128 u32 period, prescaler, pwm_clk, val;
129 u64 tmp;
130 int ret;
131
132 ret = pwm_imx27_clk_prepare_enable(imx);
133 if (ret < 0)
134 return ret;
135
136 val = readl(imx->mmio_base + MX3_PWMCR);
137
138 if (val & MX3_PWMCR_EN)
139 state->enabled = true;
140 else
141 state->enabled = false;
142
143 switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
144 case MX3_PWMCR_POUTC_NORMAL:
145 state->polarity = PWM_POLARITY_NORMAL;
146 break;
147 case MX3_PWMCR_POUTC_INVERTED:
148 state->polarity = PWM_POLARITY_INVERSED;
149 break;
150 default:
151 dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected");
152 }
153
154 prescaler = MX3_PWMCR_PRESCALER_GET(val);
155 pwm_clk = clk_get_rate(imx->clk_per);
156 val = readl(imx->mmio_base + MX3_PWMPR);
157 period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
158
159 /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
160 tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
161 state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
162
163 /*
164 * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
165 * use the cached value.
166 */
167 if (state->enabled)
168 val = readl(imx->mmio_base + MX3_PWMSAR);
169 else
170 val = imx->duty_cycle;
171
172 tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
173 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
174
175 pwm_imx27_clk_disable_unprepare(imx);
176
177 return 0;
178 }
179
pwm_imx27_sw_reset(struct pwm_chip * chip)180 static void pwm_imx27_sw_reset(struct pwm_chip *chip)
181 {
182 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
183 struct device *dev = pwmchip_parent(chip);
184 int wait_count = 0;
185 u32 cr;
186
187 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
188 do {
189 usleep_range(200, 1000);
190 cr = readl(imx->mmio_base + MX3_PWMCR);
191 } while ((cr & MX3_PWMCR_SWR) &&
192 (wait_count++ < MX3_PWM_SWR_LOOP));
193
194 if (cr & MX3_PWMCR_SWR)
195 dev_warn(dev, "software reset timeout\n");
196 }
197
pwm_imx27_wait_fifo_slot(struct pwm_chip * chip,struct pwm_device * pwm)198 static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
199 struct pwm_device *pwm)
200 {
201 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
202 struct device *dev = pwmchip_parent(chip);
203 unsigned int period_ms;
204 int fifoav;
205 u32 sr;
206
207 sr = readl(imx->mmio_base + MX3_PWMSR);
208 fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
209 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
210 period_ms = DIV_ROUND_UP_ULL(pwm->state.period,
211 NSEC_PER_MSEC);
212 msleep(period_ms);
213
214 sr = readl(imx->mmio_base + MX3_PWMSR);
215 if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
216 dev_warn(dev, "there is no free FIFO slot\n");
217 }
218 }
219
pwm_imx27_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)220 static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
221 const struct pwm_state *state)
222 {
223 unsigned long period_cycles, duty_cycles, prescale, period_us, tmp;
224 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
225 unsigned long long c;
226 unsigned long long clkrate;
227 unsigned long flags;
228 int val;
229 int ret;
230 u32 cr;
231
232 clkrate = clk_get_rate(imx->clk_per);
233 c = clkrate * state->period;
234
235 do_div(c, NSEC_PER_SEC);
236 period_cycles = c;
237
238 prescale = period_cycles / 0x10000 + 1;
239
240 period_cycles /= prescale;
241 c = clkrate * state->duty_cycle;
242 do_div(c, NSEC_PER_SEC);
243 duty_cycles = c;
244 duty_cycles /= prescale;
245
246 /*
247 * according to imx pwm RM, the real period value should be PERIOD
248 * value in PWMPR plus 2.
249 */
250 if (period_cycles > 2)
251 period_cycles -= 2;
252 else
253 period_cycles = 0;
254
255 /*
256 * Wait for a free FIFO slot if the PWM is already enabled, and flush
257 * the FIFO if the PWM was disabled and is about to be enabled.
258 */
259 if (pwm->state.enabled) {
260 pwm_imx27_wait_fifo_slot(chip, pwm);
261 } else {
262 ret = pwm_imx27_clk_prepare_enable(imx);
263 if (ret)
264 return ret;
265
266 pwm_imx27_sw_reset(chip);
267 }
268
269 val = readl(imx->mmio_base + MX3_PWMPR);
270 val = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
271 cr = readl(imx->mmio_base + MX3_PWMCR);
272 tmp = NSEC_PER_SEC * (u64)(val + 2) * MX3_PWMCR_PRESCALER_GET(cr);
273 tmp = DIV_ROUND_UP_ULL(tmp, clkrate);
274 period_us = DIV_ROUND_UP_ULL(tmp, 1000);
275
276 /*
277 * ERR051198:
278 * PWM: PWM output may not function correctly if the FIFO is empty when
279 * a new SAR value is programmed
280 *
281 * Description:
282 * When the PWM FIFO is empty, a new value programmed to the PWM Sample
283 * register (PWM_PWMSAR) will be directly applied even if the current
284 * timer period has not expired.
285 *
286 * If the new SAMPLE value programmed in the PWM_PWMSAR register is
287 * less than the previous value, and the PWM counter register
288 * (PWM_PWMCNR) that contains the current COUNT value is greater than
289 * the new programmed SAMPLE value, the current period will not flip
290 * the level. This may result in an output pulse with a duty cycle of
291 * 100%.
292 *
293 * Consider a change from
294 * ________
295 * / \______/
296 * ^ * ^
297 * to
298 * ____
299 * / \__________/
300 * ^ ^
301 * At the time marked by *, the new write value will be directly applied
302 * to SAR even the current period is not over if FIFO is empty.
303 *
304 * ________ ____________________
305 * / \______/ \__________/
306 * ^ ^ * ^ ^
307 * |<-- old SAR -->| |<-- new SAR -->|
308 *
309 * That is the output is active for a whole period.
310 *
311 * Workaround:
312 * Check new SAR less than old SAR and current counter is in errata
313 * windows, write extra old SAR into FIFO and new SAR will effect at
314 * next period.
315 *
316 * Sometime period is quite long, such as over 1 second. If add old SAR
317 * into FIFO unconditional, new SAR have to wait for next period. It
318 * may be too long.
319 *
320 * Turn off the interrupt to ensure that not IRQ and schedule happen
321 * during above operations. If any irq and schedule happen, counter
322 * in PWM will be out of data and take wrong action.
323 *
324 * Add a safety margin 1.5us because it needs some time to complete
325 * IO write.
326 *
327 * Use writel_relaxed() to minimize the interval between two writes to
328 * the SAR register to increase the fastest PWM frequency supported.
329 *
330 * When the PWM period is longer than 2us(or <500kHz), this workaround
331 * can solve this problem. No software workaround is available if PWM
332 * period is shorter than IO write. Just try best to fill old data
333 * into FIFO.
334 */
335 c = clkrate * 1500;
336 do_div(c, NSEC_PER_SEC);
337
338 local_irq_save(flags);
339 val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR));
340
341 if (duty_cycles < imx->duty_cycle && (cr & MX3_PWMCR_EN)) {
342 if (period_us < 2) { /* 2us = 500 kHz */
343 /* Best effort attempt to fix up >500 kHz case */
344 udelay(3 * period_us);
345 writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
346 writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
347 } else if (val < MX3_PWMSR_FIFOAV_2WORDS) {
348 val = readl_relaxed(imx->mmio_base + MX3_PWMCNR);
349 /*
350 * If counter is close to period, controller may roll over when
351 * next IO write.
352 */
353 if ((val + c >= duty_cycles && val < imx->duty_cycle) ||
354 val + c >= period_cycles)
355 writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
356 }
357 }
358 writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR);
359 local_irq_restore(flags);
360
361 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
362
363 /*
364 * Store the duty cycle for future reference in cases where the
365 * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
366 */
367 imx->duty_cycle = duty_cycles;
368
369 cr = MX3_PWMCR_PRESCALER_SET(prescale) |
370 MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
371 FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
372 MX3_PWMCR_DBGEN;
373
374 if (state->polarity == PWM_POLARITY_INVERSED)
375 cr |= FIELD_PREP(MX3_PWMCR_POUTC,
376 MX3_PWMCR_POUTC_INVERTED);
377
378 if (state->enabled)
379 cr |= MX3_PWMCR_EN;
380
381 writel(cr, imx->mmio_base + MX3_PWMCR);
382
383 if (!state->enabled)
384 pwm_imx27_clk_disable_unprepare(imx);
385
386 return 0;
387 }
388
389 static const struct pwm_ops pwm_imx27_ops = {
390 .apply = pwm_imx27_apply,
391 .get_state = pwm_imx27_get_state,
392 };
393
394 static const struct of_device_id pwm_imx27_dt_ids[] = {
395 { .compatible = "fsl,imx27-pwm", },
396 { /* sentinel */ }
397 };
398 MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
399
pwm_imx27_probe(struct platform_device * pdev)400 static int pwm_imx27_probe(struct platform_device *pdev)
401 {
402 struct pwm_chip *chip;
403 struct pwm_imx27_chip *imx;
404 int ret;
405 u32 pwmcr;
406
407 chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx));
408 if (IS_ERR(chip))
409 return PTR_ERR(chip);
410 imx = to_pwm_imx27_chip(chip);
411
412 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
413 if (IS_ERR(imx->clk_ipg))
414 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
415 "getting ipg clock failed\n");
416
417 imx->clk_per = devm_clk_get(&pdev->dev, "per");
418 if (IS_ERR(imx->clk_per))
419 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
420 "failed to get peripheral clock\n");
421
422 chip->ops = &pwm_imx27_ops;
423
424 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
425 if (IS_ERR(imx->mmio_base))
426 return PTR_ERR(imx->mmio_base);
427
428 ret = pwm_imx27_clk_prepare_enable(imx);
429 if (ret)
430 return ret;
431
432 /* keep clks on if pwm is running */
433 pwmcr = readl(imx->mmio_base + MX3_PWMCR);
434 if (!(pwmcr & MX3_PWMCR_EN))
435 pwm_imx27_clk_disable_unprepare(imx);
436
437 return devm_pwmchip_add(&pdev->dev, chip);
438 }
439
440 static struct platform_driver imx_pwm_driver = {
441 .driver = {
442 .name = "pwm-imx27",
443 .of_match_table = pwm_imx27_dt_ids,
444 },
445 .probe = pwm_imx27_probe,
446 };
447 module_platform_driver(imx_pwm_driver);
448
449 MODULE_DESCRIPTION("i.MX27 and later i.MX SoCs Pulse Width Modulator driver");
450 MODULE_LICENSE("GPL v2");
451 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
452