1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek Pulse Width Modulator driver
4 *
5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
7 *
8 */
9
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/ioport.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21
22 /* PWM registers and bits definitions */
23 #define PWMCON 0x00
24 #define PWMHDUR 0x04
25 #define PWMLDUR 0x08
26 #define PWMGDUR 0x0c
27 #define PWMWAVENUM 0x28
28 #define PWMDWIDTH 0x2c
29 #define PWM45DWIDTH_FIXUP 0x30
30 #define PWMTHRES 0x30
31 #define PWM45THRES_FIXUP 0x34
32 #define PWM_CK_26M_SEL 0x210
33
34 #define PWM_CLK_DIV_MAX 7
35
36 struct pwm_mediatek_of_data {
37 unsigned int num_pwms;
38 bool pwm45_fixup;
39 bool has_ck_26m_sel;
40 const unsigned int *reg_offset;
41 };
42
43 /**
44 * struct pwm_mediatek_chip - struct representing PWM chip
45 * @regs: base address of PWM chip
46 * @clk_top: the top clock generator
47 * @clk_main: the clock used by PWM core
48 * @clk_pwms: the clock used by each PWM channel
49 * @soc: pointer to chip's platform data
50 */
51 struct pwm_mediatek_chip {
52 void __iomem *regs;
53 struct clk *clk_top;
54 struct clk *clk_main;
55 struct clk **clk_pwms;
56 const struct pwm_mediatek_of_data *soc;
57 };
58
59 static const unsigned int mtk_pwm_reg_offset_v1[] = {
60 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
61 };
62
63 static const unsigned int mtk_pwm_reg_offset_v2[] = {
64 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
65 };
66
67 static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip * chip)68 to_pwm_mediatek_chip(struct pwm_chip *chip)
69 {
70 return pwmchip_get_drvdata(chip);
71 }
72
pwm_mediatek_clk_enable(struct pwm_chip * chip,struct pwm_device * pwm)73 static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
74 struct pwm_device *pwm)
75 {
76 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
77 int ret;
78
79 ret = clk_prepare_enable(pc->clk_top);
80 if (ret < 0)
81 return ret;
82
83 ret = clk_prepare_enable(pc->clk_main);
84 if (ret < 0)
85 goto disable_clk_top;
86
87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
88 if (ret < 0)
89 goto disable_clk_main;
90
91 return 0;
92
93 disable_clk_main:
94 clk_disable_unprepare(pc->clk_main);
95 disable_clk_top:
96 clk_disable_unprepare(pc->clk_top);
97
98 return ret;
99 }
100
pwm_mediatek_clk_disable(struct pwm_chip * chip,struct pwm_device * pwm)101 static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
102 struct pwm_device *pwm)
103 {
104 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
105
106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
107 clk_disable_unprepare(pc->clk_main);
108 clk_disable_unprepare(pc->clk_top);
109 }
110
pwm_mediatek_writel(struct pwm_mediatek_chip * chip,unsigned int num,unsigned int offset,u32 value)111 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
112 unsigned int num, unsigned int offset,
113 u32 value)
114 {
115 writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
116 }
117
pwm_mediatek_enable(struct pwm_chip * chip,struct pwm_device * pwm)118 static void pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
119 {
120 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
121 u32 value;
122
123 value = readl(pc->regs);
124 value |= BIT(pwm->hwpwm);
125 writel(value, pc->regs);
126 }
127
pwm_mediatek_disable(struct pwm_chip * chip,struct pwm_device * pwm)128 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
129 {
130 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
131 u32 value;
132
133 value = readl(pc->regs);
134 value &= ~BIT(pwm->hwpwm);
135 writel(value, pc->regs);
136 }
137
pwm_mediatek_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)138 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
139 int duty_ns, int period_ns)
140 {
141 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
142 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
143 reg_thres = PWMTHRES;
144 unsigned long clk_rate;
145 u64 resolution;
146 int ret;
147
148 ret = pwm_mediatek_clk_enable(chip, pwm);
149 if (ret < 0)
150 return ret;
151
152 clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
153 if (!clk_rate) {
154 ret = -EINVAL;
155 goto out;
156 }
157
158 /* Make sure we use the bus clock and not the 26MHz clock */
159 if (pc->soc->has_ck_26m_sel)
160 writel(0, pc->regs + PWM_CK_26M_SEL);
161
162 /* Using resolution in picosecond gets accuracy higher */
163 resolution = (u64)NSEC_PER_SEC * 1000;
164 do_div(resolution, clk_rate);
165
166 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
167 if (!cnt_period)
168 return -EINVAL;
169
170 while (cnt_period > 8192) {
171 resolution *= 2;
172 clkdiv++;
173 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
174 resolution);
175 }
176
177 if (clkdiv > PWM_CLK_DIV_MAX) {
178 dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
179 ret = -EINVAL;
180 goto out;
181 }
182
183 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
184 /*
185 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
186 * from the other PWMs on MT7623.
187 */
188 reg_width = PWM45DWIDTH_FIXUP;
189 reg_thres = PWM45THRES_FIXUP;
190 }
191
192 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
193
194 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
195 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
196
197 if (cnt_duty) {
198 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty - 1);
199 pwm_mediatek_enable(chip, pwm);
200 } else {
201 pwm_mediatek_disable(chip, pwm);
202 }
203
204 out:
205 pwm_mediatek_clk_disable(chip, pwm);
206
207 return ret;
208 }
209
pwm_mediatek_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)210 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
211 const struct pwm_state *state)
212 {
213 int err;
214
215 if (state->polarity != PWM_POLARITY_NORMAL)
216 return -EINVAL;
217
218 if (!state->enabled) {
219 if (pwm->state.enabled) {
220 pwm_mediatek_disable(chip, pwm);
221 pwm_mediatek_clk_disable(chip, pwm);
222 }
223
224 return 0;
225 }
226
227 err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period);
228 if (err)
229 return err;
230
231 if (!pwm->state.enabled)
232 err = pwm_mediatek_clk_enable(chip, pwm);
233
234 return err;
235 }
236
237 static const struct pwm_ops pwm_mediatek_ops = {
238 .apply = pwm_mediatek_apply,
239 };
240
pwm_mediatek_probe(struct platform_device * pdev)241 static int pwm_mediatek_probe(struct platform_device *pdev)
242 {
243 struct pwm_chip *chip;
244 struct pwm_mediatek_chip *pc;
245 const struct pwm_mediatek_of_data *soc;
246 unsigned int i;
247 int ret;
248
249 soc = of_device_get_match_data(&pdev->dev);
250
251 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
252 if (IS_ERR(chip))
253 return PTR_ERR(chip);
254 pc = to_pwm_mediatek_chip(chip);
255
256 pc->soc = soc;
257
258 pc->regs = devm_platform_ioremap_resource(pdev, 0);
259 if (IS_ERR(pc->regs))
260 return PTR_ERR(pc->regs);
261
262 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
263 sizeof(*pc->clk_pwms), GFP_KERNEL);
264 if (!pc->clk_pwms)
265 return -ENOMEM;
266
267 pc->clk_top = devm_clk_get(&pdev->dev, "top");
268 if (IS_ERR(pc->clk_top))
269 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
270 "Failed to get top clock\n");
271
272 pc->clk_main = devm_clk_get(&pdev->dev, "main");
273 if (IS_ERR(pc->clk_main))
274 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
275 "Failed to get main clock\n");
276
277 for (i = 0; i < soc->num_pwms; i++) {
278 char name[8];
279
280 snprintf(name, sizeof(name), "pwm%d", i + 1);
281
282 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
283 if (IS_ERR(pc->clk_pwms[i]))
284 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
285 "Failed to get %s clock\n", name);
286 }
287
288 chip->ops = &pwm_mediatek_ops;
289
290 ret = devm_pwmchip_add(&pdev->dev, chip);
291 if (ret < 0)
292 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
293
294 return 0;
295 }
296
297 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
298 .num_pwms = 8,
299 .pwm45_fixup = false,
300 .has_ck_26m_sel = false,
301 .reg_offset = mtk_pwm_reg_offset_v1,
302 };
303
304 static const struct pwm_mediatek_of_data mt6795_pwm_data = {
305 .num_pwms = 7,
306 .pwm45_fixup = false,
307 .has_ck_26m_sel = false,
308 .reg_offset = mtk_pwm_reg_offset_v1,
309 };
310
311 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
312 .num_pwms = 6,
313 .pwm45_fixup = false,
314 .has_ck_26m_sel = true,
315 .reg_offset = mtk_pwm_reg_offset_v1,
316 };
317
318 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
319 .num_pwms = 5,
320 .pwm45_fixup = true,
321 .has_ck_26m_sel = false,
322 .reg_offset = mtk_pwm_reg_offset_v1,
323 };
324
325 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
326 .num_pwms = 4,
327 .pwm45_fixup = true,
328 .has_ck_26m_sel = false,
329 .reg_offset = mtk_pwm_reg_offset_v1,
330 };
331
332 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
333 .num_pwms = 1,
334 .pwm45_fixup = false,
335 .has_ck_26m_sel = false,
336 .reg_offset = mtk_pwm_reg_offset_v1,
337 };
338
339 static const struct pwm_mediatek_of_data mt7981_pwm_data = {
340 .num_pwms = 3,
341 .pwm45_fixup = false,
342 .has_ck_26m_sel = true,
343 .reg_offset = mtk_pwm_reg_offset_v2,
344 };
345
346 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
347 .num_pwms = 2,
348 .pwm45_fixup = false,
349 .has_ck_26m_sel = true,
350 .reg_offset = mtk_pwm_reg_offset_v1,
351 };
352
353 static const struct pwm_mediatek_of_data mt7988_pwm_data = {
354 .num_pwms = 8,
355 .pwm45_fixup = false,
356 .has_ck_26m_sel = false,
357 .reg_offset = mtk_pwm_reg_offset_v2,
358 };
359
360 static const struct pwm_mediatek_of_data mt8183_pwm_data = {
361 .num_pwms = 4,
362 .pwm45_fixup = false,
363 .has_ck_26m_sel = true,
364 .reg_offset = mtk_pwm_reg_offset_v1,
365 };
366
367 static const struct pwm_mediatek_of_data mt8365_pwm_data = {
368 .num_pwms = 3,
369 .pwm45_fixup = false,
370 .has_ck_26m_sel = true,
371 .reg_offset = mtk_pwm_reg_offset_v1,
372 };
373
374 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
375 .num_pwms = 5,
376 .pwm45_fixup = false,
377 .has_ck_26m_sel = true,
378 .reg_offset = mtk_pwm_reg_offset_v1,
379 };
380
381 static const struct of_device_id pwm_mediatek_of_match[] = {
382 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
383 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
384 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
385 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
386 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
387 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
388 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
389 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
390 { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
391 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
392 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
393 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
394 { },
395 };
396 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
397
398 static struct platform_driver pwm_mediatek_driver = {
399 .driver = {
400 .name = "pwm-mediatek",
401 .of_match_table = pwm_mediatek_of_match,
402 },
403 .probe = pwm_mediatek_probe,
404 };
405 module_platform_driver(pwm_mediatek_driver);
406
407 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
408 MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver");
409 MODULE_LICENSE("GPL v2");
410