1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI K3 R5F (MCU) Remote Processor driver
4 *
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/mailbox_client.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/of_platform.h>
19 #include <linux/omap-mailbox.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/remoteproc.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25
26 #include "omap_remoteproc.h"
27 #include "remoteproc_internal.h"
28 #include "ti_sci_proc.h"
29
30 /* This address can either be for ATCM or BTCM with the other at address 0x0 */
31 #define K3_R5_TCM_DEV_ADDR 0x41010000
32
33 /* R5 TI-SCI Processor Configuration Flags */
34 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
35 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
36 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
37 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
38 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
39 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
40 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
41 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
42 /* Available from J7200 SoCs onwards */
43 #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
44 /* Applicable to only AM64x SoCs */
45 #define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000
46
47 /* R5 TI-SCI Processor Control Flags */
48 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
49
50 /* R5 TI-SCI Processor Status Flags */
51 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
52 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
53 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
54 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
55 /* Applicable to only AM64x SoCs */
56 #define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x00000200
57
58 /**
59 * struct k3_r5_mem - internal memory structure
60 * @cpu_addr: MPU virtual address of the memory region
61 * @bus_addr: Bus address used to access the memory region
62 * @dev_addr: Device address from remoteproc view
63 * @size: Size of the memory region
64 */
65 struct k3_r5_mem {
66 void __iomem *cpu_addr;
67 phys_addr_t bus_addr;
68 u32 dev_addr;
69 size_t size;
70 };
71
72 /*
73 * All cluster mode values are not applicable on all SoCs. The following
74 * are the modes supported on various SoCs:
75 * Split mode : AM65x, J721E, J7200 and AM64x SoCs
76 * LockStep mode : AM65x, J721E and J7200 SoCs
77 * Single-CPU mode : AM64x SoCs only
78 * Single-Core mode : AM62x, AM62A SoCs
79 */
80 enum cluster_mode {
81 CLUSTER_MODE_SPLIT = 0,
82 CLUSTER_MODE_LOCKSTEP,
83 CLUSTER_MODE_SINGLECPU,
84 CLUSTER_MODE_SINGLECORE
85 };
86
87 /**
88 * struct k3_r5_soc_data - match data to handle SoC variations
89 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
90 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
91 * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode
92 * @is_single_core: flag to denote if SoC/IP has only single core R5
93 */
94 struct k3_r5_soc_data {
95 bool tcm_is_double;
96 bool tcm_ecc_autoinit;
97 bool single_cpu_mode;
98 bool is_single_core;
99 };
100
101 /**
102 * struct k3_r5_cluster - K3 R5F Cluster structure
103 * @dev: cached device pointer
104 * @mode: Mode to configure the Cluster - Split or LockStep
105 * @cores: list of R5 cores within the cluster
106 * @core_transition: wait queue to sync core state changes
107 * @soc_data: SoC-specific feature data for a R5FSS
108 */
109 struct k3_r5_cluster {
110 struct device *dev;
111 enum cluster_mode mode;
112 struct list_head cores;
113 wait_queue_head_t core_transition;
114 const struct k3_r5_soc_data *soc_data;
115 };
116
117 /**
118 * struct k3_r5_core - K3 R5 core structure
119 * @elem: linked list item
120 * @dev: cached device pointer
121 * @rproc: rproc handle representing this core
122 * @mem: internal memory regions data
123 * @sram: on-chip SRAM memory regions data
124 * @num_mems: number of internal memory regions
125 * @num_sram: number of on-chip SRAM memory regions
126 * @reset: reset control handle
127 * @tsp: TI-SCI processor control handle
128 * @ti_sci: TI-SCI handle
129 * @ti_sci_id: TI-SCI device identifier
130 * @atcm_enable: flag to control ATCM enablement
131 * @btcm_enable: flag to control BTCM enablement
132 * @loczrama: flag to dictate which TCM is at device address 0x0
133 * @released_from_reset: flag to signal when core is out of reset
134 */
135 struct k3_r5_core {
136 struct list_head elem;
137 struct device *dev;
138 struct rproc *rproc;
139 struct k3_r5_mem *mem;
140 struct k3_r5_mem *sram;
141 int num_mems;
142 int num_sram;
143 struct reset_control *reset;
144 struct ti_sci_proc *tsp;
145 const struct ti_sci_handle *ti_sci;
146 u32 ti_sci_id;
147 u32 atcm_enable;
148 u32 btcm_enable;
149 u32 loczrama;
150 bool released_from_reset;
151 };
152
153 /**
154 * struct k3_r5_rproc - K3 remote processor state
155 * @dev: cached device pointer
156 * @cluster: cached pointer to parent cluster structure
157 * @mbox: mailbox channel handle
158 * @client: mailbox client to request the mailbox channel
159 * @rproc: rproc handle
160 * @core: cached pointer to r5 core structure being used
161 * @rmem: reserved memory regions data
162 * @num_rmems: number of reserved memory regions
163 */
164 struct k3_r5_rproc {
165 struct device *dev;
166 struct k3_r5_cluster *cluster;
167 struct mbox_chan *mbox;
168 struct mbox_client client;
169 struct rproc *rproc;
170 struct k3_r5_core *core;
171 struct k3_r5_mem *rmem;
172 int num_rmems;
173 };
174
175 /**
176 * k3_r5_rproc_mbox_callback() - inbound mailbox message handler
177 * @client: mailbox client pointer used for requesting the mailbox channel
178 * @data: mailbox payload
179 *
180 * This handler is invoked by the OMAP mailbox driver whenever a mailbox
181 * message is received. Usually, the mailbox payload simply contains
182 * the index of the virtqueue that is kicked by the remote processor,
183 * and we let remoteproc core handle it.
184 *
185 * In addition to virtqueue indices, we also have some out-of-band values
186 * that indicate different events. Those values are deliberately very
187 * large so they don't coincide with virtqueue indices.
188 */
k3_r5_rproc_mbox_callback(struct mbox_client * client,void * data)189 static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data)
190 {
191 struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc,
192 client);
193 struct device *dev = kproc->rproc->dev.parent;
194 const char *name = kproc->rproc->name;
195 u32 msg = omap_mbox_message(data);
196
197 dev_dbg(dev, "mbox msg: 0x%x\n", msg);
198
199 switch (msg) {
200 case RP_MBOX_CRASH:
201 /*
202 * remoteproc detected an exception, but error recovery is not
203 * supported. So, just log this for now
204 */
205 dev_err(dev, "K3 R5F rproc %s crashed\n", name);
206 break;
207 case RP_MBOX_ECHO_REPLY:
208 dev_info(dev, "received echo reply from %s\n", name);
209 break;
210 default:
211 /* silently handle all other valid messages */
212 if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG)
213 return;
214 if (msg > kproc->rproc->max_notifyid) {
215 dev_dbg(dev, "dropping unknown message 0x%x", msg);
216 return;
217 }
218 /* msg contains the index of the triggered vring */
219 if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE)
220 dev_dbg(dev, "no message was found in vqid %d\n", msg);
221 }
222 }
223
224 /* kick a virtqueue */
k3_r5_rproc_kick(struct rproc * rproc,int vqid)225 static void k3_r5_rproc_kick(struct rproc *rproc, int vqid)
226 {
227 struct k3_r5_rproc *kproc = rproc->priv;
228 struct device *dev = rproc->dev.parent;
229 mbox_msg_t msg = (mbox_msg_t)vqid;
230 int ret;
231
232 /* send the index of the triggered virtqueue in the mailbox payload */
233 ret = mbox_send_message(kproc->mbox, (void *)msg);
234 if (ret < 0)
235 dev_err(dev, "failed to send mailbox message, status = %d\n",
236 ret);
237 }
238
k3_r5_split_reset(struct k3_r5_core * core)239 static int k3_r5_split_reset(struct k3_r5_core *core)
240 {
241 int ret;
242
243 ret = reset_control_assert(core->reset);
244 if (ret) {
245 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
246 ret);
247 return ret;
248 }
249
250 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
251 core->ti_sci_id);
252 if (ret) {
253 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
254 ret);
255 if (reset_control_deassert(core->reset))
256 dev_warn(core->dev, "local-reset deassert back failed\n");
257 }
258
259 return ret;
260 }
261
k3_r5_split_release(struct k3_r5_core * core)262 static int k3_r5_split_release(struct k3_r5_core *core)
263 {
264 int ret;
265
266 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
267 core->ti_sci_id);
268 if (ret) {
269 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
270 ret);
271 return ret;
272 }
273
274 ret = reset_control_deassert(core->reset);
275 if (ret) {
276 dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
277 ret);
278 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
279 core->ti_sci_id))
280 dev_warn(core->dev, "module-reset assert back failed\n");
281 }
282
283 return ret;
284 }
285
k3_r5_lockstep_reset(struct k3_r5_cluster * cluster)286 static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)
287 {
288 struct k3_r5_core *core;
289 int ret;
290
291 /* assert local reset on all applicable cores */
292 list_for_each_entry(core, &cluster->cores, elem) {
293 ret = reset_control_assert(core->reset);
294 if (ret) {
295 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
296 ret);
297 core = list_prev_entry(core, elem);
298 goto unroll_local_reset;
299 }
300 }
301
302 /* disable PSC modules on all applicable cores */
303 list_for_each_entry(core, &cluster->cores, elem) {
304 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
305 core->ti_sci_id);
306 if (ret) {
307 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
308 ret);
309 goto unroll_module_reset;
310 }
311 }
312
313 return 0;
314
315 unroll_module_reset:
316 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {
317 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
318 core->ti_sci_id))
319 dev_warn(core->dev, "module-reset assert back failed\n");
320 }
321 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
322 unroll_local_reset:
323 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
324 if (reset_control_deassert(core->reset))
325 dev_warn(core->dev, "local-reset deassert back failed\n");
326 }
327
328 return ret;
329 }
330
k3_r5_lockstep_release(struct k3_r5_cluster * cluster)331 static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)
332 {
333 struct k3_r5_core *core;
334 int ret;
335
336 /* enable PSC modules on all applicable cores */
337 list_for_each_entry_reverse(core, &cluster->cores, elem) {
338 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,
339 core->ti_sci_id);
340 if (ret) {
341 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
342 ret);
343 core = list_next_entry(core, elem);
344 goto unroll_module_reset;
345 }
346 }
347
348 /* deassert local reset on all applicable cores */
349 list_for_each_entry_reverse(core, &cluster->cores, elem) {
350 ret = reset_control_deassert(core->reset);
351 if (ret) {
352 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
353 ret);
354 goto unroll_local_reset;
355 }
356 }
357
358 return 0;
359
360 unroll_local_reset:
361 list_for_each_entry_continue(core, &cluster->cores, elem) {
362 if (reset_control_assert(core->reset))
363 dev_warn(core->dev, "local-reset assert back failed\n");
364 }
365 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
366 unroll_module_reset:
367 list_for_each_entry_from(core, &cluster->cores, elem) {
368 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,
369 core->ti_sci_id))
370 dev_warn(core->dev, "module-reset assert back failed\n");
371 }
372
373 return ret;
374 }
375
k3_r5_core_halt(struct k3_r5_core * core)376 static inline int k3_r5_core_halt(struct k3_r5_core *core)
377 {
378 return ti_sci_proc_set_control(core->tsp,
379 PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
380 }
381
k3_r5_core_run(struct k3_r5_core * core)382 static inline int k3_r5_core_run(struct k3_r5_core *core)
383 {
384 return ti_sci_proc_set_control(core->tsp,
385 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
386 }
387
k3_r5_rproc_request_mbox(struct rproc * rproc)388 static int k3_r5_rproc_request_mbox(struct rproc *rproc)
389 {
390 struct k3_r5_rproc *kproc = rproc->priv;
391 struct mbox_client *client = &kproc->client;
392 struct device *dev = kproc->dev;
393 int ret;
394
395 client->dev = dev;
396 client->tx_done = NULL;
397 client->rx_callback = k3_r5_rproc_mbox_callback;
398 client->tx_block = false;
399 client->knows_txdone = false;
400
401 kproc->mbox = mbox_request_channel(client, 0);
402 if (IS_ERR(kproc->mbox))
403 return dev_err_probe(dev, PTR_ERR(kproc->mbox),
404 "mbox_request_channel failed\n");
405
406 /*
407 * Ping the remote processor, this is only for sanity-sake for now;
408 * there is no functional effect whatsoever.
409 *
410 * Note that the reply will _not_ arrive immediately: this message
411 * will wait in the mailbox fifo until the remote processor is booted.
412 */
413 ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST);
414 if (ret < 0) {
415 dev_err(dev, "mbox_send_message failed: %d\n", ret);
416 mbox_free_channel(kproc->mbox);
417 return ret;
418 }
419
420 return 0;
421 }
422
423 /*
424 * The R5F cores have controls for both a reset and a halt/run. The code
425 * execution from DDR requires the initial boot-strapping code to be run
426 * from the internal TCMs. This function is used to release the resets on
427 * applicable cores to allow loading into the TCMs. The .prepare() ops is
428 * invoked by remoteproc core before any firmware loading, and is followed
429 * by the .start() ops after loading to actually let the R5 cores run.
430 *
431 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
432 * execute code, but combines the TCMs from both cores. The resets for both
433 * cores need to be released to make this possible, as the TCMs are in general
434 * private to each core. Only Core0 needs to be unhalted for running the
435 * cluster in this mode. The function uses the same reset logic as LockStep
436 * mode for this (though the behavior is agnostic of the reset release order).
437 * This callback is invoked only in remoteproc mode.
438 */
k3_r5_rproc_prepare(struct rproc * rproc)439 static int k3_r5_rproc_prepare(struct rproc *rproc)
440 {
441 struct k3_r5_rproc *kproc = rproc->priv;
442 struct k3_r5_cluster *cluster = kproc->cluster;
443 struct k3_r5_core *core = kproc->core, *core0, *core1;
444 struct device *dev = kproc->dev;
445 u32 ctrl = 0, cfg = 0, stat = 0;
446 u64 boot_vec = 0;
447 bool mem_init_dis;
448 int ret;
449
450 /*
451 * R5 cores require to be powered on sequentially, core0 should be in
452 * higher power state than core1 in a cluster. So, wait for core0 to
453 * power up before proceeding to core1 and put timeout of 2sec. This
454 * waiting mechanism is necessary because rproc_auto_boot_callback() for
455 * core1 can be called before core0 due to thread execution order.
456 *
457 * By placing the wait mechanism here in .prepare() ops, this condition
458 * is enforced for rproc boot requests from sysfs as well.
459 */
460 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
461 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
462 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1 &&
463 !core0->released_from_reset) {
464 ret = wait_event_interruptible_timeout(cluster->core_transition,
465 core0->released_from_reset,
466 msecs_to_jiffies(2000));
467 if (ret <= 0) {
468 dev_err(dev, "can not power up core1 before core0");
469 return -EPERM;
470 }
471 }
472
473 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat);
474 if (ret < 0)
475 return ret;
476 mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
477
478 /* Re-use LockStep-mode reset logic for Single-CPU mode */
479 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
480 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
481 k3_r5_lockstep_release(cluster) : k3_r5_split_release(core);
482 if (ret) {
483 dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",
484 ret);
485 return ret;
486 }
487
488 /*
489 * Notify all threads in the wait queue when core0 state has changed so
490 * that threads waiting for this condition can be executed.
491 */
492 core->released_from_reset = true;
493 if (core == core0)
494 wake_up_interruptible(&cluster->core_transition);
495
496 /*
497 * Newer IP revisions like on J7200 SoCs support h/w auto-initialization
498 * of TCMs, so there is no need to perform the s/w memzero. This bit is
499 * configurable through System Firmware, the default value does perform
500 * auto-init, but account for it in case it is disabled
501 */
502 if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) {
503 dev_dbg(dev, "leveraging h/w init for TCM memories\n");
504 return 0;
505 }
506
507 /*
508 * Zero out both TCMs unconditionally (access from v8 Arm core is not
509 * affected by ATCM & BTCM enable configuration values) so that ECC
510 * can be effective on all TCM addresses.
511 */
512 dev_dbg(dev, "zeroing out ATCM memory\n");
513 memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
514
515 dev_dbg(dev, "zeroing out BTCM memory\n");
516 memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
517
518 return 0;
519 }
520
521 /*
522 * This function implements the .unprepare() ops and performs the complimentary
523 * operations to that of the .prepare() ops. The function is used to assert the
524 * resets on all applicable cores for the rproc device (depending on LockStep
525 * or Split mode). This completes the second portion of powering down the R5F
526 * cores. The cores themselves are only halted in the .stop() ops, and the
527 * .unprepare() ops is invoked by the remoteproc core after the remoteproc is
528 * stopped.
529 *
530 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from
531 * both cores. The access is made possible only with releasing the resets for
532 * both cores, but with only Core0 unhalted. This function re-uses the same
533 * reset assert logic as LockStep mode for this mode (though the behavior is
534 * agnostic of the reset assert order). This callback is invoked only in
535 * remoteproc mode.
536 */
k3_r5_rproc_unprepare(struct rproc * rproc)537 static int k3_r5_rproc_unprepare(struct rproc *rproc)
538 {
539 struct k3_r5_rproc *kproc = rproc->priv;
540 struct k3_r5_cluster *cluster = kproc->cluster;
541 struct k3_r5_core *core = kproc->core, *core0, *core1;
542 struct device *dev = kproc->dev;
543 int ret;
544
545 /*
546 * Ensure power-down of cores is sequential in split mode. Core1 must
547 * power down before Core0 to maintain the expected state. By placing
548 * the wait mechanism here in .unprepare() ops, this condition is
549 * enforced for rproc stop or shutdown requests from sysfs and device
550 * removal as well.
551 */
552 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
553 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
554 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core0 &&
555 core1->released_from_reset) {
556 ret = wait_event_interruptible_timeout(cluster->core_transition,
557 !core1->released_from_reset,
558 msecs_to_jiffies(2000));
559 if (ret <= 0) {
560 dev_err(dev, "can not power down core0 before core1");
561 return -EPERM;
562 }
563 }
564
565 /* Re-use LockStep-mode reset logic for Single-CPU mode */
566 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
567 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
568 k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core);
569 if (ret)
570 dev_err(dev, "unable to disable cores, ret = %d\n", ret);
571
572 /*
573 * Notify all threads in the wait queue when core1 state has changed so
574 * that threads waiting for this condition can be executed.
575 */
576 core->released_from_reset = false;
577 if (core == core1)
578 wake_up_interruptible(&cluster->core_transition);
579
580 return ret;
581 }
582
583 /*
584 * The R5F start sequence includes two different operations
585 * 1. Configure the boot vector for R5F core(s)
586 * 2. Unhalt/Run the R5F core(s)
587 *
588 * The sequence is different between LockStep and Split modes. The LockStep
589 * mode requires the boot vector to be configured only for Core0, and then
590 * unhalt both the cores to start the execution - Core1 needs to be unhalted
591 * first followed by Core0. The Split-mode requires that Core0 to be maintained
592 * always in a higher power state that Core1 (implying Core1 needs to be started
593 * always only after Core0 is started).
594 *
595 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
596 * code, so only Core0 needs to be unhalted. The function uses the same logic
597 * flow as Split-mode for this. This callback is invoked only in remoteproc
598 * mode.
599 */
k3_r5_rproc_start(struct rproc * rproc)600 static int k3_r5_rproc_start(struct rproc *rproc)
601 {
602 struct k3_r5_rproc *kproc = rproc->priv;
603 struct k3_r5_cluster *cluster = kproc->cluster;
604 struct device *dev = kproc->dev;
605 struct k3_r5_core *core;
606 u32 boot_addr;
607 int ret;
608
609 boot_addr = rproc->bootaddr;
610 /* TODO: add boot_addr sanity checking */
611 dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);
612
613 /* boot vector need not be programmed for Core1 in LockStep mode */
614 core = kproc->core;
615 ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0);
616 if (ret)
617 return ret;
618
619 /* unhalt/run all applicable cores */
620 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
621 list_for_each_entry_reverse(core, &cluster->cores, elem) {
622 ret = k3_r5_core_run(core);
623 if (ret)
624 goto unroll_core_run;
625 }
626 } else {
627 ret = k3_r5_core_run(core);
628 if (ret)
629 return ret;
630 }
631
632 return 0;
633
634 unroll_core_run:
635 list_for_each_entry_continue(core, &cluster->cores, elem) {
636 if (k3_r5_core_halt(core))
637 dev_warn(core->dev, "core halt back failed\n");
638 }
639 return ret;
640 }
641
642 /*
643 * The R5F stop function includes the following operations
644 * 1. Halt R5F core(s)
645 *
646 * The sequence is different between LockStep and Split modes, and the order
647 * of cores the operations are performed are also in general reverse to that
648 * of the start function. The LockStep mode requires each operation to be
649 * performed first on Core0 followed by Core1. The Split-mode requires that
650 * Core0 to be maintained always in a higher power state that Core1 (implying
651 * Core1 needs to be stopped first before Core0).
652 *
653 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
654 * code, so only Core0 needs to be halted. The function uses the same logic
655 * flow as Split-mode for this.
656 *
657 * Note that the R5F halt operation in general is not effective when the R5F
658 * core is running, but is needed to make sure the core won't run after
659 * deasserting the reset the subsequent time. The asserting of reset can
660 * be done here, but is preferred to be done in the .unprepare() ops - this
661 * maintains the symmetric behavior between the .start(), .stop(), .prepare()
662 * and .unprepare() ops, and also balances them well between sysfs 'state'
663 * flow and device bind/unbind or module removal. This callback is invoked
664 * only in remoteproc mode.
665 */
k3_r5_rproc_stop(struct rproc * rproc)666 static int k3_r5_rproc_stop(struct rproc *rproc)
667 {
668 struct k3_r5_rproc *kproc = rproc->priv;
669 struct k3_r5_cluster *cluster = kproc->cluster;
670 struct k3_r5_core *core = kproc->core;
671 int ret;
672
673 /* halt all applicable cores */
674 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
675 list_for_each_entry(core, &cluster->cores, elem) {
676 ret = k3_r5_core_halt(core);
677 if (ret) {
678 core = list_prev_entry(core, elem);
679 goto unroll_core_halt;
680 }
681 }
682 } else {
683 ret = k3_r5_core_halt(core);
684 if (ret)
685 goto out;
686 }
687
688 return 0;
689
690 unroll_core_halt:
691 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
692 if (k3_r5_core_run(core))
693 dev_warn(core->dev, "core run back failed\n");
694 }
695 out:
696 return ret;
697 }
698
699 /*
700 * Attach to a running R5F remote processor (IPC-only mode)
701 *
702 * The R5F attach callback is a NOP. The remote processor is already booted, and
703 * all required resources have been acquired during probe routine, so there is
704 * no need to issue any TI-SCI commands to boot the R5F cores in IPC-only mode.
705 * This callback is invoked only in IPC-only mode and exists because
706 * rproc_validate() checks for its existence.
707 */
k3_r5_rproc_attach(struct rproc * rproc)708 static int k3_r5_rproc_attach(struct rproc *rproc) { return 0; }
709
710 /*
711 * Detach from a running R5F remote processor (IPC-only mode)
712 *
713 * The R5F detach callback is a NOP. The R5F cores are not stopped and will be
714 * left in booted state in IPC-only mode. This callback is invoked only in
715 * IPC-only mode and exists for sanity sake.
716 */
k3_r5_rproc_detach(struct rproc * rproc)717 static int k3_r5_rproc_detach(struct rproc *rproc) { return 0; }
718
719 /*
720 * This function implements the .get_loaded_rsc_table() callback and is used
721 * to provide the resource table for the booted R5F in IPC-only mode. The K3 R5F
722 * firmwares follow a design-by-contract approach and are expected to have the
723 * resource table at the base of the DDR region reserved for firmware usage.
724 * This provides flexibility for the remote processor to be booted by different
725 * bootloaders that may or may not have the ability to publish the resource table
726 * address and size through a DT property. This callback is invoked only in
727 * IPC-only mode.
728 */
k3_r5_get_loaded_rsc_table(struct rproc * rproc,size_t * rsc_table_sz)729 static struct resource_table *k3_r5_get_loaded_rsc_table(struct rproc *rproc,
730 size_t *rsc_table_sz)
731 {
732 struct k3_r5_rproc *kproc = rproc->priv;
733 struct device *dev = kproc->dev;
734
735 if (!kproc->rmem[0].cpu_addr) {
736 dev_err(dev, "memory-region #1 does not exist, loaded rsc table can't be found");
737 return ERR_PTR(-ENOMEM);
738 }
739
740 /*
741 * NOTE: The resource table size is currently hard-coded to a maximum
742 * of 256 bytes. The most common resource table usage for K3 firmwares
743 * is to only have the vdev resource entry and an optional trace entry.
744 * The exact size could be computed based on resource table address, but
745 * the hard-coded value suffices to support the IPC-only mode.
746 */
747 *rsc_table_sz = 256;
748 return (struct resource_table *)kproc->rmem[0].cpu_addr;
749 }
750
751 /*
752 * Internal Memory translation helper
753 *
754 * Custom function implementing the rproc .da_to_va ops to provide address
755 * translation (device address to kernel virtual address) for internal RAMs
756 * present in a DSP or IPU device). The translated addresses can be used
757 * either by the remoteproc core for loading, or by any rpmsg bus drivers.
758 */
k3_r5_rproc_da_to_va(struct rproc * rproc,u64 da,size_t len,bool * is_iomem)759 static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
760 {
761 struct k3_r5_rproc *kproc = rproc->priv;
762 struct k3_r5_core *core = kproc->core;
763 void __iomem *va = NULL;
764 phys_addr_t bus_addr;
765 u32 dev_addr, offset;
766 size_t size;
767 int i;
768
769 if (len == 0)
770 return NULL;
771
772 /* handle both R5 and SoC views of ATCM and BTCM */
773 for (i = 0; i < core->num_mems; i++) {
774 bus_addr = core->mem[i].bus_addr;
775 dev_addr = core->mem[i].dev_addr;
776 size = core->mem[i].size;
777
778 /* handle R5-view addresses of TCMs */
779 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
780 offset = da - dev_addr;
781 va = core->mem[i].cpu_addr + offset;
782 return (__force void *)va;
783 }
784
785 /* handle SoC-view addresses of TCMs */
786 if (da >= bus_addr && ((da + len) <= (bus_addr + size))) {
787 offset = da - bus_addr;
788 va = core->mem[i].cpu_addr + offset;
789 return (__force void *)va;
790 }
791 }
792
793 /* handle any SRAM regions using SoC-view addresses */
794 for (i = 0; i < core->num_sram; i++) {
795 dev_addr = core->sram[i].dev_addr;
796 size = core->sram[i].size;
797
798 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
799 offset = da - dev_addr;
800 va = core->sram[i].cpu_addr + offset;
801 return (__force void *)va;
802 }
803 }
804
805 /* handle static DDR reserved memory regions */
806 for (i = 0; i < kproc->num_rmems; i++) {
807 dev_addr = kproc->rmem[i].dev_addr;
808 size = kproc->rmem[i].size;
809
810 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
811 offset = da - dev_addr;
812 va = kproc->rmem[i].cpu_addr + offset;
813 return (__force void *)va;
814 }
815 }
816
817 return NULL;
818 }
819
820 static const struct rproc_ops k3_r5_rproc_ops = {
821 .prepare = k3_r5_rproc_prepare,
822 .unprepare = k3_r5_rproc_unprepare,
823 .start = k3_r5_rproc_start,
824 .stop = k3_r5_rproc_stop,
825 .kick = k3_r5_rproc_kick,
826 .da_to_va = k3_r5_rproc_da_to_va,
827 };
828
829 /*
830 * Internal R5F Core configuration
831 *
832 * Each R5FSS has a cluster-level setting for configuring the processor
833 * subsystem either in a safety/fault-tolerant LockStep mode or a performance
834 * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode
835 * as an alternate for LockStep mode that exercises only a single R5F core
836 * called Single-CPU mode. Each R5F core has a number of settings to either
837 * enable/disable each of the TCMs, control which TCM appears at the R5F core's
838 * address 0x0. These settings need to be configured before the resets for the
839 * corresponding core are released. These settings are all protected and managed
840 * by the System Processor.
841 *
842 * This function is used to pre-configure these settings for each R5F core, and
843 * the configuration is all done through various ti_sci_proc functions that
844 * communicate with the System Processor. The function also ensures that both
845 * the cores are halted before the .prepare() step.
846 *
847 * The function is called from k3_r5_cluster_rproc_init() and is invoked either
848 * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support
849 * for LockStep-mode is dictated by an eFUSE register bit, and the config
850 * settings retrieved from DT are adjusted accordingly as per the permitted
851 * cluster mode. Another eFUSE register bit dictates if the R5F cluster only
852 * supports a Single-CPU mode. All cluster level settings like Cluster mode and
853 * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set
854 * and retrieved using Core0.
855 *
856 * The function behavior is different based on the cluster mode. The R5F cores
857 * are configured independently as per their individual settings in Split mode.
858 * They are identically configured in LockStep mode using the primary Core0
859 * settings. However, some individual settings cannot be set in LockStep mode.
860 * This is overcome by switching to Split-mode initially and then programming
861 * both the cores with the same settings, before reconfiguing again for
862 * LockStep mode.
863 */
k3_r5_rproc_configure(struct k3_r5_rproc * kproc)864 static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc)
865 {
866 struct k3_r5_cluster *cluster = kproc->cluster;
867 struct device *dev = kproc->dev;
868 struct k3_r5_core *core0, *core, *temp;
869 u32 ctrl = 0, cfg = 0, stat = 0;
870 u32 set_cfg = 0, clr_cfg = 0;
871 u64 boot_vec = 0;
872 bool lockstep_en;
873 bool single_cpu;
874 int ret;
875
876 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
877 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
878 cluster->mode == CLUSTER_MODE_SINGLECPU ||
879 cluster->mode == CLUSTER_MODE_SINGLECORE) {
880 core = core0;
881 } else {
882 core = kproc->core;
883 }
884
885 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
886 &stat);
887 if (ret < 0)
888 return ret;
889
890 dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",
891 boot_vec, cfg, ctrl, stat);
892
893 single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY);
894 lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
895
896 /* Override to single CPU mode if set in status flag */
897 if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) {
898 dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n");
899 cluster->mode = CLUSTER_MODE_SINGLECPU;
900 }
901
902 /* Override to split mode if lockstep enable bit is not set in status flag */
903 if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {
904 dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");
905 cluster->mode = CLUSTER_MODE_SPLIT;
906 }
907
908 /* always enable ARM mode and set boot vector to 0 */
909 boot_vec = 0x0;
910 if (core == core0) {
911 clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;
912 /*
913 * Single-CPU configuration bit can only be configured
914 * on Core0 and system firmware will NACK any requests
915 * with the bit configured, so program it only on
916 * permitted cores
917 */
918 if (cluster->mode == CLUSTER_MODE_SINGLECPU ||
919 cluster->mode == CLUSTER_MODE_SINGLECORE) {
920 set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;
921 } else {
922 /*
923 * LockStep configuration bit is Read-only on Split-mode
924 * _only_ devices and system firmware will NACK any
925 * requests with the bit configured, so program it only
926 * on permitted devices
927 */
928 if (lockstep_en)
929 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
930 }
931 }
932
933 if (core->atcm_enable)
934 set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
935 else
936 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
937
938 if (core->btcm_enable)
939 set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
940 else
941 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
942
943 if (core->loczrama)
944 set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
945 else
946 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
947
948 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
949 /*
950 * work around system firmware limitations to make sure both
951 * cores are programmed symmetrically in LockStep. LockStep
952 * and TEINIT config is only allowed with Core0.
953 */
954 list_for_each_entry(temp, &cluster->cores, elem) {
955 ret = k3_r5_core_halt(temp);
956 if (ret)
957 goto out;
958
959 if (temp != core) {
960 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
961 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;
962 }
963 ret = ti_sci_proc_set_config(temp->tsp, boot_vec,
964 set_cfg, clr_cfg);
965 if (ret)
966 goto out;
967 }
968
969 set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
970 clr_cfg = 0;
971 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
972 set_cfg, clr_cfg);
973 } else {
974 ret = k3_r5_core_halt(core);
975 if (ret)
976 goto out;
977
978 ret = ti_sci_proc_set_config(core->tsp, boot_vec,
979 set_cfg, clr_cfg);
980 }
981
982 out:
983 return ret;
984 }
985
k3_r5_mem_release(void * data)986 static void k3_r5_mem_release(void *data)
987 {
988 struct device *dev = data;
989
990 of_reserved_mem_device_release(dev);
991 }
992
k3_r5_reserved_mem_init(struct k3_r5_rproc * kproc)993 static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)
994 {
995 struct device *dev = kproc->dev;
996 struct device_node *np = dev_of_node(dev);
997 struct device_node *rmem_np;
998 struct reserved_mem *rmem;
999 int num_rmems;
1000 int ret, i;
1001
1002 num_rmems = of_property_count_elems_of_size(np, "memory-region",
1003 sizeof(phandle));
1004 if (num_rmems <= 0) {
1005 dev_err(dev, "device does not have reserved memory regions, ret = %d\n",
1006 num_rmems);
1007 return -EINVAL;
1008 }
1009 if (num_rmems < 2) {
1010 dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",
1011 num_rmems);
1012 return -EINVAL;
1013 }
1014
1015 /* use reserved memory region 0 for vring DMA allocations */
1016 ret = of_reserved_mem_device_init_by_idx(dev, np, 0);
1017 if (ret) {
1018 dev_err(dev, "device cannot initialize DMA pool, ret = %d\n",
1019 ret);
1020 return ret;
1021 }
1022
1023 ret = devm_add_action_or_reset(dev, k3_r5_mem_release, dev);
1024 if (ret)
1025 return ret;
1026
1027 num_rmems--;
1028 kproc->rmem = devm_kcalloc(dev, num_rmems, sizeof(*kproc->rmem), GFP_KERNEL);
1029 if (!kproc->rmem)
1030 return -ENOMEM;
1031
1032 /* use remaining reserved memory regions for static carveouts */
1033 for (i = 0; i < num_rmems; i++) {
1034 rmem_np = of_parse_phandle(np, "memory-region", i + 1);
1035 if (!rmem_np)
1036 return -EINVAL;
1037
1038 rmem = of_reserved_mem_lookup(rmem_np);
1039 of_node_put(rmem_np);
1040 if (!rmem)
1041 return -EINVAL;
1042
1043 kproc->rmem[i].bus_addr = rmem->base;
1044 /*
1045 * R5Fs do not have an MMU, but have a Region Address Translator
1046 * (RAT) module that provides a fixed entry translation between
1047 * the 32-bit processor addresses to 64-bit bus addresses. The
1048 * RAT is programmable only by the R5F cores. Support for RAT
1049 * is currently not supported, so 64-bit address regions are not
1050 * supported. The absence of MMUs implies that the R5F device
1051 * addresses/supported memory regions are restricted to 32-bit
1052 * bus addresses, and are identical
1053 */
1054 kproc->rmem[i].dev_addr = (u32)rmem->base;
1055 kproc->rmem[i].size = rmem->size;
1056 kproc->rmem[i].cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size);
1057 if (!kproc->rmem[i].cpu_addr) {
1058 dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n",
1059 i + 1, &rmem->base, &rmem->size);
1060 return -ENOMEM;
1061 }
1062
1063 dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1064 i + 1, &kproc->rmem[i].bus_addr,
1065 kproc->rmem[i].size, kproc->rmem[i].cpu_addr,
1066 kproc->rmem[i].dev_addr);
1067 }
1068 kproc->num_rmems = num_rmems;
1069
1070 return 0;
1071 }
1072
1073 /*
1074 * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
1075 * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
1076 * cores are usable in Split-mode, but only the Core0 TCMs can be used in
1077 * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
1078 * leveraging the Core1 TCMs as well in certain modes where they would have
1079 * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on
1080 * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the
1081 * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for
1082 * the Core0 TCMs, and the dts representation reflects this increased size on
1083 * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only
1084 * half the original size in Split mode.
1085 */
k3_r5_adjust_tcm_sizes(struct k3_r5_rproc * kproc)1086 static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc)
1087 {
1088 struct k3_r5_cluster *cluster = kproc->cluster;
1089 struct k3_r5_core *core = kproc->core;
1090 struct device *cdev = core->dev;
1091 struct k3_r5_core *core0;
1092
1093 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1094 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1095 cluster->mode == CLUSTER_MODE_SINGLECORE ||
1096 !cluster->soc_data->tcm_is_double)
1097 return;
1098
1099 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1100 if (core == core0) {
1101 WARN_ON(core->mem[0].size != SZ_64K);
1102 WARN_ON(core->mem[1].size != SZ_64K);
1103
1104 core->mem[0].size /= 2;
1105 core->mem[1].size /= 2;
1106
1107 dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
1108 core->mem[0].size, core->mem[1].size);
1109 }
1110 }
1111
1112 /*
1113 * This function checks and configures a R5F core for IPC-only or remoteproc
1114 * mode. The driver is configured to be in IPC-only mode for a R5F core when
1115 * the core has been loaded and started by a bootloader. The IPC-only mode is
1116 * detected by querying the System Firmware for reset, power on and halt status
1117 * and ensuring that the core is running. Any incomplete steps at bootloader
1118 * are validated and errored out.
1119 *
1120 * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings
1121 * and cluster mode parsed originally from kernel DT are updated to reflect the
1122 * actual values configured by bootloader. The driver internal device memory
1123 * addresses for TCMs are also updated.
1124 */
k3_r5_rproc_configure_mode(struct k3_r5_rproc * kproc)1125 static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc)
1126 {
1127 struct k3_r5_cluster *cluster = kproc->cluster;
1128 struct k3_r5_core *core = kproc->core;
1129 struct device *cdev = core->dev;
1130 bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false;
1131 u32 ctrl = 0, cfg = 0, stat = 0, halted = 0;
1132 u64 boot_vec = 0;
1133 u32 atcm_enable, btcm_enable, loczrama;
1134 struct k3_r5_core *core0;
1135 enum cluster_mode mode = cluster->mode;
1136 int reset_ctrl_status;
1137 int ret;
1138
1139 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
1140
1141 ret = core->ti_sci->ops.dev_ops.is_on(core->ti_sci, core->ti_sci_id,
1142 &r_state, &c_state);
1143 if (ret) {
1144 dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n",
1145 ret);
1146 return ret;
1147 }
1148 if (r_state != c_state) {
1149 dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n",
1150 r_state, c_state);
1151 }
1152
1153 reset_ctrl_status = reset_control_status(core->reset);
1154 if (reset_ctrl_status < 0) {
1155 dev_err(cdev, "failed to get initial local reset status, ret = %d\n",
1156 reset_ctrl_status);
1157 return reset_ctrl_status;
1158 }
1159
1160 /*
1161 * Skip the waiting mechanism for sequential power-on of cores if the
1162 * core has already been booted by another entity.
1163 */
1164 core->released_from_reset = c_state;
1165
1166 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,
1167 &stat);
1168 if (ret < 0) {
1169 dev_err(cdev, "failed to get initial processor status, ret = %d\n",
1170 ret);
1171 return ret;
1172 }
1173 atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0;
1174 btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0;
1175 loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0;
1176 single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0;
1177 lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0;
1178
1179 if (single_cpu && mode != CLUSTER_MODE_SINGLECORE)
1180 mode = CLUSTER_MODE_SINGLECPU;
1181 if (lockstep_en)
1182 mode = CLUSTER_MODE_LOCKSTEP;
1183
1184 halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT;
1185
1186 /*
1187 * IPC-only mode detection requires both local and module resets to
1188 * be deasserted and R5F core to be unhalted. Local reset status is
1189 * irrelevant if module reset is asserted (POR value has local reset
1190 * deasserted), and is deemed as remoteproc mode
1191 */
1192 if (c_state && !reset_ctrl_status && !halted) {
1193 dev_info(cdev, "configured R5F for IPC-only mode\n");
1194 kproc->rproc->state = RPROC_DETACHED;
1195 ret = 1;
1196 /* override rproc ops with only required IPC-only mode ops */
1197 kproc->rproc->ops->prepare = NULL;
1198 kproc->rproc->ops->unprepare = NULL;
1199 kproc->rproc->ops->start = NULL;
1200 kproc->rproc->ops->stop = NULL;
1201 kproc->rproc->ops->attach = k3_r5_rproc_attach;
1202 kproc->rproc->ops->detach = k3_r5_rproc_detach;
1203 kproc->rproc->ops->get_loaded_rsc_table =
1204 k3_r5_get_loaded_rsc_table;
1205 } else if (!c_state) {
1206 dev_info(cdev, "configured R5F for remoteproc mode\n");
1207 ret = 0;
1208 } else {
1209 dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n",
1210 !reset_ctrl_status ? "deasserted" : "asserted",
1211 c_state ? "deasserted" : "asserted",
1212 halted ? "halted" : "unhalted");
1213 ret = -EINVAL;
1214 }
1215
1216 /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */
1217 if (ret > 0) {
1218 if (core == core0)
1219 cluster->mode = mode;
1220 core->atcm_enable = atcm_enable;
1221 core->btcm_enable = btcm_enable;
1222 core->loczrama = loczrama;
1223 core->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR;
1224 core->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0;
1225 }
1226
1227 return ret;
1228 }
1229
k3_r5_cluster_rproc_init(struct platform_device * pdev)1230 static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
1231 {
1232 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1233 struct device *dev = &pdev->dev;
1234 struct k3_r5_rproc *kproc;
1235 struct k3_r5_core *core, *core1;
1236 struct device *cdev;
1237 const char *fw_name;
1238 struct rproc *rproc;
1239 int ret, ret1;
1240
1241 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1242 list_for_each_entry(core, &cluster->cores, elem) {
1243 cdev = core->dev;
1244 ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
1245 if (ret) {
1246 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1247 ret);
1248 goto out;
1249 }
1250
1251 rproc = devm_rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,
1252 fw_name, sizeof(*kproc));
1253 if (!rproc) {
1254 ret = -ENOMEM;
1255 goto out;
1256 }
1257
1258 /* K3 R5s have a Region Address Translator (RAT) but no MMU */
1259 rproc->has_iommu = false;
1260 /* error recovery is not supported at present */
1261 rproc->recovery_disabled = true;
1262
1263 kproc = rproc->priv;
1264 kproc->cluster = cluster;
1265 kproc->core = core;
1266 kproc->dev = cdev;
1267 kproc->rproc = rproc;
1268 core->rproc = rproc;
1269
1270 ret = k3_r5_rproc_request_mbox(rproc);
1271 if (ret)
1272 return ret;
1273
1274 ret = k3_r5_rproc_configure_mode(kproc);
1275 if (ret < 0)
1276 goto out;
1277 if (ret)
1278 goto init_rmem;
1279
1280 ret = k3_r5_rproc_configure(kproc);
1281 if (ret) {
1282 dev_err(dev, "initial configure failed, ret = %d\n",
1283 ret);
1284 goto out;
1285 }
1286
1287 init_rmem:
1288 k3_r5_adjust_tcm_sizes(kproc);
1289
1290 ret = k3_r5_reserved_mem_init(kproc);
1291 if (ret) {
1292 dev_err(dev, "reserved memory init failed, ret = %d\n",
1293 ret);
1294 goto out;
1295 }
1296
1297 ret = devm_rproc_add(dev, rproc);
1298 if (ret) {
1299 dev_err_probe(dev, ret, "rproc_add failed\n");
1300 goto out;
1301 }
1302
1303 /* create only one rproc in lockstep, single-cpu or
1304 * single core mode
1305 */
1306 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1307 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1308 cluster->mode == CLUSTER_MODE_SINGLECORE)
1309 break;
1310 }
1311
1312 return 0;
1313
1314 err_split:
1315 if (rproc->state == RPROC_ATTACHED) {
1316 ret1 = rproc_detach(rproc);
1317 if (ret1) {
1318 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n",
1319 ret1);
1320 return ret1;
1321 }
1322 }
1323
1324 out:
1325 /* undo core0 upon any failures on core1 in split-mode */
1326 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {
1327 core = list_prev_entry(core, elem);
1328 rproc = core->rproc;
1329 kproc = rproc->priv;
1330 goto err_split;
1331 }
1332 return ret;
1333 }
1334
k3_r5_cluster_rproc_exit(void * data)1335 static void k3_r5_cluster_rproc_exit(void *data)
1336 {
1337 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1338 struct k3_r5_rproc *kproc;
1339 struct k3_r5_core *core;
1340 struct rproc *rproc;
1341 int ret;
1342
1343 /*
1344 * lockstep mode and single-cpu modes have only one rproc associated
1345 * with first core, whereas split-mode has two rprocs associated with
1346 * each core, and requires that core1 be powered down first
1347 */
1348 core = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1349 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
1350 list_first_entry(&cluster->cores, struct k3_r5_core, elem) :
1351 list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1352
1353 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
1354 rproc = core->rproc;
1355 kproc = rproc->priv;
1356
1357 if (rproc->state == RPROC_ATTACHED) {
1358 ret = rproc_detach(rproc);
1359 if (ret) {
1360 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret);
1361 return;
1362 }
1363 }
1364
1365 mbox_free_channel(kproc->mbox);
1366 }
1367 }
1368
k3_r5_core_of_get_internal_memories(struct platform_device * pdev,struct k3_r5_core * core)1369 static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
1370 struct k3_r5_core *core)
1371 {
1372 static const char * const mem_names[] = {"atcm", "btcm"};
1373 struct device *dev = &pdev->dev;
1374 struct resource *res;
1375 int num_mems;
1376 int i;
1377
1378 num_mems = ARRAY_SIZE(mem_names);
1379 core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);
1380 if (!core->mem)
1381 return -ENOMEM;
1382
1383 for (i = 0; i < num_mems; i++) {
1384 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1385 mem_names[i]);
1386 if (!res) {
1387 dev_err(dev, "found no memory resource for %s\n",
1388 mem_names[i]);
1389 return -EINVAL;
1390 }
1391 if (!devm_request_mem_region(dev, res->start,
1392 resource_size(res),
1393 dev_name(dev))) {
1394 dev_err(dev, "could not request %s region for resource\n",
1395 mem_names[i]);
1396 return -EBUSY;
1397 }
1398
1399 /*
1400 * TCMs are designed in general to support RAM-like backing
1401 * memories. So, map these as Normal Non-Cached memories. This
1402 * also avoids/fixes any potential alignment faults due to
1403 * unaligned data accesses when using memcpy() or memset()
1404 * functions (normally seen with device type memory).
1405 */
1406 core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,
1407 resource_size(res));
1408 if (!core->mem[i].cpu_addr) {
1409 dev_err(dev, "failed to map %s memory\n", mem_names[i]);
1410 return -ENOMEM;
1411 }
1412 core->mem[i].bus_addr = res->start;
1413
1414 /*
1415 * TODO:
1416 * The R5F cores can place ATCM & BTCM anywhere in its address
1417 * based on the corresponding Region Registers in the System
1418 * Control coprocessor. For now, place ATCM and BTCM at
1419 * addresses 0 and 0x41010000 (same as the bus address on AM65x
1420 * SoCs) based on loczrama setting
1421 */
1422 if (!strcmp(mem_names[i], "atcm")) {
1423 core->mem[i].dev_addr = core->loczrama ?
1424 0 : K3_R5_TCM_DEV_ADDR;
1425 } else {
1426 core->mem[i].dev_addr = core->loczrama ?
1427 K3_R5_TCM_DEV_ADDR : 0;
1428 }
1429 core->mem[i].size = resource_size(res);
1430
1431 dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1432 mem_names[i], &core->mem[i].bus_addr,
1433 core->mem[i].size, core->mem[i].cpu_addr,
1434 core->mem[i].dev_addr);
1435 }
1436 core->num_mems = num_mems;
1437
1438 return 0;
1439 }
1440
k3_r5_core_of_get_sram_memories(struct platform_device * pdev,struct k3_r5_core * core)1441 static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
1442 struct k3_r5_core *core)
1443 {
1444 struct device_node *np = pdev->dev.of_node;
1445 struct device *dev = &pdev->dev;
1446 struct device_node *sram_np;
1447 struct resource res;
1448 int num_sram;
1449 int i, ret;
1450
1451 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
1452 if (num_sram <= 0) {
1453 dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
1454 num_sram);
1455 return 0;
1456 }
1457
1458 core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
1459 if (!core->sram)
1460 return -ENOMEM;
1461
1462 for (i = 0; i < num_sram; i++) {
1463 sram_np = of_parse_phandle(np, "sram", i);
1464 if (!sram_np)
1465 return -EINVAL;
1466
1467 if (!of_device_is_available(sram_np)) {
1468 of_node_put(sram_np);
1469 return -EINVAL;
1470 }
1471
1472 ret = of_address_to_resource(sram_np, 0, &res);
1473 of_node_put(sram_np);
1474 if (ret)
1475 return -EINVAL;
1476
1477 core->sram[i].bus_addr = res.start;
1478 core->sram[i].dev_addr = res.start;
1479 core->sram[i].size = resource_size(&res);
1480 core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
1481 resource_size(&res));
1482 if (!core->sram[i].cpu_addr) {
1483 dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
1484 i, &res.start);
1485 return -ENOMEM;
1486 }
1487
1488 dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",
1489 i, &core->sram[i].bus_addr,
1490 core->sram[i].size, core->sram[i].cpu_addr,
1491 core->sram[i].dev_addr);
1492 }
1493 core->num_sram = num_sram;
1494
1495 return 0;
1496 }
1497
k3_r5_core_of_init(struct platform_device * pdev)1498 static int k3_r5_core_of_init(struct platform_device *pdev)
1499 {
1500 struct device *dev = &pdev->dev;
1501 struct device_node *np = dev_of_node(dev);
1502 struct k3_r5_core *core;
1503 int ret;
1504
1505 if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))
1506 return -ENOMEM;
1507
1508 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
1509 if (!core) {
1510 ret = -ENOMEM;
1511 goto err;
1512 }
1513
1514 core->dev = dev;
1515 /*
1516 * Use SoC Power-on-Reset values as default if no DT properties are
1517 * used to dictate the TCM configurations
1518 */
1519 core->atcm_enable = 0;
1520 core->btcm_enable = 1;
1521 core->loczrama = 1;
1522
1523 ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);
1524 if (ret < 0 && ret != -EINVAL) {
1525 dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",
1526 ret);
1527 goto err;
1528 }
1529
1530 ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);
1531 if (ret < 0 && ret != -EINVAL) {
1532 dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",
1533 ret);
1534 goto err;
1535 }
1536
1537 ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);
1538 if (ret < 0 && ret != -EINVAL) {
1539 dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);
1540 goto err;
1541 }
1542
1543 core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");
1544 if (IS_ERR(core->ti_sci)) {
1545 ret = PTR_ERR(core->ti_sci);
1546 if (ret != -EPROBE_DEFER) {
1547 dev_err(dev, "failed to get ti-sci handle, ret = %d\n",
1548 ret);
1549 }
1550 core->ti_sci = NULL;
1551 goto err;
1552 }
1553
1554 ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id);
1555 if (ret) {
1556 dev_err(dev, "missing 'ti,sci-dev-id' property\n");
1557 goto err;
1558 }
1559
1560 core->reset = devm_reset_control_get_exclusive(dev, NULL);
1561 if (IS_ERR_OR_NULL(core->reset)) {
1562 ret = PTR_ERR_OR_ZERO(core->reset);
1563 if (!ret)
1564 ret = -ENODEV;
1565 if (ret != -EPROBE_DEFER) {
1566 dev_err(dev, "failed to get reset handle, ret = %d\n",
1567 ret);
1568 }
1569 goto err;
1570 }
1571
1572 core->tsp = ti_sci_proc_of_get_tsp(dev, core->ti_sci);
1573 if (IS_ERR(core->tsp)) {
1574 ret = PTR_ERR(core->tsp);
1575 dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n",
1576 ret);
1577 goto err;
1578 }
1579
1580 ret = k3_r5_core_of_get_internal_memories(pdev, core);
1581 if (ret) {
1582 dev_err(dev, "failed to get internal memories, ret = %d\n",
1583 ret);
1584 goto err;
1585 }
1586
1587 ret = k3_r5_core_of_get_sram_memories(pdev, core);
1588 if (ret) {
1589 dev_err(dev, "failed to get sram memories, ret = %d\n", ret);
1590 goto err;
1591 }
1592
1593 ret = ti_sci_proc_request(core->tsp);
1594 if (ret < 0) {
1595 dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret);
1596 goto err;
1597 }
1598
1599 platform_set_drvdata(pdev, core);
1600 devres_close_group(dev, k3_r5_core_of_init);
1601
1602 return 0;
1603
1604 err:
1605 devres_release_group(dev, k3_r5_core_of_init);
1606 return ret;
1607 }
1608
1609 /*
1610 * free the resources explicitly since driver model is not being used
1611 * for the child R5F devices
1612 */
k3_r5_core_of_exit(struct platform_device * pdev)1613 static void k3_r5_core_of_exit(struct platform_device *pdev)
1614 {
1615 struct k3_r5_core *core = platform_get_drvdata(pdev);
1616 struct device *dev = &pdev->dev;
1617 int ret;
1618
1619 ret = ti_sci_proc_release(core->tsp);
1620 if (ret)
1621 dev_err(dev, "failed to release proc, ret = %d\n", ret);
1622
1623 platform_set_drvdata(pdev, NULL);
1624 devres_release_group(dev, k3_r5_core_of_init);
1625 }
1626
k3_r5_cluster_of_exit(void * data)1627 static void k3_r5_cluster_of_exit(void *data)
1628 {
1629 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1630 struct platform_device *cpdev;
1631 struct k3_r5_core *core, *temp;
1632
1633 list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {
1634 list_del(&core->elem);
1635 cpdev = to_platform_device(core->dev);
1636 k3_r5_core_of_exit(cpdev);
1637 }
1638 }
1639
k3_r5_cluster_of_init(struct platform_device * pdev)1640 static int k3_r5_cluster_of_init(struct platform_device *pdev)
1641 {
1642 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1643 struct device *dev = &pdev->dev;
1644 struct device_node *np = dev_of_node(dev);
1645 struct platform_device *cpdev;
1646 struct device_node *child;
1647 struct k3_r5_core *core;
1648 int ret;
1649
1650 for_each_available_child_of_node(np, child) {
1651 cpdev = of_find_device_by_node(child);
1652 if (!cpdev) {
1653 ret = -ENODEV;
1654 dev_err(dev, "could not get R5 core platform device\n");
1655 of_node_put(child);
1656 goto fail;
1657 }
1658
1659 ret = k3_r5_core_of_init(cpdev);
1660 if (ret) {
1661 dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",
1662 ret);
1663 put_device(&cpdev->dev);
1664 of_node_put(child);
1665 goto fail;
1666 }
1667
1668 core = platform_get_drvdata(cpdev);
1669 put_device(&cpdev->dev);
1670 list_add_tail(&core->elem, &cluster->cores);
1671 }
1672
1673 return 0;
1674
1675 fail:
1676 k3_r5_cluster_of_exit(pdev);
1677 return ret;
1678 }
1679
k3_r5_probe(struct platform_device * pdev)1680 static int k3_r5_probe(struct platform_device *pdev)
1681 {
1682 struct device *dev = &pdev->dev;
1683 struct device_node *np = dev_of_node(dev);
1684 struct k3_r5_cluster *cluster;
1685 const struct k3_r5_soc_data *data;
1686 int ret;
1687 int num_cores;
1688
1689 data = of_device_get_match_data(&pdev->dev);
1690 if (!data) {
1691 dev_err(dev, "SoC-specific data is not defined\n");
1692 return -ENODEV;
1693 }
1694
1695 cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
1696 if (!cluster)
1697 return -ENOMEM;
1698
1699 cluster->dev = dev;
1700 cluster->soc_data = data;
1701 INIT_LIST_HEAD(&cluster->cores);
1702 init_waitqueue_head(&cluster->core_transition);
1703
1704 ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);
1705 if (ret < 0 && ret != -EINVAL) {
1706 dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n",
1707 ret);
1708 return ret;
1709 }
1710
1711 if (ret == -EINVAL) {
1712 /*
1713 * default to most common efuse configurations - Split-mode on AM64x
1714 * and LockStep-mode on all others
1715 * default to most common efuse configurations -
1716 * Split-mode on AM64x
1717 * Single core on AM62x
1718 * LockStep-mode on all others
1719 */
1720 if (!data->is_single_core)
1721 cluster->mode = data->single_cpu_mode ?
1722 CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;
1723 else
1724 cluster->mode = CLUSTER_MODE_SINGLECORE;
1725 }
1726
1727 if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) ||
1728 (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) {
1729 dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode);
1730 return -EINVAL;
1731 }
1732
1733 num_cores = of_get_available_child_count(np);
1734 if (num_cores != 2 && !data->is_single_core) {
1735 dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",
1736 num_cores);
1737 return -ENODEV;
1738 }
1739
1740 if (num_cores != 1 && data->is_single_core) {
1741 dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n",
1742 num_cores);
1743 return -ENODEV;
1744 }
1745
1746 platform_set_drvdata(pdev, cluster);
1747
1748 ret = devm_of_platform_populate(dev);
1749 if (ret) {
1750 dev_err(dev, "devm_of_platform_populate failed, ret = %d\n",
1751 ret);
1752 return ret;
1753 }
1754
1755 ret = k3_r5_cluster_of_init(pdev);
1756 if (ret) {
1757 dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret);
1758 return ret;
1759 }
1760
1761 ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);
1762 if (ret)
1763 return ret;
1764
1765 ret = k3_r5_cluster_rproc_init(pdev);
1766 if (ret) {
1767 dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n",
1768 ret);
1769 return ret;
1770 }
1771
1772 ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);
1773 if (ret)
1774 return ret;
1775
1776 return 0;
1777 }
1778
1779 static const struct k3_r5_soc_data am65_j721e_soc_data = {
1780 .tcm_is_double = false,
1781 .tcm_ecc_autoinit = false,
1782 .single_cpu_mode = false,
1783 .is_single_core = false,
1784 };
1785
1786 static const struct k3_r5_soc_data j7200_j721s2_soc_data = {
1787 .tcm_is_double = true,
1788 .tcm_ecc_autoinit = true,
1789 .single_cpu_mode = false,
1790 .is_single_core = false,
1791 };
1792
1793 static const struct k3_r5_soc_data am64_soc_data = {
1794 .tcm_is_double = true,
1795 .tcm_ecc_autoinit = true,
1796 .single_cpu_mode = true,
1797 .is_single_core = false,
1798 };
1799
1800 static const struct k3_r5_soc_data am62_soc_data = {
1801 .tcm_is_double = false,
1802 .tcm_ecc_autoinit = true,
1803 .single_cpu_mode = false,
1804 .is_single_core = true,
1805 };
1806
1807 static const struct of_device_id k3_r5_of_match[] = {
1808 { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, },
1809 { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },
1810 { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },
1811 { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },
1812 { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, },
1813 { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },
1814 { /* sentinel */ },
1815 };
1816 MODULE_DEVICE_TABLE(of, k3_r5_of_match);
1817
1818 static struct platform_driver k3_r5_rproc_driver = {
1819 .probe = k3_r5_probe,
1820 .driver = {
1821 .name = "k3_r5_rproc",
1822 .of_match_table = k3_r5_of_match,
1823 },
1824 };
1825
1826 module_platform_driver(k3_r5_rproc_driver);
1827
1828 MODULE_LICENSE("GPL v2");
1829 MODULE_DESCRIPTION("TI K3 R5F remote processor driver");
1830 MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
1831