1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ZynqMP R5 Remote Processor driver
4 *
5 */
6
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
10 #include <linux/kernel.h>
11 #include <linux/mailbox_client.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_platform.h>
16 #include <linux/of_reserved_mem.h>
17 #include <linux/platform_device.h>
18 #include <linux/remoteproc.h>
19
20 #include "remoteproc_internal.h"
21
22 /* IPI buffer MAX length */
23 #define IPI_BUF_LEN_MAX 32U
24
25 /* RX mailbox client buffer max length */
26 #define MBOX_CLIENT_BUF_MAX (IPI_BUF_LEN_MAX + \
27 sizeof(struct zynqmp_ipi_message))
28
29 #define RSC_TBL_XLNX_MAGIC ((uint32_t)'x' << 24 | (uint32_t)'a' << 16 | \
30 (uint32_t)'m' << 8 | (uint32_t)'p')
31
32 /*
33 * settings for RPU cluster mode which
34 * reflects possible values of xlnx,cluster-mode dt-property
35 */
36 enum zynqmp_r5_cluster_mode {
37 SPLIT_MODE = 0, /* When cores run as separate processor */
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
39 SINGLE_CPU_MODE = 2, /* core0 is held in reset and only core1 runs */
40 };
41
42 /**
43 * struct mem_bank_data - Memory Bank description
44 *
45 * @addr: Start address of memory bank
46 * @da: device address
47 * @size: Size of Memory bank
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
49 * @bank_name: name of the bank for remoteproc framework
50 */
51 struct mem_bank_data {
52 phys_addr_t addr;
53 u32 da;
54 size_t size;
55 u32 pm_domain_id;
56 char *bank_name;
57 };
58
59 /**
60 * struct zynqmp_sram_bank - sram bank description
61 *
62 * @sram_res: sram address region information
63 * @da: device address of sram
64 */
65 struct zynqmp_sram_bank {
66 struct resource sram_res;
67 u32 da;
68 };
69
70 /**
71 * struct mbox_info
72 *
73 * @rx_mc_buf: to copy data from mailbox rx channel
74 * @tx_mc_buf: to copy data to mailbox tx channel
75 * @r5_core: this mailbox's corresponding r5_core pointer
76 * @mbox_work: schedule work after receiving data from mailbox
77 * @mbox_cl: mailbox client
78 * @tx_chan: mailbox tx channel
79 * @rx_chan: mailbox rx channel
80 */
81 struct mbox_info {
82 unsigned char rx_mc_buf[MBOX_CLIENT_BUF_MAX];
83 unsigned char tx_mc_buf[MBOX_CLIENT_BUF_MAX];
84 struct zynqmp_r5_core *r5_core;
85 struct work_struct mbox_work;
86 struct mbox_client mbox_cl;
87 struct mbox_chan *tx_chan;
88 struct mbox_chan *rx_chan;
89 };
90
91 /**
92 * struct rsc_tbl_data
93 *
94 * Platform specific data structure used to sync resource table address.
95 * It's important to maintain order and size of each field on remote side.
96 *
97 * @version: version of data structure
98 * @magic_num: 32-bit magic number.
99 * @comp_magic_num: complement of above magic number
100 * @rsc_tbl_size: resource table size
101 * @rsc_tbl: resource table address
102 */
103 struct rsc_tbl_data {
104 const int version;
105 const u32 magic_num;
106 const u32 comp_magic_num;
107 const u32 rsc_tbl_size;
108 const uintptr_t rsc_tbl;
109 } __packed;
110
111 /*
112 * Hardcoded TCM bank values. This will stay in driver to maintain backward
113 * compatibility with device-tree that does not have TCM information.
114 */
115 static const struct mem_bank_data zynqmp_tcm_banks_split[] = {
116 {0xffe00000UL, 0x0, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */
117 {0xffe20000UL, 0x20000, 0x10000UL, PD_R5_0_BTCM, "btcm0"},
118 {0xffe90000UL, 0x0, 0x10000UL, PD_R5_1_ATCM, "atcm1"},
119 {0xffeb0000UL, 0x20000, 0x10000UL, PD_R5_1_BTCM, "btcm1"},
120 };
121
122 /* In lockstep mode cluster uses each 64KB TCM from second core as well */
123 static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = {
124 {0xffe00000UL, 0x0, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */
125 {0xffe20000UL, 0x20000, 0x10000UL, PD_R5_0_BTCM, "btcm0"},
126 {0xffe10000UL, 0x10000, 0x10000UL, PD_R5_1_ATCM, "atcm1"},
127 {0xffe30000UL, 0x30000, 0x10000UL, PD_R5_1_BTCM, "btcm1"},
128 };
129
130 /**
131 * struct zynqmp_r5_core
132 *
133 * @rsc_tbl_va: resource table virtual address
134 * @sram: Array of sram memories assigned to this core
135 * @num_sram: number of sram for this core
136 * @dev: device of RPU instance
137 * @np: device node of RPU instance
138 * @tcm_bank_count: number TCM banks accessible to this RPU
139 * @tcm_banks: array of each TCM bank data
140 * @rproc: rproc handle
141 * @rsc_tbl_size: resource table size retrieved from remote
142 * @pm_domain_id: RPU CPU power domain id
143 * @ipi: pointer to mailbox information
144 */
145 struct zynqmp_r5_core {
146 void __iomem *rsc_tbl_va;
147 struct zynqmp_sram_bank *sram;
148 int num_sram;
149 struct device *dev;
150 struct device_node *np;
151 int tcm_bank_count;
152 struct mem_bank_data **tcm_banks;
153 struct rproc *rproc;
154 u32 rsc_tbl_size;
155 u32 pm_domain_id;
156 struct mbox_info *ipi;
157 };
158
159 /**
160 * struct zynqmp_r5_cluster
161 *
162 * @dev: r5f subsystem cluster device node
163 * @mode: cluster mode of type zynqmp_r5_cluster_mode
164 * @core_count: number of r5 cores used for this cluster mode
165 * @r5_cores: Array of pointers pointing to r5 core
166 */
167 struct zynqmp_r5_cluster {
168 struct device *dev;
169 enum zynqmp_r5_cluster_mode mode;
170 int core_count;
171 struct zynqmp_r5_core **r5_cores;
172 };
173
174 /**
175 * event_notified_idr_cb() - callback for vq_interrupt per notifyid
176 * @id: rproc->notify id
177 * @ptr: pointer to idr private data
178 * @data: data passed to idr_for_each callback
179 *
180 * Pass notification to remoteproc virtio
181 *
182 * Return: 0. having return is to satisfy the idr_for_each() function
183 * pointer input argument requirement.
184 **/
event_notified_idr_cb(int id,void * ptr,void * data)185 static int event_notified_idr_cb(int id, void *ptr, void *data)
186 {
187 struct rproc *rproc = data;
188
189 if (rproc_vq_interrupt(rproc, id) == IRQ_NONE)
190 dev_dbg(&rproc->dev, "data not found for vqid=%d\n", id);
191
192 return 0;
193 }
194
195 /**
196 * handle_event_notified() - remoteproc notification work function
197 * @work: pointer to the work structure
198 *
199 * It checks each registered remoteproc notify IDs.
200 */
handle_event_notified(struct work_struct * work)201 static void handle_event_notified(struct work_struct *work)
202 {
203 struct mbox_info *ipi;
204 struct rproc *rproc;
205
206 ipi = container_of(work, struct mbox_info, mbox_work);
207 rproc = ipi->r5_core->rproc;
208
209 /*
210 * We only use IPI for interrupt. The RPU firmware side may or may
211 * not write the notifyid when it trigger IPI.
212 * And thus, we scan through all the registered notifyids and
213 * find which one is valid to get the message.
214 * Even if message from firmware is NULL, we attempt to get vqid
215 */
216 idr_for_each(&rproc->notifyids, event_notified_idr_cb, rproc);
217 }
218
219 /**
220 * zynqmp_r5_mb_rx_cb() - receive channel mailbox callback
221 * @cl: mailbox client
222 * @msg: message pointer
223 *
224 * Receive data from ipi buffer, ack interrupt and then
225 * it will schedule the R5 notification work.
226 */
zynqmp_r5_mb_rx_cb(struct mbox_client * cl,void * msg)227 static void zynqmp_r5_mb_rx_cb(struct mbox_client *cl, void *msg)
228 {
229 struct zynqmp_ipi_message *ipi_msg, *buf_msg;
230 struct mbox_info *ipi;
231 size_t len;
232
233 ipi = container_of(cl, struct mbox_info, mbox_cl);
234
235 /* copy data from ipi buffer to r5_core */
236 ipi_msg = (struct zynqmp_ipi_message *)msg;
237 buf_msg = (struct zynqmp_ipi_message *)ipi->rx_mc_buf;
238 len = ipi_msg->len;
239 if (len > IPI_BUF_LEN_MAX) {
240 dev_warn(cl->dev, "msg size exceeded than %d\n",
241 IPI_BUF_LEN_MAX);
242 len = IPI_BUF_LEN_MAX;
243 }
244 buf_msg->len = len;
245 memcpy(buf_msg->data, ipi_msg->data, len);
246
247 /* received and processed interrupt ack */
248 if (mbox_send_message(ipi->rx_chan, NULL) < 0)
249 dev_err(cl->dev, "ack failed to mbox rx_chan\n");
250
251 schedule_work(&ipi->mbox_work);
252 }
253
254 /**
255 * zynqmp_r5_setup_mbox() - Setup mailboxes related properties
256 * this is used for each individual R5 core
257 *
258 * @cdev: child node device
259 *
260 * Function to setup mailboxes related properties
261 * return : NULL if failed else pointer to mbox_info
262 */
zynqmp_r5_setup_mbox(struct device * cdev)263 static struct mbox_info *zynqmp_r5_setup_mbox(struct device *cdev)
264 {
265 struct mbox_client *mbox_cl;
266 struct mbox_info *ipi;
267
268 ipi = kzalloc(sizeof(*ipi), GFP_KERNEL);
269 if (!ipi)
270 return NULL;
271
272 mbox_cl = &ipi->mbox_cl;
273 mbox_cl->rx_callback = zynqmp_r5_mb_rx_cb;
274 mbox_cl->tx_block = false;
275 mbox_cl->knows_txdone = false;
276 mbox_cl->tx_done = NULL;
277 mbox_cl->dev = cdev;
278
279 /* Request TX and RX channels */
280 ipi->tx_chan = mbox_request_channel_byname(mbox_cl, "tx");
281 if (IS_ERR(ipi->tx_chan)) {
282 ipi->tx_chan = NULL;
283 kfree(ipi);
284 dev_warn(cdev, "mbox tx channel request failed\n");
285 return NULL;
286 }
287
288 ipi->rx_chan = mbox_request_channel_byname(mbox_cl, "rx");
289 if (IS_ERR(ipi->rx_chan)) {
290 mbox_free_channel(ipi->tx_chan);
291 ipi->rx_chan = NULL;
292 ipi->tx_chan = NULL;
293 kfree(ipi);
294 dev_warn(cdev, "mbox rx channel request failed\n");
295 return NULL;
296 }
297
298 INIT_WORK(&ipi->mbox_work, handle_event_notified);
299
300 return ipi;
301 }
302
zynqmp_r5_free_mbox(struct mbox_info * ipi)303 static void zynqmp_r5_free_mbox(struct mbox_info *ipi)
304 {
305 if (!ipi)
306 return;
307
308 if (ipi->tx_chan) {
309 mbox_free_channel(ipi->tx_chan);
310 ipi->tx_chan = NULL;
311 }
312
313 if (ipi->rx_chan) {
314 mbox_free_channel(ipi->rx_chan);
315 ipi->rx_chan = NULL;
316 }
317
318 kfree(ipi);
319 }
320
321 /*
322 * zynqmp_r5_core_kick() - kick a firmware if mbox is provided
323 * @rproc: r5 core's corresponding rproc structure
324 * @vqid: virtqueue ID
325 */
zynqmp_r5_rproc_kick(struct rproc * rproc,int vqid)326 static void zynqmp_r5_rproc_kick(struct rproc *rproc, int vqid)
327 {
328 struct zynqmp_r5_core *r5_core = rproc->priv;
329 struct device *dev = r5_core->dev;
330 struct zynqmp_ipi_message *mb_msg;
331 struct mbox_info *ipi;
332 int ret;
333
334 ipi = r5_core->ipi;
335 if (!ipi)
336 return;
337
338 mb_msg = (struct zynqmp_ipi_message *)ipi->tx_mc_buf;
339 memcpy(mb_msg->data, &vqid, sizeof(vqid));
340 mb_msg->len = sizeof(vqid);
341 ret = mbox_send_message(ipi->tx_chan, mb_msg);
342 if (ret < 0)
343 dev_warn(dev, "failed to send message\n");
344 }
345
346 /*
347 * zynqmp_r5_rproc_start()
348 * @rproc: single R5 core's corresponding rproc instance
349 *
350 * Start R5 Core from designated boot address.
351 *
352 * return 0 on success, otherwise non-zero value on failure
353 */
zynqmp_r5_rproc_start(struct rproc * rproc)354 static int zynqmp_r5_rproc_start(struct rproc *rproc)
355 {
356 struct zynqmp_r5_core *r5_core = rproc->priv;
357 enum rpu_boot_mem bootmem;
358 int ret;
359
360 /*
361 * The exception vector pointers (EVP) refer to the base-address of
362 * exception vectors (for reset, IRQ, FIQ, etc). The reset-vector
363 * starts at the base-address and subsequent vectors are on 4-byte
364 * boundaries.
365 *
366 * Exception vectors can start either from 0x0000_0000 (LOVEC) or
367 * from 0xFFFF_0000 (HIVEC) which is mapped in the OCM (On-Chip Memory)
368 *
369 * Usually firmware will put Exception vectors at LOVEC.
370 *
371 * It is not recommend that you change the exception vector.
372 * Changing the EVP to HIVEC will result in increased interrupt latency
373 * and jitter. Also, if the OCM is secured and the Cortex-R5F processor
374 * is non-secured, then the Cortex-R5F processor cannot access the
375 * HIVEC exception vectors in the OCM.
376 */
377 bootmem = (rproc->bootaddr >= 0xFFFC0000) ?
378 PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC;
379
380 dev_dbg(r5_core->dev, "RPU boot addr 0x%llx from %s.", rproc->bootaddr,
381 bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM");
382
383 ret = zynqmp_pm_request_wake(r5_core->pm_domain_id, 1,
384 bootmem, ZYNQMP_PM_REQUEST_ACK_NO);
385 if (ret)
386 dev_err(r5_core->dev,
387 "failed to start RPU = 0x%x\n", r5_core->pm_domain_id);
388 return ret;
389 }
390
391 /*
392 * zynqmp_r5_rproc_stop()
393 * @rproc: single R5 core's corresponding rproc instance
394 *
395 * Power down R5 Core.
396 *
397 * return 0 on success, otherwise non-zero value on failure
398 */
zynqmp_r5_rproc_stop(struct rproc * rproc)399 static int zynqmp_r5_rproc_stop(struct rproc *rproc)
400 {
401 struct zynqmp_r5_core *r5_core = rproc->priv;
402 int ret;
403
404 ret = zynqmp_pm_force_pwrdwn(r5_core->pm_domain_id,
405 ZYNQMP_PM_REQUEST_ACK_BLOCKING);
406 if (ret)
407 dev_err(r5_core->dev, "failed to stop remoteproc RPU %d\n", ret);
408
409 return ret;
410 }
411
412 /*
413 * zynqmp_r5_mem_region_map()
414 * @rproc: single R5 core's corresponding rproc instance
415 * @mem: mem descriptor to map reserved memory-regions
416 *
417 * Callback to map va for memory-region's carveout.
418 *
419 * return 0 on success, otherwise non-zero value on failure
420 */
zynqmp_r5_mem_region_map(struct rproc * rproc,struct rproc_mem_entry * mem)421 static int zynqmp_r5_mem_region_map(struct rproc *rproc,
422 struct rproc_mem_entry *mem)
423 {
424 void __iomem *va;
425
426 va = ioremap_wc(mem->dma, mem->len);
427 if (IS_ERR_OR_NULL(va))
428 return -ENOMEM;
429
430 mem->va = (void *)va;
431
432 return 0;
433 }
434
435 /*
436 * zynqmp_r5_rproc_mem_unmap
437 * @rproc: single R5 core's corresponding rproc instance
438 * @mem: mem entry to unmap
439 *
440 * Unmap memory-region carveout
441 *
442 * return: always returns 0
443 */
zynqmp_r5_mem_region_unmap(struct rproc * rproc,struct rproc_mem_entry * mem)444 static int zynqmp_r5_mem_region_unmap(struct rproc *rproc,
445 struct rproc_mem_entry *mem)
446 {
447 iounmap((void __iomem *)mem->va);
448 return 0;
449 }
450
451 /*
452 * add_mem_regions_carveout()
453 * @rproc: single R5 core's corresponding rproc instance
454 *
455 * Construct rproc mem carveouts from memory-region property nodes
456 *
457 * return 0 on success, otherwise non-zero value on failure
458 */
add_mem_regions_carveout(struct rproc * rproc)459 static int add_mem_regions_carveout(struct rproc *rproc)
460 {
461 struct rproc_mem_entry *rproc_mem;
462 struct zynqmp_r5_core *r5_core;
463 struct of_phandle_iterator it;
464 struct reserved_mem *rmem;
465 int i = 0;
466
467 r5_core = rproc->priv;
468
469 /* Register associated reserved memory regions */
470 of_phandle_iterator_init(&it, r5_core->np, "memory-region", NULL, 0);
471
472 while (of_phandle_iterator_next(&it) == 0) {
473 rmem = of_reserved_mem_lookup(it.node);
474 if (!rmem) {
475 of_node_put(it.node);
476 dev_err(&rproc->dev, "unable to acquire memory-region\n");
477 return -EINVAL;
478 }
479
480 if (!strcmp(it.node->name, "vdev0buffer")) {
481 /* Init reserved memory for vdev buffer */
482 rproc_mem = rproc_of_resm_mem_entry_init(&rproc->dev, i,
483 rmem->size,
484 rmem->base,
485 it.node->name);
486 } else {
487 /* Register associated reserved memory regions */
488 rproc_mem = rproc_mem_entry_init(&rproc->dev, NULL,
489 (dma_addr_t)rmem->base,
490 rmem->size, rmem->base,
491 zynqmp_r5_mem_region_map,
492 zynqmp_r5_mem_region_unmap,
493 it.node->name);
494 }
495
496 if (!rproc_mem) {
497 of_node_put(it.node);
498 return -ENOMEM;
499 }
500
501 rproc_add_carveout(rproc, rproc_mem);
502 rproc_coredump_add_segment(rproc, rmem->base, rmem->size);
503
504 dev_dbg(&rproc->dev, "reserved mem carveout %s addr=%llx, size=0x%llx",
505 it.node->name, rmem->base, rmem->size);
506 i++;
507 }
508
509 return 0;
510 }
511
add_sram_carveouts(struct rproc * rproc)512 static int add_sram_carveouts(struct rproc *rproc)
513 {
514 struct zynqmp_r5_core *r5_core = rproc->priv;
515 struct rproc_mem_entry *rproc_mem;
516 struct zynqmp_sram_bank *sram;
517 dma_addr_t dma_addr;
518 size_t len;
519 int da, i;
520
521 for (i = 0; i < r5_core->num_sram; i++) {
522 sram = &r5_core->sram[i];
523
524 dma_addr = (dma_addr_t)sram->sram_res.start;
525
526 len = resource_size(&sram->sram_res);
527 da = sram->da;
528
529 rproc_mem = rproc_mem_entry_init(&rproc->dev, NULL,
530 dma_addr,
531 len, da,
532 zynqmp_r5_mem_region_map,
533 zynqmp_r5_mem_region_unmap,
534 sram->sram_res.name);
535 if (!rproc_mem) {
536 dev_err(&rproc->dev, "failed to add sram %s da=0x%x, size=0x%lx",
537 sram->sram_res.name, da, len);
538 return -ENOMEM;
539 }
540
541 rproc_add_carveout(rproc, rproc_mem);
542 rproc_coredump_add_segment(rproc, da, len);
543
544 dev_dbg(&rproc->dev, "sram carveout %s addr=%llx, da=0x%x, size=0x%lx",
545 sram->sram_res.name, dma_addr, da, len);
546 }
547
548 return 0;
549 }
550
551 /*
552 * tcm_mem_unmap()
553 * @rproc: single R5 core's corresponding rproc instance
554 * @mem: tcm mem entry to unmap
555 *
556 * Unmap TCM banks when powering down R5 core.
557 *
558 * return always 0
559 */
tcm_mem_unmap(struct rproc * rproc,struct rproc_mem_entry * mem)560 static int tcm_mem_unmap(struct rproc *rproc, struct rproc_mem_entry *mem)
561 {
562 iounmap((void __iomem *)mem->va);
563
564 return 0;
565 }
566
567 /*
568 * tcm_mem_map()
569 * @rproc: single R5 core's corresponding rproc instance
570 * @mem: tcm memory entry descriptor
571 *
572 * Given TCM bank entry, this func setup virtual address for TCM bank
573 * remoteproc carveout. It also takes care of va to da address translation
574 *
575 * return 0 on success, otherwise non-zero value on failure
576 */
tcm_mem_map(struct rproc * rproc,struct rproc_mem_entry * mem)577 static int tcm_mem_map(struct rproc *rproc,
578 struct rproc_mem_entry *mem)
579 {
580 void __iomem *va;
581
582 va = ioremap_wc(mem->dma, mem->len);
583 if (IS_ERR_OR_NULL(va))
584 return -ENOMEM;
585
586 /* Update memory entry va */
587 mem->va = (void *)va;
588
589 /* clear TCMs */
590 memset_io(va, 0, mem->len);
591
592 return 0;
593 }
594
595 /*
596 * add_tcm_banks()
597 * @rproc: single R5 core's corresponding rproc instance
598 *
599 * allocate and add remoteproc carveout for TCM memory
600 *
601 * return 0 on success, otherwise non-zero value on failure
602 */
add_tcm_banks(struct rproc * rproc)603 static int add_tcm_banks(struct rproc *rproc)
604 {
605 struct rproc_mem_entry *rproc_mem;
606 struct zynqmp_r5_core *r5_core;
607 int i, num_banks, ret;
608 phys_addr_t bank_addr;
609 struct device *dev;
610 u32 pm_domain_id;
611 size_t bank_size;
612 char *bank_name;
613 u32 da;
614
615 r5_core = rproc->priv;
616 dev = r5_core->dev;
617 num_banks = r5_core->tcm_bank_count;
618
619 /*
620 * Power-on Each 64KB TCM,
621 * register its address space, map and unmap functions
622 * and add carveouts accordingly
623 */
624 for (i = 0; i < num_banks; i++) {
625 bank_addr = r5_core->tcm_banks[i]->addr;
626 da = r5_core->tcm_banks[i]->da;
627 bank_name = r5_core->tcm_banks[i]->bank_name;
628 bank_size = r5_core->tcm_banks[i]->size;
629 pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
630
631 ret = zynqmp_pm_request_node(pm_domain_id,
632 ZYNQMP_PM_CAPABILITY_ACCESS, 0,
633 ZYNQMP_PM_REQUEST_ACK_BLOCKING);
634 if (ret < 0) {
635 dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id);
636 goto release_tcm;
637 }
638
639 dev_dbg(dev, "TCM carveout %s addr=%llx, da=0x%x, size=0x%lx",
640 bank_name, bank_addr, da, bank_size);
641
642 /*
643 * In DETACHED state firmware is already running so no need to
644 * request add TCM registers. However, request TCM PD node to let
645 * platform management firmware know that TCM is in use.
646 */
647 if (rproc->state == RPROC_DETACHED)
648 continue;
649
650 rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr,
651 bank_size, da,
652 tcm_mem_map, tcm_mem_unmap,
653 bank_name);
654 if (!rproc_mem) {
655 ret = -ENOMEM;
656 zynqmp_pm_release_node(pm_domain_id);
657 goto release_tcm;
658 }
659
660 rproc_add_carveout(rproc, rproc_mem);
661 rproc_coredump_add_segment(rproc, da, bank_size);
662 }
663
664 return 0;
665
666 release_tcm:
667 /* If failed, Turn off all TCM banks turned on before */
668 for (i--; i >= 0; i--) {
669 pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
670 zynqmp_pm_release_node(pm_domain_id);
671 }
672 return ret;
673 }
674
675 /*
676 * zynqmp_r5_parse_fw()
677 * @rproc: single R5 core's corresponding rproc instance
678 * @fw: ptr to firmware to be loaded onto r5 core
679 *
680 * get resource table if available
681 *
682 * return 0 on success, otherwise non-zero value on failure
683 */
zynqmp_r5_parse_fw(struct rproc * rproc,const struct firmware * fw)684 static int zynqmp_r5_parse_fw(struct rproc *rproc, const struct firmware *fw)
685 {
686 int ret;
687
688 ret = rproc_elf_load_rsc_table(rproc, fw);
689 if (ret == -EINVAL) {
690 /*
691 * resource table only required for IPC.
692 * if not present, this is not necessarily an error;
693 * for example, loading r5 hello world application
694 * so simply inform user and keep going.
695 */
696 dev_info(&rproc->dev, "no resource table found.\n");
697 ret = 0;
698 }
699 return ret;
700 }
701
702 /**
703 * zynqmp_r5_rproc_prepare()
704 * adds carveouts for TCM bank and reserved memory regions
705 *
706 * @rproc: Device node of each rproc
707 *
708 * Return: 0 for success else < 0 error code
709 */
zynqmp_r5_rproc_prepare(struct rproc * rproc)710 static int zynqmp_r5_rproc_prepare(struct rproc *rproc)
711 {
712 int ret;
713
714 ret = add_tcm_banks(rproc);
715 if (ret) {
716 dev_err(&rproc->dev, "failed to get TCM banks, err %d\n", ret);
717 return ret;
718 }
719
720 ret = add_mem_regions_carveout(rproc);
721 if (ret) {
722 dev_err(&rproc->dev, "failed to get reserve mem regions %d\n", ret);
723 return ret;
724 }
725
726 ret = add_sram_carveouts(rproc);
727 if (ret) {
728 dev_err(&rproc->dev, "failed to get sram carveout %d\n", ret);
729 return ret;
730 }
731
732 return 0;
733 }
734
735 /**
736 * zynqmp_r5_rproc_unprepare()
737 * Turns off TCM banks using power-domain id
738 *
739 * @rproc: Device node of each rproc
740 *
741 * Return: always 0
742 */
zynqmp_r5_rproc_unprepare(struct rproc * rproc)743 static int zynqmp_r5_rproc_unprepare(struct rproc *rproc)
744 {
745 struct zynqmp_r5_core *r5_core;
746 u32 pm_domain_id;
747 int i;
748
749 r5_core = rproc->priv;
750
751 for (i = 0; i < r5_core->tcm_bank_count; i++) {
752 pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
753 if (zynqmp_pm_release_node(pm_domain_id))
754 dev_warn(r5_core->dev,
755 "can't turn off TCM bank 0x%x", pm_domain_id);
756 }
757
758 return 0;
759 }
760
zynqmp_r5_get_loaded_rsc_table(struct rproc * rproc,size_t * size)761 static struct resource_table *zynqmp_r5_get_loaded_rsc_table(struct rproc *rproc,
762 size_t *size)
763 {
764 struct zynqmp_r5_core *r5_core;
765
766 r5_core = rproc->priv;
767
768 *size = r5_core->rsc_tbl_size;
769
770 return (struct resource_table *)r5_core->rsc_tbl_va;
771 }
772
zynqmp_r5_get_rsc_table_va(struct zynqmp_r5_core * r5_core)773 static int zynqmp_r5_get_rsc_table_va(struct zynqmp_r5_core *r5_core)
774 {
775 struct resource_table *rsc_tbl_addr;
776 struct device *dev = r5_core->dev;
777 struct rsc_tbl_data *rsc_data_va;
778 struct resource res_mem;
779 struct device_node *np;
780 int ret;
781
782 /*
783 * It is expected from remote processor firmware to provide resource
784 * table address via struct rsc_tbl_data data structure.
785 * Start address of first entry under "memory-region" property list
786 * contains that data structure which holds resource table address, size
787 * and some magic number to validate correct resource table entry.
788 */
789 np = of_parse_phandle(r5_core->np, "memory-region", 0);
790 if (!np) {
791 dev_err(dev, "failed to get memory region dev node\n");
792 return -EINVAL;
793 }
794
795 ret = of_address_to_resource(np, 0, &res_mem);
796 of_node_put(np);
797 if (ret) {
798 dev_err(dev, "failed to get memory-region resource addr\n");
799 return -EINVAL;
800 }
801
802 rsc_data_va = (struct rsc_tbl_data *)ioremap_wc(res_mem.start,
803 sizeof(struct rsc_tbl_data));
804 if (!rsc_data_va) {
805 dev_err(dev, "failed to map resource table data address\n");
806 return -EIO;
807 }
808
809 /*
810 * If RSC_TBL_XLNX_MAGIC number and its complement isn't found then
811 * do not consider resource table address valid and don't attach
812 */
813 if (rsc_data_va->magic_num != RSC_TBL_XLNX_MAGIC ||
814 rsc_data_va->comp_magic_num != ~RSC_TBL_XLNX_MAGIC) {
815 dev_dbg(dev, "invalid magic number, won't attach\n");
816 return -EINVAL;
817 }
818
819 r5_core->rsc_tbl_va = ioremap_wc(rsc_data_va->rsc_tbl,
820 rsc_data_va->rsc_tbl_size);
821 if (!r5_core->rsc_tbl_va) {
822 dev_err(dev, "failed to get resource table va\n");
823 return -EINVAL;
824 }
825
826 rsc_tbl_addr = (struct resource_table *)r5_core->rsc_tbl_va;
827
828 /*
829 * As of now resource table version 1 is expected. Don't fail to attach
830 * but warn users about it.
831 */
832 if (rsc_tbl_addr->ver != 1)
833 dev_warn(dev, "unexpected resource table version %d\n",
834 rsc_tbl_addr->ver);
835
836 r5_core->rsc_tbl_size = rsc_data_va->rsc_tbl_size;
837
838 iounmap((void __iomem *)rsc_data_va);
839
840 return 0;
841 }
842
zynqmp_r5_attach(struct rproc * rproc)843 static int zynqmp_r5_attach(struct rproc *rproc)
844 {
845 dev_dbg(&rproc->dev, "rproc %d attached\n", rproc->index);
846
847 return 0;
848 }
849
zynqmp_r5_detach(struct rproc * rproc)850 static int zynqmp_r5_detach(struct rproc *rproc)
851 {
852 /*
853 * Generate last notification to remote after clearing virtio flag.
854 * Remote can avoid polling on virtio reset flag if kick is generated
855 * during detach by host and check virtio reset flag on kick interrupt.
856 */
857 zynqmp_r5_rproc_kick(rproc, 0);
858
859 return 0;
860 }
861
862 static const struct rproc_ops zynqmp_r5_rproc_ops = {
863 .prepare = zynqmp_r5_rproc_prepare,
864 .unprepare = zynqmp_r5_rproc_unprepare,
865 .start = zynqmp_r5_rproc_start,
866 .stop = zynqmp_r5_rproc_stop,
867 .load = rproc_elf_load_segments,
868 .parse_fw = zynqmp_r5_parse_fw,
869 .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
870 .sanity_check = rproc_elf_sanity_check,
871 .get_boot_addr = rproc_elf_get_boot_addr,
872 .kick = zynqmp_r5_rproc_kick,
873 .get_loaded_rsc_table = zynqmp_r5_get_loaded_rsc_table,
874 .attach = zynqmp_r5_attach,
875 .detach = zynqmp_r5_detach,
876 };
877
878 /**
879 * zynqmp_r5_add_rproc_core()
880 * Allocate and add struct rproc object for each r5f core
881 * This is called for each individual r5f core
882 *
883 * @cdev: Device node of each r5 core
884 *
885 * Return: zynqmp_r5_core object for success else error code pointer
886 */
zynqmp_r5_add_rproc_core(struct device * cdev)887 static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev)
888 {
889 struct zynqmp_r5_core *r5_core;
890 struct rproc *r5_rproc;
891 int ret;
892
893 /* Set up DMA mask */
894 ret = dma_set_coherent_mask(cdev, DMA_BIT_MASK(32));
895 if (ret)
896 return ERR_PTR(ret);
897
898 /* Allocate remoteproc instance */
899 r5_rproc = rproc_alloc(cdev, dev_name(cdev),
900 &zynqmp_r5_rproc_ops,
901 NULL, sizeof(struct zynqmp_r5_core));
902 if (!r5_rproc) {
903 dev_err(cdev, "failed to allocate memory for rproc instance\n");
904 return ERR_PTR(-ENOMEM);
905 }
906
907 rproc_coredump_set_elf_info(r5_rproc, ELFCLASS32, EM_ARM);
908
909 r5_rproc->recovery_disabled = true;
910 r5_rproc->has_iommu = false;
911 r5_rproc->auto_boot = false;
912 r5_core = r5_rproc->priv;
913 r5_core->dev = cdev;
914 r5_core->np = dev_of_node(cdev);
915 if (!r5_core->np) {
916 dev_err(cdev, "can't get device node for r5 core\n");
917 ret = -EINVAL;
918 goto free_rproc;
919 }
920
921 /* Add R5 remoteproc core */
922 ret = rproc_add(r5_rproc);
923 if (ret) {
924 dev_err(cdev, "failed to add r5 remoteproc\n");
925 goto free_rproc;
926 }
927
928 /*
929 * If firmware is already available in the memory then move rproc state
930 * to DETACHED. Firmware can be preloaded via debugger or by any other
931 * agent (processors) in the system.
932 * If firmware isn't available in the memory and resource table isn't
933 * found, then rproc state remains OFFLINE.
934 */
935 if (!zynqmp_r5_get_rsc_table_va(r5_core))
936 r5_rproc->state = RPROC_DETACHED;
937
938 r5_core->rproc = r5_rproc;
939 return r5_core;
940
941 free_rproc:
942 rproc_free(r5_rproc);
943 return ERR_PTR(ret);
944 }
945
zynqmp_r5_get_sram_banks(struct zynqmp_r5_core * r5_core)946 static int zynqmp_r5_get_sram_banks(struct zynqmp_r5_core *r5_core)
947 {
948 struct device_node *np = r5_core->np;
949 struct device *dev = r5_core->dev;
950 struct zynqmp_sram_bank *sram;
951 struct device_node *sram_np;
952 int num_sram, i, ret;
953 u64 abs_addr, size;
954
955 /* "sram" is optional property. Do not fail, if unavailable. */
956 if (!of_property_present(r5_core->np, "sram"))
957 return 0;
958
959 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
960 if (num_sram <= 0) {
961 dev_err(dev, "Invalid sram property, ret = %d\n",
962 num_sram);
963 return -EINVAL;
964 }
965
966 sram = devm_kcalloc(dev, num_sram,
967 sizeof(struct zynqmp_sram_bank), GFP_KERNEL);
968 if (!sram)
969 return -ENOMEM;
970
971 for (i = 0; i < num_sram; i++) {
972 sram_np = of_parse_phandle(np, "sram", i);
973 if (!sram_np) {
974 dev_err(dev, "failed to get sram %d phandle\n", i);
975 return -EINVAL;
976 }
977
978 if (!of_device_is_available(sram_np)) {
979 dev_err(dev, "sram device not available\n");
980 ret = -EINVAL;
981 goto fail_sram_get;
982 }
983
984 ret = of_address_to_resource(sram_np, 0, &sram[i].sram_res);
985 if (ret) {
986 dev_err(dev, "addr to res failed\n");
987 goto fail_sram_get;
988 }
989
990 /* Get SRAM device address */
991 ret = of_property_read_reg(sram_np, i, &abs_addr, &size);
992 if (ret) {
993 dev_err(dev, "failed to get reg property\n");
994 goto fail_sram_get;
995 }
996
997 sram[i].da = (u32)abs_addr;
998
999 of_node_put(sram_np);
1000
1001 dev_dbg(dev, "sram %d: name=%s, addr=0x%llx, da=0x%x, size=0x%llx\n",
1002 i, sram[i].sram_res.name, sram[i].sram_res.start,
1003 sram[i].da, resource_size(&sram[i].sram_res));
1004 }
1005
1006 r5_core->sram = sram;
1007 r5_core->num_sram = num_sram;
1008
1009 return 0;
1010
1011 fail_sram_get:
1012 of_node_put(sram_np);
1013
1014 return ret;
1015 }
1016
zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster * cluster)1017 static int zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster *cluster)
1018 {
1019 int i, j, tcm_bank_count, ret, tcm_pd_idx, pd_count;
1020 struct of_phandle_args out_args;
1021 struct zynqmp_r5_core *r5_core;
1022 struct platform_device *cpdev;
1023 struct mem_bank_data *tcm;
1024 struct device_node *np;
1025 struct resource *res;
1026 u64 abs_addr, size;
1027 struct device *dev;
1028
1029 for (i = 0; i < cluster->core_count; i++) {
1030 r5_core = cluster->r5_cores[i];
1031 dev = r5_core->dev;
1032 np = r5_core->np;
1033
1034 pd_count = of_count_phandle_with_args(np, "power-domains",
1035 "#power-domain-cells");
1036
1037 if (pd_count <= 0) {
1038 dev_err(dev, "invalid power-domains property, %d\n", pd_count);
1039 return -EINVAL;
1040 }
1041
1042 /* First entry in power-domains list is for r5 core, rest for TCM. */
1043 tcm_bank_count = pd_count - 1;
1044
1045 if (tcm_bank_count <= 0) {
1046 dev_err(dev, "invalid TCM count %d\n", tcm_bank_count);
1047 return -EINVAL;
1048 }
1049
1050 r5_core->tcm_banks = devm_kcalloc(dev, tcm_bank_count,
1051 sizeof(struct mem_bank_data *),
1052 GFP_KERNEL);
1053 if (!r5_core->tcm_banks)
1054 return -ENOMEM;
1055
1056 r5_core->tcm_bank_count = tcm_bank_count;
1057 for (j = 0, tcm_pd_idx = 1; j < tcm_bank_count; j++, tcm_pd_idx++) {
1058 tcm = devm_kzalloc(dev, sizeof(struct mem_bank_data),
1059 GFP_KERNEL);
1060 if (!tcm)
1061 return -ENOMEM;
1062
1063 r5_core->tcm_banks[j] = tcm;
1064
1065 /* Get power-domains id of TCM. */
1066 ret = of_parse_phandle_with_args(np, "power-domains",
1067 "#power-domain-cells",
1068 tcm_pd_idx, &out_args);
1069 if (ret) {
1070 dev_err(r5_core->dev,
1071 "failed to get tcm %d pm domain, ret %d\n",
1072 tcm_pd_idx, ret);
1073 return ret;
1074 }
1075 tcm->pm_domain_id = out_args.args[0];
1076 of_node_put(out_args.np);
1077
1078 /* Get TCM address without translation. */
1079 ret = of_property_read_reg(np, j, &abs_addr, &size);
1080 if (ret) {
1081 dev_err(dev, "failed to get reg property\n");
1082 return ret;
1083 }
1084
1085 /*
1086 * Remote processor can address only 32 bits
1087 * so convert 64-bits into 32-bits. This will discard
1088 * any unwanted upper 32-bits.
1089 */
1090 tcm->da = (u32)abs_addr;
1091 tcm->size = (u32)size;
1092
1093 cpdev = to_platform_device(dev);
1094 res = platform_get_resource(cpdev, IORESOURCE_MEM, j);
1095 if (!res) {
1096 dev_err(dev, "failed to get tcm resource\n");
1097 return -EINVAL;
1098 }
1099
1100 tcm->addr = (u32)res->start;
1101 tcm->bank_name = (char *)res->name;
1102 res = devm_request_mem_region(dev, tcm->addr, tcm->size,
1103 tcm->bank_name);
1104 if (!res) {
1105 dev_err(dev, "failed to request tcm resource\n");
1106 return -EINVAL;
1107 }
1108 }
1109 }
1110
1111 return 0;
1112 }
1113
1114 /**
1115 * zynqmp_r5_get_tcm_node()
1116 * Ideally this function should parse tcm node and store information
1117 * in r5_core instance. For now, Hardcoded TCM information is used.
1118 * This approach is used as TCM bindings for system-dt is being developed
1119 *
1120 * @cluster: pointer to zynqmp_r5_cluster type object
1121 *
1122 * Return: 0 for success and < 0 error code for failure.
1123 */
zynqmp_r5_get_tcm_node(struct zynqmp_r5_cluster * cluster)1124 static int zynqmp_r5_get_tcm_node(struct zynqmp_r5_cluster *cluster)
1125 {
1126 const struct mem_bank_data *zynqmp_tcm_banks;
1127 struct device *dev = cluster->dev;
1128 struct zynqmp_r5_core *r5_core;
1129 int tcm_bank_count, tcm_node;
1130 int i, j;
1131
1132 if (cluster->mode == SPLIT_MODE) {
1133 zynqmp_tcm_banks = zynqmp_tcm_banks_split;
1134 tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks_split);
1135 } else {
1136 zynqmp_tcm_banks = zynqmp_tcm_banks_lockstep;
1137 tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks_lockstep);
1138 }
1139
1140 /* count per core tcm banks */
1141 tcm_bank_count = tcm_bank_count / cluster->core_count;
1142
1143 /*
1144 * r5 core 0 will use all of TCM banks in lockstep mode.
1145 * In split mode, r5 core0 will use 128k and r5 core1 will use another
1146 * 128k. Assign TCM banks to each core accordingly
1147 */
1148 tcm_node = 0;
1149 for (i = 0; i < cluster->core_count; i++) {
1150 r5_core = cluster->r5_cores[i];
1151 r5_core->tcm_banks = devm_kcalloc(dev, tcm_bank_count,
1152 sizeof(struct mem_bank_data *),
1153 GFP_KERNEL);
1154 if (!r5_core->tcm_banks)
1155 return -ENOMEM;
1156
1157 for (j = 0; j < tcm_bank_count; j++) {
1158 /*
1159 * Use pre-defined TCM reg values.
1160 * Eventually this should be replaced by values
1161 * parsed from dts.
1162 */
1163 r5_core->tcm_banks[j] =
1164 (struct mem_bank_data *)&zynqmp_tcm_banks[tcm_node];
1165 tcm_node++;
1166 }
1167
1168 r5_core->tcm_bank_count = tcm_bank_count;
1169 }
1170
1171 return 0;
1172 }
1173
1174 /*
1175 * zynqmp_r5_core_init()
1176 * Create and initialize zynqmp_r5_core type object
1177 *
1178 * @cluster: pointer to zynqmp_r5_cluster type object
1179 * @fw_reg_val: value expected by firmware to configure RPU cluster mode
1180 * @tcm_mode: value expected by fw to configure TCM mode (lockstep or split)
1181 *
1182 * Return: 0 for success and error code for failure.
1183 */
zynqmp_r5_core_init(struct zynqmp_r5_cluster * cluster,enum rpu_oper_mode fw_reg_val,enum rpu_tcm_comb tcm_mode)1184 static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster,
1185 enum rpu_oper_mode fw_reg_val,
1186 enum rpu_tcm_comb tcm_mode)
1187 {
1188 struct device *dev = cluster->dev;
1189 struct zynqmp_r5_core *r5_core;
1190 int ret = -EINVAL, i;
1191
1192 r5_core = cluster->r5_cores[0];
1193
1194 /* Maintain backward compatibility for zynqmp by using hardcode TCM address. */
1195 if (of_property_present(r5_core->np, "reg"))
1196 ret = zynqmp_r5_get_tcm_node_from_dt(cluster);
1197 else if (device_is_compatible(dev, "xlnx,zynqmp-r5fss"))
1198 ret = zynqmp_r5_get_tcm_node(cluster);
1199
1200 if (ret) {
1201 dev_err(dev, "can't get tcm, err %d\n", ret);
1202 return ret;
1203 }
1204
1205 for (i = 0; i < cluster->core_count; i++) {
1206 r5_core = cluster->r5_cores[i];
1207
1208 /* Initialize r5 cores with power-domains parsed from dts */
1209 ret = of_property_read_u32_index(r5_core->np, "power-domains",
1210 1, &r5_core->pm_domain_id);
1211 if (ret) {
1212 dev_err(dev, "failed to get power-domains property\n");
1213 return ret;
1214 }
1215
1216 ret = zynqmp_pm_set_rpu_mode(r5_core->pm_domain_id, fw_reg_val);
1217 if (ret < 0) {
1218 dev_err(r5_core->dev, "failed to set RPU mode\n");
1219 return ret;
1220 }
1221
1222 if (of_property_present(dev_of_node(dev), "xlnx,tcm-mode") ||
1223 device_is_compatible(dev, "xlnx,zynqmp-r5fss")) {
1224 ret = zynqmp_pm_set_tcm_config(r5_core->pm_domain_id,
1225 tcm_mode);
1226 if (ret < 0) {
1227 dev_err(r5_core->dev, "failed to configure TCM\n");
1228 return ret;
1229 }
1230 }
1231
1232 ret = zynqmp_r5_get_sram_banks(r5_core);
1233 if (ret)
1234 return ret;
1235 }
1236
1237 return 0;
1238 }
1239
1240 /*
1241 * zynqmp_r5_cluster_init()
1242 * Create and initialize zynqmp_r5_cluster type object
1243 *
1244 * @cluster: pointer to zynqmp_r5_cluster type object
1245 *
1246 * Return: 0 for success and error code for failure.
1247 */
zynqmp_r5_cluster_init(struct zynqmp_r5_cluster * cluster)1248 static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster)
1249 {
1250 enum zynqmp_r5_cluster_mode cluster_mode = LOCKSTEP_MODE;
1251 struct device *dev = cluster->dev;
1252 struct device_node *dev_node = dev_of_node(dev);
1253 struct platform_device *child_pdev;
1254 struct zynqmp_r5_core **r5_cores;
1255 enum rpu_oper_mode fw_reg_val;
1256 struct device **child_devs;
1257 struct device_node *child;
1258 enum rpu_tcm_comb tcm_mode;
1259 int core_count, ret, i;
1260 struct mbox_info *ipi;
1261
1262 ret = of_property_read_u32(dev_node, "xlnx,cluster-mode", &cluster_mode);
1263
1264 /*
1265 * on success returns 0, if not defined then returns -EINVAL,
1266 * In that case, default is LOCKSTEP mode. Other than that
1267 * returns relative error code < 0.
1268 */
1269 if (ret != -EINVAL && ret != 0) {
1270 dev_err(dev, "Invalid xlnx,cluster-mode property\n");
1271 return ret;
1272 }
1273
1274 /*
1275 * For now driver only supports split mode and lockstep mode.
1276 * fail driver probe if either of that is not set in dts.
1277 */
1278 if (cluster_mode == LOCKSTEP_MODE) {
1279 fw_reg_val = PM_RPU_MODE_LOCKSTEP;
1280 } else if (cluster_mode == SPLIT_MODE) {
1281 fw_reg_val = PM_RPU_MODE_SPLIT;
1282 } else {
1283 dev_err(dev, "driver does not support cluster mode %d\n", cluster_mode);
1284 return -EINVAL;
1285 }
1286
1287 if (of_property_present(dev_node, "xlnx,tcm-mode")) {
1288 ret = of_property_read_u32(dev_node, "xlnx,tcm-mode", (u32 *)&tcm_mode);
1289 if (ret)
1290 return ret;
1291 } else if (device_is_compatible(dev, "xlnx,zynqmp-r5fss")) {
1292 if (cluster_mode == LOCKSTEP_MODE)
1293 tcm_mode = PM_RPU_TCM_COMB;
1294 else
1295 tcm_mode = PM_RPU_TCM_SPLIT;
1296 } else {
1297 tcm_mode = PM_RPU_TCM_COMB;
1298 }
1299
1300 /*
1301 * Number of cores is decided by number of child nodes of
1302 * r5f subsystem node in dts. If Split mode is used in dts
1303 * 2 child nodes are expected.
1304 * In lockstep mode if two child nodes are available,
1305 * only use first child node and consider it as core0
1306 * and ignore core1 dt node.
1307 */
1308 core_count = of_get_available_child_count(dev_node);
1309 if (core_count == 0) {
1310 dev_err(dev, "Invalid number of r5 cores %d", core_count);
1311 return -EINVAL;
1312 } else if (cluster_mode == SPLIT_MODE && core_count != 2) {
1313 dev_err(dev, "Invalid number of r5 cores for split mode\n");
1314 return -EINVAL;
1315 } else if (cluster_mode == LOCKSTEP_MODE && core_count == 2) {
1316 dev_warn(dev, "Only r5 core0 will be used\n");
1317 core_count = 1;
1318 }
1319
1320 child_devs = kcalloc(core_count, sizeof(struct device *), GFP_KERNEL);
1321 if (!child_devs)
1322 return -ENOMEM;
1323
1324 r5_cores = kcalloc(core_count,
1325 sizeof(struct zynqmp_r5_core *), GFP_KERNEL);
1326 if (!r5_cores) {
1327 kfree(child_devs);
1328 return -ENOMEM;
1329 }
1330
1331 i = 0;
1332 for_each_available_child_of_node(dev_node, child) {
1333 child_pdev = of_find_device_by_node(child);
1334 if (!child_pdev) {
1335 of_node_put(child);
1336 ret = -ENODEV;
1337 goto release_r5_cores;
1338 }
1339
1340 child_devs[i] = &child_pdev->dev;
1341
1342 /* create and add remoteproc instance of type struct rproc */
1343 r5_cores[i] = zynqmp_r5_add_rproc_core(&child_pdev->dev);
1344 if (IS_ERR(r5_cores[i])) {
1345 of_node_put(child);
1346 ret = PTR_ERR(r5_cores[i]);
1347 r5_cores[i] = NULL;
1348 goto release_r5_cores;
1349 }
1350
1351 /*
1352 * If mailbox nodes are disabled using "status" property then
1353 * setting up mailbox channels will fail.
1354 */
1355 ipi = zynqmp_r5_setup_mbox(&child_pdev->dev);
1356 if (ipi) {
1357 r5_cores[i]->ipi = ipi;
1358 ipi->r5_core = r5_cores[i];
1359 }
1360
1361 /*
1362 * If two child nodes are available in dts in lockstep mode,
1363 * then ignore second child node.
1364 */
1365 if (cluster_mode == LOCKSTEP_MODE) {
1366 of_node_put(child);
1367 break;
1368 }
1369
1370 i++;
1371 }
1372
1373 cluster->mode = cluster_mode;
1374 cluster->core_count = core_count;
1375 cluster->r5_cores = r5_cores;
1376
1377 ret = zynqmp_r5_core_init(cluster, fw_reg_val, tcm_mode);
1378 if (ret < 0) {
1379 dev_err(dev, "failed to init r5 core err %d\n", ret);
1380 cluster->core_count = 0;
1381 cluster->r5_cores = NULL;
1382
1383 /*
1384 * at this point rproc resources for each core are allocated.
1385 * adjust index to free resources in reverse order
1386 */
1387 i = core_count - 1;
1388 goto release_r5_cores;
1389 }
1390
1391 kfree(child_devs);
1392 return 0;
1393
1394 release_r5_cores:
1395 while (i >= 0) {
1396 put_device(child_devs[i]);
1397 if (r5_cores[i]) {
1398 zynqmp_r5_free_mbox(r5_cores[i]->ipi);
1399 of_reserved_mem_device_release(r5_cores[i]->dev);
1400 rproc_del(r5_cores[i]->rproc);
1401 rproc_free(r5_cores[i]->rproc);
1402 }
1403 i--;
1404 }
1405 kfree(r5_cores);
1406 kfree(child_devs);
1407 return ret;
1408 }
1409
zynqmp_r5_cluster_exit(void * data)1410 static void zynqmp_r5_cluster_exit(void *data)
1411 {
1412 struct platform_device *pdev = data;
1413 struct zynqmp_r5_cluster *cluster;
1414 struct zynqmp_r5_core *r5_core;
1415 int i;
1416
1417 cluster = platform_get_drvdata(pdev);
1418 if (!cluster)
1419 return;
1420
1421 for (i = 0; i < cluster->core_count; i++) {
1422 r5_core = cluster->r5_cores[i];
1423 zynqmp_r5_free_mbox(r5_core->ipi);
1424 iounmap(r5_core->rsc_tbl_va);
1425 of_reserved_mem_device_release(r5_core->dev);
1426 put_device(r5_core->dev);
1427 rproc_del(r5_core->rproc);
1428 rproc_free(r5_core->rproc);
1429 }
1430
1431 kfree(cluster->r5_cores);
1432 kfree(cluster);
1433 platform_set_drvdata(pdev, NULL);
1434 }
1435
1436 /*
1437 * zynqmp_r5_remoteproc_probe()
1438 * parse device-tree, initialize hardware and allocate required resources
1439 * and remoteproc ops
1440 *
1441 * @pdev: domain platform device for R5 cluster
1442 *
1443 * Return: 0 for success and < 0 for failure.
1444 */
zynqmp_r5_remoteproc_probe(struct platform_device * pdev)1445 static int zynqmp_r5_remoteproc_probe(struct platform_device *pdev)
1446 {
1447 struct zynqmp_r5_cluster *cluster;
1448 struct device *dev = &pdev->dev;
1449 int ret;
1450
1451 cluster = kzalloc(sizeof(*cluster), GFP_KERNEL);
1452 if (!cluster)
1453 return -ENOMEM;
1454
1455 cluster->dev = dev;
1456
1457 ret = devm_of_platform_populate(dev);
1458 if (ret) {
1459 dev_err_probe(dev, ret, "failed to populate platform dev\n");
1460 kfree(cluster);
1461 return ret;
1462 }
1463
1464 /* wire in so each core can be cleaned up at driver remove */
1465 platform_set_drvdata(pdev, cluster);
1466
1467 ret = zynqmp_r5_cluster_init(cluster);
1468 if (ret) {
1469 kfree(cluster);
1470 platform_set_drvdata(pdev, NULL);
1471 dev_err_probe(dev, ret, "Invalid r5f subsystem device tree\n");
1472 return ret;
1473 }
1474
1475 ret = devm_add_action_or_reset(dev, zynqmp_r5_cluster_exit, pdev);
1476 if (ret)
1477 return ret;
1478
1479 return 0;
1480 }
1481
1482 /* Match table for OF platform binding */
1483 static const struct of_device_id zynqmp_r5_remoteproc_match[] = {
1484 { .compatible = "xlnx,versal-net-r52fss", },
1485 { .compatible = "xlnx,versal-r5fss", },
1486 { .compatible = "xlnx,zynqmp-r5fss", },
1487 { /* end of list */ },
1488 };
1489 MODULE_DEVICE_TABLE(of, zynqmp_r5_remoteproc_match);
1490
1491 static struct platform_driver zynqmp_r5_remoteproc_driver = {
1492 .probe = zynqmp_r5_remoteproc_probe,
1493 .driver = {
1494 .name = "zynqmp_r5_remoteproc",
1495 .of_match_table = zynqmp_r5_remoteproc_match,
1496 },
1497 };
1498 module_platform_driver(zynqmp_r5_remoteproc_driver);
1499
1500 MODULE_DESCRIPTION("Xilinx R5F remote processor driver");
1501 MODULE_AUTHOR("Xilinx Inc.");
1502 MODULE_LICENSE("GPL");
1503