1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
4 *
5 * The driver handles Error's from Control Backbone(CBB) version 2.0.
6 * generated due to illegal accesses. The driver prints debug information
7 * about failed transaction on receiving interrupt from Error Notifier.
8 * Error types supported by CBB2.0 are:
9 * UNSUPPORTED_ERR, PWRDOWN_ERR, TIMEOUT_ERR, FIREWALL_ERR, DECODE_ERR,
10 * SLAVE_ERR
11 */
12
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/cpufeature.h>
16 #include <linux/debugfs.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/device.h>
21 #include <linux/io.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <soc/tegra/fuse.h>
25 #include <soc/tegra/tegra-cbb.h>
26
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
32
33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
37
38 #define FABRIC_MN_MASTER_LOG_ERR_STATUS_0 0x300
39 #define FABRIC_MN_MASTER_LOG_ADDR_LOW_0 0x304
40 #define FABRIC_MN_MASTER_LOG_ADDR_HIGH_0 0x308
41 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0 0x30c
42 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0 0x310
43 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0 0x314
44 #define FABRIC_MN_MASTER_LOG_USER_BITS0_0 0x318
45
46 #define AXI_SLV_TIMEOUT_STATUS_0_0 0x8
47 #define APB_BLOCK_TMO_STATUS_0 0xc00
48 #define APB_BLOCK_NUM_TMO_OFFSET 0x20
49
50 #define FAB_EM_EL_MSTRID GENMASK(29, 24)
51 #define FAB_EM_EL_VQC GENMASK(17, 16)
52 #define FAB_EM_EL_GRPSEC GENMASK(14, 8)
53 #define FAB_EM_EL_FALCONSEC GENMASK(1, 0)
54
55 #define FAB_EM_EL_FABID GENMASK(20, 16)
56 #define FAB_EM_EL_SLAVEID GENMASK(7, 0)
57
58 #define FAB_EM_EL_ACCESSID GENMASK(7, 0)
59
60 #define FAB_EM_EL_AXCACHE GENMASK(27, 24)
61 #define FAB_EM_EL_AXPROT GENMASK(22, 20)
62 #define FAB_EM_EL_BURSTLENGTH GENMASK(19, 12)
63 #define FAB_EM_EL_BURSTTYPE GENMASK(9, 8)
64 #define FAB_EM_EL_BEATSIZE GENMASK(6, 4)
65 #define FAB_EM_EL_ACCESSTYPE GENMASK(0, 0)
66
67 #define USRBITS_MSTR_ID GENMASK(29, 24)
68
69 #define REQ_SOCKET_ID GENMASK(27, 24)
70
71 #define CCPLEX_MSTRID 0x1
72 #define FIREWALL_APERTURE_SZ 0x10000
73 /* Write firewall check enable */
74 #define WEN 0x20000
75
76 enum tegra234_cbb_fabric_ids {
77 CBB_FAB_ID,
78 SCE_FAB_ID,
79 RCE_FAB_ID,
80 DCE_FAB_ID,
81 AON_FAB_ID,
82 PSC_FAB_ID,
83 BPMP_FAB_ID,
84 FSI_FAB_ID,
85 MAX_FAB_ID,
86 };
87
88 struct tegra234_slave_lookup {
89 const char *name;
90 unsigned int offset;
91 };
92
93 struct tegra234_cbb_fabric {
94 const char *name;
95 phys_addr_t off_mask_erd;
96 phys_addr_t firewall_base;
97 unsigned int firewall_ctl;
98 unsigned int firewall_wr_ctl;
99 const char * const *master_id;
100 unsigned int notifier_offset;
101 const struct tegra_cbb_error *errors;
102 const int max_errors;
103 const struct tegra234_slave_lookup *slave_map;
104 const int max_slaves;
105 };
106
107 struct tegra234_cbb {
108 struct tegra_cbb base;
109
110 const struct tegra234_cbb_fabric *fabric;
111 struct resource *res;
112 void __iomem *regs;
113
114 int num_intr;
115 int sec_irq;
116
117 /* record */
118 void __iomem *mon;
119 unsigned int type;
120 u32 mask;
121 u64 access;
122 u32 mn_attr0;
123 u32 mn_attr1;
124 u32 mn_attr2;
125 u32 mn_user_bits;
126 };
127
to_tegra234_cbb(struct tegra_cbb * cbb)128 static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb)
129 {
130 return container_of(cbb, struct tegra234_cbb, base);
131 }
132
133 static LIST_HEAD(cbb_list);
134 static DEFINE_SPINLOCK(cbb_lock);
135
136 static bool
tegra234_cbb_write_access_allowed(struct platform_device * pdev,struct tegra234_cbb * cbb)137 tegra234_cbb_write_access_allowed(struct platform_device *pdev, struct tegra234_cbb *cbb)
138 {
139 u32 val;
140
141 if (!cbb->fabric->firewall_base ||
142 !cbb->fabric->firewall_ctl ||
143 !cbb->fabric->firewall_wr_ctl) {
144 dev_info(&pdev->dev, "SoC data missing for firewall\n");
145 return false;
146 }
147
148 if ((cbb->fabric->firewall_ctl > FIREWALL_APERTURE_SZ) ||
149 (cbb->fabric->firewall_wr_ctl > FIREWALL_APERTURE_SZ)) {
150 dev_err(&pdev->dev, "wrong firewall offset value\n");
151 return false;
152 }
153
154 val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_ctl);
155 /*
156 * If the firewall check feature for allowing or blocking the
157 * write accesses through the firewall of a fabric is disabled
158 * then CCPLEX can write to the registers of that fabric.
159 */
160 if (!(val & WEN))
161 return true;
162
163 /*
164 * If the firewall check is enabled then check whether CCPLEX
165 * has write access to the fabric's error notifier registers
166 */
167 val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_wr_ctl);
168 if (val & (BIT(CCPLEX_MSTRID)))
169 return true;
170
171 return false;
172 }
173
tegra234_cbb_fault_enable(struct tegra_cbb * cbb)174 static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb)
175 {
176 struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
177 void __iomem *addr;
178
179 addr = priv->regs + priv->fabric->notifier_offset;
180 writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
181 dsb(sy);
182 }
183
tegra234_cbb_error_clear(struct tegra_cbb * cbb)184 static void tegra234_cbb_error_clear(struct tegra_cbb *cbb)
185 {
186 struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
187
188 writel(0, priv->mon + FABRIC_MN_MASTER_ERR_FORCE_0);
189
190 writel(0x3f, priv->mon + FABRIC_MN_MASTER_ERR_STATUS_0);
191 dsb(sy);
192 }
193
tegra234_cbb_get_status(struct tegra_cbb * cbb)194 static u32 tegra234_cbb_get_status(struct tegra_cbb *cbb)
195 {
196 struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
197 void __iomem *addr;
198 u32 value;
199
200 addr = priv->regs + priv->fabric->notifier_offset;
201 value = readl(addr + FABRIC_EN_CFG_STATUS_0_0);
202 dsb(sy);
203
204 return value;
205 }
206
tegra234_cbb_mask_serror(struct tegra234_cbb * cbb)207 static void tegra234_cbb_mask_serror(struct tegra234_cbb *cbb)
208 {
209 writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);
210 dsb(sy);
211 }
212
tegra234_cbb_get_tmo_slv(void __iomem * addr)213 static u32 tegra234_cbb_get_tmo_slv(void __iomem *addr)
214 {
215 u32 timeout;
216
217 timeout = readl(addr);
218 return timeout;
219 }
220
tegra234_cbb_tmo_slv(struct seq_file * file,const char * slave,void __iomem * addr,u32 status)221 static void tegra234_cbb_tmo_slv(struct seq_file *file, const char *slave, void __iomem *addr,
222 u32 status)
223 {
224 tegra_cbb_print_err(file, "\t %s : %#x\n", slave, status);
225 }
226
tegra234_cbb_lookup_apbslv(struct seq_file * file,const char * slave,void __iomem * base)227 static void tegra234_cbb_lookup_apbslv(struct seq_file *file, const char *slave,
228 void __iomem *base)
229 {
230 unsigned int block = 0;
231 void __iomem *addr;
232 char name[64];
233 u32 status;
234
235 status = tegra234_cbb_get_tmo_slv(base);
236 if (status)
237 tegra_cbb_print_err(file, "\t %s_BLOCK_TMO_STATUS : %#x\n", slave, status);
238
239 while (status) {
240 if (status & BIT(0)) {
241 u32 timeout, clients, client = 0;
242
243 addr = base + APB_BLOCK_NUM_TMO_OFFSET + (block * 4);
244 timeout = tegra234_cbb_get_tmo_slv(addr);
245 clients = timeout;
246
247 while (timeout) {
248 if (timeout & BIT(0)) {
249 if (clients != 0xffffffff)
250 clients &= BIT(client);
251
252 sprintf(name, "%s_BLOCK%d_TMO", slave, block);
253
254 tegra234_cbb_tmo_slv(file, name, addr, clients);
255 }
256
257 timeout >>= 1;
258 client++;
259 }
260 }
261
262 status >>= 1;
263 block++;
264 }
265 }
266
tegra234_lookup_slave_timeout(struct seq_file * file,struct tegra234_cbb * cbb,u8 slave_id,u8 fab_id)267 static void tegra234_lookup_slave_timeout(struct seq_file *file, struct tegra234_cbb *cbb,
268 u8 slave_id, u8 fab_id)
269 {
270 const struct tegra234_slave_lookup *map = cbb->fabric->slave_map;
271 void __iomem *addr;
272
273 /*
274 * 1) Get slave node name and address mapping using slave_id.
275 * 2) Check if the timed out slave node is APB or AXI.
276 * 3) If AXI, then print timeout register and reset axi slave
277 * using <FABRIC>_SN_<>_SLV_TIMEOUT_STATUS_0_0 register.
278 * 4) If APB, then perform an additional lookup to find the client
279 * which timed out.
280 * a) Get block number from the index of set bit in
281 * <FABRIC>_SN_AXI2APB_<>_BLOCK_TMO_STATUS_0 register.
282 * b) Get address of register repective to block number i.e.
283 * <FABRIC>_SN_AXI2APB_<>_BLOCK<index-set-bit>_TMO_0.
284 * c) Read the register in above step to get client_id which
285 * timed out as per the set bits.
286 * d) Reset the timedout client and print details.
287 * e) Goto step-a till all bits are set.
288 */
289
290 addr = cbb->regs + map[slave_id].offset;
291
292 if (strstr(map[slave_id].name, "AXI2APB")) {
293 addr += APB_BLOCK_TMO_STATUS_0;
294
295 tegra234_cbb_lookup_apbslv(file, map[slave_id].name, addr);
296 } else {
297 char name[64];
298 u32 status;
299
300 addr += AXI_SLV_TIMEOUT_STATUS_0_0;
301
302 status = tegra234_cbb_get_tmo_slv(addr);
303 if (status) {
304 sprintf(name, "%s_SLV_TIMEOUT_STATUS", map[slave_id].name);
305 tegra234_cbb_tmo_slv(file, name, addr, status);
306 }
307 }
308 }
309
tegra234_cbb_print_error(struct seq_file * file,struct tegra234_cbb * cbb,u32 status,u32 overflow)310 static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb *cbb, u32 status,
311 u32 overflow)
312 {
313 unsigned int type = 0;
314
315 if (status & (status - 1))
316 tegra_cbb_print_err(file, "\t Multiple type of errors reported\n");
317
318 while (status) {
319 if (type >= cbb->fabric->max_errors) {
320 tegra_cbb_print_err(file, "\t Wrong type index:%u, status:%u\n",
321 type, status);
322 return;
323 }
324
325 if (status & 0x1)
326 tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
327 cbb->fabric->errors[type].code);
328
329 status >>= 1;
330 type++;
331 }
332
333 type = 0;
334
335 while (overflow) {
336 if (type >= cbb->fabric->max_errors) {
337 tegra_cbb_print_err(file, "\t Wrong type index:%u, overflow:%u\n",
338 type, overflow);
339 return;
340 }
341
342 if (overflow & 0x1)
343 tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n",
344 cbb->fabric->errors[type].code);
345
346 overflow >>= 1;
347 type++;
348 }
349 }
350
print_errlog_err(struct seq_file * file,struct tegra234_cbb * cbb)351 static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
352 {
353 u8 cache_type, prot_type, burst_length, mstr_id, grpsec, vqc, falconsec, beat_size;
354 u8 access_type, access_id, requester_socket_id, local_socket_id, slave_id, fab_id;
355 char fabric_name[20];
356 bool is_numa = false;
357 u8 burst_type;
358
359 if (num_possible_nodes() > 1)
360 is_numa = true;
361
362 mstr_id = FIELD_GET(FAB_EM_EL_MSTRID, cbb->mn_user_bits);
363 vqc = FIELD_GET(FAB_EM_EL_VQC, cbb->mn_user_bits);
364 grpsec = FIELD_GET(FAB_EM_EL_GRPSEC, cbb->mn_user_bits);
365 falconsec = FIELD_GET(FAB_EM_EL_FALCONSEC, cbb->mn_user_bits);
366
367 /*
368 * For SOC with multiple NUMA nodes, print cross socket access
369 * errors only if initiator/master_id is CCPLEX, CPMU or GPU.
370 */
371 if (is_numa) {
372 local_socket_id = numa_node_id();
373 requester_socket_id = FIELD_GET(REQ_SOCKET_ID, cbb->mn_attr2);
374
375 if (requester_socket_id != local_socket_id) {
376 if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))
377 return;
378 }
379 }
380
381 fab_id = FIELD_GET(FAB_EM_EL_FABID, cbb->mn_attr2);
382 slave_id = FIELD_GET(FAB_EM_EL_SLAVEID, cbb->mn_attr2);
383
384 access_id = FIELD_GET(FAB_EM_EL_ACCESSID, cbb->mn_attr1);
385
386 cache_type = FIELD_GET(FAB_EM_EL_AXCACHE, cbb->mn_attr0);
387 prot_type = FIELD_GET(FAB_EM_EL_AXPROT, cbb->mn_attr0);
388 burst_length = FIELD_GET(FAB_EM_EL_BURSTLENGTH, cbb->mn_attr0);
389 burst_type = FIELD_GET(FAB_EM_EL_BURSTTYPE, cbb->mn_attr0);
390 beat_size = FIELD_GET(FAB_EM_EL_BEATSIZE, cbb->mn_attr0);
391 access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, cbb->mn_attr0);
392
393 tegra_cbb_print_err(file, "\n");
394 if (cbb->type < cbb->fabric->max_errors)
395 tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n",
396 cbb->fabric->errors[cbb->type].code);
397 else
398 tegra_cbb_print_err(file, "\t Wrong type index:%u\n", cbb->type);
399
400 tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", cbb->fabric->master_id[mstr_id]);
401 tegra_cbb_print_err(file, "\t Address\t\t: %#llx\n", cbb->access);
402
403 tegra_cbb_print_cache(file, cache_type);
404 tegra_cbb_print_prot(file, prot_type);
405
406 tegra_cbb_print_err(file, "\t Access_Type\t\t: %s", (access_type) ? "Write\n" : "Read\n");
407 tegra_cbb_print_err(file, "\t Access_ID\t\t: %#x", access_id);
408
409 if (fab_id == PSC_FAB_ID)
410 strcpy(fabric_name, "psc-fabric");
411 else if (fab_id == FSI_FAB_ID)
412 strcpy(fabric_name, "fsi-fabric");
413 else
414 strcpy(fabric_name, cbb->fabric->name);
415
416 if (is_numa) {
417 tegra_cbb_print_err(file, "\t Requester_Socket_Id\t: %#x\n",
418 requester_socket_id);
419 tegra_cbb_print_err(file, "\t Local_Socket_Id\t: %#x\n",
420 local_socket_id);
421 tegra_cbb_print_err(file, "\t No. of NUMA_NODES\t: %#x\n",
422 num_possible_nodes());
423 }
424
425 tegra_cbb_print_err(file, "\t Fabric\t\t: %s\n", fabric_name);
426 tegra_cbb_print_err(file, "\t Slave_Id\t\t: %#x\n", slave_id);
427 tegra_cbb_print_err(file, "\t Burst_length\t\t: %#x\n", burst_length);
428 tegra_cbb_print_err(file, "\t Burst_type\t\t: %#x\n", burst_type);
429 tegra_cbb_print_err(file, "\t Beat_size\t\t: %#x\n", beat_size);
430 tegra_cbb_print_err(file, "\t VQC\t\t\t: %#x\n", vqc);
431 tegra_cbb_print_err(file, "\t GRPSEC\t\t: %#x\n", grpsec);
432 tegra_cbb_print_err(file, "\t FALCONSEC\t\t: %#x\n", falconsec);
433
434 if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID))
435 return;
436
437 if (slave_id >= cbb->fabric->max_slaves) {
438 tegra_cbb_print_err(file, "\t Invalid slave_id:%d\n", slave_id);
439 return;
440 }
441
442 if (!strcmp(cbb->fabric->errors[cbb->type].code, "TIMEOUT_ERR")) {
443 tegra234_lookup_slave_timeout(file, cbb, slave_id, fab_id);
444 return;
445 }
446
447 tegra_cbb_print_err(file, "\t Slave\t\t\t: %s\n", cbb->fabric->slave_map[slave_id].name);
448 }
449
print_errmonX_info(struct seq_file * file,struct tegra234_cbb * cbb)450 static int print_errmonX_info(struct seq_file *file, struct tegra234_cbb *cbb)
451 {
452 u32 overflow, status, error;
453
454 status = readl(cbb->mon + FABRIC_MN_MASTER_ERR_STATUS_0);
455 if (!status) {
456 pr_err("Error Notifier received a spurious notification\n");
457 return -ENODATA;
458 }
459
460 if (status == 0xffffffff) {
461 pr_err("CBB registers returning all 1's which is invalid\n");
462 return -EINVAL;
463 }
464
465 overflow = readl(cbb->mon + FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0);
466
467 tegra234_cbb_print_error(file, cbb, status, overflow);
468
469 error = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ERR_STATUS_0);
470 if (!error) {
471 pr_info("Error Monitor doesn't have Error Logger\n");
472 return -EINVAL;
473 }
474
475 cbb->type = 0;
476
477 while (error) {
478 if (error & BIT(0)) {
479 u32 hi, lo;
480
481 hi = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ADDR_HIGH_0);
482 lo = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ADDR_LOW_0);
483
484 cbb->access = (u64)hi << 32 | lo;
485
486 cbb->mn_attr0 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0);
487 cbb->mn_attr1 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0);
488 cbb->mn_attr2 = readl(cbb->mon + FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0);
489 cbb->mn_user_bits = readl(cbb->mon + FABRIC_MN_MASTER_LOG_USER_BITS0_0);
490
491 print_errlog_err(file, cbb);
492 }
493
494 cbb->type++;
495 error >>= 1;
496 }
497
498 return 0;
499 }
500
print_err_notifier(struct seq_file * file,struct tegra234_cbb * cbb,u32 status)501 static int print_err_notifier(struct seq_file *file, struct tegra234_cbb *cbb, u32 status)
502 {
503 unsigned int index = 0;
504 int err;
505
506 pr_crit("**************************************\n");
507 pr_crit("CPU:%d, Error:%s, Errmon:%d\n", smp_processor_id(),
508 cbb->fabric->name, status);
509
510 while (status) {
511 if (status & BIT(0)) {
512 unsigned int notifier = cbb->fabric->notifier_offset;
513 u32 hi, lo, mask = BIT(index);
514 phys_addr_t addr;
515 u64 offset;
516
517 writel(mask, cbb->regs + notifier + FABRIC_EN_CFG_ADDR_INDEX_0_0);
518 hi = readl(cbb->regs + notifier + FABRIC_EN_CFG_ADDR_HI_0);
519 lo = readl(cbb->regs + notifier + FABRIC_EN_CFG_ADDR_LOW_0);
520
521 addr = (u64)hi << 32 | lo;
522
523 offset = addr - cbb->res->start;
524 cbb->mon = cbb->regs + offset;
525 cbb->mask = BIT(index);
526
527 err = print_errmonX_info(file, cbb);
528 tegra234_cbb_error_clear(&cbb->base);
529 if (err)
530 return err;
531 }
532
533 status >>= 1;
534 index++;
535 }
536
537 tegra_cbb_print_err(file, "\t**************************************\n");
538 return 0;
539 }
540
541 #ifdef CONFIG_DEBUG_FS
542 static DEFINE_MUTEX(cbb_debugfs_mutex);
543
tegra234_cbb_debugfs_show(struct tegra_cbb * cbb,struct seq_file * file,void * data)544 static int tegra234_cbb_debugfs_show(struct tegra_cbb *cbb, struct seq_file *file, void *data)
545 {
546 int err = 0;
547
548 mutex_lock(&cbb_debugfs_mutex);
549
550 list_for_each_entry(cbb, &cbb_list, node) {
551 struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
552 u32 status;
553
554 status = tegra_cbb_get_status(&priv->base);
555 if (status) {
556 err = print_err_notifier(file, priv, status);
557 if (err)
558 break;
559 }
560 }
561
562 mutex_unlock(&cbb_debugfs_mutex);
563 return err;
564 }
565 #endif
566
567 /*
568 * Handler for CBB errors
569 */
tegra234_cbb_isr(int irq,void * data)570 static irqreturn_t tegra234_cbb_isr(int irq, void *data)
571 {
572 bool is_inband_err = false;
573 struct tegra_cbb *cbb;
574 unsigned long flags;
575 u8 mstr_id;
576 int err;
577
578 spin_lock_irqsave(&cbb_lock, flags);
579
580 list_for_each_entry(cbb, &cbb_list, node) {
581 struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
582 u32 status = tegra_cbb_get_status(cbb);
583
584 if (status && (irq == priv->sec_irq)) {
585 tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@0x%llx, irq=%d\n",
586 smp_processor_id(), priv->fabric->name,
587 priv->res->start, irq);
588
589 err = print_err_notifier(NULL, priv, status);
590 if (err)
591 goto unlock;
592
593 /*
594 * If illegal request is from CCPLEX(id:0x1) master then call WARN()
595 */
596 if (priv->fabric->off_mask_erd) {
597 mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits);
598 if (mstr_id == CCPLEX_MSTRID)
599 is_inband_err = 1;
600 }
601 }
602 }
603
604 unlock:
605 spin_unlock_irqrestore(&cbb_lock, flags);
606 WARN_ON(is_inband_err);
607 return IRQ_HANDLED;
608 }
609
610 /*
611 * Register handler for CBB_SECURE interrupt for reporting errors
612 */
tegra234_cbb_interrupt_enable(struct tegra_cbb * cbb)613 static int tegra234_cbb_interrupt_enable(struct tegra_cbb *cbb)
614 {
615 struct tegra234_cbb *priv = to_tegra234_cbb(cbb);
616
617 if (priv->sec_irq) {
618 int err = devm_request_irq(cbb->dev, priv->sec_irq, tegra234_cbb_isr, 0,
619 dev_name(cbb->dev), priv);
620 if (err) {
621 dev_err(cbb->dev, "failed to register interrupt %u: %d\n", priv->sec_irq,
622 err);
623 return err;
624 }
625 }
626
627 return 0;
628 }
629
tegra234_cbb_error_enable(struct tegra_cbb * cbb)630 static void tegra234_cbb_error_enable(struct tegra_cbb *cbb)
631 {
632 tegra_cbb_fault_enable(cbb);
633 }
634
635 static const struct tegra_cbb_ops tegra234_cbb_ops = {
636 .get_status = tegra234_cbb_get_status,
637 .error_clear = tegra234_cbb_error_clear,
638 .fault_enable = tegra234_cbb_fault_enable,
639 .error_enable = tegra234_cbb_error_enable,
640 .interrupt_enable = tegra234_cbb_interrupt_enable,
641 #ifdef CONFIG_DEBUG_FS
642 .debugfs_show = tegra234_cbb_debugfs_show,
643 #endif
644 };
645
646 static const char * const tegra234_master_id[] = {
647 [0x00] = "TZ",
648 [0x01] = "CCPLEX",
649 [0x02] = "CCPMU",
650 [0x03] = "BPMP_FW",
651 [0x04] = "AON",
652 [0x05] = "SCE",
653 [0x06] = "GPCDMA_P",
654 [0x07] = "TSECA_NONSECURE",
655 [0x08] = "TSECA_LIGHTSECURE",
656 [0x09] = "TSECA_HEAVYSECURE",
657 [0x0a] = "CORESIGHT",
658 [0x0b] = "APE",
659 [0x0c] = "PEATRANS",
660 [0x0d] = "JTAGM_DFT",
661 [0x0e] = "RCE",
662 [0x0f] = "DCE",
663 [0x10] = "PSC_FW_USER",
664 [0x11] = "PSC_FW_SUPERVISOR",
665 [0x12] = "PSC_FW_MACHINE",
666 [0x13] = "PSC_BOOT",
667 [0x14] = "BPMP_BOOT",
668 [0x15] = "NVDEC_NONSECURE",
669 [0x16] = "NVDEC_LIGHTSECURE",
670 [0x17] = "NVDEC_HEAVYSECURE",
671 [0x18] = "CBB_INTERNAL",
672 [0x19] = "RSVD"
673 };
674
675 static const struct tegra_cbb_error tegra234_cbb_errors[] = {
676 {
677 .code = "SLAVE_ERR",
678 .desc = "Slave being accessed responded with an error"
679 }, {
680 .code = "DECODE_ERR",
681 .desc = "Attempt to access an address hole"
682 }, {
683 .code = "FIREWALL_ERR",
684 .desc = "Attempt to access a region which is firewall protected"
685 }, {
686 .code = "TIMEOUT_ERR",
687 .desc = "No response returned by slave"
688 }, {
689 .code = "PWRDOWN_ERR",
690 .desc = "Attempt to access a portion of fabric that is powered down"
691 }, {
692 .code = "UNSUPPORTED_ERR",
693 .desc = "Attempt to access a slave through an unsupported access"
694 }
695 };
696
697 static const struct tegra234_slave_lookup tegra234_aon_slave_map[] = {
698 { "AXI2APB", 0x00000 },
699 { "AST", 0x14000 },
700 { "CBB", 0x15000 },
701 { "CPU", 0x16000 },
702 };
703
704 static const struct tegra234_cbb_fabric tegra234_aon_fabric = {
705 .name = "aon-fabric",
706 .master_id = tegra234_master_id,
707 .slave_map = tegra234_aon_slave_map,
708 .max_slaves = ARRAY_SIZE(tegra234_aon_slave_map),
709 .errors = tegra234_cbb_errors,
710 .max_errors = ARRAY_SIZE(tegra234_cbb_errors),
711 .notifier_offset = 0x17000,
712 .firewall_base = 0x30000,
713 .firewall_ctl = 0x8d0,
714 .firewall_wr_ctl = 0x8c8,
715 };
716
717 static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = {
718 { "AXI2APB", 0x00000 },
719 { "AST0", 0x15000 },
720 { "AST1", 0x16000 },
721 { "CBB", 0x17000 },
722 { "CPU", 0x18000 },
723 };
724
725 static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = {
726 .name = "bpmp-fabric",
727 .master_id = tegra234_master_id,
728 .slave_map = tegra234_bpmp_slave_map,
729 .max_slaves = ARRAY_SIZE(tegra234_bpmp_slave_map),
730 .errors = tegra234_cbb_errors,
731 .max_errors = ARRAY_SIZE(tegra234_cbb_errors),
732 .notifier_offset = 0x19000,
733 .firewall_base = 0x30000,
734 .firewall_ctl = 0x8f0,
735 .firewall_wr_ctl = 0x8e8,
736 };
737
738 static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = {
739 { "AON", 0x40000 },
740 { "BPMP", 0x41000 },
741 { "CBB", 0x42000 },
742 { "HOST1X", 0x43000 },
743 { "STM", 0x44000 },
744 { "FSI", 0x45000 },
745 { "PSC", 0x46000 },
746 { "PCIE_C1", 0x47000 },
747 { "PCIE_C2", 0x48000 },
748 { "PCIE_C3", 0x49000 },
749 { "PCIE_C0", 0x4a000 },
750 { "PCIE_C4", 0x4b000 },
751 { "GPU", 0x4c000 },
752 { "SMMU0", 0x4d000 },
753 { "SMMU1", 0x4e000 },
754 { "SMMU2", 0x4f000 },
755 { "SMMU3", 0x50000 },
756 { "SMMU4", 0x51000 },
757 { "PCIE_C10", 0x52000 },
758 { "PCIE_C7", 0x53000 },
759 { "PCIE_C8", 0x54000 },
760 { "PCIE_C9", 0x55000 },
761 { "PCIE_C5", 0x56000 },
762 { "PCIE_C6", 0x57000 },
763 { "DCE", 0x58000 },
764 { "RCE", 0x59000 },
765 { "SCE", 0x5a000 },
766 { "AXI2APB_1", 0x70000 },
767 { "AXI2APB_10", 0x71000 },
768 { "AXI2APB_11", 0x72000 },
769 { "AXI2APB_12", 0x73000 },
770 { "AXI2APB_13", 0x74000 },
771 { "AXI2APB_14", 0x75000 },
772 { "AXI2APB_15", 0x76000 },
773 { "AXI2APB_16", 0x77000 },
774 { "AXI2APB_17", 0x78000 },
775 { "AXI2APB_18", 0x79000 },
776 { "AXI2APB_19", 0x7a000 },
777 { "AXI2APB_2", 0x7b000 },
778 { "AXI2APB_20", 0x7c000 },
779 { "AXI2APB_21", 0x7d000 },
780 { "AXI2APB_22", 0x7e000 },
781 { "AXI2APB_23", 0x7f000 },
782 { "AXI2APB_25", 0x80000 },
783 { "AXI2APB_26", 0x81000 },
784 { "AXI2APB_27", 0x82000 },
785 { "AXI2APB_28", 0x83000 },
786 { "AXI2APB_29", 0x84000 },
787 { "AXI2APB_30", 0x85000 },
788 { "AXI2APB_31", 0x86000 },
789 { "AXI2APB_32", 0x87000 },
790 { "AXI2APB_33", 0x88000 },
791 { "AXI2APB_34", 0x89000 },
792 { "AXI2APB_35", 0x92000 },
793 { "AXI2APB_4", 0x8b000 },
794 { "AXI2APB_5", 0x8c000 },
795 { "AXI2APB_6", 0x8d000 },
796 { "AXI2APB_7", 0x8e000 },
797 { "AXI2APB_8", 0x8f000 },
798 { "AXI2APB_9", 0x90000 },
799 { "AXI2APB_3", 0x91000 },
800 };
801
802 static const struct tegra234_cbb_fabric tegra234_cbb_fabric = {
803 .name = "cbb-fabric",
804 .master_id = tegra234_master_id,
805 .slave_map = tegra234_cbb_slave_map,
806 .max_slaves = ARRAY_SIZE(tegra234_cbb_slave_map),
807 .errors = tegra234_cbb_errors,
808 .max_errors = ARRAY_SIZE(tegra234_cbb_errors),
809 .notifier_offset = 0x60000,
810 .off_mask_erd = 0x3a004,
811 .firewall_base = 0x10000,
812 .firewall_ctl = 0x23f0,
813 .firewall_wr_ctl = 0x23e8,
814 };
815
816 static const struct tegra234_slave_lookup tegra234_common_slave_map[] = {
817 { "AXI2APB", 0x00000 },
818 { "AST0", 0x15000 },
819 { "AST1", 0x16000 },
820 { "CBB", 0x17000 },
821 { "RSVD", 0x00000 },
822 { "CPU", 0x18000 },
823 };
824
825 static const struct tegra234_cbb_fabric tegra234_dce_fabric = {
826 .name = "dce-fabric",
827 .master_id = tegra234_master_id,
828 .slave_map = tegra234_common_slave_map,
829 .max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
830 .errors = tegra234_cbb_errors,
831 .max_errors = ARRAY_SIZE(tegra234_cbb_errors),
832 .notifier_offset = 0x19000,
833 .firewall_base = 0x30000,
834 .firewall_ctl = 0x290,
835 .firewall_wr_ctl = 0x288,
836 };
837
838 static const struct tegra234_cbb_fabric tegra234_rce_fabric = {
839 .name = "rce-fabric",
840 .master_id = tegra234_master_id,
841 .slave_map = tegra234_common_slave_map,
842 .max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
843 .errors = tegra234_cbb_errors,
844 .max_errors = ARRAY_SIZE(tegra234_cbb_errors),
845 .notifier_offset = 0x19000,
846 .firewall_base = 0x30000,
847 .firewall_ctl = 0x290,
848 .firewall_wr_ctl = 0x288,
849 };
850
851 static const struct tegra234_cbb_fabric tegra234_sce_fabric = {
852 .name = "sce-fabric",
853 .master_id = tegra234_master_id,
854 .slave_map = tegra234_common_slave_map,
855 .max_slaves = ARRAY_SIZE(tegra234_common_slave_map),
856 .errors = tegra234_cbb_errors,
857 .max_errors = ARRAY_SIZE(tegra234_cbb_errors),
858 .notifier_offset = 0x19000,
859 .firewall_base = 0x30000,
860 .firewall_ctl = 0x290,
861 .firewall_wr_ctl = 0x288,
862 };
863
864 static const char * const tegra241_master_id[] = {
865 [0x0] = "TZ",
866 [0x1] = "CCPLEX",
867 [0x2] = "CCPMU",
868 [0x3] = "BPMP_FW",
869 [0x4] = "PSC_FW_USER",
870 [0x5] = "PSC_FW_SUPERVISOR",
871 [0x6] = "PSC_FW_MACHINE",
872 [0x7] = "PSC_BOOT",
873 [0x8] = "BPMP_BOOT",
874 [0x9] = "JTAGM_DFT",
875 [0xa] = "CORESIGHT",
876 [0xb] = "GPU",
877 [0xc] = "PEATRANS",
878 [0xd ... 0x3f] = "RSVD"
879 };
880
881 /*
882 * Possible causes for Slave and Timeout errors.
883 * SLAVE_ERR:
884 * Slave being accessed responded with an error. Slave could return
885 * an error for various cases :
886 * Unsupported access, clamp setting when power gated, register
887 * level firewall(SCR), address hole within the slave, etc
888 *
889 * TIMEOUT_ERR:
890 * No response returned by slave. Can be due to slave being clock
891 * gated, under reset, powered down or slave inability to respond
892 * for an internal slave issue
893 */
894 static const struct tegra_cbb_error tegra241_cbb_errors[] = {
895 {
896 .code = "SLAVE_ERR",
897 .desc = "Slave being accessed responded with an error."
898 }, {
899 .code = "DECODE_ERR",
900 .desc = "Attempt to access an address hole or Reserved region of memory."
901 }, {
902 .code = "FIREWALL_ERR",
903 .desc = "Attempt to access a region which is firewalled."
904 }, {
905 .code = "TIMEOUT_ERR",
906 .desc = "No response returned by slave."
907 }, {
908 .code = "PWRDOWN_ERR",
909 .desc = "Attempt to access a portion of the fabric that is powered down."
910 }, {
911 .code = "UNSUPPORTED_ERR",
912 .desc = "Attempt to access a slave through an unsupported access."
913 }, {
914 .code = "POISON_ERR",
915 .desc = "Slave responds with poison error to indicate error in data."
916 }, {
917 .code = "RSVD"
918 }, {
919 .code = "RSVD"
920 }, {
921 .code = "RSVD"
922 }, {
923 .code = "RSVD"
924 }, {
925 .code = "RSVD"
926 }, {
927 .code = "RSVD"
928 }, {
929 .code = "RSVD"
930 }, {
931 .code = "RSVD"
932 }, {
933 .code = "RSVD"
934 }, {
935 .code = "NO_SUCH_ADDRESS_ERR",
936 .desc = "The address belongs to the pri_target range but there is no register "
937 "implemented at the address."
938 }, {
939 .code = "TASK_ERR",
940 .desc = "Attempt to update a PRI task when the current task has still not "
941 "completed."
942 }, {
943 .code = "EXTERNAL_ERR",
944 .desc = "Indicates that an external PRI register access met with an error due to "
945 "any issue in the unit."
946 }, {
947 .code = "INDEX_ERR",
948 .desc = "Applicable to PRI index aperture pair, when the programmed index is "
949 "outside the range defined in the manual."
950 }, {
951 .code = "RESET_ERR",
952 .desc = "Target in Reset Error: Attempt to access a SubPri or external PRI "
953 "register but they are in reset."
954 }, {
955 .code = "REGISTER_RST_ERR",
956 .desc = "Attempt to access a PRI register but the register is partial or "
957 "completely in reset."
958 }, {
959 .code = "POWER_GATED_ERR",
960 .desc = "Returned by external PRI client when the external access goes to a power "
961 "gated domain."
962 }, {
963 .code = "SUBPRI_FS_ERR",
964 .desc = "Subpri is floorswept: Attempt to access a subpri through the main pri "
965 "target but subPri logic is floorswept."
966 }, {
967 .code = "SUBPRI_CLK_OFF_ERR",
968 .desc = "Subpri clock is off: Attempt to access a subpri through the main pri "
969 "target but subPris clock is gated/off."
970 },
971 };
972
973 static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = {
974 { "RSVD", 0x00000 },
975 { "PCIE_C8", 0x51000 },
976 { "PCIE_C9", 0x52000 },
977 { "RSVD", 0x00000 },
978 { "RSVD", 0x00000 },
979 { "RSVD", 0x00000 },
980 { "RSVD", 0x00000 },
981 { "RSVD", 0x00000 },
982 { "RSVD", 0x00000 },
983 { "RSVD", 0x00000 },
984 { "RSVD", 0x00000 },
985 { "AON", 0x5b000 },
986 { "BPMP", 0x5c000 },
987 { "RSVD", 0x00000 },
988 { "RSVD", 0x00000 },
989 { "PSC", 0x5d000 },
990 { "STM", 0x5e000 },
991 { "AXI2APB_1", 0x70000 },
992 { "AXI2APB_10", 0x71000 },
993 { "AXI2APB_11", 0x72000 },
994 { "AXI2APB_12", 0x73000 },
995 { "AXI2APB_13", 0x74000 },
996 { "AXI2APB_14", 0x75000 },
997 { "AXI2APB_15", 0x76000 },
998 { "AXI2APB_16", 0x77000 },
999 { "AXI2APB_17", 0x78000 },
1000 { "AXI2APB_18", 0x79000 },
1001 { "AXI2APB_19", 0x7a000 },
1002 { "AXI2APB_2", 0x7b000 },
1003 { "AXI2APB_20", 0x7c000 },
1004 { "AXI2APB_4", 0x87000 },
1005 { "AXI2APB_5", 0x88000 },
1006 { "AXI2APB_6", 0x89000 },
1007 { "AXI2APB_7", 0x8a000 },
1008 { "AXI2APB_8", 0x8b000 },
1009 { "AXI2APB_9", 0x8c000 },
1010 { "AXI2APB_3", 0x8d000 },
1011 { "AXI2APB_21", 0x7d000 },
1012 { "AXI2APB_22", 0x7e000 },
1013 { "AXI2APB_23", 0x7f000 },
1014 { "AXI2APB_24", 0x80000 },
1015 { "AXI2APB_25", 0x81000 },
1016 { "AXI2APB_26", 0x82000 },
1017 { "AXI2APB_27", 0x83000 },
1018 { "AXI2APB_28", 0x84000 },
1019 { "PCIE_C4", 0x53000 },
1020 { "PCIE_C5", 0x54000 },
1021 { "PCIE_C6", 0x55000 },
1022 { "PCIE_C7", 0x56000 },
1023 { "PCIE_C2", 0x57000 },
1024 { "PCIE_C3", 0x58000 },
1025 { "PCIE_C0", 0x59000 },
1026 { "PCIE_C1", 0x5a000 },
1027 { "CCPLEX", 0x50000 },
1028 { "AXI2APB_29", 0x85000 },
1029 { "AXI2APB_30", 0x86000 },
1030 { "CBB_CENTRAL", 0x00000 },
1031 { "AXI2APB_31", 0x8E000 },
1032 { "AXI2APB_32", 0x8F000 },
1033 };
1034
1035 static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {
1036 .name = "cbb-fabric",
1037 .master_id = tegra241_master_id,
1038 .slave_map = tegra241_cbb_slave_map,
1039 .max_slaves = ARRAY_SIZE(tegra241_cbb_slave_map),
1040 .errors = tegra241_cbb_errors,
1041 .max_errors = ARRAY_SIZE(tegra241_cbb_errors),
1042 .notifier_offset = 0x60000,
1043 .off_mask_erd = 0x40004,
1044 .firewall_base = 0x20000,
1045 .firewall_ctl = 0x2370,
1046 .firewall_wr_ctl = 0x2368,
1047 };
1048
1049 static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = {
1050 { "RSVD", 0x00000 },
1051 { "RSVD", 0x00000 },
1052 { "RSVD", 0x00000 },
1053 { "CBB", 0x15000 },
1054 { "CPU", 0x16000 },
1055 { "AXI2APB", 0x00000 },
1056 { "DBB0", 0x17000 },
1057 { "DBB1", 0x18000 },
1058 };
1059
1060 static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
1061 .name = "bpmp-fabric",
1062 .master_id = tegra241_master_id,
1063 .slave_map = tegra241_bpmp_slave_map,
1064 .max_slaves = ARRAY_SIZE(tegra241_bpmp_slave_map),
1065 .errors = tegra241_cbb_errors,
1066 .max_errors = ARRAY_SIZE(tegra241_cbb_errors),
1067 .notifier_offset = 0x19000,
1068 .firewall_base = 0x30000,
1069 .firewall_ctl = 0x8f0,
1070 .firewall_wr_ctl = 0x8e8,
1071 };
1072
1073 static const struct of_device_id tegra234_cbb_dt_ids[] = {
1074 { .compatible = "nvidia,tegra234-cbb-fabric", .data = &tegra234_cbb_fabric },
1075 { .compatible = "nvidia,tegra234-aon-fabric", .data = &tegra234_aon_fabric },
1076 { .compatible = "nvidia,tegra234-bpmp-fabric", .data = &tegra234_bpmp_fabric },
1077 { .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },
1078 { .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },
1079 { .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },
1080 { /* sentinel */ },
1081 };
1082 MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);
1083
1084 struct tegra234_cbb_acpi_uid {
1085 const char *hid;
1086 const char *uid;
1087 const struct tegra234_cbb_fabric *fabric;
1088 };
1089
1090 static const struct tegra234_cbb_acpi_uid tegra234_cbb_acpi_uids[] = {
1091 { "NVDA1070", "1", &tegra241_cbb_fabric },
1092 { "NVDA1070", "2", &tegra241_bpmp_fabric },
1093 { },
1094 };
1095
1096 static const struct
tegra234_cbb_acpi_get_fabric(struct acpi_device * adev)1097 tegra234_cbb_fabric *tegra234_cbb_acpi_get_fabric(struct acpi_device *adev)
1098 {
1099 const struct tegra234_cbb_acpi_uid *entry;
1100
1101 for (entry = tegra234_cbb_acpi_uids; entry->hid; entry++) {
1102 if (acpi_dev_hid_uid_match(adev, entry->hid, entry->uid))
1103 return entry->fabric;
1104 }
1105
1106 return NULL;
1107 }
1108
1109 static const struct acpi_device_id tegra241_cbb_acpi_ids[] = {
1110 { "NVDA1070" },
1111 { },
1112 };
1113 MODULE_DEVICE_TABLE(acpi, tegra241_cbb_acpi_ids);
1114
tegra234_cbb_probe(struct platform_device * pdev)1115 static int tegra234_cbb_probe(struct platform_device *pdev)
1116 {
1117 const struct tegra234_cbb_fabric *fabric;
1118 struct tegra234_cbb *cbb;
1119 unsigned long flags = 0;
1120 int err;
1121
1122 if (pdev->dev.of_node) {
1123 fabric = of_device_get_match_data(&pdev->dev);
1124 } else {
1125 struct acpi_device *device = ACPI_COMPANION(&pdev->dev);
1126 if (!device)
1127 return -ENODEV;
1128
1129 fabric = tegra234_cbb_acpi_get_fabric(device);
1130 if (!fabric) {
1131 dev_err(&pdev->dev, "no device match found\n");
1132 return -ENODEV;
1133 }
1134 }
1135
1136 cbb = devm_kzalloc(&pdev->dev, sizeof(*cbb), GFP_KERNEL);
1137 if (!cbb)
1138 return -ENOMEM;
1139
1140 INIT_LIST_HEAD(&cbb->base.node);
1141 cbb->base.ops = &tegra234_cbb_ops;
1142 cbb->base.dev = &pdev->dev;
1143 cbb->fabric = fabric;
1144
1145 cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);
1146 if (IS_ERR(cbb->regs))
1147 return PTR_ERR(cbb->regs);
1148
1149 err = tegra_cbb_get_irq(pdev, NULL, &cbb->sec_irq);
1150 if (err)
1151 return err;
1152
1153 platform_set_drvdata(pdev, cbb);
1154
1155 /*
1156 * Don't enable error reporting for a Fabric if write to it's registers
1157 * is blocked by CBB firewall.
1158 */
1159 if (!tegra234_cbb_write_access_allowed(pdev, cbb)) {
1160 dev_info(&pdev->dev, "error reporting not enabled due to firewall\n");
1161 return 0;
1162 }
1163
1164 spin_lock_irqsave(&cbb_lock, flags);
1165 list_add(&cbb->base.node, &cbb_list);
1166 spin_unlock_irqrestore(&cbb_lock, flags);
1167
1168 /* set ERD bit to mask SError and generate interrupt to report error */
1169 if (cbb->fabric->off_mask_erd)
1170 tegra234_cbb_mask_serror(cbb);
1171
1172 return tegra_cbb_register(&cbb->base);
1173 }
1174
tegra234_cbb_resume_noirq(struct device * dev)1175 static int __maybe_unused tegra234_cbb_resume_noirq(struct device *dev)
1176 {
1177 struct tegra234_cbb *cbb = dev_get_drvdata(dev);
1178
1179 tegra234_cbb_error_enable(&cbb->base);
1180
1181 dev_dbg(dev, "%s resumed\n", cbb->fabric->name);
1182
1183 return 0;
1184 }
1185
1186 static const struct dev_pm_ops tegra234_cbb_pm = {
1187 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, tegra234_cbb_resume_noirq)
1188 };
1189
1190 static struct platform_driver tegra234_cbb_driver = {
1191 .probe = tegra234_cbb_probe,
1192 .driver = {
1193 .name = "tegra234-cbb",
1194 .of_match_table = tegra234_cbb_dt_ids,
1195 .acpi_match_table = tegra241_cbb_acpi_ids,
1196 .pm = &tegra234_cbb_pm,
1197 },
1198 };
1199
tegra234_cbb_init(void)1200 static int __init tegra234_cbb_init(void)
1201 {
1202 return platform_driver_register(&tegra234_cbb_driver);
1203 }
1204 pure_initcall(tegra234_cbb_init);
1205
tegra234_cbb_exit(void)1206 static void __exit tegra234_cbb_exit(void)
1207 {
1208 platform_driver_unregister(&tegra234_cbb_driver);
1209 }
1210 module_exit(tegra234_cbb_exit);
1211
1212 MODULE_DESCRIPTION("Control Backbone 2.0 error handling driver for Tegra234");
1213