1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/iio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/thermal.h>
17
18 #include "../thermal_hwmon.h"
19
20 #define QPNP_TM_REG_DIG_MINOR 0x00
21 #define QPNP_TM_REG_DIG_MAJOR 0x01
22 #define QPNP_TM_REG_TYPE 0x04
23 #define QPNP_TM_REG_SUBTYPE 0x05
24 #define QPNP_TM_REG_STATUS 0x08
25 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40
26 #define QPNP_TM_REG_ALARM_CTRL 0x46
27
28 #define QPNP_TM_TYPE 0x09
29 #define QPNP_TM_SUBTYPE_GEN1 0x08
30 #define QPNP_TM_SUBTYPE_GEN2 0x09
31
32 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0)
33 #define STATUS_GEN2_STATE_MASK GENMASK(6, 4)
34 #define STATUS_GEN2_STATE_SHIFT 4
35
36 #define SHUTDOWN_CTRL1_OVERRIDE_STAGE2 BIT(6)
37 #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0)
38
39 #define SHUTDOWN_CTRL1_RATE_25HZ BIT(3)
40
41 #define ALARM_CTRL_FORCE_ENABLE BIT(7)
42
43 #define THRESH_COUNT 4
44 #define STAGE_COUNT 3
45
46 /* Over-temperature trip point values in mC */
47 static const long temp_map_gen1[THRESH_COUNT][STAGE_COUNT] = {
48 { 105000, 125000, 145000 },
49 { 110000, 130000, 150000 },
50 { 115000, 135000, 155000 },
51 { 120000, 140000, 160000 },
52 };
53
54 static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = {
55 { 90000, 110000, 140000 },
56 { 95000, 115000, 145000 },
57 { 100000, 120000, 150000 },
58 { 105000, 125000, 155000 },
59 };
60
61 #define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
62
63 #define THRESH_MIN 0
64 #define THRESH_MAX 3
65
66 #define TEMP_STAGE_HYSTERESIS 2000
67
68 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
69 #define DEFAULT_TEMP 37000
70
71 struct qpnp_tm_chip {
72 struct regmap *map;
73 struct device *dev;
74 struct thermal_zone_device *tz_dev;
75 unsigned int subtype;
76 long temp;
77 unsigned int thresh;
78 unsigned int stage;
79 unsigned int base;
80 /* protects .thresh, .stage and chip registers */
81 struct mutex lock;
82 bool initialized;
83 bool require_stage2_shutdown;
84
85 struct iio_channel *adc;
86 const long (*temp_map)[THRESH_COUNT][STAGE_COUNT];
87 };
88
89 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
90 static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
91
qpnp_tm_read(struct qpnp_tm_chip * chip,u16 addr,u8 * data)92 static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
93 {
94 unsigned int val;
95 int ret;
96
97 ret = regmap_read(chip->map, chip->base + addr, &val);
98 if (ret < 0)
99 return ret;
100
101 *data = val;
102 return 0;
103 }
104
qpnp_tm_write(struct qpnp_tm_chip * chip,u16 addr,u8 data)105 static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
106 {
107 return regmap_write(chip->map, chip->base + addr, data);
108 }
109
110 /**
111 * qpnp_tm_decode_temp() - return temperature in mC corresponding to the
112 * specified over-temperature stage
113 * @chip: Pointer to the qpnp_tm chip
114 * @stage: Over-temperature stage
115 *
116 * Return: temperature in mC
117 */
qpnp_tm_decode_temp(struct qpnp_tm_chip * chip,unsigned int stage)118 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage)
119 {
120 if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 ||
121 stage > STAGE_COUNT)
122 return 0;
123
124 return (*chip->temp_map)[chip->thresh][stage - 1];
125 }
126
127 /**
128 * qpnp_tm_get_temp_stage() - return over-temperature stage
129 * @chip: Pointer to the qpnp_tm chip
130 *
131 * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
132 */
qpnp_tm_get_temp_stage(struct qpnp_tm_chip * chip)133 static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
134 {
135 int ret;
136 u8 reg = 0;
137
138 ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®);
139 if (ret < 0)
140 return ret;
141
142 if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
143 ret = reg & STATUS_GEN1_STAGE_MASK;
144 else
145 ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
146
147 return ret;
148 }
149
150 /*
151 * This function updates the internal temp value based on the
152 * current thermal stage and threshold as well as the previous stage
153 */
qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip * chip)154 static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
155 {
156 unsigned int stage, stage_new, stage_old;
157 int ret;
158
159 WARN_ON(!mutex_is_locked(&chip->lock));
160
161 ret = qpnp_tm_get_temp_stage(chip);
162 if (ret < 0)
163 return ret;
164 stage = ret;
165
166 if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
167 stage_new = stage;
168 stage_old = chip->stage;
169 } else {
170 stage_new = alarm_state_map[stage];
171 stage_old = alarm_state_map[chip->stage];
172 }
173
174 if (stage_new > stage_old) {
175 /* increasing stage, use lower bound */
176 chip->temp = qpnp_tm_decode_temp(chip, stage_new)
177 + TEMP_STAGE_HYSTERESIS;
178 } else if (stage_new < stage_old) {
179 /* decreasing stage, use upper bound */
180 chip->temp = qpnp_tm_decode_temp(chip, stage_new + 1)
181 - TEMP_STAGE_HYSTERESIS;
182 }
183
184 chip->stage = stage;
185
186 return 0;
187 }
188
qpnp_tm_get_temp(struct thermal_zone_device * tz,int * temp)189 static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp)
190 {
191 struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz);
192 int ret, mili_celsius;
193
194 if (!temp)
195 return -EINVAL;
196
197 if (!chip->initialized) {
198 *temp = DEFAULT_TEMP;
199 return 0;
200 }
201
202 if (!chip->adc) {
203 mutex_lock(&chip->lock);
204 ret = qpnp_tm_update_temp_no_adc(chip);
205 mutex_unlock(&chip->lock);
206 if (ret < 0)
207 return ret;
208 } else {
209 ret = iio_read_channel_processed(chip->adc, &mili_celsius);
210 if (ret < 0)
211 return ret;
212
213 chip->temp = mili_celsius;
214 }
215
216 *temp = chip->temp;
217
218 return 0;
219 }
220
qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip * chip,int temp)221 static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
222 int temp)
223 {
224 long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1];
225 long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1];
226 bool disable_stage2_shutdown = false;
227 u8 reg;
228
229 WARN_ON(!mutex_is_locked(&chip->lock));
230
231 /*
232 * Default: Stage 2 and Stage 3 shutdown enabled, thresholds at
233 * lowest threshold set, monitoring at 25Hz
234 */
235 reg = SHUTDOWN_CTRL1_RATE_25HZ;
236
237 if (temp == THERMAL_TEMP_INVALID ||
238 temp < stage2_threshold_min) {
239 chip->thresh = THRESH_MIN;
240 goto skip;
241 }
242
243 if (temp <= stage2_threshold_max) {
244 chip->thresh = THRESH_MAX -
245 ((stage2_threshold_max - temp) /
246 TEMP_THRESH_STEP);
247 disable_stage2_shutdown = true;
248 } else {
249 chip->thresh = THRESH_MAX;
250
251 if (chip->adc)
252 disable_stage2_shutdown = true;
253 else
254 dev_warn(chip->dev,
255 "No ADC is configured and critical temperature %d mC is above the maximum stage 2 threshold of %ld mC! Configuring stage 2 shutdown at %ld mC.\n",
256 temp, stage2_threshold_max, stage2_threshold_max);
257 }
258
259 skip:
260 reg |= chip->thresh;
261 if (disable_stage2_shutdown && !chip->require_stage2_shutdown)
262 reg |= SHUTDOWN_CTRL1_OVERRIDE_STAGE2;
263
264 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
265 }
266
qpnp_tm_set_trip_temp(struct thermal_zone_device * tz,const struct thermal_trip * trip,int temp)267 static int qpnp_tm_set_trip_temp(struct thermal_zone_device *tz,
268 const struct thermal_trip *trip, int temp)
269 {
270 struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz);
271 int ret;
272
273 if (trip->type != THERMAL_TRIP_CRITICAL)
274 return 0;
275
276 mutex_lock(&chip->lock);
277 ret = qpnp_tm_update_critical_trip_temp(chip, temp);
278 mutex_unlock(&chip->lock);
279
280 return ret;
281 }
282
283 static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = {
284 .get_temp = qpnp_tm_get_temp,
285 .set_trip_temp = qpnp_tm_set_trip_temp,
286 };
287
qpnp_tm_isr(int irq,void * data)288 static irqreturn_t qpnp_tm_isr(int irq, void *data)
289 {
290 struct qpnp_tm_chip *chip = data;
291
292 thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
293
294 return IRQ_HANDLED;
295 }
296
297 /*
298 * This function initializes the internal temp value based on only the
299 * current thermal stage and threshold. Setup threshold control and
300 * disable shutdown override.
301 */
qpnp_tm_init(struct qpnp_tm_chip * chip)302 static int qpnp_tm_init(struct qpnp_tm_chip *chip)
303 {
304 unsigned int stage;
305 int ret;
306 u8 reg = 0;
307 int crit_temp;
308
309 mutex_lock(&chip->lock);
310
311 ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®);
312 if (ret < 0)
313 goto out;
314
315 chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
316 chip->temp = DEFAULT_TEMP;
317
318 ret = qpnp_tm_get_temp_stage(chip);
319 if (ret < 0)
320 goto out;
321 chip->stage = ret;
322
323 stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
324 ? chip->stage : alarm_state_map[chip->stage];
325
326 if (stage)
327 chip->temp = qpnp_tm_decode_temp(chip, stage);
328
329 mutex_unlock(&chip->lock);
330
331 ret = thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp);
332 if (ret)
333 crit_temp = THERMAL_TEMP_INVALID;
334
335 mutex_lock(&chip->lock);
336
337 ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
338 if (ret < 0)
339 goto out;
340
341 /* Enable the thermal alarm PMIC module in always-on mode. */
342 reg = ALARM_CTRL_FORCE_ENABLE;
343 ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
344
345 chip->initialized = true;
346
347 out:
348 mutex_unlock(&chip->lock);
349 return ret;
350 }
351
qpnp_tm_probe(struct platform_device * pdev)352 static int qpnp_tm_probe(struct platform_device *pdev)
353 {
354 struct qpnp_tm_chip *chip;
355 struct device_node *node;
356 u8 type, subtype, dig_major, dig_minor;
357 u32 res, dig_revision;
358 int ret, irq;
359
360 node = pdev->dev.of_node;
361
362 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
363 if (!chip)
364 return -ENOMEM;
365
366 dev_set_drvdata(&pdev->dev, chip);
367 chip->dev = &pdev->dev;
368
369 mutex_init(&chip->lock);
370
371 chip->map = dev_get_regmap(pdev->dev.parent, NULL);
372 if (!chip->map)
373 return -ENXIO;
374
375 ret = of_property_read_u32(node, "reg", &res);
376 if (ret < 0)
377 return ret;
378
379 irq = platform_get_irq(pdev, 0);
380 if (irq < 0)
381 return irq;
382
383 /* ADC based measurements are optional */
384 chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
385 if (IS_ERR(chip->adc)) {
386 ret = PTR_ERR(chip->adc);
387 chip->adc = NULL;
388 if (ret == -EPROBE_DEFER)
389 return ret;
390 }
391
392 chip->base = res;
393
394 ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
395 if (ret < 0)
396 return dev_err_probe(&pdev->dev, ret,
397 "could not read type\n");
398
399 ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
400 if (ret < 0)
401 return dev_err_probe(&pdev->dev, ret,
402 "could not read subtype\n");
403
404 ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MAJOR, &dig_major);
405 if (ret < 0)
406 return dev_err_probe(&pdev->dev, ret,
407 "could not read dig_major\n");
408
409 ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor);
410 if (ret < 0)
411 return dev_err_probe(&pdev->dev, ret,
412 "could not read dig_minor\n");
413
414 if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
415 && subtype != QPNP_TM_SUBTYPE_GEN2)) {
416 dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
417 type, subtype);
418 return -ENODEV;
419 }
420
421 chip->subtype = subtype;
422 if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1)
423 chip->temp_map = &temp_map_gen2_v1;
424 else
425 chip->temp_map = &temp_map_gen1;
426
427 if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) {
428 dig_revision = (dig_major << 8) | dig_minor;
429 /*
430 * Check if stage 2 automatic partial shutdown must remain
431 * enabled to avoid potential repeated faults upon reaching
432 * over-temperature stage 3.
433 */
434 switch (dig_revision) {
435 case 0x0001:
436 case 0x0002:
437 case 0x0100:
438 case 0x0101:
439 chip->require_stage2_shutdown = true;
440 break;
441 }
442 }
443
444 /*
445 * Register the sensor before initializing the hardware to be able to
446 * read the trip points. get_temp() returns the default temperature
447 * before the hardware initialization is completed.
448 */
449 chip->tz_dev = devm_thermal_of_zone_register(
450 &pdev->dev, 0, chip, &qpnp_tm_sensor_ops);
451 if (IS_ERR(chip->tz_dev))
452 return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev),
453 "failed to register sensor\n");
454
455 ret = qpnp_tm_init(chip);
456 if (ret < 0)
457 return dev_err_probe(&pdev->dev, ret, "init failed\n");
458
459 devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev);
460
461 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
462 IRQF_ONESHOT, node->name, chip);
463 if (ret < 0)
464 return ret;
465
466 thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
467
468 return 0;
469 }
470
471 static const struct of_device_id qpnp_tm_match_table[] = {
472 { .compatible = "qcom,spmi-temp-alarm" },
473 { }
474 };
475 MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
476
477 static struct platform_driver qpnp_tm_driver = {
478 .driver = {
479 .name = "spmi-temp-alarm",
480 .of_match_table = qpnp_tm_match_table,
481 },
482 .probe = qpnp_tm_probe,
483 };
484 module_platform_driver(qpnp_tm_driver);
485
486 MODULE_ALIAS("platform:spmi-temp-alarm");
487 MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
488 MODULE_LICENSE("GPL v2");
489