1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12 #include <linux/units.h>
13
14 #include "sb_regs.h"
15 #include "tb.h"
16
17 #define USB4_DATA_RETRIES 3
18 #define USB4_DATA_DWORDS 16
19
20 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
21 #define USB4_NVM_READ_OFFSET_SHIFT 2
22 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
23 #define USB4_NVM_READ_LENGTH_SHIFT 24
24
25 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
26 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
27
28 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
29 #define USB4_DROM_ADDRESS_SHIFT 2
30 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
31 #define USB4_DROM_SIZE_SHIFT 15
32
33 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
34
35 #define USB4_BA_LENGTH_MASK GENMASK(7, 0)
36 #define USB4_BA_INDEX_MASK GENMASK(15, 0)
37
38 enum usb4_ba_index {
39 USB4_BA_MAX_USB3 = 0x1,
40 USB4_BA_MIN_DP_AUX = 0x2,
41 USB4_BA_MIN_DP_MAIN = 0x3,
42 USB4_BA_MAX_PCIE = 0x4,
43 USB4_BA_MAX_HI = 0x5,
44 };
45
46 #define USB4_BA_VALUE_MASK GENMASK(31, 16)
47 #define USB4_BA_VALUE_SHIFT 16
48
49 /* Delays in us used with usb4_port_wait_for_bit() */
50 #define USB4_PORT_DELAY 50
51 #define USB4_PORT_SB_DELAY 1000
52
usb4_native_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)53 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
54 u32 *metadata, u8 *status,
55 const void *tx_data, size_t tx_dwords,
56 void *rx_data, size_t rx_dwords)
57 {
58 u32 val;
59 int ret;
60
61 if (metadata) {
62 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
63 if (ret)
64 return ret;
65 }
66 if (tx_dwords) {
67 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
68 tx_dwords);
69 if (ret)
70 return ret;
71 }
72
73 val = opcode | ROUTER_CS_26_OV;
74 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
75 if (ret)
76 return ret;
77
78 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
79 if (ret)
80 return ret;
81
82 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
83 if (ret)
84 return ret;
85
86 if (val & ROUTER_CS_26_ONS)
87 return -EOPNOTSUPP;
88
89 if (status)
90 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
91 ROUTER_CS_26_STATUS_SHIFT;
92
93 if (metadata) {
94 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
95 if (ret)
96 return ret;
97 }
98 if (rx_dwords) {
99 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
100 rx_dwords);
101 if (ret)
102 return ret;
103 }
104
105 return 0;
106 }
107
__usb4_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)108 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
109 u8 *status, const void *tx_data, size_t tx_dwords,
110 void *rx_data, size_t rx_dwords)
111 {
112 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
113
114 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
115 return -EINVAL;
116
117 /*
118 * If the connection manager implementation provides USB4 router
119 * operation proxy callback, call it here instead of running the
120 * operation natively.
121 */
122 if (cm_ops->usb4_switch_op) {
123 int ret;
124
125 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
126 tx_data, tx_dwords, rx_data,
127 rx_dwords);
128 if (ret != -EOPNOTSUPP)
129 return ret;
130
131 /*
132 * If the proxy was not supported then run the native
133 * router operation instead.
134 */
135 }
136
137 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
138 tx_dwords, rx_data, rx_dwords);
139 }
140
usb4_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status)141 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
142 u32 *metadata, u8 *status)
143 {
144 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
145 }
146
usb4_switch_op_data(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)147 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
148 u32 *metadata, u8 *status,
149 const void *tx_data, size_t tx_dwords,
150 void *rx_data, size_t rx_dwords)
151 {
152 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
153 tx_dwords, rx_data, rx_dwords);
154 }
155
156 /**
157 * usb4_switch_check_wakes() - Check for wakes and notify PM core about them
158 * @sw: Router whose wakes to check
159 *
160 * Checks wakes occurred during suspend and notify the PM core about them.
161 */
usb4_switch_check_wakes(struct tb_switch * sw)162 void usb4_switch_check_wakes(struct tb_switch *sw)
163 {
164 bool wakeup_usb4 = false;
165 struct usb4_port *usb4;
166 struct tb_port *port;
167 bool wakeup = false;
168 u32 val;
169
170 if (tb_route(sw)) {
171 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
172 return;
173
174 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
175 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
176 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
177
178 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
179 }
180
181 /*
182 * Check for any downstream ports for USB4 wake,
183 * connection wake and disconnection wake.
184 */
185 tb_switch_for_each_port(sw, port) {
186 if (!port->cap_usb4)
187 continue;
188
189 if (tb_port_read(port, &val, TB_CFG_PORT,
190 port->cap_usb4 + PORT_CS_18, 1))
191 break;
192
193 tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
194 (val & PORT_CS_18_WOU4S) ? "yes" : "no",
195 (val & PORT_CS_18_WOCS) ? "yes" : "no",
196 (val & PORT_CS_18_WODS) ? "yes" : "no");
197
198 wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
199 PORT_CS_18_WODS);
200
201 usb4 = port->usb4;
202 if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
203 pm_wakeup_event(&usb4->dev, 0);
204
205 wakeup |= wakeup_usb4;
206 }
207
208 if (wakeup)
209 pm_wakeup_event(&sw->dev, 0);
210 }
211
link_is_usb4(struct tb_port * port)212 static bool link_is_usb4(struct tb_port *port)
213 {
214 u32 val;
215
216 if (!port->cap_usb4)
217 return false;
218
219 if (tb_port_read(port, &val, TB_CFG_PORT,
220 port->cap_usb4 + PORT_CS_18, 1))
221 return false;
222
223 return !(val & PORT_CS_18_TCM);
224 }
225
226 /**
227 * usb4_switch_setup() - Additional setup for USB4 device
228 * @sw: USB4 router to setup
229 *
230 * USB4 routers need additional settings in order to enable all the
231 * tunneling. This function enables USB and PCIe tunneling if it can be
232 * enabled (e.g the parent switch also supports them). If USB tunneling
233 * is not available for some reason (like that there is Thunderbolt 3
234 * switch upstream) then the internal xHCI controller is enabled
235 * instead.
236 *
237 * This does not set the configuration valid bit of the router. To do
238 * that call usb4_switch_configuration_valid().
239 */
usb4_switch_setup(struct tb_switch * sw)240 int usb4_switch_setup(struct tb_switch *sw)
241 {
242 struct tb_switch *parent = tb_switch_parent(sw);
243 struct tb_port *down;
244 bool tbt3, xhci;
245 u32 val = 0;
246 int ret;
247
248 if (!tb_route(sw))
249 return 0;
250
251 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
252 if (ret)
253 return ret;
254
255 down = tb_switch_downstream_port(sw);
256 sw->link_usb4 = link_is_usb4(down);
257 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
258
259 xhci = val & ROUTER_CS_6_HCI;
260 tbt3 = !(val & ROUTER_CS_6_TNS);
261
262 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
263 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
264
265 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
266 if (ret)
267 return ret;
268
269 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
270 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
271 val |= ROUTER_CS_5_UTO;
272 xhci = false;
273 }
274
275 /*
276 * Only enable PCIe tunneling if the parent router supports it
277 * and it is not disabled.
278 */
279 if (tb_acpi_may_tunnel_pcie() &&
280 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
281 val |= ROUTER_CS_5_PTO;
282 /*
283 * xHCI can be enabled if PCIe tunneling is supported
284 * and the parent does not have any USB3 dowstream
285 * adapters (so we cannot do USB 3.x tunneling).
286 */
287 if (xhci)
288 val |= ROUTER_CS_5_HCO;
289 }
290
291 /* TBT3 supported by the CM */
292 val &= ~ROUTER_CS_5_CNS;
293
294 return tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
295 }
296
297 /**
298 * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
299 * @sw: USB4 router
300 *
301 * Sets configuration valid bit for the router. Must be called before
302 * any tunnels can be set through the router and after
303 * usb4_switch_setup() has been called. Can be called to host and device
304 * routers (does nothing for the latter).
305 *
306 * Returns %0 in success and negative errno otherwise.
307 */
usb4_switch_configuration_valid(struct tb_switch * sw)308 int usb4_switch_configuration_valid(struct tb_switch *sw)
309 {
310 u32 val;
311 int ret;
312
313 if (!tb_route(sw))
314 return 0;
315
316 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
317 if (ret)
318 return ret;
319
320 val |= ROUTER_CS_5_CV;
321
322 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
323 if (ret)
324 return ret;
325
326 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
327 ROUTER_CS_6_CR, 50);
328 }
329
330 /**
331 * usb4_switch_read_uid() - Read UID from USB4 router
332 * @sw: USB4 router
333 * @uid: UID is stored here
334 *
335 * Reads 64-bit UID from USB4 router config space.
336 */
usb4_switch_read_uid(struct tb_switch * sw,u64 * uid)337 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
338 {
339 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
340 }
341
usb4_switch_drom_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)342 static int usb4_switch_drom_read_block(void *data,
343 unsigned int dwaddress, void *buf,
344 size_t dwords)
345 {
346 struct tb_switch *sw = data;
347 u8 status = 0;
348 u32 metadata;
349 int ret;
350
351 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
352 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
353 USB4_DROM_ADDRESS_MASK;
354
355 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
356 &status, NULL, 0, buf, dwords);
357 if (ret)
358 return ret;
359
360 return status ? -EIO : 0;
361 }
362
363 /**
364 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
365 * @sw: USB4 router
366 * @address: Byte address inside DROM to start reading
367 * @buf: Buffer where the DROM content is stored
368 * @size: Number of bytes to read from DROM
369 *
370 * Uses USB4 router operations to read router DROM. For devices this
371 * should always work but for hosts it may return %-EOPNOTSUPP in which
372 * case the host router does not have DROM.
373 */
usb4_switch_drom_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)374 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
375 size_t size)
376 {
377 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
378 usb4_switch_drom_read_block, sw);
379 }
380
381 /**
382 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
383 * @sw: USB4 router
384 *
385 * Checks whether conditions are met so that lane bonding can be
386 * established with the upstream router. Call only for device routers.
387 */
usb4_switch_lane_bonding_possible(struct tb_switch * sw)388 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
389 {
390 struct tb_port *up;
391 int ret;
392 u32 val;
393
394 up = tb_upstream_port(sw);
395 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
396 if (ret)
397 return false;
398
399 return !!(val & PORT_CS_18_BE);
400 }
401
402 /**
403 * usb4_switch_set_wake() - Enabled/disable wake
404 * @sw: USB4 router
405 * @flags: Wakeup flags (%0 to disable)
406 * @runtime: Wake is being programmed during system runtime
407 *
408 * Enables/disables router to wake up from sleep.
409 */
usb4_switch_set_wake(struct tb_switch * sw,unsigned int flags,bool runtime)410 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags, bool runtime)
411 {
412 struct tb_port *port;
413 u64 route = tb_route(sw);
414 u32 val;
415 int ret;
416
417 /*
418 * Enable wakes coming from all USB4 downstream ports (from
419 * child routers). For device routers do this also for the
420 * upstream USB4 port.
421 */
422 tb_switch_for_each_port(sw, port) {
423 if (!tb_port_is_null(port))
424 continue;
425 if (!route && tb_is_upstream_port(port))
426 continue;
427 if (!port->cap_usb4)
428 continue;
429
430 ret = tb_port_read(port, &val, TB_CFG_PORT,
431 port->cap_usb4 + PORT_CS_19, 1);
432 if (ret)
433 return ret;
434
435 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
436
437 if (tb_is_upstream_port(port)) {
438 val |= PORT_CS_19_WOU4;
439 } else {
440 bool configured = val & PORT_CS_19_PC;
441 bool wakeup = runtime || device_may_wakeup(&port->usb4->dev);
442
443 if ((flags & TB_WAKE_ON_CONNECT) && wakeup && !configured)
444 val |= PORT_CS_19_WOC;
445 if ((flags & TB_WAKE_ON_DISCONNECT) && wakeup && configured)
446 val |= PORT_CS_19_WOD;
447 if ((flags & TB_WAKE_ON_USB4) && configured)
448 val |= PORT_CS_19_WOU4;
449 }
450
451 ret = tb_port_write(port, &val, TB_CFG_PORT,
452 port->cap_usb4 + PORT_CS_19, 1);
453 if (ret)
454 return ret;
455 }
456
457 /*
458 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
459 * needed for device routers.
460 */
461 if (route) {
462 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
463 if (ret)
464 return ret;
465
466 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
467 if (flags & TB_WAKE_ON_USB3)
468 val |= ROUTER_CS_5_WOU;
469 if (flags & TB_WAKE_ON_PCIE)
470 val |= ROUTER_CS_5_WOP;
471 if (flags & TB_WAKE_ON_DP)
472 val |= ROUTER_CS_5_WOD;
473
474 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
475 if (ret)
476 return ret;
477 }
478
479 return 0;
480 }
481
482 /**
483 * usb4_switch_set_sleep() - Prepare the router to enter sleep
484 * @sw: USB4 router
485 *
486 * Sets sleep bit for the router. Returns when the router sleep ready
487 * bit has been asserted.
488 */
usb4_switch_set_sleep(struct tb_switch * sw)489 int usb4_switch_set_sleep(struct tb_switch *sw)
490 {
491 int ret;
492 u32 val;
493
494 /* Set sleep bit and wait for sleep ready to be asserted */
495 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
496 if (ret)
497 return ret;
498
499 val |= ROUTER_CS_5_SLP;
500
501 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
502 if (ret)
503 return ret;
504
505 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
506 ROUTER_CS_6_SLPR, 500);
507 }
508
509 /**
510 * usb4_switch_nvm_sector_size() - Return router NVM sector size
511 * @sw: USB4 router
512 *
513 * If the router supports NVM operations this function returns the NVM
514 * sector size in bytes. If NVM operations are not supported returns
515 * %-EOPNOTSUPP.
516 */
usb4_switch_nvm_sector_size(struct tb_switch * sw)517 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
518 {
519 u32 metadata;
520 u8 status;
521 int ret;
522
523 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
524 &status);
525 if (ret)
526 return ret;
527
528 if (status)
529 return status == 0x2 ? -EOPNOTSUPP : -EIO;
530
531 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
532 }
533
usb4_switch_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)534 static int usb4_switch_nvm_read_block(void *data,
535 unsigned int dwaddress, void *buf, size_t dwords)
536 {
537 struct tb_switch *sw = data;
538 u8 status = 0;
539 u32 metadata;
540 int ret;
541
542 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
543 USB4_NVM_READ_LENGTH_MASK;
544 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
545 USB4_NVM_READ_OFFSET_MASK;
546
547 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
548 &status, NULL, 0, buf, dwords);
549 if (ret)
550 return ret;
551
552 return status ? -EIO : 0;
553 }
554
555 /**
556 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
557 * @sw: USB4 router
558 * @address: Starting address in bytes
559 * @buf: Read data is placed here
560 * @size: How many bytes to read
561 *
562 * Reads NVM contents of the router. If NVM is not supported returns
563 * %-EOPNOTSUPP.
564 */
usb4_switch_nvm_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)565 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
566 size_t size)
567 {
568 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
569 usb4_switch_nvm_read_block, sw);
570 }
571
572 /**
573 * usb4_switch_nvm_set_offset() - Set NVM write offset
574 * @sw: USB4 router
575 * @address: Start offset
576 *
577 * Explicitly sets NVM write offset. Normally when writing to NVM this
578 * is done automatically by usb4_switch_nvm_write().
579 *
580 * Returns %0 in success and negative errno if there was a failure.
581 */
usb4_switch_nvm_set_offset(struct tb_switch * sw,unsigned int address)582 int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
583 {
584 u32 metadata, dwaddress;
585 u8 status = 0;
586 int ret;
587
588 dwaddress = address / 4;
589 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
590 USB4_NVM_SET_OFFSET_MASK;
591
592 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
593 &status);
594 if (ret)
595 return ret;
596
597 return status ? -EIO : 0;
598 }
599
usb4_switch_nvm_write_next_block(void * data,unsigned int dwaddress,const void * buf,size_t dwords)600 static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
601 const void *buf, size_t dwords)
602 {
603 struct tb_switch *sw = data;
604 u8 status;
605 int ret;
606
607 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
608 buf, dwords, NULL, 0);
609 if (ret)
610 return ret;
611
612 return status ? -EIO : 0;
613 }
614
615 /**
616 * usb4_switch_nvm_write() - Write to the router NVM
617 * @sw: USB4 router
618 * @address: Start address where to write in bytes
619 * @buf: Pointer to the data to write
620 * @size: Size of @buf in bytes
621 *
622 * Writes @buf to the router NVM using USB4 router operations. If NVM
623 * write is not supported returns %-EOPNOTSUPP.
624 */
usb4_switch_nvm_write(struct tb_switch * sw,unsigned int address,const void * buf,size_t size)625 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
626 const void *buf, size_t size)
627 {
628 int ret;
629
630 ret = usb4_switch_nvm_set_offset(sw, address);
631 if (ret)
632 return ret;
633
634 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
635 usb4_switch_nvm_write_next_block, sw);
636 }
637
638 /**
639 * usb4_switch_nvm_authenticate() - Authenticate new NVM
640 * @sw: USB4 router
641 *
642 * After the new NVM has been written via usb4_switch_nvm_write(), this
643 * function triggers NVM authentication process. The router gets power
644 * cycled and if the authentication is successful the new NVM starts
645 * running. In case of failure returns negative errno.
646 *
647 * The caller should call usb4_switch_nvm_authenticate_status() to read
648 * the status of the authentication after power cycle. It should be the
649 * first router operation to avoid the status being lost.
650 */
usb4_switch_nvm_authenticate(struct tb_switch * sw)651 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
652 {
653 int ret;
654
655 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
656 switch (ret) {
657 /*
658 * The router is power cycled once NVM_AUTH is started so it is
659 * expected to get any of the following errors back.
660 */
661 case -EACCES:
662 case -ENOTCONN:
663 case -ETIMEDOUT:
664 return 0;
665
666 default:
667 return ret;
668 }
669 }
670
671 /**
672 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
673 * @sw: USB4 router
674 * @status: Status code of the operation
675 *
676 * The function checks if there is status available from the last NVM
677 * authenticate router operation. If there is status then %0 is returned
678 * and the status code is placed in @status. Returns negative errno in case
679 * of failure.
680 *
681 * Must be called before any other router operation.
682 */
usb4_switch_nvm_authenticate_status(struct tb_switch * sw,u32 * status)683 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
684 {
685 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
686 u16 opcode;
687 u32 val;
688 int ret;
689
690 if (cm_ops->usb4_switch_nvm_authenticate_status) {
691 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
692 if (ret != -EOPNOTSUPP)
693 return ret;
694 }
695
696 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
697 if (ret)
698 return ret;
699
700 /* Check that the opcode is correct */
701 opcode = val & ROUTER_CS_26_OPCODE_MASK;
702 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
703 if (val & ROUTER_CS_26_OV)
704 return -EBUSY;
705 if (val & ROUTER_CS_26_ONS)
706 return -EOPNOTSUPP;
707
708 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
709 ROUTER_CS_26_STATUS_SHIFT;
710 } else {
711 *status = 0;
712 }
713
714 return 0;
715 }
716
717 /**
718 * usb4_switch_credits_init() - Read buffer allocation parameters
719 * @sw: USB4 router
720 *
721 * Reads @sw buffer allocation parameters and initializes @sw buffer
722 * allocation fields accordingly. Specifically @sw->credits_allocation
723 * is set to %true if these parameters can be used in tunneling.
724 *
725 * Returns %0 on success and negative errno otherwise.
726 */
usb4_switch_credits_init(struct tb_switch * sw)727 int usb4_switch_credits_init(struct tb_switch *sw)
728 {
729 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
730 int ret, length, i, nports;
731 const struct tb_port *port;
732 u32 data[USB4_DATA_DWORDS];
733 u32 metadata = 0;
734 u8 status = 0;
735
736 memset(data, 0, sizeof(data));
737 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
738 &status, NULL, 0, data, ARRAY_SIZE(data));
739 if (ret)
740 return ret;
741 if (status)
742 return -EIO;
743
744 length = metadata & USB4_BA_LENGTH_MASK;
745 if (WARN_ON(length > ARRAY_SIZE(data)))
746 return -EMSGSIZE;
747
748 max_usb3 = -1;
749 min_dp_aux = -1;
750 min_dp_main = -1;
751 max_pcie = -1;
752 max_dma = -1;
753
754 tb_sw_dbg(sw, "credit allocation parameters:\n");
755
756 for (i = 0; i < length; i++) {
757 u16 index, value;
758
759 index = data[i] & USB4_BA_INDEX_MASK;
760 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
761
762 switch (index) {
763 case USB4_BA_MAX_USB3:
764 tb_sw_dbg(sw, " USB3: %u\n", value);
765 max_usb3 = value;
766 break;
767 case USB4_BA_MIN_DP_AUX:
768 tb_sw_dbg(sw, " DP AUX: %u\n", value);
769 min_dp_aux = value;
770 break;
771 case USB4_BA_MIN_DP_MAIN:
772 tb_sw_dbg(sw, " DP main: %u\n", value);
773 min_dp_main = value;
774 break;
775 case USB4_BA_MAX_PCIE:
776 tb_sw_dbg(sw, " PCIe: %u\n", value);
777 max_pcie = value;
778 break;
779 case USB4_BA_MAX_HI:
780 tb_sw_dbg(sw, " DMA: %u\n", value);
781 max_dma = value;
782 break;
783 default:
784 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
785 index);
786 break;
787 }
788 }
789
790 /*
791 * Validate the buffer allocation preferences. If we find
792 * issues, log a warning and fall back using the hard-coded
793 * values.
794 */
795
796 /* Host router must report baMaxHI */
797 if (!tb_route(sw) && max_dma < 0) {
798 tb_sw_warn(sw, "host router is missing baMaxHI\n");
799 goto err_invalid;
800 }
801
802 nports = 0;
803 tb_switch_for_each_port(sw, port) {
804 if (tb_port_is_null(port))
805 nports++;
806 }
807
808 /* Must have DP buffer allocation (multiple USB4 ports) */
809 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
810 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
811 goto err_invalid;
812 }
813
814 tb_switch_for_each_port(sw, port) {
815 if (tb_port_is_dpout(port) && min_dp_main < 0) {
816 tb_sw_warn(sw, "missing baMinDPmain");
817 goto err_invalid;
818 }
819 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
820 min_dp_aux < 0) {
821 tb_sw_warn(sw, "missing baMinDPaux");
822 goto err_invalid;
823 }
824 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
825 max_usb3 < 0) {
826 tb_sw_warn(sw, "missing baMaxUSB3");
827 goto err_invalid;
828 }
829 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
830 max_pcie < 0) {
831 tb_sw_warn(sw, "missing baMaxPCIe");
832 goto err_invalid;
833 }
834 }
835
836 /*
837 * Buffer allocation passed the validation so we can use it in
838 * path creation.
839 */
840 sw->credit_allocation = true;
841 if (max_usb3 > 0)
842 sw->max_usb3_credits = max_usb3;
843 if (min_dp_aux > 0)
844 sw->min_dp_aux_credits = min_dp_aux;
845 if (min_dp_main > 0)
846 sw->min_dp_main_credits = min_dp_main;
847 if (max_pcie > 0)
848 sw->max_pcie_credits = max_pcie;
849 if (max_dma > 0)
850 sw->max_dma_credits = max_dma;
851
852 return 0;
853
854 err_invalid:
855 return -EINVAL;
856 }
857
858 /**
859 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
860 * @sw: USB4 router
861 * @in: DP IN adapter
862 *
863 * For DP tunneling this function can be used to query availability of
864 * DP IN resource. Returns true if the resource is available for DP
865 * tunneling, false otherwise.
866 */
usb4_switch_query_dp_resource(struct tb_switch * sw,struct tb_port * in)867 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
868 {
869 u32 metadata = in->port;
870 u8 status;
871 int ret;
872
873 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
874 &status);
875 /*
876 * If DP resource allocation is not supported assume it is
877 * always available.
878 */
879 if (ret == -EOPNOTSUPP)
880 return true;
881 if (ret)
882 return false;
883
884 return !status;
885 }
886
887 /**
888 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
889 * @sw: USB4 router
890 * @in: DP IN adapter
891 *
892 * Allocates DP IN resource for DP tunneling using USB4 router
893 * operations. If the resource was allocated returns %0. Otherwise
894 * returns negative errno, in particular %-EBUSY if the resource is
895 * already allocated.
896 */
usb4_switch_alloc_dp_resource(struct tb_switch * sw,struct tb_port * in)897 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
898 {
899 u32 metadata = in->port;
900 u8 status;
901 int ret;
902
903 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
904 &status);
905 if (ret == -EOPNOTSUPP)
906 return 0;
907 if (ret)
908 return ret;
909
910 return status ? -EBUSY : 0;
911 }
912
913 /**
914 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
915 * @sw: USB4 router
916 * @in: DP IN adapter
917 *
918 * Releases the previously allocated DP IN resource.
919 */
usb4_switch_dealloc_dp_resource(struct tb_switch * sw,struct tb_port * in)920 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
921 {
922 u32 metadata = in->port;
923 u8 status;
924 int ret;
925
926 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
927 &status);
928 if (ret == -EOPNOTSUPP)
929 return 0;
930 if (ret)
931 return ret;
932
933 return status ? -EIO : 0;
934 }
935
usb4_port_idx(const struct tb_switch * sw,const struct tb_port * port)936 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
937 {
938 struct tb_port *p;
939 int usb4_idx = 0;
940
941 /* Assume port is primary */
942 tb_switch_for_each_port(sw, p) {
943 if (!tb_port_is_null(p))
944 continue;
945 if (tb_is_upstream_port(p))
946 continue;
947 if (!p->link_nr) {
948 if (p == port)
949 break;
950 usb4_idx++;
951 }
952 }
953
954 return usb4_idx;
955 }
956
957 /**
958 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
959 * @sw: USB4 router
960 * @port: USB4 port
961 *
962 * USB4 routers have direct mapping between USB4 ports and PCIe
963 * downstream adapters where the PCIe topology is extended. This
964 * function returns the corresponding downstream PCIe adapter or %NULL
965 * if no such mapping was possible.
966 */
usb4_switch_map_pcie_down(struct tb_switch * sw,const struct tb_port * port)967 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
968 const struct tb_port *port)
969 {
970 int usb4_idx = usb4_port_idx(sw, port);
971 struct tb_port *p;
972 int pcie_idx = 0;
973
974 /* Find PCIe down port matching usb4_port */
975 tb_switch_for_each_port(sw, p) {
976 if (!tb_port_is_pcie_down(p))
977 continue;
978
979 if (pcie_idx == usb4_idx)
980 return p;
981
982 pcie_idx++;
983 }
984
985 return NULL;
986 }
987
988 /**
989 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
990 * @sw: USB4 router
991 * @port: USB4 port
992 *
993 * USB4 routers have direct mapping between USB4 ports and USB 3.x
994 * downstream adapters where the USB 3.x topology is extended. This
995 * function returns the corresponding downstream USB 3.x adapter or
996 * %NULL if no such mapping was possible.
997 */
usb4_switch_map_usb3_down(struct tb_switch * sw,const struct tb_port * port)998 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
999 const struct tb_port *port)
1000 {
1001 int usb4_idx = usb4_port_idx(sw, port);
1002 struct tb_port *p;
1003 int usb_idx = 0;
1004
1005 /* Find USB3 down port matching usb4_port */
1006 tb_switch_for_each_port(sw, p) {
1007 if (!tb_port_is_usb3_down(p))
1008 continue;
1009
1010 if (usb_idx == usb4_idx)
1011 return p;
1012
1013 usb_idx++;
1014 }
1015
1016 return NULL;
1017 }
1018
1019 /**
1020 * usb4_switch_add_ports() - Add USB4 ports for this router
1021 * @sw: USB4 router
1022 *
1023 * For USB4 router finds all USB4 ports and registers devices for each.
1024 * Can be called to any router.
1025 *
1026 * Return %0 in case of success and negative errno in case of failure.
1027 */
usb4_switch_add_ports(struct tb_switch * sw)1028 int usb4_switch_add_ports(struct tb_switch *sw)
1029 {
1030 struct tb_port *port;
1031
1032 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1033 return 0;
1034
1035 tb_switch_for_each_port(sw, port) {
1036 struct usb4_port *usb4;
1037
1038 if (!tb_port_is_null(port))
1039 continue;
1040 if (!port->cap_usb4)
1041 continue;
1042
1043 usb4 = usb4_port_device_add(port);
1044 if (IS_ERR(usb4)) {
1045 usb4_switch_remove_ports(sw);
1046 return PTR_ERR(usb4);
1047 }
1048
1049 port->usb4 = usb4;
1050 }
1051
1052 return 0;
1053 }
1054
1055 /**
1056 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1057 * @sw: USB4 router
1058 *
1059 * Unregisters previously registered USB4 ports.
1060 */
usb4_switch_remove_ports(struct tb_switch * sw)1061 void usb4_switch_remove_ports(struct tb_switch *sw)
1062 {
1063 struct tb_port *port;
1064
1065 tb_switch_for_each_port(sw, port) {
1066 if (port->usb4) {
1067 usb4_port_device_remove(port->usb4);
1068 port->usb4 = NULL;
1069 }
1070 }
1071 }
1072
1073 /**
1074 * usb4_port_unlock() - Unlock USB4 downstream port
1075 * @port: USB4 port to unlock
1076 *
1077 * Unlocks USB4 downstream port so that the connection manager can
1078 * access the router below this port.
1079 */
usb4_port_unlock(struct tb_port * port)1080 int usb4_port_unlock(struct tb_port *port)
1081 {
1082 int ret;
1083 u32 val;
1084
1085 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1086 if (ret)
1087 return ret;
1088
1089 val &= ~ADP_CS_4_LCK;
1090 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1091 }
1092
1093 /**
1094 * usb4_port_hotplug_enable() - Enables hotplug for a port
1095 * @port: USB4 port to operate on
1096 *
1097 * Enables hot plug events on a given port. This is only intended
1098 * to be used on lane, DP-IN, and DP-OUT adapters.
1099 */
usb4_port_hotplug_enable(struct tb_port * port)1100 int usb4_port_hotplug_enable(struct tb_port *port)
1101 {
1102 int ret;
1103 u32 val;
1104
1105 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1106 if (ret)
1107 return ret;
1108
1109 val &= ~ADP_CS_5_DHP;
1110 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1111 }
1112
1113 /**
1114 * usb4_port_reset() - Issue downstream port reset
1115 * @port: USB4 port to reset
1116 *
1117 * Issues downstream port reset to @port.
1118 */
usb4_port_reset(struct tb_port * port)1119 int usb4_port_reset(struct tb_port *port)
1120 {
1121 int ret;
1122 u32 val;
1123
1124 if (!port->cap_usb4)
1125 return -EINVAL;
1126
1127 ret = tb_port_read(port, &val, TB_CFG_PORT,
1128 port->cap_usb4 + PORT_CS_19, 1);
1129 if (ret)
1130 return ret;
1131
1132 val |= PORT_CS_19_DPR;
1133
1134 ret = tb_port_write(port, &val, TB_CFG_PORT,
1135 port->cap_usb4 + PORT_CS_19, 1);
1136 if (ret)
1137 return ret;
1138
1139 fsleep(10000);
1140
1141 ret = tb_port_read(port, &val, TB_CFG_PORT,
1142 port->cap_usb4 + PORT_CS_19, 1);
1143 if (ret)
1144 return ret;
1145
1146 val &= ~PORT_CS_19_DPR;
1147
1148 return tb_port_write(port, &val, TB_CFG_PORT,
1149 port->cap_usb4 + PORT_CS_19, 1);
1150 }
1151
usb4_port_set_configured(struct tb_port * port,bool configured)1152 static int usb4_port_set_configured(struct tb_port *port, bool configured)
1153 {
1154 int ret;
1155 u32 val;
1156
1157 if (!port->cap_usb4)
1158 return -EINVAL;
1159
1160 ret = tb_port_read(port, &val, TB_CFG_PORT,
1161 port->cap_usb4 + PORT_CS_19, 1);
1162 if (ret)
1163 return ret;
1164
1165 if (configured)
1166 val |= PORT_CS_19_PC;
1167 else
1168 val &= ~PORT_CS_19_PC;
1169
1170 return tb_port_write(port, &val, TB_CFG_PORT,
1171 port->cap_usb4 + PORT_CS_19, 1);
1172 }
1173
1174 /**
1175 * usb4_port_configure() - Set USB4 port configured
1176 * @port: USB4 router
1177 *
1178 * Sets the USB4 link to be configured for power management purposes.
1179 */
usb4_port_configure(struct tb_port * port)1180 int usb4_port_configure(struct tb_port *port)
1181 {
1182 return usb4_port_set_configured(port, true);
1183 }
1184
1185 /**
1186 * usb4_port_unconfigure() - Set USB4 port unconfigured
1187 * @port: USB4 router
1188 *
1189 * Sets the USB4 link to be unconfigured for power management purposes.
1190 */
usb4_port_unconfigure(struct tb_port * port)1191 void usb4_port_unconfigure(struct tb_port *port)
1192 {
1193 usb4_port_set_configured(port, false);
1194 }
1195
usb4_set_xdomain_configured(struct tb_port * port,bool configured)1196 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1197 {
1198 int ret;
1199 u32 val;
1200
1201 if (!port->cap_usb4)
1202 return -EINVAL;
1203
1204 ret = tb_port_read(port, &val, TB_CFG_PORT,
1205 port->cap_usb4 + PORT_CS_19, 1);
1206 if (ret)
1207 return ret;
1208
1209 if (configured)
1210 val |= PORT_CS_19_PID;
1211 else
1212 val &= ~PORT_CS_19_PID;
1213
1214 return tb_port_write(port, &val, TB_CFG_PORT,
1215 port->cap_usb4 + PORT_CS_19, 1);
1216 }
1217
1218 /**
1219 * usb4_port_configure_xdomain() - Configure port for XDomain
1220 * @port: USB4 port connected to another host
1221 * @xd: XDomain that is connected to the port
1222 *
1223 * Marks the USB4 port as being connected to another host and updates
1224 * the link type. Returns %0 in success and negative errno in failure.
1225 */
usb4_port_configure_xdomain(struct tb_port * port,struct tb_xdomain * xd)1226 int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1227 {
1228 xd->link_usb4 = link_is_usb4(port);
1229 return usb4_set_xdomain_configured(port, true);
1230 }
1231
1232 /**
1233 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1234 * @port: USB4 port that was connected to another host
1235 *
1236 * Clears USB4 port from being marked as XDomain.
1237 */
usb4_port_unconfigure_xdomain(struct tb_port * port)1238 void usb4_port_unconfigure_xdomain(struct tb_port *port)
1239 {
1240 usb4_set_xdomain_configured(port, false);
1241 }
1242
usb4_port_wait_for_bit(struct tb_port * port,u32 offset,u32 bit,u32 value,int timeout_msec,unsigned long delay_usec)1243 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1244 u32 value, int timeout_msec, unsigned long delay_usec)
1245 {
1246 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1247
1248 do {
1249 u32 val;
1250 int ret;
1251
1252 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1253 if (ret)
1254 return ret;
1255
1256 if ((val & bit) == value)
1257 return 0;
1258
1259 fsleep(delay_usec);
1260 } while (ktime_before(ktime_get(), timeout));
1261
1262 return -ETIMEDOUT;
1263 }
1264
usb4_port_read_data(struct tb_port * port,void * data,size_t dwords)1265 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1266 {
1267 if (dwords > USB4_DATA_DWORDS)
1268 return -EINVAL;
1269
1270 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1271 dwords);
1272 }
1273
usb4_port_write_data(struct tb_port * port,const void * data,size_t dwords)1274 static int usb4_port_write_data(struct tb_port *port, const void *data,
1275 size_t dwords)
1276 {
1277 if (dwords > USB4_DATA_DWORDS)
1278 return -EINVAL;
1279
1280 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1281 dwords);
1282 }
1283
1284 /**
1285 * usb4_port_sb_read() - Read from sideband register
1286 * @port: USB4 port to read
1287 * @target: Sideband target
1288 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1289 * @reg: Sideband register index
1290 * @buf: Buffer where the sideband data is copied
1291 * @size: Size of @buf
1292 *
1293 * Reads data from sideband register @reg and copies it into @buf.
1294 * Returns %0 in case of success and negative errno in case of failure.
1295 */
usb4_port_sb_read(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,void * buf,u8 size)1296 int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, u8 index,
1297 u8 reg, void *buf, u8 size)
1298 {
1299 size_t dwords = DIV_ROUND_UP(size, 4);
1300 int ret;
1301 u32 val;
1302
1303 if (!port->cap_usb4)
1304 return -EINVAL;
1305
1306 val = reg;
1307 val |= size << PORT_CS_1_LENGTH_SHIFT;
1308 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1309 if (target == USB4_SB_TARGET_RETIMER)
1310 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1311 val |= PORT_CS_1_PND;
1312
1313 ret = tb_port_write(port, &val, TB_CFG_PORT,
1314 port->cap_usb4 + PORT_CS_1, 1);
1315 if (ret)
1316 return ret;
1317
1318 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1319 PORT_CS_1_PND, 0, 500, USB4_PORT_SB_DELAY);
1320 if (ret)
1321 return ret;
1322
1323 ret = tb_port_read(port, &val, TB_CFG_PORT,
1324 port->cap_usb4 + PORT_CS_1, 1);
1325 if (ret)
1326 return ret;
1327
1328 if (val & PORT_CS_1_NR)
1329 return -ENODEV;
1330 if (val & PORT_CS_1_RC)
1331 return -EIO;
1332
1333 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1334 }
1335
1336 /**
1337 * usb4_port_sb_write() - Write to sideband register
1338 * @port: USB4 port to write
1339 * @target: Sideband target
1340 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1341 * @reg: Sideband register index
1342 * @buf: Data to write
1343 * @size: Size of @buf
1344 *
1345 * Writes @buf to sideband register @reg. Returns %0 in case of success
1346 * and negative errno in case of failure.
1347 */
usb4_port_sb_write(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,const void * buf,u8 size)1348 int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1349 u8 index, u8 reg, const void *buf, u8 size)
1350 {
1351 size_t dwords = DIV_ROUND_UP(size, 4);
1352 int ret;
1353 u32 val;
1354
1355 if (!port->cap_usb4)
1356 return -EINVAL;
1357
1358 if (buf) {
1359 ret = usb4_port_write_data(port, buf, dwords);
1360 if (ret)
1361 return ret;
1362 }
1363
1364 val = reg;
1365 val |= size << PORT_CS_1_LENGTH_SHIFT;
1366 val |= PORT_CS_1_WNR_WRITE;
1367 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1368 if (target == USB4_SB_TARGET_RETIMER)
1369 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1370 val |= PORT_CS_1_PND;
1371
1372 ret = tb_port_write(port, &val, TB_CFG_PORT,
1373 port->cap_usb4 + PORT_CS_1, 1);
1374 if (ret)
1375 return ret;
1376
1377 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1378 PORT_CS_1_PND, 0, 500, USB4_PORT_SB_DELAY);
1379 if (ret)
1380 return ret;
1381
1382 ret = tb_port_read(port, &val, TB_CFG_PORT,
1383 port->cap_usb4 + PORT_CS_1, 1);
1384 if (ret)
1385 return ret;
1386
1387 if (val & PORT_CS_1_NR)
1388 return -ENODEV;
1389 if (val & PORT_CS_1_RC)
1390 return -EIO;
1391
1392 return 0;
1393 }
1394
usb4_port_sb_opcode_err_to_errno(u32 val)1395 static int usb4_port_sb_opcode_err_to_errno(u32 val)
1396 {
1397 switch (val) {
1398 case 0:
1399 return 0;
1400 case USB4_SB_OPCODE_ERR:
1401 return -EAGAIN;
1402 case USB4_SB_OPCODE_ONS:
1403 return -EOPNOTSUPP;
1404 default:
1405 return -EIO;
1406 }
1407 }
1408
usb4_port_sb_op(struct tb_port * port,enum usb4_sb_target target,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1409 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1410 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1411 {
1412 ktime_t timeout;
1413 u32 val;
1414 int ret;
1415
1416 val = opcode;
1417 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1418 sizeof(val));
1419 if (ret)
1420 return ret;
1421
1422 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1423
1424 do {
1425 /* Check results */
1426 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1427 &val, sizeof(val));
1428 if (ret)
1429 return ret;
1430
1431 if (val != opcode)
1432 return usb4_port_sb_opcode_err_to_errno(val);
1433
1434 fsleep(USB4_PORT_SB_DELAY);
1435 } while (ktime_before(ktime_get(), timeout));
1436
1437 return -ETIMEDOUT;
1438 }
1439
usb4_port_set_router_offline(struct tb_port * port,bool offline)1440 static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1441 {
1442 u32 val = !offline;
1443 int ret;
1444
1445 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1446 USB4_SB_METADATA, &val, sizeof(val));
1447 if (ret)
1448 return ret;
1449
1450 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1451 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1452 USB4_SB_OPCODE, &val, sizeof(val));
1453 }
1454
1455 /**
1456 * usb4_port_router_offline() - Put the USB4 port to offline mode
1457 * @port: USB4 port
1458 *
1459 * This function puts the USB4 port into offline mode. In this mode the
1460 * port does not react on hotplug events anymore. This needs to be
1461 * called before retimer access is done when the USB4 links is not up.
1462 *
1463 * Returns %0 in case of success and negative errno if there was an
1464 * error.
1465 */
usb4_port_router_offline(struct tb_port * port)1466 int usb4_port_router_offline(struct tb_port *port)
1467 {
1468 return usb4_port_set_router_offline(port, true);
1469 }
1470
1471 /**
1472 * usb4_port_router_online() - Put the USB4 port back to online
1473 * @port: USB4 port
1474 *
1475 * Makes the USB4 port functional again.
1476 */
usb4_port_router_online(struct tb_port * port)1477 int usb4_port_router_online(struct tb_port *port)
1478 {
1479 return usb4_port_set_router_offline(port, false);
1480 }
1481
1482 /**
1483 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1484 * @port: USB4 port
1485 *
1486 * This forces the USB4 port to send broadcast RT transaction which
1487 * makes the retimers on the link to assign index to themselves. Returns
1488 * %0 in case of success and negative errno if there was an error.
1489 */
usb4_port_enumerate_retimers(struct tb_port * port)1490 int usb4_port_enumerate_retimers(struct tb_port *port)
1491 {
1492 u32 val;
1493
1494 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1495 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1496 USB4_SB_OPCODE, &val, sizeof(val));
1497 }
1498
1499 /**
1500 * usb4_port_clx_supported() - Check if CLx is supported by the link
1501 * @port: Port to check for CLx support for
1502 *
1503 * PORT_CS_18_CPS bit reflects if the link supports CLx including
1504 * active cables (if connected on the link).
1505 */
usb4_port_clx_supported(struct tb_port * port)1506 bool usb4_port_clx_supported(struct tb_port *port)
1507 {
1508 int ret;
1509 u32 val;
1510
1511 ret = tb_port_read(port, &val, TB_CFG_PORT,
1512 port->cap_usb4 + PORT_CS_18, 1);
1513 if (ret)
1514 return false;
1515
1516 return !!(val & PORT_CS_18_CPS);
1517 }
1518
1519 /**
1520 * usb4_port_asym_supported() - If the port supports asymmetric link
1521 * @port: USB4 port
1522 *
1523 * Checks if the port and the cable supports asymmetric link and returns
1524 * %true in that case.
1525 */
usb4_port_asym_supported(struct tb_port * port)1526 bool usb4_port_asym_supported(struct tb_port *port)
1527 {
1528 u32 val;
1529
1530 if (!port->cap_usb4)
1531 return false;
1532
1533 if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
1534 return false;
1535
1536 return !!(val & PORT_CS_18_CSA);
1537 }
1538
1539 /**
1540 * usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1541 * @port: USB4 port
1542 * @width: Asymmetric width to configure
1543 *
1544 * Sets USB4 port link width to @width. Can be called for widths where
1545 * usb4_port_asym_width_supported() returned @true.
1546 */
usb4_port_asym_set_link_width(struct tb_port * port,enum tb_link_width width)1547 int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1548 {
1549 u32 val;
1550 int ret;
1551
1552 if (!port->cap_phy)
1553 return -EINVAL;
1554
1555 ret = tb_port_read(port, &val, TB_CFG_PORT,
1556 port->cap_phy + LANE_ADP_CS_1, 1);
1557 if (ret)
1558 return ret;
1559
1560 val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1561 switch (width) {
1562 case TB_LINK_WIDTH_DUAL:
1563 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1564 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1565 break;
1566 case TB_LINK_WIDTH_ASYM_TX:
1567 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1568 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1569 break;
1570 case TB_LINK_WIDTH_ASYM_RX:
1571 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1572 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1573 break;
1574 default:
1575 return -EINVAL;
1576 }
1577
1578 return tb_port_write(port, &val, TB_CFG_PORT,
1579 port->cap_phy + LANE_ADP_CS_1, 1);
1580 }
1581
1582 /**
1583 * usb4_port_asym_start() - Start symmetry change and wait for completion
1584 * @port: USB4 port
1585 *
1586 * Start symmetry change of the link to asymmetric or symmetric
1587 * (according to what was previously set in tb_port_set_link_width().
1588 * Wait for completion of the change.
1589 *
1590 * Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
1591 * a negative errno in case of a failure.
1592 */
usb4_port_asym_start(struct tb_port * port)1593 int usb4_port_asym_start(struct tb_port *port)
1594 {
1595 int ret;
1596 u32 val;
1597
1598 ret = tb_port_read(port, &val, TB_CFG_PORT,
1599 port->cap_usb4 + PORT_CS_19, 1);
1600 if (ret)
1601 return ret;
1602
1603 val &= ~PORT_CS_19_START_ASYM;
1604 val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1605
1606 ret = tb_port_write(port, &val, TB_CFG_PORT,
1607 port->cap_usb4 + PORT_CS_19, 1);
1608 if (ret)
1609 return ret;
1610
1611 /*
1612 * Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1613 * port started the symmetry transition.
1614 */
1615 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
1616 PORT_CS_19_START_ASYM, 0, 1000,
1617 USB4_PORT_DELAY);
1618 if (ret)
1619 return ret;
1620
1621 /* Then wait for the transtion to be completed */
1622 return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
1623 PORT_CS_18_TIP, 0, 5000, USB4_PORT_DELAY);
1624 }
1625
1626 /**
1627 * usb4_port_margining_caps() - Read USB4 port marginig capabilities
1628 * @port: USB4 port
1629 * @target: Sideband target
1630 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1631 * @caps: Array with at least two elements to hold the results
1632 *
1633 * Reads the USB4 port lane margining capabilities into @caps.
1634 */
usb4_port_margining_caps(struct tb_port * port,enum usb4_sb_target target,u8 index,u32 * caps)1635 int usb4_port_margining_caps(struct tb_port *port, enum usb4_sb_target target,
1636 u8 index, u32 *caps)
1637 {
1638 int ret;
1639
1640 ret = usb4_port_sb_op(port, target, index,
1641 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1642 if (ret)
1643 return ret;
1644
1645 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, caps,
1646 sizeof(*caps) * 2);
1647 }
1648
1649 /**
1650 * usb4_port_hw_margin() - Run hardware lane margining on port
1651 * @port: USB4 port
1652 * @target: Sideband target
1653 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1654 * @params: Parameters for USB4 hardware margining
1655 * @results: Array with at least two elements to hold the results
1656 *
1657 * Runs hardware lane margining on USB4 port and returns the result in
1658 * @results.
1659 */
usb4_port_hw_margin(struct tb_port * port,enum usb4_sb_target target,u8 index,const struct usb4_port_margining_params * params,u32 * results)1660 int usb4_port_hw_margin(struct tb_port *port, enum usb4_sb_target target,
1661 u8 index, const struct usb4_port_margining_params *params,
1662 u32 *results)
1663 {
1664 u32 val;
1665 int ret;
1666
1667 if (WARN_ON_ONCE(!params))
1668 return -EINVAL;
1669
1670 val = params->lanes;
1671 if (params->time)
1672 val |= USB4_MARGIN_HW_TIME;
1673 if (params->right_high)
1674 val |= USB4_MARGIN_HW_RH;
1675 if (params->ber_level)
1676 val |= FIELD_PREP(USB4_MARGIN_HW_BER_MASK, params->ber_level);
1677 if (params->optional_voltage_offset_range)
1678 val |= USB4_MARGIN_HW_OPT_VOLTAGE;
1679
1680 ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
1681 sizeof(val));
1682 if (ret)
1683 return ret;
1684
1685 ret = usb4_port_sb_op(port, target, index,
1686 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1687 if (ret)
1688 return ret;
1689
1690 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, results,
1691 sizeof(*results) * 2);
1692 }
1693
1694 /**
1695 * usb4_port_sw_margin() - Run software lane margining on port
1696 * @port: USB4 port
1697 * @target: Sideband target
1698 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1699 * @params: Parameters for USB4 software margining
1700 * @results: Data word for the operation completion data
1701 *
1702 * Runs software lane margining on USB4 port. Read back the error
1703 * counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1704 * success and negative errno otherwise.
1705 */
usb4_port_sw_margin(struct tb_port * port,enum usb4_sb_target target,u8 index,const struct usb4_port_margining_params * params,u32 * results)1706 int usb4_port_sw_margin(struct tb_port *port, enum usb4_sb_target target,
1707 u8 index, const struct usb4_port_margining_params *params,
1708 u32 *results)
1709 {
1710 u32 val;
1711 int ret;
1712
1713 if (WARN_ON_ONCE(!params))
1714 return -EINVAL;
1715
1716 val = params->lanes;
1717 if (params->time)
1718 val |= USB4_MARGIN_SW_TIME;
1719 if (params->optional_voltage_offset_range)
1720 val |= USB4_MARGIN_SW_OPT_VOLTAGE;
1721 if (params->right_high)
1722 val |= USB4_MARGIN_SW_RH;
1723 val |= FIELD_PREP(USB4_MARGIN_SW_COUNTER_MASK, params->error_counter);
1724 val |= FIELD_PREP(USB4_MARGIN_SW_VT_MASK, params->voltage_time_offset);
1725
1726 ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
1727 sizeof(val));
1728 if (ret)
1729 return ret;
1730
1731 ret = usb4_port_sb_op(port, target, index,
1732 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1733 if (ret)
1734 return ret;
1735
1736 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, results,
1737 sizeof(*results));
1738
1739 }
1740
1741 /**
1742 * usb4_port_sw_margin_errors() - Read the software margining error counters
1743 * @port: USB4 port
1744 * @target: Sideband target
1745 * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
1746 * @errors: Error metadata is copied here.
1747 *
1748 * This reads back the software margining error counters from the port.
1749 * Returns %0 in success and negative errno otherwise.
1750 */
usb4_port_sw_margin_errors(struct tb_port * port,enum usb4_sb_target target,u8 index,u32 * errors)1751 int usb4_port_sw_margin_errors(struct tb_port *port, enum usb4_sb_target target,
1752 u8 index, u32 *errors)
1753 {
1754 int ret;
1755
1756 ret = usb4_port_sb_op(port, target, index,
1757 USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1758 if (ret)
1759 return ret;
1760
1761 return usb4_port_sb_read(port, target, index, USB4_SB_METADATA, errors,
1762 sizeof(*errors));
1763 }
1764
usb4_port_retimer_op(struct tb_port * port,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1765 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1766 enum usb4_sb_opcode opcode,
1767 int timeout_msec)
1768 {
1769 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1770 timeout_msec);
1771 }
1772
1773 /**
1774 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1775 * @port: USB4 port
1776 * @index: Retimer index
1777 *
1778 * Enables sideband channel transations on SBTX. Can be used when USB4
1779 * link does not go up, for example if there is no device connected.
1780 */
usb4_port_retimer_set_inbound_sbtx(struct tb_port * port,u8 index)1781 int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1782 {
1783 int ret;
1784
1785 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1786 500);
1787
1788 if (ret != -ENODEV)
1789 return ret;
1790
1791 /*
1792 * Per the USB4 retimer spec, the retimer is not required to
1793 * send an RT (Retimer Transaction) response for the first
1794 * SET_INBOUND_SBTX command
1795 */
1796 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1797 500);
1798 }
1799
1800 /**
1801 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1802 * @port: USB4 port
1803 * @index: Retimer index
1804 *
1805 * Disables sideband channel transations on SBTX. The reverse of
1806 * usb4_port_retimer_set_inbound_sbtx().
1807 */
usb4_port_retimer_unset_inbound_sbtx(struct tb_port * port,u8 index)1808 int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1809 {
1810 return usb4_port_retimer_op(port, index,
1811 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1812 }
1813
1814 /**
1815 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1816 * @port: USB4 port
1817 * @index: Retimer index
1818 *
1819 * If the retimer at @index is last one (connected directly to the
1820 * Type-C port) this function returns %1. If it is not returns %0. If
1821 * the retimer is not present returns %-ENODEV. Otherwise returns
1822 * negative errno.
1823 */
usb4_port_retimer_is_last(struct tb_port * port,u8 index)1824 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1825 {
1826 u32 metadata;
1827 int ret;
1828
1829 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1830 500);
1831 if (ret)
1832 return ret;
1833
1834 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1835 USB4_SB_METADATA, &metadata, sizeof(metadata));
1836 return ret ? ret : metadata & 1;
1837 }
1838
1839 /**
1840 * usb4_port_retimer_is_cable() - Is the retimer cable retimer
1841 * @port: USB4 port
1842 * @index: Retimer index
1843 *
1844 * If the retimer at @index is last cable retimer this function returns
1845 * %1 and %0 if it is on-board retimer. In case a retimer is not present
1846 * at @index returns %-ENODEV. Otherwise returns negative errno.
1847 */
usb4_port_retimer_is_cable(struct tb_port * port,u8 index)1848 int usb4_port_retimer_is_cable(struct tb_port *port, u8 index)
1849 {
1850 u32 metadata;
1851 int ret;
1852
1853 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_CABLE_RETIMER,
1854 500);
1855 if (ret)
1856 return ret;
1857
1858 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1859 USB4_SB_METADATA, &metadata, sizeof(metadata));
1860 return ret ? ret : metadata & 1;
1861 }
1862
1863 /**
1864 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1865 * @port: USB4 port
1866 * @index: Retimer index
1867 *
1868 * Reads NVM sector size (in bytes) of a retimer at @index. This
1869 * operation can be used to determine whether the retimer supports NVM
1870 * upgrade for example. Returns sector size in bytes or negative errno
1871 * in case of error. Specifically returns %-ENODEV if there is no
1872 * retimer at @index.
1873 */
usb4_port_retimer_nvm_sector_size(struct tb_port * port,u8 index)1874 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1875 {
1876 u32 metadata;
1877 int ret;
1878
1879 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1880 500);
1881 if (ret)
1882 return ret;
1883
1884 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1885 USB4_SB_METADATA, &metadata, sizeof(metadata));
1886 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1887 }
1888
1889 /**
1890 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1891 * @port: USB4 port
1892 * @index: Retimer index
1893 * @address: Start offset
1894 *
1895 * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1896 * done automatically by usb4_port_retimer_nvm_write().
1897 *
1898 * Returns %0 in success and negative errno if there was a failure.
1899 */
usb4_port_retimer_nvm_set_offset(struct tb_port * port,u8 index,unsigned int address)1900 int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1901 unsigned int address)
1902 {
1903 u32 metadata, dwaddress;
1904 int ret;
1905
1906 dwaddress = address / 4;
1907 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1908 USB4_NVM_SET_OFFSET_MASK;
1909
1910 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1911 USB4_SB_METADATA, &metadata, sizeof(metadata));
1912 if (ret)
1913 return ret;
1914
1915 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1916 500);
1917 }
1918
1919 struct retimer_info {
1920 struct tb_port *port;
1921 u8 index;
1922 };
1923
usb4_port_retimer_nvm_write_next_block(void * data,unsigned int dwaddress,const void * buf,size_t dwords)1924 static int usb4_port_retimer_nvm_write_next_block(void *data,
1925 unsigned int dwaddress, const void *buf, size_t dwords)
1926
1927 {
1928 const struct retimer_info *info = data;
1929 struct tb_port *port = info->port;
1930 u8 index = info->index;
1931 int ret;
1932
1933 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1934 USB4_SB_DATA, buf, dwords * 4);
1935 if (ret)
1936 return ret;
1937
1938 return usb4_port_retimer_op(port, index,
1939 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1940 }
1941
1942 /**
1943 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1944 * @port: USB4 port
1945 * @index: Retimer index
1946 * @address: Byte address where to start the write
1947 * @buf: Data to write
1948 * @size: Size in bytes how much to write
1949 *
1950 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1951 * upgrade. Returns %0 if the data was written successfully and negative
1952 * errno in case of failure. Specifically returns %-ENODEV if there is
1953 * no retimer at @index.
1954 */
usb4_port_retimer_nvm_write(struct tb_port * port,u8 index,unsigned int address,const void * buf,size_t size)1955 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1956 const void *buf, size_t size)
1957 {
1958 struct retimer_info info = { .port = port, .index = index };
1959 int ret;
1960
1961 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1962 if (ret)
1963 return ret;
1964
1965 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1966 usb4_port_retimer_nvm_write_next_block, &info);
1967 }
1968
1969 /**
1970 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1971 * @port: USB4 port
1972 * @index: Retimer index
1973 *
1974 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1975 * this function can be used to trigger the NVM upgrade process. If
1976 * successful the retimer restarts with the new NVM and may not have the
1977 * index set so one needs to call usb4_port_enumerate_retimers() to
1978 * force index to be assigned.
1979 */
usb4_port_retimer_nvm_authenticate(struct tb_port * port,u8 index)1980 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1981 {
1982 u32 val;
1983
1984 /*
1985 * We need to use the raw operation here because once the
1986 * authentication completes the retimer index is not set anymore
1987 * so we do not get back the status now.
1988 */
1989 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1990 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1991 USB4_SB_OPCODE, &val, sizeof(val));
1992 }
1993
1994 /**
1995 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1996 * @port: USB4 port
1997 * @index: Retimer index
1998 * @status: Raw status code read from metadata
1999 *
2000 * This can be called after usb4_port_retimer_nvm_authenticate() and
2001 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
2002 *
2003 * Returns %0 if the authentication status was successfully read. The
2004 * completion metadata (the result) is then stored into @status. If
2005 * reading the status fails, returns negative errno.
2006 */
usb4_port_retimer_nvm_authenticate_status(struct tb_port * port,u8 index,u32 * status)2007 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
2008 u32 *status)
2009 {
2010 u32 metadata, val;
2011 int ret;
2012
2013 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2014 USB4_SB_OPCODE, &val, sizeof(val));
2015 if (ret)
2016 return ret;
2017
2018 ret = usb4_port_sb_opcode_err_to_errno(val);
2019 switch (ret) {
2020 case 0:
2021 *status = 0;
2022 return 0;
2023
2024 case -EAGAIN:
2025 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2026 USB4_SB_METADATA, &metadata,
2027 sizeof(metadata));
2028 if (ret)
2029 return ret;
2030
2031 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
2032 return 0;
2033
2034 default:
2035 return ret;
2036 }
2037 }
2038
usb4_port_retimer_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)2039 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
2040 void *buf, size_t dwords)
2041 {
2042 const struct retimer_info *info = data;
2043 struct tb_port *port = info->port;
2044 u8 index = info->index;
2045 u32 metadata;
2046 int ret;
2047
2048 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
2049 if (dwords < USB4_DATA_DWORDS)
2050 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
2051
2052 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
2053 USB4_SB_METADATA, &metadata, sizeof(metadata));
2054 if (ret)
2055 return ret;
2056
2057 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
2058 if (ret)
2059 return ret;
2060
2061 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2062 USB4_SB_DATA, buf, dwords * 4);
2063 }
2064
2065 /**
2066 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2067 * @port: USB4 port
2068 * @index: Retimer index
2069 * @address: NVM address (in bytes) to start reading
2070 * @buf: Data read from NVM is stored here
2071 * @size: Number of bytes to read
2072 *
2073 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
2074 * read was successful and negative errno in case of failure.
2075 * Specifically returns %-ENODEV if there is no retimer at @index.
2076 */
usb4_port_retimer_nvm_read(struct tb_port * port,u8 index,unsigned int address,void * buf,size_t size)2077 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2078 unsigned int address, void *buf, size_t size)
2079 {
2080 struct retimer_info info = { .port = port, .index = index };
2081
2082 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2083 usb4_port_retimer_nvm_read_block, &info);
2084 }
2085
2086 static inline unsigned int
usb4_usb3_port_max_bandwidth(const struct tb_port * port,unsigned int bw)2087 usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2088 {
2089 /* Take the possible bandwidth limitation into account */
2090 if (port->max_bw)
2091 return min(bw, port->max_bw);
2092 return bw;
2093 }
2094
2095 /**
2096 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
2097 * @port: USB3 adapter port
2098 *
2099 * Return maximum supported link rate of a USB3 adapter in Mb/s.
2100 * Negative errno in case of error.
2101 */
usb4_usb3_port_max_link_rate(struct tb_port * port)2102 int usb4_usb3_port_max_link_rate(struct tb_port *port)
2103 {
2104 int ret, lr;
2105 u32 val;
2106
2107 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2108 return -EINVAL;
2109
2110 ret = tb_port_read(port, &val, TB_CFG_PORT,
2111 port->cap_adap + ADP_USB3_CS_4, 1);
2112 if (ret)
2113 return ret;
2114
2115 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2116 ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2117
2118 return usb4_usb3_port_max_bandwidth(port, ret);
2119 }
2120
usb4_usb3_port_cm_request(struct tb_port * port,bool request)2121 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2122 {
2123 int ret;
2124 u32 val;
2125
2126 if (!tb_port_is_usb3_down(port))
2127 return -EINVAL;
2128 if (tb_route(port->sw))
2129 return -EINVAL;
2130
2131 ret = tb_port_read(port, &val, TB_CFG_PORT,
2132 port->cap_adap + ADP_USB3_CS_2, 1);
2133 if (ret)
2134 return ret;
2135
2136 if (request)
2137 val |= ADP_USB3_CS_2_CMR;
2138 else
2139 val &= ~ADP_USB3_CS_2_CMR;
2140
2141 ret = tb_port_write(port, &val, TB_CFG_PORT,
2142 port->cap_adap + ADP_USB3_CS_2, 1);
2143 if (ret)
2144 return ret;
2145
2146 /*
2147 * We can use val here directly as the CMR bit is in the same place
2148 * as HCA. Just mask out others.
2149 */
2150 val &= ADP_USB3_CS_2_CMR;
2151 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2152 ADP_USB3_CS_1_HCA, val, 1500,
2153 USB4_PORT_DELAY);
2154 }
2155
usb4_usb3_port_set_cm_request(struct tb_port * port)2156 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2157 {
2158 return usb4_usb3_port_cm_request(port, true);
2159 }
2160
usb4_usb3_port_clear_cm_request(struct tb_port * port)2161 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2162 {
2163 return usb4_usb3_port_cm_request(port, false);
2164 }
2165
usb3_bw_to_mbps(u32 bw,u8 scale)2166 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2167 {
2168 unsigned long uframes;
2169
2170 uframes = bw * 512UL << scale;
2171 return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2172 }
2173
mbps_to_usb3_bw(unsigned int mbps,u8 scale)2174 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2175 {
2176 unsigned long uframes;
2177
2178 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2179 uframes = ((unsigned long)mbps * MEGA) / 8000;
2180 return DIV_ROUND_UP(uframes, 512UL << scale);
2181 }
2182
usb4_usb3_port_read_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2183 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2184 int *upstream_bw,
2185 int *downstream_bw)
2186 {
2187 u32 val, bw, scale;
2188 int ret;
2189
2190 ret = tb_port_read(port, &val, TB_CFG_PORT,
2191 port->cap_adap + ADP_USB3_CS_2, 1);
2192 if (ret)
2193 return ret;
2194
2195 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2196 port->cap_adap + ADP_USB3_CS_3, 1);
2197 if (ret)
2198 return ret;
2199
2200 scale &= ADP_USB3_CS_3_SCALE_MASK;
2201
2202 bw = val & ADP_USB3_CS_2_AUBW_MASK;
2203 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2204
2205 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2206 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2207
2208 return 0;
2209 }
2210
2211 /**
2212 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2213 * @port: USB3 adapter port
2214 * @upstream_bw: Allocated upstream bandwidth is stored here
2215 * @downstream_bw: Allocated downstream bandwidth is stored here
2216 *
2217 * Stores currently allocated USB3 bandwidth into @upstream_bw and
2218 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
2219 * errno in failure.
2220 */
usb4_usb3_port_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2221 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2222 int *downstream_bw)
2223 {
2224 int ret;
2225
2226 ret = usb4_usb3_port_set_cm_request(port);
2227 if (ret)
2228 return ret;
2229
2230 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2231 downstream_bw);
2232 usb4_usb3_port_clear_cm_request(port);
2233
2234 return ret;
2235 }
2236
usb4_usb3_port_read_consumed_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2237 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2238 int *upstream_bw,
2239 int *downstream_bw)
2240 {
2241 u32 val, bw, scale;
2242 int ret;
2243
2244 ret = tb_port_read(port, &val, TB_CFG_PORT,
2245 port->cap_adap + ADP_USB3_CS_1, 1);
2246 if (ret)
2247 return ret;
2248
2249 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2250 port->cap_adap + ADP_USB3_CS_3, 1);
2251 if (ret)
2252 return ret;
2253
2254 scale &= ADP_USB3_CS_3_SCALE_MASK;
2255
2256 bw = val & ADP_USB3_CS_1_CUBW_MASK;
2257 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2258
2259 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2260 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2261
2262 return 0;
2263 }
2264
usb4_usb3_port_write_allocated_bandwidth(struct tb_port * port,int upstream_bw,int downstream_bw)2265 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2266 int upstream_bw,
2267 int downstream_bw)
2268 {
2269 u32 val, ubw, dbw, scale;
2270 int ret, max_bw;
2271
2272 /* Figure out suitable scale */
2273 scale = 0;
2274 max_bw = max(upstream_bw, downstream_bw);
2275 while (scale < 64) {
2276 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2277 break;
2278 scale++;
2279 }
2280
2281 if (WARN_ON(scale >= 64))
2282 return -EINVAL;
2283
2284 ret = tb_port_write(port, &scale, TB_CFG_PORT,
2285 port->cap_adap + ADP_USB3_CS_3, 1);
2286 if (ret)
2287 return ret;
2288
2289 ubw = mbps_to_usb3_bw(upstream_bw, scale);
2290 dbw = mbps_to_usb3_bw(downstream_bw, scale);
2291
2292 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2293
2294 ret = tb_port_read(port, &val, TB_CFG_PORT,
2295 port->cap_adap + ADP_USB3_CS_2, 1);
2296 if (ret)
2297 return ret;
2298
2299 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2300 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2301 val |= ubw;
2302
2303 return tb_port_write(port, &val, TB_CFG_PORT,
2304 port->cap_adap + ADP_USB3_CS_2, 1);
2305 }
2306
2307 /**
2308 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2309 * @port: USB3 adapter port
2310 * @upstream_bw: New upstream bandwidth
2311 * @downstream_bw: New downstream bandwidth
2312 *
2313 * This can be used to set how much bandwidth is allocated for the USB3
2314 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2315 * new values programmed to the USB3 adapter allocation registers. If
2316 * the values are lower than what is currently consumed the allocation
2317 * is set to what is currently consumed instead (consumed bandwidth
2318 * cannot be taken away by CM). The actual new values are returned in
2319 * @upstream_bw and @downstream_bw.
2320 *
2321 * Returns %0 in case of success and negative errno if there was a
2322 * failure.
2323 */
usb4_usb3_port_allocate_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2324 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2325 int *downstream_bw)
2326 {
2327 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2328
2329 ret = usb4_usb3_port_set_cm_request(port);
2330 if (ret)
2331 return ret;
2332
2333 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2334 &consumed_down);
2335 if (ret)
2336 goto err_request;
2337
2338 /* Don't allow it go lower than what is consumed */
2339 allocate_up = max(*upstream_bw, consumed_up);
2340 allocate_down = max(*downstream_bw, consumed_down);
2341
2342 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2343 allocate_down);
2344 if (ret)
2345 goto err_request;
2346
2347 *upstream_bw = allocate_up;
2348 *downstream_bw = allocate_down;
2349
2350 err_request:
2351 usb4_usb3_port_clear_cm_request(port);
2352 return ret;
2353 }
2354
2355 /**
2356 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2357 * @port: USB3 adapter port
2358 * @upstream_bw: New allocated upstream bandwidth
2359 * @downstream_bw: New allocated downstream bandwidth
2360 *
2361 * Releases USB3 allocated bandwidth down to what is actually consumed.
2362 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2363 *
2364 * Returns 0% in success and negative errno in case of failure.
2365 */
usb4_usb3_port_release_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2366 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2367 int *downstream_bw)
2368 {
2369 int ret, consumed_up, consumed_down;
2370
2371 ret = usb4_usb3_port_set_cm_request(port);
2372 if (ret)
2373 return ret;
2374
2375 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2376 &consumed_down);
2377 if (ret)
2378 goto err_request;
2379
2380 /*
2381 * Always keep 900 Mb/s to make sure xHCI has at least some
2382 * bandwidth available for isochronous traffic.
2383 */
2384 if (consumed_up < 900)
2385 consumed_up = 900;
2386 if (consumed_down < 900)
2387 consumed_down = 900;
2388
2389 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2390 consumed_down);
2391 if (ret)
2392 goto err_request;
2393
2394 *upstream_bw = consumed_up;
2395 *downstream_bw = consumed_down;
2396
2397 err_request:
2398 usb4_usb3_port_clear_cm_request(port);
2399 return ret;
2400 }
2401
is_usb4_dpin(const struct tb_port * port)2402 static bool is_usb4_dpin(const struct tb_port *port)
2403 {
2404 if (!tb_port_is_dpin(port))
2405 return false;
2406 if (!tb_switch_is_usb4(port->sw))
2407 return false;
2408 return true;
2409 }
2410
2411 /**
2412 * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2413 * @port: DP IN adapter
2414 * @cm_id: CM ID to assign
2415 *
2416 * Sets CM ID for the @port. Returns %0 on success and negative errno
2417 * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2418 * support this.
2419 */
usb4_dp_port_set_cm_id(struct tb_port * port,int cm_id)2420 int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2421 {
2422 u32 val;
2423 int ret;
2424
2425 if (!is_usb4_dpin(port))
2426 return -EOPNOTSUPP;
2427
2428 ret = tb_port_read(port, &val, TB_CFG_PORT,
2429 port->cap_adap + ADP_DP_CS_2, 1);
2430 if (ret)
2431 return ret;
2432
2433 val &= ~ADP_DP_CS_2_CM_ID_MASK;
2434 val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2435
2436 return tb_port_write(port, &val, TB_CFG_PORT,
2437 port->cap_adap + ADP_DP_CS_2, 1);
2438 }
2439
2440 /**
2441 * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2442 * supported
2443 * @port: DP IN adapter to check
2444 *
2445 * Can be called to any DP IN adapter. Returns true if the adapter
2446 * supports USB4 bandwidth allocation mode, false otherwise.
2447 */
usb4_dp_port_bandwidth_mode_supported(struct tb_port * port)2448 bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2449 {
2450 int ret;
2451 u32 val;
2452
2453 if (!is_usb4_dpin(port))
2454 return false;
2455
2456 ret = tb_port_read(port, &val, TB_CFG_PORT,
2457 port->cap_adap + DP_LOCAL_CAP, 1);
2458 if (ret)
2459 return false;
2460
2461 return !!(val & DP_COMMON_CAP_BW_MODE);
2462 }
2463
2464 /**
2465 * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2466 * enabled
2467 * @port: DP IN adapter to check
2468 *
2469 * Can be called to any DP IN adapter. Returns true if the bandwidth
2470 * allocation mode has been enabled, false otherwise.
2471 */
usb4_dp_port_bandwidth_mode_enabled(struct tb_port * port)2472 bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2473 {
2474 int ret;
2475 u32 val;
2476
2477 if (!is_usb4_dpin(port))
2478 return false;
2479
2480 ret = tb_port_read(port, &val, TB_CFG_PORT,
2481 port->cap_adap + ADP_DP_CS_8, 1);
2482 if (ret)
2483 return false;
2484
2485 return !!(val & ADP_DP_CS_8_DPME);
2486 }
2487
2488 /**
2489 * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2490 * bandwidth allocation mode
2491 * @port: DP IN adapter
2492 * @supported: Does the CM support bandwidth allocation mode
2493 *
2494 * Can be called to any DP IN adapter. Sets or clears the CM support bit
2495 * of the DP IN adapter. Returns %0 in success and negative errno
2496 * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2497 * does not support this.
2498 */
usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port * port,bool supported)2499 int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2500 bool supported)
2501 {
2502 u32 val;
2503 int ret;
2504
2505 if (!is_usb4_dpin(port))
2506 return -EOPNOTSUPP;
2507
2508 ret = tb_port_read(port, &val, TB_CFG_PORT,
2509 port->cap_adap + ADP_DP_CS_2, 1);
2510 if (ret)
2511 return ret;
2512
2513 if (supported)
2514 val |= ADP_DP_CS_2_CMMS;
2515 else
2516 val &= ~ADP_DP_CS_2_CMMS;
2517
2518 return tb_port_write(port, &val, TB_CFG_PORT,
2519 port->cap_adap + ADP_DP_CS_2, 1);
2520 }
2521
2522 /**
2523 * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2524 * @port: DP IN adapter
2525 *
2526 * Reads bandwidth allocation Group ID from the DP IN adapter and
2527 * returns it. If the adapter does not support setting Group_ID
2528 * %-EOPNOTSUPP is returned.
2529 */
usb4_dp_port_group_id(struct tb_port * port)2530 int usb4_dp_port_group_id(struct tb_port *port)
2531 {
2532 u32 val;
2533 int ret;
2534
2535 if (!is_usb4_dpin(port))
2536 return -EOPNOTSUPP;
2537
2538 ret = tb_port_read(port, &val, TB_CFG_PORT,
2539 port->cap_adap + ADP_DP_CS_2, 1);
2540 if (ret)
2541 return ret;
2542
2543 return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2544 }
2545
2546 /**
2547 * usb4_dp_port_set_group_id() - Set adapter Group ID
2548 * @port: DP IN adapter
2549 * @group_id: Group ID for the adapter
2550 *
2551 * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2552 * Returns %0 in case of success and negative errno otherwise.
2553 * Specifically returns %-EOPNOTSUPP if the adapter does not support
2554 * this.
2555 */
usb4_dp_port_set_group_id(struct tb_port * port,int group_id)2556 int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2557 {
2558 u32 val;
2559 int ret;
2560
2561 if (!is_usb4_dpin(port))
2562 return -EOPNOTSUPP;
2563
2564 ret = tb_port_read(port, &val, TB_CFG_PORT,
2565 port->cap_adap + ADP_DP_CS_2, 1);
2566 if (ret)
2567 return ret;
2568
2569 val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2570 val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2571
2572 return tb_port_write(port, &val, TB_CFG_PORT,
2573 port->cap_adap + ADP_DP_CS_2, 1);
2574 }
2575
2576 /**
2577 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2578 * @port: DP IN adapter
2579 * @rate: Non-reduced rate in Mb/s is placed here
2580 * @lanes: Non-reduced lanes are placed here
2581 *
2582 * Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2583 * %0 in success and negative errno otherwise. Specifically returns
2584 * %-EOPNOTSUPP if the adapter does not support this.
2585 */
usb4_dp_port_nrd(struct tb_port * port,int * rate,int * lanes)2586 int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2587 {
2588 u32 val, tmp;
2589 int ret;
2590
2591 if (!is_usb4_dpin(port))
2592 return -EOPNOTSUPP;
2593
2594 ret = tb_port_read(port, &val, TB_CFG_PORT,
2595 port->cap_adap + ADP_DP_CS_2, 1);
2596 if (ret)
2597 return ret;
2598
2599 tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2600 switch (tmp) {
2601 case DP_COMMON_CAP_RATE_RBR:
2602 *rate = 1620;
2603 break;
2604 case DP_COMMON_CAP_RATE_HBR:
2605 *rate = 2700;
2606 break;
2607 case DP_COMMON_CAP_RATE_HBR2:
2608 *rate = 5400;
2609 break;
2610 case DP_COMMON_CAP_RATE_HBR3:
2611 *rate = 8100;
2612 break;
2613 }
2614
2615 tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2616 switch (tmp) {
2617 case DP_COMMON_CAP_1_LANE:
2618 *lanes = 1;
2619 break;
2620 case DP_COMMON_CAP_2_LANES:
2621 *lanes = 2;
2622 break;
2623 case DP_COMMON_CAP_4_LANES:
2624 *lanes = 4;
2625 break;
2626 }
2627
2628 return 0;
2629 }
2630
2631 /**
2632 * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2633 * @port: DP IN adapter
2634 * @rate: Non-reduced rate in Mb/s
2635 * @lanes: Non-reduced lanes
2636 *
2637 * Before the capabilities reduction this function can be used to set
2638 * the non-reduced values for the DP IN adapter. Returns %0 in success
2639 * and negative errno otherwise. If the adapter does not support this
2640 * %-EOPNOTSUPP is returned.
2641 */
usb4_dp_port_set_nrd(struct tb_port * port,int rate,int lanes)2642 int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2643 {
2644 u32 val;
2645 int ret;
2646
2647 if (!is_usb4_dpin(port))
2648 return -EOPNOTSUPP;
2649
2650 ret = tb_port_read(port, &val, TB_CFG_PORT,
2651 port->cap_adap + ADP_DP_CS_2, 1);
2652 if (ret)
2653 return ret;
2654
2655 val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2656
2657 switch (rate) {
2658 case 1620:
2659 break;
2660 case 2700:
2661 val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2662 & ADP_DP_CS_2_NRD_MLR_MASK;
2663 break;
2664 case 5400:
2665 val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2666 & ADP_DP_CS_2_NRD_MLR_MASK;
2667 break;
2668 case 8100:
2669 val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2670 & ADP_DP_CS_2_NRD_MLR_MASK;
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675
2676 val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2677
2678 switch (lanes) {
2679 case 1:
2680 break;
2681 case 2:
2682 val |= DP_COMMON_CAP_2_LANES;
2683 break;
2684 case 4:
2685 val |= DP_COMMON_CAP_4_LANES;
2686 break;
2687 default:
2688 return -EINVAL;
2689 }
2690
2691 return tb_port_write(port, &val, TB_CFG_PORT,
2692 port->cap_adap + ADP_DP_CS_2, 1);
2693 }
2694
2695 /**
2696 * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2697 * @port: DP IN adapter
2698 *
2699 * Reads the programmed granularity from @port. If the DP IN adapter does
2700 * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2701 * errno in other error cases.
2702 */
usb4_dp_port_granularity(struct tb_port * port)2703 int usb4_dp_port_granularity(struct tb_port *port)
2704 {
2705 u32 val;
2706 int ret;
2707
2708 if (!is_usb4_dpin(port))
2709 return -EOPNOTSUPP;
2710
2711 ret = tb_port_read(port, &val, TB_CFG_PORT,
2712 port->cap_adap + ADP_DP_CS_2, 1);
2713 if (ret)
2714 return ret;
2715
2716 val &= ADP_DP_CS_2_GR_MASK;
2717 val >>= ADP_DP_CS_2_GR_SHIFT;
2718
2719 switch (val) {
2720 case ADP_DP_CS_2_GR_0_25G:
2721 return 250;
2722 case ADP_DP_CS_2_GR_0_5G:
2723 return 500;
2724 case ADP_DP_CS_2_GR_1G:
2725 return 1000;
2726 }
2727
2728 return -EINVAL;
2729 }
2730
2731 /**
2732 * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2733 * @port: DP IN adapter
2734 * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2735 *
2736 * Sets the granularity used with the estimated, allocated and requested
2737 * bandwidth. Returns %0 in success and negative errno otherwise. If the
2738 * adapter does not support this %-EOPNOTSUPP is returned.
2739 */
usb4_dp_port_set_granularity(struct tb_port * port,int granularity)2740 int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2741 {
2742 u32 val;
2743 int ret;
2744
2745 if (!is_usb4_dpin(port))
2746 return -EOPNOTSUPP;
2747
2748 ret = tb_port_read(port, &val, TB_CFG_PORT,
2749 port->cap_adap + ADP_DP_CS_2, 1);
2750 if (ret)
2751 return ret;
2752
2753 val &= ~ADP_DP_CS_2_GR_MASK;
2754
2755 switch (granularity) {
2756 case 250:
2757 val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2758 break;
2759 case 500:
2760 val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2761 break;
2762 case 1000:
2763 val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2764 break;
2765 default:
2766 return -EINVAL;
2767 }
2768
2769 return tb_port_write(port, &val, TB_CFG_PORT,
2770 port->cap_adap + ADP_DP_CS_2, 1);
2771 }
2772
2773 /**
2774 * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2775 * @port: DP IN adapter
2776 * @bw: Estimated bandwidth in Mb/s.
2777 *
2778 * Sets the estimated bandwidth to @bw. Set the granularity by calling
2779 * usb4_dp_port_set_granularity() before calling this. The @bw is round
2780 * down to the closest granularity multiplier. Returns %0 in success
2781 * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2782 * the adapter does not support this.
2783 */
usb4_dp_port_set_estimated_bandwidth(struct tb_port * port,int bw)2784 int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2785 {
2786 u32 val, granularity;
2787 int ret;
2788
2789 if (!is_usb4_dpin(port))
2790 return -EOPNOTSUPP;
2791
2792 ret = usb4_dp_port_granularity(port);
2793 if (ret < 0)
2794 return ret;
2795 granularity = ret;
2796
2797 ret = tb_port_read(port, &val, TB_CFG_PORT,
2798 port->cap_adap + ADP_DP_CS_2, 1);
2799 if (ret)
2800 return ret;
2801
2802 val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2803 val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2804
2805 return tb_port_write(port, &val, TB_CFG_PORT,
2806 port->cap_adap + ADP_DP_CS_2, 1);
2807 }
2808
2809 /**
2810 * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2811 * @port: DP IN adapter
2812 *
2813 * Reads and returns allocated bandwidth for @port in Mb/s (taking into
2814 * account the programmed granularity). Returns negative errno in case
2815 * of error.
2816 */
usb4_dp_port_allocated_bandwidth(struct tb_port * port)2817 int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2818 {
2819 u32 val, granularity;
2820 int ret;
2821
2822 if (!is_usb4_dpin(port))
2823 return -EOPNOTSUPP;
2824
2825 ret = usb4_dp_port_granularity(port);
2826 if (ret < 0)
2827 return ret;
2828 granularity = ret;
2829
2830 ret = tb_port_read(port, &val, TB_CFG_PORT,
2831 port->cap_adap + DP_STATUS, 1);
2832 if (ret)
2833 return ret;
2834
2835 val &= DP_STATUS_ALLOCATED_BW_MASK;
2836 val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2837
2838 return val * granularity;
2839 }
2840
__usb4_dp_port_set_cm_ack(struct tb_port * port,bool ack)2841 static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2842 {
2843 u32 val;
2844 int ret;
2845
2846 ret = tb_port_read(port, &val, TB_CFG_PORT,
2847 port->cap_adap + ADP_DP_CS_2, 1);
2848 if (ret)
2849 return ret;
2850
2851 if (ack)
2852 val |= ADP_DP_CS_2_CA;
2853 else
2854 val &= ~ADP_DP_CS_2_CA;
2855
2856 return tb_port_write(port, &val, TB_CFG_PORT,
2857 port->cap_adap + ADP_DP_CS_2, 1);
2858 }
2859
usb4_dp_port_set_cm_ack(struct tb_port * port)2860 static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2861 {
2862 return __usb4_dp_port_set_cm_ack(port, true);
2863 }
2864
usb4_dp_port_wait_and_clear_cm_ack(struct tb_port * port,int timeout_msec)2865 static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2866 int timeout_msec)
2867 {
2868 ktime_t end;
2869 u32 val;
2870 int ret;
2871
2872 ret = __usb4_dp_port_set_cm_ack(port, false);
2873 if (ret)
2874 return ret;
2875
2876 end = ktime_add_ms(ktime_get(), timeout_msec);
2877 do {
2878 ret = tb_port_read(port, &val, TB_CFG_PORT,
2879 port->cap_adap + ADP_DP_CS_8, 1);
2880 if (ret)
2881 return ret;
2882
2883 if (!(val & ADP_DP_CS_8_DR))
2884 break;
2885
2886 usleep_range(50, 100);
2887 } while (ktime_before(ktime_get(), end));
2888
2889 if (val & ADP_DP_CS_8_DR) {
2890 tb_port_warn(port, "timeout waiting for DPTX request to clear\n");
2891 return -ETIMEDOUT;
2892 }
2893
2894 ret = tb_port_read(port, &val, TB_CFG_PORT,
2895 port->cap_adap + ADP_DP_CS_2, 1);
2896 if (ret)
2897 return ret;
2898
2899 val &= ~ADP_DP_CS_2_CA;
2900 return tb_port_write(port, &val, TB_CFG_PORT,
2901 port->cap_adap + ADP_DP_CS_2, 1);
2902 }
2903
2904 /**
2905 * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2906 * @port: DP IN adapter
2907 * @bw: New allocated bandwidth in Mb/s
2908 *
2909 * Communicates the new allocated bandwidth with the DPCD (graphics
2910 * driver). Takes into account the programmed granularity. Returns %0 in
2911 * success and negative errno in case of error.
2912 */
usb4_dp_port_allocate_bandwidth(struct tb_port * port,int bw)2913 int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2914 {
2915 u32 val, granularity;
2916 int ret;
2917
2918 if (!is_usb4_dpin(port))
2919 return -EOPNOTSUPP;
2920
2921 ret = usb4_dp_port_granularity(port);
2922 if (ret < 0)
2923 return ret;
2924 granularity = ret;
2925
2926 ret = tb_port_read(port, &val, TB_CFG_PORT,
2927 port->cap_adap + DP_STATUS, 1);
2928 if (ret)
2929 return ret;
2930
2931 val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2932 val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2933
2934 ret = tb_port_write(port, &val, TB_CFG_PORT,
2935 port->cap_adap + DP_STATUS, 1);
2936 if (ret)
2937 return ret;
2938
2939 ret = usb4_dp_port_set_cm_ack(port);
2940 if (ret)
2941 return ret;
2942
2943 return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
2944 }
2945
2946 /**
2947 * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2948 * @port: DP IN adapter
2949 *
2950 * Reads the DPCD (graphics driver) requested bandwidth and returns it
2951 * in Mb/s. Takes the programmed granularity into account. In case of
2952 * error returns negative errno. Specifically returns %-EOPNOTSUPP if
2953 * the adapter does not support bandwidth allocation mode, and %ENODATA
2954 * if there is no active bandwidth request from the graphics driver.
2955 */
usb4_dp_port_requested_bandwidth(struct tb_port * port)2956 int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2957 {
2958 u32 val, granularity;
2959 int ret;
2960
2961 if (!is_usb4_dpin(port))
2962 return -EOPNOTSUPP;
2963
2964 ret = usb4_dp_port_granularity(port);
2965 if (ret < 0)
2966 return ret;
2967 granularity = ret;
2968
2969 ret = tb_port_read(port, &val, TB_CFG_PORT,
2970 port->cap_adap + ADP_DP_CS_8, 1);
2971 if (ret)
2972 return ret;
2973
2974 if (!(val & ADP_DP_CS_8_DR))
2975 return -ENODATA;
2976
2977 return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2978 }
2979
2980 /**
2981 * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2982 * @port: PCIe adapter
2983 * @enable: Enable/disable extended encapsulation
2984 *
2985 * Enables or disables extended encapsulation used in PCIe tunneling. Caller
2986 * needs to make sure both adapters support this before enabling. Returns %0 on
2987 * success and negative errno otherwise.
2988 */
usb4_pci_port_set_ext_encapsulation(struct tb_port * port,bool enable)2989 int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2990 {
2991 u32 val;
2992 int ret;
2993
2994 if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2995 return -EINVAL;
2996
2997 ret = tb_port_read(port, &val, TB_CFG_PORT,
2998 port->cap_adap + ADP_PCIE_CS_1, 1);
2999 if (ret)
3000 return ret;
3001
3002 if (enable)
3003 val |= ADP_PCIE_CS_1_EE;
3004 else
3005 val &= ~ADP_PCIE_CS_1_EE;
3006
3007 return tb_port_write(port, &val, TB_CFG_PORT,
3008 port->cap_adap + ADP_PCIE_CS_1, 1);
3009 }
3010