1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
70
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
75
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
78
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
97
98 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
99 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
100 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
101
102 /*
103 * init function returns:
104 * > 0 - number of ports
105 * = 0 - use board->num_ports
106 * < 0 - error
107 */
108 struct pci_serial_quirk {
109 u32 vendor;
110 u32 device;
111 u32 subvendor;
112 u32 subdevice;
113 int (*probe)(struct pci_dev *dev);
114 int (*init)(struct pci_dev *dev);
115 int (*setup)(struct serial_private *,
116 const struct pciserial_board *,
117 struct uart_8250_port *, int);
118 void (*exit)(struct pci_dev *dev);
119 };
120
121 struct f815xxa_data {
122 spinlock_t lock;
123 int idx;
124 };
125
126 struct serial_private {
127 struct pci_dev *dev;
128 unsigned int nr;
129 struct pci_serial_quirk *quirk;
130 const struct pciserial_board *board;
131 int line[];
132 };
133
134 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
135
136 static const struct pci_device_id pci_use_msi[] = {
137 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
138 0xA000, 0x1000) },
139 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
140 0xA000, 0x1000) },
141 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
142 0xA000, 0x1000) },
143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
144 0xA000, 0x1000) },
145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
146 PCI_ANY_ID, PCI_ANY_ID) },
147 { }
148 };
149
150 static int pci_default_setup(struct serial_private*,
151 const struct pciserial_board*, struct uart_8250_port *, int);
152
moan_device(const char * str,struct pci_dev * dev)153 static void moan_device(const char *str, struct pci_dev *dev)
154 {
155 pci_err(dev, "%s\n"
156 "Please send the output of lspci -vv, this\n"
157 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
158 "manufacturer and name of serial board or\n"
159 "modem board to <linux-serial@vger.kernel.org>.\n",
160 str, dev->vendor, dev->device,
161 dev->subsystem_vendor, dev->subsystem_device);
162 }
163
164 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)165 setup_port(struct serial_private *priv, struct uart_8250_port *port,
166 u8 bar, unsigned int offset, int regshift)
167 {
168 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
169 }
170
171 /*
172 * ADDI-DATA GmbH communication cards <info@addi-data.com>
173 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)174 static int addidata_apci7800_setup(struct serial_private *priv,
175 const struct pciserial_board *board,
176 struct uart_8250_port *port, int idx)
177 {
178 unsigned int bar = 0, offset = board->first_offset;
179 bar = FL_GET_BASE(board->flags);
180
181 if (idx < 2) {
182 offset += idx * board->uart_offset;
183 } else if ((idx >= 2) && (idx < 4)) {
184 bar += 1;
185 offset += ((idx - 2) * board->uart_offset);
186 } else if ((idx >= 4) && (idx < 6)) {
187 bar += 2;
188 offset += ((idx - 4) * board->uart_offset);
189 } else if (idx >= 6) {
190 bar += 3;
191 offset += ((idx - 6) * board->uart_offset);
192 }
193
194 return setup_port(priv, port, bar, offset, board->reg_shift);
195 }
196
197 /*
198 * AFAVLAB uses a different mixture of BARs and offsets
199 * Not that ugly ;) -- HW
200 */
201 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)202 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
203 struct uart_8250_port *port, int idx)
204 {
205 unsigned int bar, offset = board->first_offset;
206
207 bar = FL_GET_BASE(board->flags);
208 if (idx < 4)
209 bar += idx;
210 else {
211 bar = 4;
212 offset += (idx - 4) * board->uart_offset;
213 }
214
215 return setup_port(priv, port, bar, offset, board->reg_shift);
216 }
217
218 /*
219 * HP's Remote Management Console. The Diva chip came in several
220 * different versions. N-class, L2000 and A500 have two Diva chips, each
221 * with 3 UARTs (the third UART on the second chip is unused). Superdome
222 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
223 * one Diva chip, but it has been expanded to 5 UARTs.
224 */
pci_hp_diva_init(struct pci_dev * dev)225 static int pci_hp_diva_init(struct pci_dev *dev)
226 {
227 int rc = 0;
228
229 switch (dev->subsystem_device) {
230 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
231 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
232 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
233 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
234 rc = 3;
235 break;
236 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
237 rc = 2;
238 break;
239 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
240 rc = 4;
241 break;
242 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
243 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
244 rc = 1;
245 break;
246 }
247
248 return rc;
249 }
250
251 /*
252 * HP's Diva chip puts the 4th/5th serial port further out, and
253 * some serial ports are supposed to be hidden on certain models.
254 */
255 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)256 pci_hp_diva_setup(struct serial_private *priv,
257 const struct pciserial_board *board,
258 struct uart_8250_port *port, int idx)
259 {
260 unsigned int offset = board->first_offset;
261 unsigned int bar = FL_GET_BASE(board->flags);
262
263 switch (priv->dev->subsystem_device) {
264 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
265 if (idx == 3)
266 idx++;
267 break;
268 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
269 if (idx > 0)
270 idx++;
271 if (idx > 2)
272 idx++;
273 break;
274 }
275 if (idx > 2)
276 offset = 0x18;
277
278 offset += idx * board->uart_offset;
279
280 return setup_port(priv, port, bar, offset, board->reg_shift);
281 }
282
283 /*
284 * Added for EKF Intel i960 serial boards
285 */
pci_inteli960ni_init(struct pci_dev * dev)286 static int pci_inteli960ni_init(struct pci_dev *dev)
287 {
288 u32 oldval;
289
290 if (!(dev->subsystem_device & 0x1000))
291 return -ENODEV;
292
293 /* is firmware started? */
294 pci_read_config_dword(dev, 0x44, &oldval);
295 if (oldval == 0x00001000L) { /* RESET value */
296 pci_dbg(dev, "Local i960 firmware missing\n");
297 return -ENODEV;
298 }
299 return 0;
300 }
301
302 /*
303 * Some PCI serial cards using the PLX 9050 PCI interface chip require
304 * that the card interrupt be explicitly enabled or disabled. This
305 * seems to be mainly needed on card using the PLX which also use I/O
306 * mapped memory.
307 */
pci_plx9050_init(struct pci_dev * dev)308 static int pci_plx9050_init(struct pci_dev *dev)
309 {
310 u8 irq_config;
311 void __iomem *p;
312
313 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
314 moan_device("no memory in bar 0", dev);
315 return 0;
316 }
317
318 irq_config = 0x41;
319 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
320 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
321 irq_config = 0x43;
322
323 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
324 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
325 /*
326 * As the megawolf cards have the int pins active
327 * high, and have 2 UART chips, both ints must be
328 * enabled on the 9050. Also, the UARTS are set in
329 * 16450 mode by default, so we have to enable the
330 * 16C950 'enhanced' mode so that we can use the
331 * deep FIFOs
332 */
333 irq_config = 0x5b;
334 /*
335 * enable/disable interrupts
336 */
337 p = ioremap(pci_resource_start(dev, 0), 0x80);
338 if (p == NULL)
339 return -ENOMEM;
340 writel(irq_config, p + 0x4c);
341
342 /*
343 * Read the register back to ensure that it took effect.
344 */
345 readl(p + 0x4c);
346 iounmap(p);
347
348 return 0;
349 }
350
pci_plx9050_exit(struct pci_dev * dev)351 static void pci_plx9050_exit(struct pci_dev *dev)
352 {
353 u8 __iomem *p;
354
355 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
356 return;
357
358 /*
359 * disable interrupts
360 */
361 p = ioremap(pci_resource_start(dev, 0), 0x80);
362 if (p != NULL) {
363 writel(0, p + 0x4c);
364
365 /*
366 * Read the register back to ensure that it took effect.
367 */
368 readl(p + 0x4c);
369 iounmap(p);
370 }
371 }
372
373 #define NI8420_INT_ENABLE_REG 0x38
374 #define NI8420_INT_ENABLE_BIT 0x2000
375
pci_ni8420_exit(struct pci_dev * dev)376 static void pci_ni8420_exit(struct pci_dev *dev)
377 {
378 void __iomem *p;
379 unsigned int bar = 0;
380
381 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
382 moan_device("no memory in bar", dev);
383 return;
384 }
385
386 p = pci_ioremap_bar(dev, bar);
387 if (p == NULL)
388 return;
389
390 /* Disable the CPU Interrupt */
391 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
392 p + NI8420_INT_ENABLE_REG);
393 iounmap(p);
394 }
395
396
397 /* MITE registers */
398 #define MITE_IOWBSR1 0xc4
399 #define MITE_IOWCR1 0xf4
400 #define MITE_LCIMR1 0x08
401 #define MITE_LCIMR2 0x10
402
403 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
404
pci_ni8430_exit(struct pci_dev * dev)405 static void pci_ni8430_exit(struct pci_dev *dev)
406 {
407 void __iomem *p;
408 unsigned int bar = 0;
409
410 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
411 moan_device("no memory in bar", dev);
412 return;
413 }
414
415 p = pci_ioremap_bar(dev, bar);
416 if (p == NULL)
417 return;
418
419 /* Disable the CPU Interrupt */
420 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
421 iounmap(p);
422 }
423
424 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
425 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)426 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
427 struct uart_8250_port *port, int idx)
428 {
429 unsigned int bar, offset = board->first_offset;
430
431 bar = 0;
432
433 if (idx < 4) {
434 /* first four channels map to 0, 0x100, 0x200, 0x300 */
435 offset += idx * board->uart_offset;
436 } else if (idx < 8) {
437 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
438 offset += idx * board->uart_offset + 0xC00;
439 } else /* we have only 8 ports on PMC-OCTALPRO */
440 return 1;
441
442 return setup_port(priv, port, bar, offset, board->reg_shift);
443 }
444
445 /*
446 * This does initialization for PMC OCTALPRO cards:
447 * maps the device memory, resets the UARTs (needed, bc
448 * if the module is removed and inserted again, the card
449 * is in the sleep mode) and enables global interrupt.
450 */
451
452 /* global control register offset for SBS PMC-OctalPro */
453 #define OCT_REG_CR_OFF 0x500
454
sbs_init(struct pci_dev * dev)455 static int sbs_init(struct pci_dev *dev)
456 {
457 u8 __iomem *p;
458
459 p = pci_ioremap_bar(dev, 0);
460
461 if (p == NULL)
462 return -ENOMEM;
463 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
464 writeb(0x10, p + OCT_REG_CR_OFF);
465 udelay(50);
466 writeb(0x0, p + OCT_REG_CR_OFF);
467
468 /* Set bit-2 (INTENABLE) of Control Register */
469 writeb(0x4, p + OCT_REG_CR_OFF);
470 iounmap(p);
471
472 return 0;
473 }
474
475 /*
476 * Disables the global interrupt of PMC-OctalPro
477 */
478
sbs_exit(struct pci_dev * dev)479 static void sbs_exit(struct pci_dev *dev)
480 {
481 u8 __iomem *p;
482
483 p = pci_ioremap_bar(dev, 0);
484 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
485 if (p != NULL)
486 writeb(0, p + OCT_REG_CR_OFF);
487 iounmap(p);
488 }
489
490 /*
491 * SIIG serial cards have an PCI interface chip which also controls
492 * the UART clocking frequency. Each UART can be clocked independently
493 * (except cards equipped with 4 UARTs) and initial clocking settings
494 * are stored in the EEPROM chip. It can cause problems because this
495 * version of serial driver doesn't support differently clocked UART's
496 * on single PCI card. To prevent this, initialization functions set
497 * high frequency clocking for all UART's on given card. It is safe (I
498 * hope) because it doesn't touch EEPROM settings to prevent conflicts
499 * with other OSes (like M$ DOS).
500 *
501 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
502 *
503 * There is two family of SIIG serial cards with different PCI
504 * interface chip and different configuration methods:
505 * - 10x cards have control registers in IO and/or memory space;
506 * - 20x cards have control registers in standard PCI configuration space.
507 *
508 * Note: all 10x cards have PCI device ids 0x10..
509 * all 20x cards have PCI device ids 0x20..
510 *
511 * There are also Quartet Serial cards which use Oxford Semiconductor
512 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
513 *
514 * Note: some SIIG cards are probed by the parport_serial object.
515 */
516
517 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
518 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
519
pci_siig10x_init(struct pci_dev * dev)520 static int pci_siig10x_init(struct pci_dev *dev)
521 {
522 u16 data;
523 void __iomem *p;
524
525 switch (dev->device & 0xfff8) {
526 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
527 data = 0xffdf;
528 break;
529 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
530 data = 0xf7ff;
531 break;
532 default: /* 1S1P, 4S */
533 data = 0xfffb;
534 break;
535 }
536
537 p = ioremap(pci_resource_start(dev, 0), 0x80);
538 if (p == NULL)
539 return -ENOMEM;
540
541 writew(readw(p + 0x28) & data, p + 0x28);
542 readw(p + 0x28);
543 iounmap(p);
544 return 0;
545 }
546
547 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
548 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
549
pci_siig20x_init(struct pci_dev * dev)550 static int pci_siig20x_init(struct pci_dev *dev)
551 {
552 u8 data;
553
554 /* Change clock frequency for the first UART. */
555 pci_read_config_byte(dev, 0x6f, &data);
556 pci_write_config_byte(dev, 0x6f, data & 0xef);
557
558 /* If this card has 2 UART, we have to do the same with second UART. */
559 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
560 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
561 pci_read_config_byte(dev, 0x73, &data);
562 pci_write_config_byte(dev, 0x73, data & 0xef);
563 }
564 return 0;
565 }
566
pci_siig_init(struct pci_dev * dev)567 static int pci_siig_init(struct pci_dev *dev)
568 {
569 unsigned int type = dev->device & 0xff00;
570
571 if (type == 0x1000)
572 return pci_siig10x_init(dev);
573 if (type == 0x2000)
574 return pci_siig20x_init(dev);
575
576 moan_device("Unknown SIIG card", dev);
577 return -ENODEV;
578 }
579
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)580 static int pci_siig_setup(struct serial_private *priv,
581 const struct pciserial_board *board,
582 struct uart_8250_port *port, int idx)
583 {
584 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
585
586 if (idx > 3) {
587 bar = 4;
588 offset = (idx - 4) * 8;
589 }
590
591 return setup_port(priv, port, bar, offset, 0);
592 }
593
594 /*
595 * Timedia has an explosion of boards, and to avoid the PCI table from
596 * growing *huge*, we use this function to collapse some 70 entries
597 * in the PCI table into one, for sanity's and compactness's sake.
598 */
599 static const unsigned short timedia_single_port[] = {
600 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
601 };
602
603 static const unsigned short timedia_dual_port[] = {
604 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
605 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
606 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
607 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
608 0xD079, 0
609 };
610
611 static const unsigned short timedia_quad_port[] = {
612 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
613 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
614 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
615 0xB157, 0
616 };
617
618 static const unsigned short timedia_eight_port[] = {
619 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
620 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
621 };
622
623 static const struct timedia_struct {
624 int num;
625 const unsigned short *ids;
626 } timedia_data[] = {
627 { 1, timedia_single_port },
628 { 2, timedia_dual_port },
629 { 4, timedia_quad_port },
630 { 8, timedia_eight_port }
631 };
632
633 /*
634 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
635 * listing them individually, this driver merely grabs them all with
636 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
637 * and should be left free to be claimed by parport_serial instead.
638 */
pci_timedia_probe(struct pci_dev * dev)639 static int pci_timedia_probe(struct pci_dev *dev)
640 {
641 /*
642 * Check the third digit of the subdevice ID
643 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
644 */
645 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
646 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
647 dev->subsystem_device);
648 return -ENODEV;
649 }
650
651 return 0;
652 }
653
pci_timedia_init(struct pci_dev * dev)654 static int pci_timedia_init(struct pci_dev *dev)
655 {
656 const unsigned short *ids;
657 int i, j;
658
659 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
660 ids = timedia_data[i].ids;
661 for (j = 0; ids[j]; j++)
662 if (dev->subsystem_device == ids[j])
663 return timedia_data[i].num;
664 }
665 return 0;
666 }
667
668 /*
669 * Timedia/SUNIX uses a mixture of BARs and offsets
670 * Ugh, this is ugly as all hell --- TYT
671 */
672 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)673 pci_timedia_setup(struct serial_private *priv,
674 const struct pciserial_board *board,
675 struct uart_8250_port *port, int idx)
676 {
677 unsigned int bar = 0, offset = board->first_offset;
678
679 switch (idx) {
680 case 0:
681 bar = 0;
682 break;
683 case 1:
684 offset = board->uart_offset;
685 bar = 0;
686 break;
687 case 2:
688 bar = 1;
689 break;
690 case 3:
691 offset = board->uart_offset;
692 fallthrough;
693 case 4: /* BAR 2 */
694 case 5: /* BAR 3 */
695 case 6: /* BAR 4 */
696 case 7: /* BAR 5 */
697 bar = idx - 2;
698 }
699
700 return setup_port(priv, port, bar, offset, board->reg_shift);
701 }
702
703 /*
704 * Some Titan cards are also a little weird
705 */
706 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)707 titan_400l_800l_setup(struct serial_private *priv,
708 const struct pciserial_board *board,
709 struct uart_8250_port *port, int idx)
710 {
711 unsigned int bar, offset = board->first_offset;
712
713 switch (idx) {
714 case 0:
715 bar = 1;
716 break;
717 case 1:
718 bar = 2;
719 break;
720 default:
721 bar = 4;
722 offset = (idx - 2) * board->uart_offset;
723 }
724
725 return setup_port(priv, port, bar, offset, board->reg_shift);
726 }
727
pci_xircom_init(struct pci_dev * dev)728 static int pci_xircom_init(struct pci_dev *dev)
729 {
730 msleep(100);
731 return 0;
732 }
733
pci_ni8420_init(struct pci_dev * dev)734 static int pci_ni8420_init(struct pci_dev *dev)
735 {
736 void __iomem *p;
737 unsigned int bar = 0;
738
739 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
740 moan_device("no memory in bar", dev);
741 return 0;
742 }
743
744 p = pci_ioremap_bar(dev, bar);
745 if (p == NULL)
746 return -ENOMEM;
747
748 /* Enable CPU Interrupt */
749 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
750 p + NI8420_INT_ENABLE_REG);
751
752 iounmap(p);
753 return 0;
754 }
755
756 #define MITE_IOWBSR1_WSIZE 0xa
757 #define MITE_IOWBSR1_WIN_OFFSET 0x800
758 #define MITE_IOWBSR1_WENAB (1 << 7)
759 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
760 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
761 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
762
pci_ni8430_init(struct pci_dev * dev)763 static int pci_ni8430_init(struct pci_dev *dev)
764 {
765 void __iomem *p;
766 struct pci_bus_region region;
767 u32 device_window;
768 unsigned int bar = 0;
769
770 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
771 moan_device("no memory in bar", dev);
772 return 0;
773 }
774
775 p = pci_ioremap_bar(dev, bar);
776 if (p == NULL)
777 return -ENOMEM;
778
779 /*
780 * Set device window address and size in BAR0, while acknowledging that
781 * the resource structure may contain a translated address that differs
782 * from the address the device responds to.
783 */
784 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
785 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
786 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
787 writel(device_window, p + MITE_IOWBSR1);
788
789 /* Set window access to go to RAMSEL IO address space */
790 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
791 p + MITE_IOWCR1);
792
793 /* Enable IO Bus Interrupt 0 */
794 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
795
796 /* Enable CPU Interrupt */
797 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
798
799 iounmap(p);
800 return 0;
801 }
802
803 /* UART Port Control Register */
804 #define NI8430_PORTCON 0x0f
805 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
806
807 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)808 pci_ni8430_setup(struct serial_private *priv,
809 const struct pciserial_board *board,
810 struct uart_8250_port *port, int idx)
811 {
812 struct pci_dev *dev = priv->dev;
813 void __iomem *p;
814 unsigned int bar, offset = board->first_offset;
815
816 if (idx >= board->num_ports)
817 return 1;
818
819 bar = FL_GET_BASE(board->flags);
820 offset += idx * board->uart_offset;
821
822 p = pci_ioremap_bar(dev, bar);
823 if (!p)
824 return -ENOMEM;
825
826 /* enable the transceiver */
827 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
828 p + offset + NI8430_PORTCON);
829
830 iounmap(p);
831
832 return setup_port(priv, port, bar, offset, board->reg_shift);
833 }
834
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)835 static int pci_netmos_9900_setup(struct serial_private *priv,
836 const struct pciserial_board *board,
837 struct uart_8250_port *port, int idx)
838 {
839 unsigned int bar;
840
841 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
842 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
843 /* netmos apparently orders BARs by datasheet layout, so serial
844 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
845 */
846 bar = 3 * idx;
847
848 return setup_port(priv, port, bar, 0, board->reg_shift);
849 }
850
851 return pci_default_setup(priv, board, port, idx);
852 }
853
854 /* the 99xx series comes with a range of device IDs and a variety
855 * of capabilities:
856 *
857 * 9900 has varying capabilities and can cascade to sub-controllers
858 * (cascading should be purely internal)
859 * 9904 is hardwired with 4 serial ports
860 * 9912 and 9922 are hardwired with 2 serial ports
861 */
pci_netmos_9900_numports(struct pci_dev * dev)862 static int pci_netmos_9900_numports(struct pci_dev *dev)
863 {
864 unsigned int c = dev->class;
865 unsigned int pi;
866 unsigned short sub_serports;
867
868 pi = c & 0xff;
869
870 if (pi == 2)
871 return 1;
872
873 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
874 /* two possibilities: 0x30ps encodes number of parallel and
875 * serial ports, or 0x1000 indicates *something*. This is not
876 * immediately obvious, since the 2s1p+4s configuration seems
877 * to offer all functionality on functions 0..2, while still
878 * advertising the same function 3 as the 4s+2s1p config.
879 */
880 sub_serports = dev->subsystem_device & 0xf;
881 if (sub_serports > 0)
882 return sub_serports;
883
884 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
885 return 0;
886 }
887
888 moan_device("unknown NetMos/Mostech program interface", dev);
889 return 0;
890 }
891
pci_netmos_init(struct pci_dev * dev)892 static int pci_netmos_init(struct pci_dev *dev)
893 {
894 /* subdevice 0x00PS means <P> parallel, <S> serial */
895 unsigned int num_serial = dev->subsystem_device & 0xf;
896
897 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
898 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
899 return 0;
900
901 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
902 dev->subsystem_device == 0x0299)
903 return 0;
904
905 switch (dev->device) { /* FALLTHROUGH on all */
906 case PCI_DEVICE_ID_NETMOS_9904:
907 case PCI_DEVICE_ID_NETMOS_9912:
908 case PCI_DEVICE_ID_NETMOS_9922:
909 case PCI_DEVICE_ID_NETMOS_9900:
910 num_serial = pci_netmos_9900_numports(dev);
911 break;
912
913 default:
914 break;
915 }
916
917 if (num_serial == 0) {
918 moan_device("unknown NetMos/Mostech device", dev);
919 return -ENODEV;
920 }
921
922 return num_serial;
923 }
924
925 /*
926 * These chips are available with optionally one parallel port and up to
927 * two serial ports. Unfortunately they all have the same product id.
928 *
929 * Basic configuration is done over a region of 32 I/O ports. The base
930 * ioport is called INTA or INTC, depending on docs/other drivers.
931 *
932 * The region of the 32 I/O ports is configured in POSIO0R...
933 */
934
935 /* registers */
936 #define ITE_887x_MISCR 0x9c
937 #define ITE_887x_INTCBAR 0x78
938 #define ITE_887x_UARTBAR 0x7c
939 #define ITE_887x_PS0BAR 0x10
940 #define ITE_887x_POSIO0 0x60
941
942 /* I/O space size */
943 #define ITE_887x_IOSIZE 32
944 /* I/O space size (bits 26-24; 8 bytes = 011b) */
945 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
946 /* I/O space size (bits 26-24; 32 bytes = 101b) */
947 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
948 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
949 #define ITE_887x_POSIO_SPEED (3 << 29)
950 /* enable IO_Space bit */
951 #define ITE_887x_POSIO_ENABLE (1 << 31)
952
953 /* inta_addr are the configuration addresses of the ITE */
954 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)955 static int pci_ite887x_init(struct pci_dev *dev)
956 {
957 int ret, i, type;
958 struct resource *iobase = NULL;
959 u32 miscr, uartbar, ioport;
960
961 /* search for the base-ioport */
962 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
963 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
964 "ite887x");
965 if (iobase != NULL) {
966 /* write POSIO0R - speed | size | ioport */
967 pci_write_config_dword(dev, ITE_887x_POSIO0,
968 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
969 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
970 /* write INTCBAR - ioport */
971 pci_write_config_dword(dev, ITE_887x_INTCBAR,
972 inta_addr[i]);
973 ret = inb(inta_addr[i]);
974 if (ret != 0xff) {
975 /* ioport connected */
976 break;
977 }
978 release_region(iobase->start, ITE_887x_IOSIZE);
979 }
980 }
981
982 if (i == ARRAY_SIZE(inta_addr)) {
983 pci_err(dev, "could not find iobase\n");
984 return -ENODEV;
985 }
986
987 /* start of undocumented type checking (see parport_pc.c) */
988 type = inb(iobase->start + 0x18) & 0x0f;
989
990 switch (type) {
991 case 0x2: /* ITE8871 (1P) */
992 case 0xa: /* ITE8875 (1P) */
993 ret = 0;
994 break;
995 case 0xe: /* ITE8872 (2S1P) */
996 ret = 2;
997 break;
998 case 0x6: /* ITE8873 (1S) */
999 ret = 1;
1000 break;
1001 case 0x8: /* ITE8874 (2S) */
1002 ret = 2;
1003 break;
1004 default:
1005 moan_device("Unknown ITE887x", dev);
1006 ret = -ENODEV;
1007 }
1008
1009 /* configure all serial ports */
1010 for (i = 0; i < ret; i++) {
1011 /* read the I/O port from the device */
1012 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1013 &ioport);
1014 ioport &= 0x0000FF00; /* the actual base address */
1015 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1016 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1017 ITE_887x_POSIO_IOSIZE_8 | ioport);
1018
1019 /* write the ioport to the UARTBAR */
1020 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1021 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1022 uartbar |= (ioport << (16 * i)); /* set the ioport */
1023 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1024
1025 /* get current config */
1026 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1027 /* disable interrupts (UARTx_Routing[3:0]) */
1028 miscr &= ~(0xf << (12 - 4 * i));
1029 /* activate the UART (UARTx_En) */
1030 miscr |= 1 << (23 - i);
1031 /* write new config with activated UART */
1032 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1033 }
1034
1035 if (ret <= 0) {
1036 /* the device has no UARTs if we get here */
1037 release_region(iobase->start, ITE_887x_IOSIZE);
1038 }
1039
1040 return ret;
1041 }
1042
pci_ite887x_exit(struct pci_dev * dev)1043 static void pci_ite887x_exit(struct pci_dev *dev)
1044 {
1045 u32 ioport;
1046 /* the ioport is bit 0-15 in POSIO0R */
1047 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1048 ioport &= 0xffff;
1049 release_region(ioport, ITE_887x_IOSIZE);
1050 }
1051
1052 /*
1053 * Oxford Semiconductor Inc.
1054 * Check if an OxSemi device is part of the Tornado range of devices.
1055 */
1056 #define PCI_VENDOR_ID_ENDRUN 0x7401
1057 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1058
pci_oxsemi_tornado_p(struct pci_dev * dev)1059 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1060 {
1061 /* OxSemi Tornado devices are all 0xCxxx */
1062 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1063 (dev->device & 0xf000) != 0xc000)
1064 return false;
1065
1066 /* EndRun devices are all 0xExxx */
1067 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1068 (dev->device & 0xf000) != 0xe000)
1069 return false;
1070
1071 return true;
1072 }
1073
1074 /*
1075 * Determine the number of ports available on a Tornado device.
1076 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1077 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1078 {
1079 u8 __iomem *p;
1080 unsigned long deviceID;
1081 unsigned int number_uarts = 0;
1082
1083 if (!pci_oxsemi_tornado_p(dev))
1084 return 0;
1085
1086 p = pci_iomap(dev, 0, 5);
1087 if (p == NULL)
1088 return -ENOMEM;
1089
1090 deviceID = ioread32(p);
1091 /* Tornado device */
1092 if (deviceID == 0x07000200) {
1093 number_uarts = ioread8(p + 4);
1094 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1095 number_uarts,
1096 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1097 "EndRun" : "Oxford");
1098 }
1099 pci_iounmap(dev, p);
1100 return number_uarts;
1101 }
1102
1103 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1104 #define OXSEMI_TORNADO_TCR_MASK 0xf
1105 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1106 #define OXSEMI_TORNADO_CPR_MIN 0x008
1107 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1108
1109 /*
1110 * Determine the oversampling rate, the clock prescaler, and the clock
1111 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1112 * which is four times the baud base, and the prescaler increments in
1113 * steps of 1/8. Therefore to make calculations on integers we need
1114 * to use a scaled clock rate, which is the baud base multiplied by 32
1115 * (or our assumed UART clock rate multiplied by 2).
1116 *
1117 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1118 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1119 * values between 1.000 and 63.875 inclusive (operation for values from
1120 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1121 * unsigned 16-bit integer.
1122 *
1123 * For the most accurate baud rate we use a table of predetermined
1124 * oversampling rates and clock prescalers that records all possible
1125 * products of the two parameters in the range from 4 up to 255 inclusive,
1126 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1127 * by 8. The table is sorted by the decreasing value of the oversampling
1128 * rate and ties are resolved by sorting by the decreasing value of the
1129 * product. This way preference is given to higher oversampling rates.
1130 *
1131 * We iterate over the table and choose the product of an oversampling
1132 * rate and a clock prescaler that gives the lowest integer division
1133 * result deviation, or if an exact integer divider is found we stop
1134 * looking for it right away. We do some fixup if the resulting clock
1135 * divisor required would be out of its unsigned 16-bit integer range.
1136 *
1137 * Finally we abuse the supposed fractional part returned to encode the
1138 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1139 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1140 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1141 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1142 unsigned int baud,
1143 unsigned int *frac)
1144 {
1145 static u8 p[][2] = {
1146 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1147 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1148 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1149 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1150 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1151 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1152 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1153 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1154 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1155 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1156 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1157 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1158 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1159 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1160 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1161 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1162 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1163 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1164 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1165 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1166 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1167 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1168 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1169 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1170 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1171 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1172 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1173 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1174 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1175 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1176 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1177 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1178 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1179 { 4, 9, }, { 4, 8, },
1180 };
1181 /* Scale the quotient for comparison to get the fractional part. */
1182 const unsigned int quot_scale = 65536;
1183 unsigned int sclk = port->uartclk * 2;
1184 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1185 unsigned int best_squot;
1186 unsigned int squot;
1187 unsigned int quot;
1188 u16 cpr;
1189 u8 tcr;
1190 int i;
1191
1192 /* Old custom speed handling. */
1193 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1194 unsigned int cust_div = port->custom_divisor;
1195
1196 quot = cust_div & UART_DIV_MAX;
1197 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1198 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1199 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1200 cpr = OXSEMI_TORNADO_CPR_DEF;
1201 } else {
1202 best_squot = quot_scale;
1203 for (i = 0; i < ARRAY_SIZE(p); i++) {
1204 unsigned int spre;
1205 unsigned int srem;
1206 u8 cp;
1207 u8 tc;
1208
1209 tc = p[i][0];
1210 cp = p[i][1];
1211 spre = tc * cp;
1212
1213 srem = sdiv % spre;
1214 if (srem > spre / 2)
1215 srem = spre - srem;
1216 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1217
1218 if (srem == 0) {
1219 tcr = tc;
1220 cpr = cp;
1221 quot = sdiv / spre;
1222 break;
1223 } else if (squot < best_squot) {
1224 best_squot = squot;
1225 tcr = tc;
1226 cpr = cp;
1227 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1228 }
1229 }
1230 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1231 quot % 2 == 0) {
1232 quot >>= 1;
1233 tcr <<= 1;
1234 }
1235 while (quot > UART_DIV_MAX) {
1236 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1237 quot >>= 1;
1238 tcr <<= 1;
1239 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1240 quot >>= 1;
1241 cpr <<= 1;
1242 } else {
1243 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1244 cpr = OXSEMI_TORNADO_CPR_MASK;
1245 }
1246 }
1247 }
1248
1249 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1250 return quot;
1251 }
1252
1253 /*
1254 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1255 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1256 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1257 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1258 * has to be written first, followed by CPR2, which occupies the location
1259 * of CKS used with earlier UART designs.
1260 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1261 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1262 unsigned int baud,
1263 unsigned int quot,
1264 unsigned int quot_frac)
1265 {
1266 struct uart_8250_port *up = up_to_u8250p(port);
1267 u8 cpr2 = quot_frac >> 16;
1268 u8 cpr = quot_frac >> 8;
1269 u8 tcr = quot_frac;
1270
1271 serial_icr_write(up, UART_TCR, tcr);
1272 serial_icr_write(up, UART_CPR, cpr);
1273 serial_icr_write(up, UART_CKS, cpr2);
1274 serial8250_do_set_divisor(port, baud, quot);
1275 }
1276
1277 /*
1278 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1279 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1280 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1281 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1282 unsigned int mctrl)
1283 {
1284 struct uart_8250_port *up = up_to_u8250p(port);
1285
1286 up->mcr |= UART_MCR_CLKSEL;
1287 serial8250_do_set_mctrl(port, mctrl);
1288 }
1289
1290 /*
1291 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1292 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1293 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1294 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1295 const struct pciserial_board *board,
1296 struct uart_8250_port *up, int idx)
1297 {
1298 struct pci_dev *dev = priv->dev;
1299
1300 if (pci_oxsemi_tornado_p(dev)) {
1301 up->port.flags |= UPF_FULL_PROBE;
1302 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1303 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1304 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1305 }
1306
1307 return pci_default_setup(priv, board, up, idx);
1308 }
1309
1310 #define QPCR_TEST_FOR1 0x3F
1311 #define QPCR_TEST_GET1 0x00
1312 #define QPCR_TEST_FOR2 0x40
1313 #define QPCR_TEST_GET2 0x40
1314 #define QPCR_TEST_FOR3 0x80
1315 #define QPCR_TEST_GET3 0x40
1316 #define QPCR_TEST_FOR4 0xC0
1317 #define QPCR_TEST_GET4 0x80
1318
1319 #define QOPR_CLOCK_X1 0x0000
1320 #define QOPR_CLOCK_X2 0x0001
1321 #define QOPR_CLOCK_X4 0x0002
1322 #define QOPR_CLOCK_X8 0x0003
1323 #define QOPR_CLOCK_RATE_MASK 0x0003
1324
1325 /* Quatech devices have their own extra interface features */
1326 static struct pci_device_id quatech_cards[] = {
1327 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1328 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1329 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1330 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1331 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1332 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1333 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1334 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1335 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1336 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1337 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1338 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1339 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1340 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1341 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1342 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1343 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1344 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1345 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1346 { 0, }
1347 };
1348
pci_quatech_rqopr(struct uart_8250_port * port)1349 static int pci_quatech_rqopr(struct uart_8250_port *port)
1350 {
1351 unsigned long base = port->port.iobase;
1352 u8 LCR, val;
1353
1354 LCR = inb(base + UART_LCR);
1355 outb(0xBF, base + UART_LCR);
1356 val = inb(base + UART_SCR);
1357 outb(LCR, base + UART_LCR);
1358 return val;
1359 }
1360
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1361 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1362 {
1363 unsigned long base = port->port.iobase;
1364 u8 LCR;
1365
1366 LCR = inb(base + UART_LCR);
1367 outb(0xBF, base + UART_LCR);
1368 inb(base + UART_SCR);
1369 outb(qopr, base + UART_SCR);
1370 outb(LCR, base + UART_LCR);
1371 }
1372
pci_quatech_rqmcr(struct uart_8250_port * port)1373 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1374 {
1375 unsigned long base = port->port.iobase;
1376 u8 LCR, val, qmcr;
1377
1378 LCR = inb(base + UART_LCR);
1379 outb(0xBF, base + UART_LCR);
1380 val = inb(base + UART_SCR);
1381 outb(val | 0x10, base + UART_SCR);
1382 qmcr = inb(base + UART_MCR);
1383 outb(val, base + UART_SCR);
1384 outb(LCR, base + UART_LCR);
1385
1386 return qmcr;
1387 }
1388
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1389 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1390 {
1391 unsigned long base = port->port.iobase;
1392 u8 LCR, val;
1393
1394 LCR = inb(base + UART_LCR);
1395 outb(0xBF, base + UART_LCR);
1396 val = inb(base + UART_SCR);
1397 outb(val | 0x10, base + UART_SCR);
1398 outb(qmcr, base + UART_MCR);
1399 outb(val, base + UART_SCR);
1400 outb(LCR, base + UART_LCR);
1401 }
1402
pci_quatech_has_qmcr(struct uart_8250_port * port)1403 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1404 {
1405 unsigned long base = port->port.iobase;
1406 u8 LCR, val;
1407
1408 LCR = inb(base + UART_LCR);
1409 outb(0xBF, base + UART_LCR);
1410 val = inb(base + UART_SCR);
1411 if (val & 0x20) {
1412 outb(0x80, UART_LCR);
1413 if (!(inb(UART_SCR) & 0x20)) {
1414 outb(LCR, base + UART_LCR);
1415 return 1;
1416 }
1417 }
1418 return 0;
1419 }
1420
pci_quatech_test(struct uart_8250_port * port)1421 static int pci_quatech_test(struct uart_8250_port *port)
1422 {
1423 u8 reg, qopr;
1424
1425 qopr = pci_quatech_rqopr(port);
1426 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1427 reg = pci_quatech_rqopr(port) & 0xC0;
1428 if (reg != QPCR_TEST_GET1)
1429 return -EINVAL;
1430 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1431 reg = pci_quatech_rqopr(port) & 0xC0;
1432 if (reg != QPCR_TEST_GET2)
1433 return -EINVAL;
1434 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1435 reg = pci_quatech_rqopr(port) & 0xC0;
1436 if (reg != QPCR_TEST_GET3)
1437 return -EINVAL;
1438 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1439 reg = pci_quatech_rqopr(port) & 0xC0;
1440 if (reg != QPCR_TEST_GET4)
1441 return -EINVAL;
1442
1443 pci_quatech_wqopr(port, qopr);
1444 return 0;
1445 }
1446
pci_quatech_clock(struct uart_8250_port * port)1447 static int pci_quatech_clock(struct uart_8250_port *port)
1448 {
1449 u8 qopr, reg, set;
1450 unsigned long clock;
1451
1452 if (pci_quatech_test(port) < 0)
1453 return 1843200;
1454
1455 qopr = pci_quatech_rqopr(port);
1456
1457 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1458 reg = pci_quatech_rqopr(port);
1459 if (reg & QOPR_CLOCK_X8) {
1460 clock = 1843200;
1461 goto out;
1462 }
1463 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1464 reg = pci_quatech_rqopr(port);
1465 if (!(reg & QOPR_CLOCK_X8)) {
1466 clock = 1843200;
1467 goto out;
1468 }
1469 reg &= QOPR_CLOCK_X8;
1470 if (reg == QOPR_CLOCK_X2) {
1471 clock = 3685400;
1472 set = QOPR_CLOCK_X2;
1473 } else if (reg == QOPR_CLOCK_X4) {
1474 clock = 7372800;
1475 set = QOPR_CLOCK_X4;
1476 } else if (reg == QOPR_CLOCK_X8) {
1477 clock = 14745600;
1478 set = QOPR_CLOCK_X8;
1479 } else {
1480 clock = 1843200;
1481 set = QOPR_CLOCK_X1;
1482 }
1483 qopr &= ~QOPR_CLOCK_RATE_MASK;
1484 qopr |= set;
1485
1486 out:
1487 pci_quatech_wqopr(port, qopr);
1488 return clock;
1489 }
1490
pci_quatech_rs422(struct uart_8250_port * port)1491 static int pci_quatech_rs422(struct uart_8250_port *port)
1492 {
1493 u8 qmcr;
1494 int rs422 = 0;
1495
1496 if (!pci_quatech_has_qmcr(port))
1497 return 0;
1498 qmcr = pci_quatech_rqmcr(port);
1499 pci_quatech_wqmcr(port, 0xFF);
1500 if (pci_quatech_rqmcr(port))
1501 rs422 = 1;
1502 pci_quatech_wqmcr(port, qmcr);
1503 return rs422;
1504 }
1505
pci_quatech_init(struct pci_dev * dev)1506 static int pci_quatech_init(struct pci_dev *dev)
1507 {
1508 const struct pci_device_id *match;
1509 bool amcc = false;
1510
1511 match = pci_match_id(quatech_cards, dev);
1512 if (match)
1513 amcc = match->driver_data;
1514 else
1515 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1516
1517 if (amcc) {
1518 unsigned long base = pci_resource_start(dev, 0);
1519 if (base) {
1520 u32 tmp;
1521
1522 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1523 tmp = inl(base + 0x3c);
1524 outl(tmp | 0x01000000, base + 0x3c);
1525 outl(tmp & ~0x01000000, base + 0x3c);
1526 }
1527 }
1528 return 0;
1529 }
1530
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1531 static int pci_quatech_setup(struct serial_private *priv,
1532 const struct pciserial_board *board,
1533 struct uart_8250_port *port, int idx)
1534 {
1535 /* Needed by pci_quatech calls below */
1536 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1537 /* Set up the clocking */
1538 port->port.uartclk = pci_quatech_clock(port);
1539 /* For now just warn about RS422 */
1540 if (pci_quatech_rs422(port))
1541 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1542 return pci_default_setup(priv, board, port, idx);
1543 }
1544
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1545 static int pci_default_setup(struct serial_private *priv,
1546 const struct pciserial_board *board,
1547 struct uart_8250_port *port, int idx)
1548 {
1549 unsigned int bar, offset = board->first_offset, maxnr;
1550
1551 bar = FL_GET_BASE(board->flags);
1552 if (board->flags & FL_BASE_BARS)
1553 bar += idx;
1554 else
1555 offset += idx * board->uart_offset;
1556
1557 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1558 (board->reg_shift + 3);
1559
1560 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1561 return 1;
1562
1563 return setup_port(priv, port, bar, offset, board->reg_shift);
1564 }
1565
1566 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1567 ce4100_serial_setup(struct serial_private *priv,
1568 const struct pciserial_board *board,
1569 struct uart_8250_port *port, int idx)
1570 {
1571 int ret;
1572
1573 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1574 port->port.iotype = UPIO_MEM32;
1575 port->port.type = PORT_XSCALE;
1576 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1577 port->port.regshift = 2;
1578
1579 return ret;
1580 }
1581
1582 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1583 pci_omegapci_setup(struct serial_private *priv,
1584 const struct pciserial_board *board,
1585 struct uart_8250_port *port, int idx)
1586 {
1587 return setup_port(priv, port, 2, idx * 8, 0);
1588 }
1589
1590 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1591 pci_brcm_trumanage_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1594 {
1595 int ret = pci_default_setup(priv, board, port, idx);
1596
1597 port->port.type = PORT_BRCM_TRUMANAGE;
1598 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1599 return ret;
1600 }
1601
1602 /* RTS will control by MCR if this bit is 0 */
1603 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1604 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1605 #define FINTEK_RTS_INVERT BIT(5)
1606
1607 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1608 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1609 struct serial_rs485 *rs485)
1610 {
1611 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1612 u8 setting;
1613 u8 *index = (u8 *) port->private_data;
1614
1615 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1616
1617 if (rs485->flags & SER_RS485_ENABLED) {
1618 /* Enable RTS H/W control mode */
1619 setting |= FINTEK_RTS_CONTROL_BY_HW;
1620
1621 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1622 /* RTS driving high on TX */
1623 setting &= ~FINTEK_RTS_INVERT;
1624 } else {
1625 /* RTS driving low on TX */
1626 setting |= FINTEK_RTS_INVERT;
1627 }
1628 } else {
1629 /* Disable RTS H/W control mode */
1630 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1631 }
1632
1633 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1634
1635 return 0;
1636 }
1637
1638 static const struct serial_rs485 pci_fintek_rs485_supported = {
1639 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1640 /* F81504/508/512 does not support RTS delay before or after send */
1641 };
1642
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1643 static int pci_fintek_setup(struct serial_private *priv,
1644 const struct pciserial_board *board,
1645 struct uart_8250_port *port, int idx)
1646 {
1647 struct pci_dev *pdev = priv->dev;
1648 u8 *data;
1649 u8 config_base;
1650 u16 iobase;
1651
1652 config_base = 0x40 + 0x08 * idx;
1653
1654 /* Get the io address from configuration space */
1655 pci_read_config_word(pdev, config_base + 4, &iobase);
1656
1657 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1658
1659 port->port.iotype = UPIO_PORT;
1660 port->port.iobase = iobase;
1661 port->port.rs485_config = pci_fintek_rs485_config;
1662 port->port.rs485_supported = pci_fintek_rs485_supported;
1663
1664 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1665 if (!data)
1666 return -ENOMEM;
1667
1668 /* preserve index in PCI configuration space */
1669 *data = idx;
1670 port->port.private_data = data;
1671
1672 return 0;
1673 }
1674
pci_fintek_init(struct pci_dev * dev)1675 static int pci_fintek_init(struct pci_dev *dev)
1676 {
1677 unsigned long iobase;
1678 u32 max_port, i;
1679 resource_size_t bar_data[3];
1680 u8 config_base;
1681 struct serial_private *priv = pci_get_drvdata(dev);
1682
1683 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1684 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1685 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1686 return -ENODEV;
1687
1688 switch (dev->device) {
1689 case 0x1104: /* 4 ports */
1690 case 0x1108: /* 8 ports */
1691 max_port = dev->device & 0xff;
1692 break;
1693 case 0x1112: /* 12 ports */
1694 max_port = 12;
1695 break;
1696 default:
1697 return -EINVAL;
1698 }
1699
1700 /* Get the io address dispatch from the BIOS */
1701 bar_data[0] = pci_resource_start(dev, 5);
1702 bar_data[1] = pci_resource_start(dev, 4);
1703 bar_data[2] = pci_resource_start(dev, 3);
1704
1705 for (i = 0; i < max_port; ++i) {
1706 /* UART0 configuration offset start from 0x40 */
1707 config_base = 0x40 + 0x08 * i;
1708
1709 /* Calculate Real IO Port */
1710 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1711
1712 /* Enable UART I/O port */
1713 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1714
1715 /* Select 128-byte FIFO and 8x FIFO threshold */
1716 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1717
1718 /* LSB UART */
1719 pci_write_config_byte(dev, config_base + 0x04,
1720 (u8)(iobase & 0xff));
1721
1722 /* MSB UART */
1723 pci_write_config_byte(dev, config_base + 0x05,
1724 (u8)((iobase & 0xff00) >> 8));
1725
1726 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1727
1728 if (!priv) {
1729 /* First init without port data
1730 * force init to RS232 Mode
1731 */
1732 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1733 }
1734 }
1735
1736 return max_port;
1737 }
1738
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1739 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1740 {
1741 struct f815xxa_data *data = p->private_data;
1742 unsigned long flags;
1743
1744 spin_lock_irqsave(&data->lock, flags);
1745 writeb(value, p->membase + offset);
1746 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1747 spin_unlock_irqrestore(&data->lock, flags);
1748 }
1749
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1750 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1751 const struct pciserial_board *board,
1752 struct uart_8250_port *port, int idx)
1753 {
1754 struct pci_dev *pdev = priv->dev;
1755 struct f815xxa_data *data;
1756
1757 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1758 if (!data)
1759 return -ENOMEM;
1760
1761 data->idx = idx;
1762 spin_lock_init(&data->lock);
1763
1764 port->port.private_data = data;
1765 port->port.iotype = UPIO_MEM;
1766 port->port.flags |= UPF_IOREMAP;
1767 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1768 port->port.serial_out = f815xxa_mem_serial_out;
1769
1770 return 0;
1771 }
1772
pci_fintek_f815xxa_init(struct pci_dev * dev)1773 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1774 {
1775 u32 max_port, i;
1776 int config_base;
1777
1778 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1779 return -ENODEV;
1780
1781 switch (dev->device) {
1782 case 0x1204: /* 4 ports */
1783 case 0x1208: /* 8 ports */
1784 max_port = dev->device & 0xff;
1785 break;
1786 case 0x1212: /* 12 ports */
1787 max_port = 12;
1788 break;
1789 default:
1790 return -EINVAL;
1791 }
1792
1793 /* Set to mmio decode */
1794 pci_write_config_byte(dev, 0x209, 0x40);
1795
1796 for (i = 0; i < max_port; ++i) {
1797 /* UART0 configuration offset start from 0x2A0 */
1798 config_base = 0x2A0 + 0x08 * i;
1799
1800 /* Select 128-byte FIFO and 8x FIFO threshold */
1801 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1802
1803 /* Enable UART I/O port */
1804 pci_write_config_byte(dev, config_base + 0, 0x01);
1805 }
1806
1807 return max_port;
1808 }
1809
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1810 static int skip_tx_en_setup(struct serial_private *priv,
1811 const struct pciserial_board *board,
1812 struct uart_8250_port *port, int idx)
1813 {
1814 port->port.quirks |= UPQ_NO_TXEN_TEST;
1815 pci_dbg(priv->dev,
1816 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1817 priv->dev->vendor, priv->dev->device,
1818 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1819
1820 return pci_default_setup(priv, board, port, idx);
1821 }
1822
kt_handle_break(struct uart_port * p)1823 static void kt_handle_break(struct uart_port *p)
1824 {
1825 struct uart_8250_port *up = up_to_u8250p(p);
1826 /*
1827 * On receipt of a BI, serial device in Intel ME (Intel
1828 * management engine) needs to have its fifos cleared for sane
1829 * SOL (Serial Over Lan) output.
1830 */
1831 serial8250_clear_and_reinit_fifos(up);
1832 }
1833
kt_serial_in(struct uart_port * p,int offset)1834 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1835 {
1836 struct uart_8250_port *up = up_to_u8250p(p);
1837 unsigned int val;
1838
1839 /*
1840 * When the Intel ME (management engine) gets reset its serial
1841 * port registers could return 0 momentarily. Functions like
1842 * serial8250_console_write, read and save the IER, perform
1843 * some operation and then restore it. In order to avoid
1844 * setting IER register inadvertently to 0, if the value read
1845 * is 0, double check with ier value in uart_8250_port and use
1846 * that instead. up->ier should be the same value as what is
1847 * currently configured.
1848 */
1849 val = inb(p->iobase + offset);
1850 if (offset == UART_IER) {
1851 if (val == 0)
1852 val = up->ier;
1853 }
1854 return val;
1855 }
1856
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1857 static int kt_serial_setup(struct serial_private *priv,
1858 const struct pciserial_board *board,
1859 struct uart_8250_port *port, int idx)
1860 {
1861 port->port.flags |= UPF_BUG_THRE;
1862 port->port.serial_in = kt_serial_in;
1863 port->port.handle_break = kt_handle_break;
1864 return skip_tx_en_setup(priv, board, port, idx);
1865 }
1866
pci_eg20t_init(struct pci_dev * dev)1867 static int pci_eg20t_init(struct pci_dev *dev)
1868 {
1869 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1870 return -ENODEV;
1871 #else
1872 return 0;
1873 #endif
1874 }
1875
1876 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1877 pci_wch_ch353_setup(struct serial_private *priv,
1878 const struct pciserial_board *board,
1879 struct uart_8250_port *port, int idx)
1880 {
1881 port->port.flags |= UPF_FIXED_TYPE;
1882 port->port.type = PORT_16550A;
1883 return pci_default_setup(priv, board, port, idx);
1884 }
1885
1886 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1887 pci_wch_ch355_setup(struct serial_private *priv,
1888 const struct pciserial_board *board,
1889 struct uart_8250_port *port, int idx)
1890 {
1891 port->port.flags |= UPF_FIXED_TYPE;
1892 port->port.type = PORT_16550A;
1893 return pci_default_setup(priv, board, port, idx);
1894 }
1895
1896 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1897 pci_wch_ch38x_setup(struct serial_private *priv,
1898 const struct pciserial_board *board,
1899 struct uart_8250_port *port, int idx)
1900 {
1901 port->port.flags |= UPF_FIXED_TYPE;
1902 port->port.type = PORT_16850;
1903 return pci_default_setup(priv, board, port, idx);
1904 }
1905
1906
1907 #define CH384_XINT_ENABLE_REG 0xEB
1908 #define CH384_XINT_ENABLE_BIT 0x02
1909
pci_wch_ch38x_init(struct pci_dev * dev)1910 static int pci_wch_ch38x_init(struct pci_dev *dev)
1911 {
1912 int max_port;
1913 unsigned long iobase;
1914
1915
1916 switch (dev->device) {
1917 case 0x3853: /* 8 ports */
1918 max_port = 8;
1919 break;
1920 default:
1921 return -EINVAL;
1922 }
1923
1924 iobase = pci_resource_start(dev, 0);
1925 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1926
1927 return max_port;
1928 }
1929
pci_wch_ch38x_exit(struct pci_dev * dev)1930 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1931 {
1932 unsigned long iobase;
1933
1934 iobase = pci_resource_start(dev, 0);
1935 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1936 }
1937
1938
1939 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1940 pci_sunix_setup(struct serial_private *priv,
1941 const struct pciserial_board *board,
1942 struct uart_8250_port *port, int idx)
1943 {
1944 int bar;
1945 int offset;
1946
1947 port->port.flags |= UPF_FIXED_TYPE;
1948 port->port.type = PORT_SUNIX;
1949
1950 if (idx < 4) {
1951 bar = 0;
1952 offset = idx * board->uart_offset;
1953 } else {
1954 bar = 1;
1955 idx -= 4;
1956 idx = div_s64_rem(idx, 4, &offset);
1957 offset = idx * 64 + offset * board->uart_offset;
1958 }
1959
1960 return setup_port(priv, port, bar, offset, 0);
1961 }
1962
1963 #define MOXA_PUART_GPIO_EN 0x09
1964 #define MOXA_PUART_GPIO_OUT 0x0A
1965
1966 #define MOXA_GPIO_PIN2 BIT(2)
1967
1968 #define MOXA_RS232 0x00
1969 #define MOXA_RS422 0x01
1970 #define MOXA_RS485_4W 0x0B
1971 #define MOXA_RS485_2W 0x0F
1972 #define MOXA_UIR_OFFSET 0x04
1973 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
1974 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
1975
1976 enum {
1977 MOXA_SUPP_RS232 = BIT(0),
1978 MOXA_SUPP_RS422 = BIT(1),
1979 MOXA_SUPP_RS485 = BIT(2),
1980 };
1981
moxa_get_nports(unsigned short device)1982 static unsigned short moxa_get_nports(unsigned short device)
1983 {
1984 switch (device) {
1985 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
1986 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
1987 return 8;
1988 }
1989
1990 return FIELD_GET(0x00F0, device);
1991 }
1992
pci_moxa_is_mini_pcie(unsigned short device)1993 static bool pci_moxa_is_mini_pcie(unsigned short device)
1994 {
1995 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
1996 device == PCI_DEVICE_ID_MOXA_CP104N ||
1997 device == PCI_DEVICE_ID_MOXA_CP112N ||
1998 device == PCI_DEVICE_ID_MOXA_CP114N ||
1999 device == PCI_DEVICE_ID_MOXA_CP132N ||
2000 device == PCI_DEVICE_ID_MOXA_CP134N)
2001 return true;
2002
2003 return false;
2004 }
2005
pci_moxa_supported_rs(struct pci_dev * dev)2006 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2007 {
2008 switch (dev->device & 0x0F00) {
2009 case 0x0000:
2010 case 0x0600:
2011 return MOXA_SUPP_RS232;
2012 case 0x0100:
2013 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2014 case 0x0300:
2015 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2016 }
2017 return 0;
2018 }
2019
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2020 static int pci_moxa_set_interface(const struct pci_dev *dev,
2021 unsigned int port_idx,
2022 u8 mode)
2023 {
2024 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2025 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2026 u8 val;
2027
2028 val = inb(UIR_addr);
2029
2030 if (port_idx % 2) {
2031 val &= ~MOXA_ODD_RS_MASK;
2032 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2033 } else {
2034 val &= ~MOXA_EVEN_RS_MASK;
2035 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2036 }
2037 outb(val, UIR_addr);
2038
2039 return 0;
2040 }
2041
pci_moxa_init(struct pci_dev * dev)2042 static int pci_moxa_init(struct pci_dev *dev)
2043 {
2044 unsigned short device = dev->device;
2045 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2046 unsigned int i, num_ports = moxa_get_nports(device);
2047 u8 val, init_mode = MOXA_RS232;
2048
2049 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2050 init_mode = MOXA_RS422;
2051 }
2052 for (i = 0; i < num_ports; ++i)
2053 pci_moxa_set_interface(dev, i, init_mode);
2054
2055 /*
2056 * Enable hardware buffer to prevent break signal output when system boots up.
2057 * This hardware buffer is only supported on Mini PCIe series.
2058 */
2059 if (pci_moxa_is_mini_pcie(device)) {
2060 /* Set GPIO direction */
2061 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2062 val |= MOXA_GPIO_PIN2;
2063 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2064 /* Enable low GPIO */
2065 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2066 val &= ~MOXA_GPIO_PIN2;
2067 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2068 }
2069
2070 return num_ports;
2071 }
2072
2073 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2074 pci_moxa_setup(struct serial_private *priv,
2075 const struct pciserial_board *board,
2076 struct uart_8250_port *port, int idx)
2077 {
2078 unsigned int bar = FL_GET_BASE(board->flags);
2079 int offset;
2080
2081 if (board->num_ports == 4 && idx == 3)
2082 offset = 7 * board->uart_offset;
2083 else
2084 offset = idx * board->uart_offset;
2085
2086 return setup_port(priv, port, bar, offset, 0);
2087 }
2088
2089 /*
2090 * Master list of serial port init/setup/exit quirks.
2091 * This does not describe the general nature of the port.
2092 * (ie, baud base, number and location of ports, etc)
2093 *
2094 * This list is ordered alphabetically by vendor then device.
2095 * Specific entries must come before more generic entries.
2096 */
2097 static struct pci_serial_quirk pci_serial_quirks[] = {
2098 /*
2099 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2100 */
2101 {
2102 .vendor = PCI_VENDOR_ID_AMCC,
2103 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2104 .subvendor = PCI_ANY_ID,
2105 .subdevice = PCI_ANY_ID,
2106 .setup = addidata_apci7800_setup,
2107 },
2108 /*
2109 * AFAVLAB cards - these may be called via parport_serial
2110 * It is not clear whether this applies to all products.
2111 */
2112 {
2113 .vendor = PCI_VENDOR_ID_AFAVLAB,
2114 .device = PCI_ANY_ID,
2115 .subvendor = PCI_ANY_ID,
2116 .subdevice = PCI_ANY_ID,
2117 .setup = afavlab_setup,
2118 },
2119 /*
2120 * HP Diva
2121 */
2122 {
2123 .vendor = PCI_VENDOR_ID_HP,
2124 .device = PCI_DEVICE_ID_HP_DIVA,
2125 .subvendor = PCI_ANY_ID,
2126 .subdevice = PCI_ANY_ID,
2127 .init = pci_hp_diva_init,
2128 .setup = pci_hp_diva_setup,
2129 },
2130 /*
2131 * HPE PCI serial device
2132 */
2133 {
2134 .vendor = PCI_VENDOR_ID_HP_3PAR,
2135 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .setup = pci_hp_diva_setup,
2139 },
2140 /*
2141 * Intel
2142 */
2143 {
2144 .vendor = PCI_VENDOR_ID_INTEL,
2145 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2146 .subvendor = 0xe4bf,
2147 .subdevice = PCI_ANY_ID,
2148 .init = pci_inteli960ni_init,
2149 .setup = pci_default_setup,
2150 },
2151 {
2152 .vendor = PCI_VENDOR_ID_INTEL,
2153 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2154 .subvendor = PCI_ANY_ID,
2155 .subdevice = PCI_ANY_ID,
2156 .setup = skip_tx_en_setup,
2157 },
2158 {
2159 .vendor = PCI_VENDOR_ID_INTEL,
2160 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .setup = skip_tx_en_setup,
2164 },
2165 {
2166 .vendor = PCI_VENDOR_ID_INTEL,
2167 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .setup = skip_tx_en_setup,
2171 },
2172 {
2173 .vendor = PCI_VENDOR_ID_INTEL,
2174 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2175 .subvendor = PCI_ANY_ID,
2176 .subdevice = PCI_ANY_ID,
2177 .setup = ce4100_serial_setup,
2178 },
2179 {
2180 .vendor = PCI_VENDOR_ID_INTEL,
2181 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .setup = kt_serial_setup,
2185 },
2186 /*
2187 * ITE
2188 */
2189 {
2190 .vendor = PCI_VENDOR_ID_ITE,
2191 .device = PCI_DEVICE_ID_ITE_8872,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_ite887x_init,
2195 .setup = pci_default_setup,
2196 .exit = pci_ite887x_exit,
2197 },
2198 /*
2199 * National Instruments
2200 */
2201 {
2202 .vendor = PCI_VENDOR_ID_NI,
2203 .device = PCI_DEVICE_ID_NI_PCI23216,
2204 .subvendor = PCI_ANY_ID,
2205 .subdevice = PCI_ANY_ID,
2206 .init = pci_ni8420_init,
2207 .setup = pci_default_setup,
2208 .exit = pci_ni8420_exit,
2209 },
2210 {
2211 .vendor = PCI_VENDOR_ID_NI,
2212 .device = PCI_DEVICE_ID_NI_PCI2328,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .init = pci_ni8420_init,
2216 .setup = pci_default_setup,
2217 .exit = pci_ni8420_exit,
2218 },
2219 {
2220 .vendor = PCI_VENDOR_ID_NI,
2221 .device = PCI_DEVICE_ID_NI_PCI2324,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .init = pci_ni8420_init,
2225 .setup = pci_default_setup,
2226 .exit = pci_ni8420_exit,
2227 },
2228 {
2229 .vendor = PCI_VENDOR_ID_NI,
2230 .device = PCI_DEVICE_ID_NI_PCI2322,
2231 .subvendor = PCI_ANY_ID,
2232 .subdevice = PCI_ANY_ID,
2233 .init = pci_ni8420_init,
2234 .setup = pci_default_setup,
2235 .exit = pci_ni8420_exit,
2236 },
2237 {
2238 .vendor = PCI_VENDOR_ID_NI,
2239 .device = PCI_DEVICE_ID_NI_PCI2324I,
2240 .subvendor = PCI_ANY_ID,
2241 .subdevice = PCI_ANY_ID,
2242 .init = pci_ni8420_init,
2243 .setup = pci_default_setup,
2244 .exit = pci_ni8420_exit,
2245 },
2246 {
2247 .vendor = PCI_VENDOR_ID_NI,
2248 .device = PCI_DEVICE_ID_NI_PCI2322I,
2249 .subvendor = PCI_ANY_ID,
2250 .subdevice = PCI_ANY_ID,
2251 .init = pci_ni8420_init,
2252 .setup = pci_default_setup,
2253 .exit = pci_ni8420_exit,
2254 },
2255 {
2256 .vendor = PCI_VENDOR_ID_NI,
2257 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2258 .subvendor = PCI_ANY_ID,
2259 .subdevice = PCI_ANY_ID,
2260 .init = pci_ni8420_init,
2261 .setup = pci_default_setup,
2262 .exit = pci_ni8420_exit,
2263 },
2264 {
2265 .vendor = PCI_VENDOR_ID_NI,
2266 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2267 .subvendor = PCI_ANY_ID,
2268 .subdevice = PCI_ANY_ID,
2269 .init = pci_ni8420_init,
2270 .setup = pci_default_setup,
2271 .exit = pci_ni8420_exit,
2272 },
2273 {
2274 .vendor = PCI_VENDOR_ID_NI,
2275 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2276 .subvendor = PCI_ANY_ID,
2277 .subdevice = PCI_ANY_ID,
2278 .init = pci_ni8420_init,
2279 .setup = pci_default_setup,
2280 .exit = pci_ni8420_exit,
2281 },
2282 {
2283 .vendor = PCI_VENDOR_ID_NI,
2284 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2285 .subvendor = PCI_ANY_ID,
2286 .subdevice = PCI_ANY_ID,
2287 .init = pci_ni8420_init,
2288 .setup = pci_default_setup,
2289 .exit = pci_ni8420_exit,
2290 },
2291 {
2292 .vendor = PCI_VENDOR_ID_NI,
2293 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2294 .subvendor = PCI_ANY_ID,
2295 .subdevice = PCI_ANY_ID,
2296 .init = pci_ni8420_init,
2297 .setup = pci_default_setup,
2298 .exit = pci_ni8420_exit,
2299 },
2300 {
2301 .vendor = PCI_VENDOR_ID_NI,
2302 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2303 .subvendor = PCI_ANY_ID,
2304 .subdevice = PCI_ANY_ID,
2305 .init = pci_ni8420_init,
2306 .setup = pci_default_setup,
2307 .exit = pci_ni8420_exit,
2308 },
2309 {
2310 .vendor = PCI_VENDOR_ID_NI,
2311 .device = PCI_ANY_ID,
2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
2314 .init = pci_ni8430_init,
2315 .setup = pci_ni8430_setup,
2316 .exit = pci_ni8430_exit,
2317 },
2318 /* Quatech */
2319 {
2320 .vendor = PCI_VENDOR_ID_QUATECH,
2321 .device = PCI_ANY_ID,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_quatech_init,
2325 .setup = pci_quatech_setup,
2326 },
2327 /*
2328 * Panacom
2329 */
2330 {
2331 .vendor = PCI_VENDOR_ID_PANACOM,
2332 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2333 .subvendor = PCI_ANY_ID,
2334 .subdevice = PCI_ANY_ID,
2335 .init = pci_plx9050_init,
2336 .setup = pci_default_setup,
2337 .exit = pci_plx9050_exit,
2338 },
2339 {
2340 .vendor = PCI_VENDOR_ID_PANACOM,
2341 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2342 .subvendor = PCI_ANY_ID,
2343 .subdevice = PCI_ANY_ID,
2344 .init = pci_plx9050_init,
2345 .setup = pci_default_setup,
2346 .exit = pci_plx9050_exit,
2347 },
2348 /*
2349 * PLX
2350 */
2351 {
2352 .vendor = PCI_VENDOR_ID_PLX,
2353 .device = PCI_DEVICE_ID_PLX_9050,
2354 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2355 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2356 .init = pci_plx9050_init,
2357 .setup = pci_default_setup,
2358 .exit = pci_plx9050_exit,
2359 },
2360 {
2361 .vendor = PCI_VENDOR_ID_PLX,
2362 .device = PCI_DEVICE_ID_PLX_9050,
2363 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2364 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2365 .init = pci_plx9050_init,
2366 .setup = pci_default_setup,
2367 .exit = pci_plx9050_exit,
2368 },
2369 {
2370 .vendor = PCI_VENDOR_ID_PLX,
2371 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2372 .subvendor = PCI_VENDOR_ID_PLX,
2373 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2374 .init = pci_plx9050_init,
2375 .setup = pci_default_setup,
2376 .exit = pci_plx9050_exit,
2377 },
2378 /*
2379 * SBS Technologies, Inc., PMC-OCTALPRO 232
2380 */
2381 {
2382 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2383 .device = PCI_DEVICE_ID_OCTPRO,
2384 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2385 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2386 .init = sbs_init,
2387 .setup = sbs_setup,
2388 .exit = sbs_exit,
2389 },
2390 /*
2391 * SBS Technologies, Inc., PMC-OCTALPRO 422
2392 */
2393 {
2394 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2395 .device = PCI_DEVICE_ID_OCTPRO,
2396 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2397 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2398 .init = sbs_init,
2399 .setup = sbs_setup,
2400 .exit = sbs_exit,
2401 },
2402 /*
2403 * SBS Technologies, Inc., P-Octal 232
2404 */
2405 {
2406 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2407 .device = PCI_DEVICE_ID_OCTPRO,
2408 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2409 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2410 .init = sbs_init,
2411 .setup = sbs_setup,
2412 .exit = sbs_exit,
2413 },
2414 /*
2415 * SBS Technologies, Inc., P-Octal 422
2416 */
2417 {
2418 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2419 .device = PCI_DEVICE_ID_OCTPRO,
2420 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2421 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2422 .init = sbs_init,
2423 .setup = sbs_setup,
2424 .exit = sbs_exit,
2425 },
2426 /*
2427 * SIIG cards - these may be called via parport_serial
2428 */
2429 {
2430 .vendor = PCI_VENDOR_ID_SIIG,
2431 .device = PCI_ANY_ID,
2432 .subvendor = PCI_ANY_ID,
2433 .subdevice = PCI_ANY_ID,
2434 .init = pci_siig_init,
2435 .setup = pci_siig_setup,
2436 },
2437 /*
2438 * Titan cards
2439 */
2440 {
2441 .vendor = PCI_VENDOR_ID_TITAN,
2442 .device = PCI_DEVICE_ID_TITAN_400L,
2443 .subvendor = PCI_ANY_ID,
2444 .subdevice = PCI_ANY_ID,
2445 .setup = titan_400l_800l_setup,
2446 },
2447 {
2448 .vendor = PCI_VENDOR_ID_TITAN,
2449 .device = PCI_DEVICE_ID_TITAN_800L,
2450 .subvendor = PCI_ANY_ID,
2451 .subdevice = PCI_ANY_ID,
2452 .setup = titan_400l_800l_setup,
2453 },
2454 /*
2455 * Timedia cards
2456 */
2457 {
2458 .vendor = PCI_VENDOR_ID_TIMEDIA,
2459 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2460 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2461 .subdevice = PCI_ANY_ID,
2462 .probe = pci_timedia_probe,
2463 .init = pci_timedia_init,
2464 .setup = pci_timedia_setup,
2465 },
2466 {
2467 .vendor = PCI_VENDOR_ID_TIMEDIA,
2468 .device = PCI_ANY_ID,
2469 .subvendor = PCI_ANY_ID,
2470 .subdevice = PCI_ANY_ID,
2471 .setup = pci_timedia_setup,
2472 },
2473 /*
2474 * Sunix PCI serial boards
2475 */
2476 {
2477 .vendor = PCI_VENDOR_ID_SUNIX,
2478 .device = PCI_DEVICE_ID_SUNIX_1999,
2479 .subvendor = PCI_VENDOR_ID_SUNIX,
2480 .subdevice = PCI_ANY_ID,
2481 .setup = pci_sunix_setup,
2482 },
2483 /*
2484 * Xircom cards
2485 */
2486 {
2487 .vendor = PCI_VENDOR_ID_XIRCOM,
2488 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .init = pci_xircom_init,
2492 .setup = pci_default_setup,
2493 },
2494 /*
2495 * Netmos cards - these may be called via parport_serial
2496 */
2497 {
2498 .vendor = PCI_VENDOR_ID_NETMOS,
2499 .device = PCI_ANY_ID,
2500 .subvendor = PCI_ANY_ID,
2501 .subdevice = PCI_ANY_ID,
2502 .init = pci_netmos_init,
2503 .setup = pci_netmos_9900_setup,
2504 },
2505 /*
2506 * EndRun Technologies
2507 */
2508 {
2509 .vendor = PCI_VENDOR_ID_ENDRUN,
2510 .device = PCI_ANY_ID,
2511 .subvendor = PCI_ANY_ID,
2512 .subdevice = PCI_ANY_ID,
2513 .init = pci_oxsemi_tornado_init,
2514 .setup = pci_default_setup,
2515 },
2516 /*
2517 * For Oxford Semiconductor Tornado based devices
2518 */
2519 {
2520 .vendor = PCI_VENDOR_ID_OXSEMI,
2521 .device = PCI_ANY_ID,
2522 .subvendor = PCI_ANY_ID,
2523 .subdevice = PCI_ANY_ID,
2524 .init = pci_oxsemi_tornado_init,
2525 .setup = pci_oxsemi_tornado_setup,
2526 },
2527 {
2528 .vendor = PCI_VENDOR_ID_MAINPINE,
2529 .device = PCI_ANY_ID,
2530 .subvendor = PCI_ANY_ID,
2531 .subdevice = PCI_ANY_ID,
2532 .init = pci_oxsemi_tornado_init,
2533 .setup = pci_oxsemi_tornado_setup,
2534 },
2535 {
2536 .vendor = PCI_VENDOR_ID_DIGI,
2537 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2538 .subvendor = PCI_SUBVENDOR_ID_IBM,
2539 .subdevice = PCI_ANY_ID,
2540 .init = pci_oxsemi_tornado_init,
2541 .setup = pci_oxsemi_tornado_setup,
2542 },
2543 /*
2544 * Brainboxes devices - all Oxsemi based
2545 */
2546 {
2547 .vendor = PCI_VENDOR_ID_INTASHIELD,
2548 .device = 0x4027,
2549 .subvendor = PCI_ANY_ID,
2550 .subdevice = PCI_ANY_ID,
2551 .init = pci_oxsemi_tornado_init,
2552 .setup = pci_oxsemi_tornado_setup,
2553 },
2554 {
2555 .vendor = PCI_VENDOR_ID_INTASHIELD,
2556 .device = 0x4028,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .init = pci_oxsemi_tornado_init,
2560 .setup = pci_oxsemi_tornado_setup,
2561 },
2562 {
2563 .vendor = PCI_VENDOR_ID_INTASHIELD,
2564 .device = 0x4029,
2565 .subvendor = PCI_ANY_ID,
2566 .subdevice = PCI_ANY_ID,
2567 .init = pci_oxsemi_tornado_init,
2568 .setup = pci_oxsemi_tornado_setup,
2569 },
2570 {
2571 .vendor = PCI_VENDOR_ID_INTASHIELD,
2572 .device = 0x4019,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .init = pci_oxsemi_tornado_init,
2576 .setup = pci_oxsemi_tornado_setup,
2577 },
2578 {
2579 .vendor = PCI_VENDOR_ID_INTASHIELD,
2580 .device = 0x4016,
2581 .subvendor = PCI_ANY_ID,
2582 .subdevice = PCI_ANY_ID,
2583 .init = pci_oxsemi_tornado_init,
2584 .setup = pci_oxsemi_tornado_setup,
2585 },
2586 {
2587 .vendor = PCI_VENDOR_ID_INTASHIELD,
2588 .device = 0x4015,
2589 .subvendor = PCI_ANY_ID,
2590 .subdevice = PCI_ANY_ID,
2591 .init = pci_oxsemi_tornado_init,
2592 .setup = pci_oxsemi_tornado_setup,
2593 },
2594 {
2595 .vendor = PCI_VENDOR_ID_INTASHIELD,
2596 .device = 0x400A,
2597 .subvendor = PCI_ANY_ID,
2598 .subdevice = PCI_ANY_ID,
2599 .init = pci_oxsemi_tornado_init,
2600 .setup = pci_oxsemi_tornado_setup,
2601 },
2602 {
2603 .vendor = PCI_VENDOR_ID_INTASHIELD,
2604 .device = 0x400E,
2605 .subvendor = PCI_ANY_ID,
2606 .subdevice = PCI_ANY_ID,
2607 .init = pci_oxsemi_tornado_init,
2608 .setup = pci_oxsemi_tornado_setup,
2609 },
2610 {
2611 .vendor = PCI_VENDOR_ID_INTASHIELD,
2612 .device = 0x400C,
2613 .subvendor = PCI_ANY_ID,
2614 .subdevice = PCI_ANY_ID,
2615 .init = pci_oxsemi_tornado_init,
2616 .setup = pci_oxsemi_tornado_setup,
2617 },
2618 {
2619 .vendor = PCI_VENDOR_ID_INTASHIELD,
2620 .device = 0x400B,
2621 .subvendor = PCI_ANY_ID,
2622 .subdevice = PCI_ANY_ID,
2623 .init = pci_oxsemi_tornado_init,
2624 .setup = pci_oxsemi_tornado_setup,
2625 },
2626 {
2627 .vendor = PCI_VENDOR_ID_INTASHIELD,
2628 .device = 0x400F,
2629 .subvendor = PCI_ANY_ID,
2630 .subdevice = PCI_ANY_ID,
2631 .init = pci_oxsemi_tornado_init,
2632 .setup = pci_oxsemi_tornado_setup,
2633 },
2634 {
2635 .vendor = PCI_VENDOR_ID_INTASHIELD,
2636 .device = 0x4010,
2637 .subvendor = PCI_ANY_ID,
2638 .subdevice = PCI_ANY_ID,
2639 .init = pci_oxsemi_tornado_init,
2640 .setup = pci_oxsemi_tornado_setup,
2641 },
2642 {
2643 .vendor = PCI_VENDOR_ID_INTASHIELD,
2644 .device = 0x4011,
2645 .subvendor = PCI_ANY_ID,
2646 .subdevice = PCI_ANY_ID,
2647 .init = pci_oxsemi_tornado_init,
2648 .setup = pci_oxsemi_tornado_setup,
2649 },
2650 {
2651 .vendor = PCI_VENDOR_ID_INTASHIELD,
2652 .device = 0x401D,
2653 .subvendor = PCI_ANY_ID,
2654 .subdevice = PCI_ANY_ID,
2655 .init = pci_oxsemi_tornado_init,
2656 .setup = pci_oxsemi_tornado_setup,
2657 },
2658 {
2659 .vendor = PCI_VENDOR_ID_INTASHIELD,
2660 .device = 0x401E,
2661 .subvendor = PCI_ANY_ID,
2662 .subdevice = PCI_ANY_ID,
2663 .init = pci_oxsemi_tornado_init,
2664 .setup = pci_oxsemi_tornado_setup,
2665 },
2666 {
2667 .vendor = PCI_VENDOR_ID_INTASHIELD,
2668 .device = 0x4013,
2669 .subvendor = PCI_ANY_ID,
2670 .subdevice = PCI_ANY_ID,
2671 .init = pci_oxsemi_tornado_init,
2672 .setup = pci_oxsemi_tornado_setup,
2673 },
2674 {
2675 .vendor = PCI_VENDOR_ID_INTASHIELD,
2676 .device = 0x4017,
2677 .subvendor = PCI_ANY_ID,
2678 .subdevice = PCI_ANY_ID,
2679 .init = pci_oxsemi_tornado_init,
2680 .setup = pci_oxsemi_tornado_setup,
2681 },
2682 {
2683 .vendor = PCI_VENDOR_ID_INTASHIELD,
2684 .device = 0x4018,
2685 .subvendor = PCI_ANY_ID,
2686 .subdevice = PCI_ANY_ID,
2687 .init = pci_oxsemi_tornado_init,
2688 .setup = pci_oxsemi_tornado_setup,
2689 },
2690 {
2691 .vendor = PCI_VENDOR_ID_INTASHIELD,
2692 .device = 0x4026,
2693 .subvendor = PCI_ANY_ID,
2694 .subdevice = PCI_ANY_ID,
2695 .init = pci_oxsemi_tornado_init,
2696 .setup = pci_oxsemi_tornado_setup,
2697 },
2698 {
2699 .vendor = PCI_VENDOR_ID_INTASHIELD,
2700 .device = 0x4021,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .init = pci_oxsemi_tornado_init,
2704 .setup = pci_oxsemi_tornado_setup,
2705 },
2706 {
2707 .vendor = PCI_VENDOR_ID_INTEL,
2708 .device = 0x8811,
2709 .subvendor = PCI_ANY_ID,
2710 .subdevice = PCI_ANY_ID,
2711 .init = pci_eg20t_init,
2712 .setup = pci_default_setup,
2713 },
2714 {
2715 .vendor = PCI_VENDOR_ID_INTEL,
2716 .device = 0x8812,
2717 .subvendor = PCI_ANY_ID,
2718 .subdevice = PCI_ANY_ID,
2719 .init = pci_eg20t_init,
2720 .setup = pci_default_setup,
2721 },
2722 {
2723 .vendor = PCI_VENDOR_ID_INTEL,
2724 .device = 0x8813,
2725 .subvendor = PCI_ANY_ID,
2726 .subdevice = PCI_ANY_ID,
2727 .init = pci_eg20t_init,
2728 .setup = pci_default_setup,
2729 },
2730 {
2731 .vendor = PCI_VENDOR_ID_INTEL,
2732 .device = 0x8814,
2733 .subvendor = PCI_ANY_ID,
2734 .subdevice = PCI_ANY_ID,
2735 .init = pci_eg20t_init,
2736 .setup = pci_default_setup,
2737 },
2738 {
2739 .vendor = 0x10DB,
2740 .device = 0x8027,
2741 .subvendor = PCI_ANY_ID,
2742 .subdevice = PCI_ANY_ID,
2743 .init = pci_eg20t_init,
2744 .setup = pci_default_setup,
2745 },
2746 {
2747 .vendor = 0x10DB,
2748 .device = 0x8028,
2749 .subvendor = PCI_ANY_ID,
2750 .subdevice = PCI_ANY_ID,
2751 .init = pci_eg20t_init,
2752 .setup = pci_default_setup,
2753 },
2754 {
2755 .vendor = 0x10DB,
2756 .device = 0x8029,
2757 .subvendor = PCI_ANY_ID,
2758 .subdevice = PCI_ANY_ID,
2759 .init = pci_eg20t_init,
2760 .setup = pci_default_setup,
2761 },
2762 {
2763 .vendor = 0x10DB,
2764 .device = 0x800C,
2765 .subvendor = PCI_ANY_ID,
2766 .subdevice = PCI_ANY_ID,
2767 .init = pci_eg20t_init,
2768 .setup = pci_default_setup,
2769 },
2770 {
2771 .vendor = 0x10DB,
2772 .device = 0x800D,
2773 .subvendor = PCI_ANY_ID,
2774 .subdevice = PCI_ANY_ID,
2775 .init = pci_eg20t_init,
2776 .setup = pci_default_setup,
2777 },
2778 /*
2779 * Cronyx Omega PCI (PLX-chip based)
2780 */
2781 {
2782 .vendor = PCI_VENDOR_ID_PLX,
2783 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2784 .subvendor = PCI_ANY_ID,
2785 .subdevice = PCI_ANY_ID,
2786 .setup = pci_omegapci_setup,
2787 },
2788 /* WCH CH353 1S1P card (16550 clone) */
2789 {
2790 .vendor = PCI_VENDOR_ID_WCHCN,
2791 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P,
2792 .subvendor = PCI_ANY_ID,
2793 .subdevice = PCI_ANY_ID,
2794 .setup = pci_wch_ch353_setup,
2795 },
2796 /* WCH CH353 2S1P card (16550 clone) */
2797 {
2798 .vendor = PCI_VENDOR_ID_WCHCN,
2799 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P,
2800 .subvendor = PCI_ANY_ID,
2801 .subdevice = PCI_ANY_ID,
2802 .setup = pci_wch_ch353_setup,
2803 },
2804 /* WCH CH353 4S card (16550 clone) */
2805 {
2806 .vendor = PCI_VENDOR_ID_WCHCN,
2807 .device = PCI_DEVICE_ID_WCHCN_CH353_4S,
2808 .subvendor = PCI_ANY_ID,
2809 .subdevice = PCI_ANY_ID,
2810 .setup = pci_wch_ch353_setup,
2811 },
2812 /* WCH CH353 2S1PF card (16550 clone) */
2813 {
2814 .vendor = PCI_VENDOR_ID_WCHCN,
2815 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
2816 .subvendor = PCI_ANY_ID,
2817 .subdevice = PCI_ANY_ID,
2818 .setup = pci_wch_ch353_setup,
2819 },
2820 /* WCH CH352 2S card (16550 clone) */
2821 {
2822 .vendor = PCI_VENDOR_ID_WCHCN,
2823 .device = PCI_DEVICE_ID_WCHCN_CH352_2S,
2824 .subvendor = PCI_ANY_ID,
2825 .subdevice = PCI_ANY_ID,
2826 .setup = pci_wch_ch353_setup,
2827 },
2828 /* WCH CH355 4S card (16550 clone) */
2829 {
2830 .vendor = PCI_VENDOR_ID_WCHCN,
2831 .device = PCI_DEVICE_ID_WCHCN_CH355_4S,
2832 .subvendor = PCI_ANY_ID,
2833 .subdevice = PCI_ANY_ID,
2834 .setup = pci_wch_ch355_setup,
2835 },
2836 /* WCH CH382 2S card (16850 clone) */
2837 {
2838 .vendor = PCI_VENDOR_ID_WCHIC,
2839 .device = PCI_DEVICE_ID_WCHIC_CH382_2S,
2840 .subvendor = PCI_ANY_ID,
2841 .subdevice = PCI_ANY_ID,
2842 .setup = pci_wch_ch38x_setup,
2843 },
2844 /* WCH CH382 2S1P card (16850 clone) */
2845 {
2846 .vendor = PCI_VENDOR_ID_WCHIC,
2847 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P,
2848 .subvendor = PCI_ANY_ID,
2849 .subdevice = PCI_ANY_ID,
2850 .setup = pci_wch_ch38x_setup,
2851 },
2852 /* WCH CH384 4S card (16850 clone) */
2853 {
2854 .vendor = PCI_VENDOR_ID_WCHIC,
2855 .device = PCI_DEVICE_ID_WCHIC_CH384_4S,
2856 .subvendor = PCI_ANY_ID,
2857 .subdevice = PCI_ANY_ID,
2858 .setup = pci_wch_ch38x_setup,
2859 },
2860 /* WCH CH384 8S card (16850 clone) */
2861 {
2862 .vendor = PCI_VENDOR_ID_WCHIC,
2863 .device = PCI_DEVICE_ID_WCHIC_CH384_8S,
2864 .subvendor = PCI_ANY_ID,
2865 .subdevice = PCI_ANY_ID,
2866 .init = pci_wch_ch38x_init,
2867 .exit = pci_wch_ch38x_exit,
2868 .setup = pci_wch_ch38x_setup,
2869 },
2870 /*
2871 * Broadcom TruManage (NetXtreme)
2872 */
2873 {
2874 .vendor = PCI_VENDOR_ID_BROADCOM,
2875 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2876 .subvendor = PCI_ANY_ID,
2877 .subdevice = PCI_ANY_ID,
2878 .setup = pci_brcm_trumanage_setup,
2879 },
2880 {
2881 .vendor = 0x1c29,
2882 .device = 0x1104,
2883 .subvendor = PCI_ANY_ID,
2884 .subdevice = PCI_ANY_ID,
2885 .setup = pci_fintek_setup,
2886 .init = pci_fintek_init,
2887 },
2888 {
2889 .vendor = 0x1c29,
2890 .device = 0x1108,
2891 .subvendor = PCI_ANY_ID,
2892 .subdevice = PCI_ANY_ID,
2893 .setup = pci_fintek_setup,
2894 .init = pci_fintek_init,
2895 },
2896 {
2897 .vendor = 0x1c29,
2898 .device = 0x1112,
2899 .subvendor = PCI_ANY_ID,
2900 .subdevice = PCI_ANY_ID,
2901 .setup = pci_fintek_setup,
2902 .init = pci_fintek_init,
2903 },
2904 /*
2905 * MOXA
2906 */
2907 {
2908 .vendor = PCI_VENDOR_ID_MOXA,
2909 .device = PCI_ANY_ID,
2910 .subvendor = PCI_ANY_ID,
2911 .subdevice = PCI_ANY_ID,
2912 .init = pci_moxa_init,
2913 .setup = pci_moxa_setup,
2914 },
2915 {
2916 .vendor = 0x1c29,
2917 .device = 0x1204,
2918 .subvendor = PCI_ANY_ID,
2919 .subdevice = PCI_ANY_ID,
2920 .setup = pci_fintek_f815xxa_setup,
2921 .init = pci_fintek_f815xxa_init,
2922 },
2923 {
2924 .vendor = 0x1c29,
2925 .device = 0x1208,
2926 .subvendor = PCI_ANY_ID,
2927 .subdevice = PCI_ANY_ID,
2928 .setup = pci_fintek_f815xxa_setup,
2929 .init = pci_fintek_f815xxa_init,
2930 },
2931 {
2932 .vendor = 0x1c29,
2933 .device = 0x1212,
2934 .subvendor = PCI_ANY_ID,
2935 .subdevice = PCI_ANY_ID,
2936 .setup = pci_fintek_f815xxa_setup,
2937 .init = pci_fintek_f815xxa_init,
2938 },
2939
2940 /*
2941 * Default "match everything" terminator entry
2942 */
2943 {
2944 .vendor = PCI_ANY_ID,
2945 .device = PCI_ANY_ID,
2946 .subvendor = PCI_ANY_ID,
2947 .subdevice = PCI_ANY_ID,
2948 .setup = pci_default_setup,
2949 }
2950 };
2951
quirk_id_matches(u32 quirk_id,u32 dev_id)2952 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2953 {
2954 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2955 }
2956
find_quirk(struct pci_dev * dev)2957 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2958 {
2959 struct pci_serial_quirk *quirk;
2960
2961 for (quirk = pci_serial_quirks; ; quirk++)
2962 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2963 quirk_id_matches(quirk->device, dev->device) &&
2964 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2965 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2966 break;
2967 return quirk;
2968 }
2969
2970 /*
2971 * This is the configuration table for all of the PCI serial boards
2972 * which we support. It is directly indexed by the pci_board_num_t enum
2973 * value, which is encoded in the pci_device_id PCI probe table's
2974 * driver_data member.
2975 *
2976 * The makeup of these names are:
2977 * pbn_bn{_bt}_n_baud{_offsetinhex}
2978 *
2979 * bn = PCI BAR number
2980 * bt = Index using PCI BARs
2981 * n = number of serial ports
2982 * baud = baud rate
2983 * offsetinhex = offset for each sequential port (in hex)
2984 *
2985 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2986 *
2987 * Please note: in theory if n = 1, _bt infix should make no difference.
2988 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2989 */
2990 enum pci_board_num_t {
2991 pbn_default = 0,
2992
2993 pbn_b0_1_115200,
2994 pbn_b0_2_115200,
2995 pbn_b0_4_115200,
2996 pbn_b0_5_115200,
2997 pbn_b0_8_115200,
2998
2999 pbn_b0_1_921600,
3000 pbn_b0_2_921600,
3001 pbn_b0_4_921600,
3002
3003 pbn_b0_2_1130000,
3004
3005 pbn_b0_4_1152000,
3006
3007 pbn_b0_4_1250000,
3008
3009 pbn_b0_2_1843200,
3010 pbn_b0_4_1843200,
3011
3012 pbn_b0_1_15625000,
3013
3014 pbn_b0_bt_1_115200,
3015 pbn_b0_bt_2_115200,
3016 pbn_b0_bt_4_115200,
3017 pbn_b0_bt_8_115200,
3018
3019 pbn_b0_bt_1_460800,
3020 pbn_b0_bt_2_460800,
3021 pbn_b0_bt_4_460800,
3022
3023 pbn_b0_bt_1_921600,
3024 pbn_b0_bt_2_921600,
3025 pbn_b0_bt_4_921600,
3026 pbn_b0_bt_8_921600,
3027
3028 pbn_b1_1_115200,
3029 pbn_b1_2_115200,
3030 pbn_b1_4_115200,
3031 pbn_b1_8_115200,
3032 pbn_b1_16_115200,
3033
3034 pbn_b1_1_921600,
3035 pbn_b1_2_921600,
3036 pbn_b1_4_921600,
3037 pbn_b1_8_921600,
3038
3039 pbn_b1_2_1250000,
3040
3041 pbn_b1_bt_1_115200,
3042 pbn_b1_bt_2_115200,
3043 pbn_b1_bt_4_115200,
3044
3045 pbn_b1_bt_2_921600,
3046
3047 pbn_b1_1_1382400,
3048 pbn_b1_2_1382400,
3049 pbn_b1_4_1382400,
3050 pbn_b1_8_1382400,
3051
3052 pbn_b2_1_115200,
3053 pbn_b2_2_115200,
3054 pbn_b2_4_115200,
3055 pbn_b2_8_115200,
3056
3057 pbn_b2_1_460800,
3058 pbn_b2_4_460800,
3059 pbn_b2_8_460800,
3060 pbn_b2_16_460800,
3061
3062 pbn_b2_1_921600,
3063 pbn_b2_4_921600,
3064 pbn_b2_8_921600,
3065
3066 pbn_b2_8_1152000,
3067
3068 pbn_b2_bt_1_115200,
3069 pbn_b2_bt_2_115200,
3070 pbn_b2_bt_4_115200,
3071
3072 pbn_b2_bt_2_921600,
3073 pbn_b2_bt_4_921600,
3074
3075 pbn_b3_2_115200,
3076 pbn_b3_4_115200,
3077 pbn_b3_8_115200,
3078
3079 pbn_b4_bt_2_921600,
3080 pbn_b4_bt_4_921600,
3081 pbn_b4_bt_8_921600,
3082
3083 /*
3084 * Board-specific versions.
3085 */
3086 pbn_panacom,
3087 pbn_panacom2,
3088 pbn_panacom4,
3089 pbn_plx_romulus,
3090 pbn_oxsemi,
3091 pbn_oxsemi_1_15625000,
3092 pbn_oxsemi_2_15625000,
3093 pbn_oxsemi_4_15625000,
3094 pbn_oxsemi_8_15625000,
3095 pbn_intel_i960,
3096 pbn_sgi_ioc3,
3097 pbn_computone_4,
3098 pbn_computone_6,
3099 pbn_computone_8,
3100 pbn_sbsxrsio,
3101 pbn_pasemi_1682M,
3102 pbn_ni8430_2,
3103 pbn_ni8430_4,
3104 pbn_ni8430_8,
3105 pbn_ni8430_16,
3106 pbn_ADDIDATA_PCIe_1_3906250,
3107 pbn_ADDIDATA_PCIe_2_3906250,
3108 pbn_ADDIDATA_PCIe_4_3906250,
3109 pbn_ADDIDATA_PCIe_8_3906250,
3110 pbn_ce4100_1_115200,
3111 pbn_omegapci,
3112 pbn_NETMOS9900_2s_115200,
3113 pbn_brcm_trumanage,
3114 pbn_fintek_4,
3115 pbn_fintek_8,
3116 pbn_fintek_12,
3117 pbn_fintek_F81504A,
3118 pbn_fintek_F81508A,
3119 pbn_fintek_F81512A,
3120 pbn_wch382_2,
3121 pbn_wch384_4,
3122 pbn_wch384_8,
3123 pbn_sunix_pci_1s,
3124 pbn_sunix_pci_2s,
3125 pbn_sunix_pci_4s,
3126 pbn_sunix_pci_8s,
3127 pbn_sunix_pci_16s,
3128 pbn_titan_1_4000000,
3129 pbn_titan_2_4000000,
3130 pbn_titan_4_4000000,
3131 pbn_titan_8_4000000,
3132 pbn_moxa_2,
3133 pbn_moxa_4,
3134 pbn_moxa_8,
3135 };
3136
3137 /*
3138 * uart_offset - the space between channels
3139 * reg_shift - describes how the UART registers are mapped
3140 * to PCI memory by the card.
3141 * For example IER register on SBS, Inc. PMC-OctPro is located at
3142 * offset 0x10 from the UART base, while UART_IER is defined as 1
3143 * in include/linux/serial_reg.h,
3144 * see first lines of serial_in() and serial_out() in 8250.c
3145 */
3146
3147 static struct pciserial_board pci_boards[] = {
3148 [pbn_default] = {
3149 .flags = FL_BASE0,
3150 .num_ports = 1,
3151 .base_baud = 115200,
3152 .uart_offset = 8,
3153 },
3154 [pbn_b0_1_115200] = {
3155 .flags = FL_BASE0,
3156 .num_ports = 1,
3157 .base_baud = 115200,
3158 .uart_offset = 8,
3159 },
3160 [pbn_b0_2_115200] = {
3161 .flags = FL_BASE0,
3162 .num_ports = 2,
3163 .base_baud = 115200,
3164 .uart_offset = 8,
3165 },
3166 [pbn_b0_4_115200] = {
3167 .flags = FL_BASE0,
3168 .num_ports = 4,
3169 .base_baud = 115200,
3170 .uart_offset = 8,
3171 },
3172 [pbn_b0_5_115200] = {
3173 .flags = FL_BASE0,
3174 .num_ports = 5,
3175 .base_baud = 115200,
3176 .uart_offset = 8,
3177 },
3178 [pbn_b0_8_115200] = {
3179 .flags = FL_BASE0,
3180 .num_ports = 8,
3181 .base_baud = 115200,
3182 .uart_offset = 8,
3183 },
3184 [pbn_b0_1_921600] = {
3185 .flags = FL_BASE0,
3186 .num_ports = 1,
3187 .base_baud = 921600,
3188 .uart_offset = 8,
3189 },
3190 [pbn_b0_2_921600] = {
3191 .flags = FL_BASE0,
3192 .num_ports = 2,
3193 .base_baud = 921600,
3194 .uart_offset = 8,
3195 },
3196 [pbn_b0_4_921600] = {
3197 .flags = FL_BASE0,
3198 .num_ports = 4,
3199 .base_baud = 921600,
3200 .uart_offset = 8,
3201 },
3202
3203 [pbn_b0_2_1130000] = {
3204 .flags = FL_BASE0,
3205 .num_ports = 2,
3206 .base_baud = 1130000,
3207 .uart_offset = 8,
3208 },
3209
3210 [pbn_b0_4_1152000] = {
3211 .flags = FL_BASE0,
3212 .num_ports = 4,
3213 .base_baud = 1152000,
3214 .uart_offset = 8,
3215 },
3216
3217 [pbn_b0_4_1250000] = {
3218 .flags = FL_BASE0,
3219 .num_ports = 4,
3220 .base_baud = 1250000,
3221 .uart_offset = 8,
3222 },
3223
3224 [pbn_b0_2_1843200] = {
3225 .flags = FL_BASE0,
3226 .num_ports = 2,
3227 .base_baud = 1843200,
3228 .uart_offset = 8,
3229 },
3230 [pbn_b0_4_1843200] = {
3231 .flags = FL_BASE0,
3232 .num_ports = 4,
3233 .base_baud = 1843200,
3234 .uart_offset = 8,
3235 },
3236
3237 [pbn_b0_1_15625000] = {
3238 .flags = FL_BASE0,
3239 .num_ports = 1,
3240 .base_baud = 15625000,
3241 .uart_offset = 8,
3242 },
3243
3244 [pbn_b0_bt_1_115200] = {
3245 .flags = FL_BASE0|FL_BASE_BARS,
3246 .num_ports = 1,
3247 .base_baud = 115200,
3248 .uart_offset = 8,
3249 },
3250 [pbn_b0_bt_2_115200] = {
3251 .flags = FL_BASE0|FL_BASE_BARS,
3252 .num_ports = 2,
3253 .base_baud = 115200,
3254 .uart_offset = 8,
3255 },
3256 [pbn_b0_bt_4_115200] = {
3257 .flags = FL_BASE0|FL_BASE_BARS,
3258 .num_ports = 4,
3259 .base_baud = 115200,
3260 .uart_offset = 8,
3261 },
3262 [pbn_b0_bt_8_115200] = {
3263 .flags = FL_BASE0|FL_BASE_BARS,
3264 .num_ports = 8,
3265 .base_baud = 115200,
3266 .uart_offset = 8,
3267 },
3268
3269 [pbn_b0_bt_1_460800] = {
3270 .flags = FL_BASE0|FL_BASE_BARS,
3271 .num_ports = 1,
3272 .base_baud = 460800,
3273 .uart_offset = 8,
3274 },
3275 [pbn_b0_bt_2_460800] = {
3276 .flags = FL_BASE0|FL_BASE_BARS,
3277 .num_ports = 2,
3278 .base_baud = 460800,
3279 .uart_offset = 8,
3280 },
3281 [pbn_b0_bt_4_460800] = {
3282 .flags = FL_BASE0|FL_BASE_BARS,
3283 .num_ports = 4,
3284 .base_baud = 460800,
3285 .uart_offset = 8,
3286 },
3287
3288 [pbn_b0_bt_1_921600] = {
3289 .flags = FL_BASE0|FL_BASE_BARS,
3290 .num_ports = 1,
3291 .base_baud = 921600,
3292 .uart_offset = 8,
3293 },
3294 [pbn_b0_bt_2_921600] = {
3295 .flags = FL_BASE0|FL_BASE_BARS,
3296 .num_ports = 2,
3297 .base_baud = 921600,
3298 .uart_offset = 8,
3299 },
3300 [pbn_b0_bt_4_921600] = {
3301 .flags = FL_BASE0|FL_BASE_BARS,
3302 .num_ports = 4,
3303 .base_baud = 921600,
3304 .uart_offset = 8,
3305 },
3306 [pbn_b0_bt_8_921600] = {
3307 .flags = FL_BASE0|FL_BASE_BARS,
3308 .num_ports = 8,
3309 .base_baud = 921600,
3310 .uart_offset = 8,
3311 },
3312
3313 [pbn_b1_1_115200] = {
3314 .flags = FL_BASE1,
3315 .num_ports = 1,
3316 .base_baud = 115200,
3317 .uart_offset = 8,
3318 },
3319 [pbn_b1_2_115200] = {
3320 .flags = FL_BASE1,
3321 .num_ports = 2,
3322 .base_baud = 115200,
3323 .uart_offset = 8,
3324 },
3325 [pbn_b1_4_115200] = {
3326 .flags = FL_BASE1,
3327 .num_ports = 4,
3328 .base_baud = 115200,
3329 .uart_offset = 8,
3330 },
3331 [pbn_b1_8_115200] = {
3332 .flags = FL_BASE1,
3333 .num_ports = 8,
3334 .base_baud = 115200,
3335 .uart_offset = 8,
3336 },
3337 [pbn_b1_16_115200] = {
3338 .flags = FL_BASE1,
3339 .num_ports = 16,
3340 .base_baud = 115200,
3341 .uart_offset = 8,
3342 },
3343
3344 [pbn_b1_1_921600] = {
3345 .flags = FL_BASE1,
3346 .num_ports = 1,
3347 .base_baud = 921600,
3348 .uart_offset = 8,
3349 },
3350 [pbn_b1_2_921600] = {
3351 .flags = FL_BASE1,
3352 .num_ports = 2,
3353 .base_baud = 921600,
3354 .uart_offset = 8,
3355 },
3356 [pbn_b1_4_921600] = {
3357 .flags = FL_BASE1,
3358 .num_ports = 4,
3359 .base_baud = 921600,
3360 .uart_offset = 8,
3361 },
3362 [pbn_b1_8_921600] = {
3363 .flags = FL_BASE1,
3364 .num_ports = 8,
3365 .base_baud = 921600,
3366 .uart_offset = 8,
3367 },
3368 [pbn_b1_2_1250000] = {
3369 .flags = FL_BASE1,
3370 .num_ports = 2,
3371 .base_baud = 1250000,
3372 .uart_offset = 8,
3373 },
3374
3375 [pbn_b1_bt_1_115200] = {
3376 .flags = FL_BASE1|FL_BASE_BARS,
3377 .num_ports = 1,
3378 .base_baud = 115200,
3379 .uart_offset = 8,
3380 },
3381 [pbn_b1_bt_2_115200] = {
3382 .flags = FL_BASE1|FL_BASE_BARS,
3383 .num_ports = 2,
3384 .base_baud = 115200,
3385 .uart_offset = 8,
3386 },
3387 [pbn_b1_bt_4_115200] = {
3388 .flags = FL_BASE1|FL_BASE_BARS,
3389 .num_ports = 4,
3390 .base_baud = 115200,
3391 .uart_offset = 8,
3392 },
3393
3394 [pbn_b1_bt_2_921600] = {
3395 .flags = FL_BASE1|FL_BASE_BARS,
3396 .num_ports = 2,
3397 .base_baud = 921600,
3398 .uart_offset = 8,
3399 },
3400
3401 [pbn_b1_1_1382400] = {
3402 .flags = FL_BASE1,
3403 .num_ports = 1,
3404 .base_baud = 1382400,
3405 .uart_offset = 8,
3406 },
3407 [pbn_b1_2_1382400] = {
3408 .flags = FL_BASE1,
3409 .num_ports = 2,
3410 .base_baud = 1382400,
3411 .uart_offset = 8,
3412 },
3413 [pbn_b1_4_1382400] = {
3414 .flags = FL_BASE1,
3415 .num_ports = 4,
3416 .base_baud = 1382400,
3417 .uart_offset = 8,
3418 },
3419 [pbn_b1_8_1382400] = {
3420 .flags = FL_BASE1,
3421 .num_ports = 8,
3422 .base_baud = 1382400,
3423 .uart_offset = 8,
3424 },
3425
3426 [pbn_b2_1_115200] = {
3427 .flags = FL_BASE2,
3428 .num_ports = 1,
3429 .base_baud = 115200,
3430 .uart_offset = 8,
3431 },
3432 [pbn_b2_2_115200] = {
3433 .flags = FL_BASE2,
3434 .num_ports = 2,
3435 .base_baud = 115200,
3436 .uart_offset = 8,
3437 },
3438 [pbn_b2_4_115200] = {
3439 .flags = FL_BASE2,
3440 .num_ports = 4,
3441 .base_baud = 115200,
3442 .uart_offset = 8,
3443 },
3444 [pbn_b2_8_115200] = {
3445 .flags = FL_BASE2,
3446 .num_ports = 8,
3447 .base_baud = 115200,
3448 .uart_offset = 8,
3449 },
3450
3451 [pbn_b2_1_460800] = {
3452 .flags = FL_BASE2,
3453 .num_ports = 1,
3454 .base_baud = 460800,
3455 .uart_offset = 8,
3456 },
3457 [pbn_b2_4_460800] = {
3458 .flags = FL_BASE2,
3459 .num_ports = 4,
3460 .base_baud = 460800,
3461 .uart_offset = 8,
3462 },
3463 [pbn_b2_8_460800] = {
3464 .flags = FL_BASE2,
3465 .num_ports = 8,
3466 .base_baud = 460800,
3467 .uart_offset = 8,
3468 },
3469 [pbn_b2_16_460800] = {
3470 .flags = FL_BASE2,
3471 .num_ports = 16,
3472 .base_baud = 460800,
3473 .uart_offset = 8,
3474 },
3475
3476 [pbn_b2_1_921600] = {
3477 .flags = FL_BASE2,
3478 .num_ports = 1,
3479 .base_baud = 921600,
3480 .uart_offset = 8,
3481 },
3482 [pbn_b2_4_921600] = {
3483 .flags = FL_BASE2,
3484 .num_ports = 4,
3485 .base_baud = 921600,
3486 .uart_offset = 8,
3487 },
3488 [pbn_b2_8_921600] = {
3489 .flags = FL_BASE2,
3490 .num_ports = 8,
3491 .base_baud = 921600,
3492 .uart_offset = 8,
3493 },
3494
3495 [pbn_b2_8_1152000] = {
3496 .flags = FL_BASE2,
3497 .num_ports = 8,
3498 .base_baud = 1152000,
3499 .uart_offset = 8,
3500 },
3501
3502 [pbn_b2_bt_1_115200] = {
3503 .flags = FL_BASE2|FL_BASE_BARS,
3504 .num_ports = 1,
3505 .base_baud = 115200,
3506 .uart_offset = 8,
3507 },
3508 [pbn_b2_bt_2_115200] = {
3509 .flags = FL_BASE2|FL_BASE_BARS,
3510 .num_ports = 2,
3511 .base_baud = 115200,
3512 .uart_offset = 8,
3513 },
3514 [pbn_b2_bt_4_115200] = {
3515 .flags = FL_BASE2|FL_BASE_BARS,
3516 .num_ports = 4,
3517 .base_baud = 115200,
3518 .uart_offset = 8,
3519 },
3520
3521 [pbn_b2_bt_2_921600] = {
3522 .flags = FL_BASE2|FL_BASE_BARS,
3523 .num_ports = 2,
3524 .base_baud = 921600,
3525 .uart_offset = 8,
3526 },
3527 [pbn_b2_bt_4_921600] = {
3528 .flags = FL_BASE2|FL_BASE_BARS,
3529 .num_ports = 4,
3530 .base_baud = 921600,
3531 .uart_offset = 8,
3532 },
3533
3534 [pbn_b3_2_115200] = {
3535 .flags = FL_BASE3,
3536 .num_ports = 2,
3537 .base_baud = 115200,
3538 .uart_offset = 8,
3539 },
3540 [pbn_b3_4_115200] = {
3541 .flags = FL_BASE3,
3542 .num_ports = 4,
3543 .base_baud = 115200,
3544 .uart_offset = 8,
3545 },
3546 [pbn_b3_8_115200] = {
3547 .flags = FL_BASE3,
3548 .num_ports = 8,
3549 .base_baud = 115200,
3550 .uart_offset = 8,
3551 },
3552
3553 [pbn_b4_bt_2_921600] = {
3554 .flags = FL_BASE4,
3555 .num_ports = 2,
3556 .base_baud = 921600,
3557 .uart_offset = 8,
3558 },
3559 [pbn_b4_bt_4_921600] = {
3560 .flags = FL_BASE4,
3561 .num_ports = 4,
3562 .base_baud = 921600,
3563 .uart_offset = 8,
3564 },
3565 [pbn_b4_bt_8_921600] = {
3566 .flags = FL_BASE4,
3567 .num_ports = 8,
3568 .base_baud = 921600,
3569 .uart_offset = 8,
3570 },
3571
3572 /*
3573 * Entries following this are board-specific.
3574 */
3575
3576 /*
3577 * Panacom - IOMEM
3578 */
3579 [pbn_panacom] = {
3580 .flags = FL_BASE2,
3581 .num_ports = 2,
3582 .base_baud = 921600,
3583 .uart_offset = 0x400,
3584 .reg_shift = 7,
3585 },
3586 [pbn_panacom2] = {
3587 .flags = FL_BASE2|FL_BASE_BARS,
3588 .num_ports = 2,
3589 .base_baud = 921600,
3590 .uart_offset = 0x400,
3591 .reg_shift = 7,
3592 },
3593 [pbn_panacom4] = {
3594 .flags = FL_BASE2|FL_BASE_BARS,
3595 .num_ports = 4,
3596 .base_baud = 921600,
3597 .uart_offset = 0x400,
3598 .reg_shift = 7,
3599 },
3600
3601 /* I think this entry is broken - the first_offset looks wrong --rmk */
3602 [pbn_plx_romulus] = {
3603 .flags = FL_BASE2,
3604 .num_ports = 4,
3605 .base_baud = 921600,
3606 .uart_offset = 8 << 2,
3607 .reg_shift = 2,
3608 .first_offset = 0x03,
3609 },
3610
3611 /*
3612 * This board uses the size of PCI Base region 0 to
3613 * signal now many ports are available
3614 */
3615 [pbn_oxsemi] = {
3616 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3617 .num_ports = 32,
3618 .base_baud = 115200,
3619 .uart_offset = 8,
3620 },
3621 [pbn_oxsemi_1_15625000] = {
3622 .flags = FL_BASE0,
3623 .num_ports = 1,
3624 .base_baud = 15625000,
3625 .uart_offset = 0x200,
3626 .first_offset = 0x1000,
3627 },
3628 [pbn_oxsemi_2_15625000] = {
3629 .flags = FL_BASE0,
3630 .num_ports = 2,
3631 .base_baud = 15625000,
3632 .uart_offset = 0x200,
3633 .first_offset = 0x1000,
3634 },
3635 [pbn_oxsemi_4_15625000] = {
3636 .flags = FL_BASE0,
3637 .num_ports = 4,
3638 .base_baud = 15625000,
3639 .uart_offset = 0x200,
3640 .first_offset = 0x1000,
3641 },
3642 [pbn_oxsemi_8_15625000] = {
3643 .flags = FL_BASE0,
3644 .num_ports = 8,
3645 .base_baud = 15625000,
3646 .uart_offset = 0x200,
3647 .first_offset = 0x1000,
3648 },
3649
3650
3651 /*
3652 * EKF addition for i960 Boards form EKF with serial port.
3653 * Max 256 ports.
3654 */
3655 [pbn_intel_i960] = {
3656 .flags = FL_BASE0,
3657 .num_ports = 32,
3658 .base_baud = 921600,
3659 .uart_offset = 8 << 2,
3660 .reg_shift = 2,
3661 .first_offset = 0x10000,
3662 },
3663 [pbn_sgi_ioc3] = {
3664 .flags = FL_BASE0|FL_NOIRQ,
3665 .num_ports = 1,
3666 .base_baud = 458333,
3667 .uart_offset = 8,
3668 .reg_shift = 0,
3669 .first_offset = 0x20178,
3670 },
3671
3672 /*
3673 * Computone - uses IOMEM.
3674 */
3675 [pbn_computone_4] = {
3676 .flags = FL_BASE0,
3677 .num_ports = 4,
3678 .base_baud = 921600,
3679 .uart_offset = 0x40,
3680 .reg_shift = 2,
3681 .first_offset = 0x200,
3682 },
3683 [pbn_computone_6] = {
3684 .flags = FL_BASE0,
3685 .num_ports = 6,
3686 .base_baud = 921600,
3687 .uart_offset = 0x40,
3688 .reg_shift = 2,
3689 .first_offset = 0x200,
3690 },
3691 [pbn_computone_8] = {
3692 .flags = FL_BASE0,
3693 .num_ports = 8,
3694 .base_baud = 921600,
3695 .uart_offset = 0x40,
3696 .reg_shift = 2,
3697 .first_offset = 0x200,
3698 },
3699 [pbn_sbsxrsio] = {
3700 .flags = FL_BASE0,
3701 .num_ports = 8,
3702 .base_baud = 460800,
3703 .uart_offset = 256,
3704 .reg_shift = 4,
3705 },
3706 /*
3707 * PA Semi PWRficient PA6T-1682M on-chip UART
3708 */
3709 [pbn_pasemi_1682M] = {
3710 .flags = FL_BASE0,
3711 .num_ports = 1,
3712 .base_baud = 8333333,
3713 },
3714 /*
3715 * National Instruments 843x
3716 */
3717 [pbn_ni8430_16] = {
3718 .flags = FL_BASE0,
3719 .num_ports = 16,
3720 .base_baud = 3686400,
3721 .uart_offset = 0x10,
3722 .first_offset = 0x800,
3723 },
3724 [pbn_ni8430_8] = {
3725 .flags = FL_BASE0,
3726 .num_ports = 8,
3727 .base_baud = 3686400,
3728 .uart_offset = 0x10,
3729 .first_offset = 0x800,
3730 },
3731 [pbn_ni8430_4] = {
3732 .flags = FL_BASE0,
3733 .num_ports = 4,
3734 .base_baud = 3686400,
3735 .uart_offset = 0x10,
3736 .first_offset = 0x800,
3737 },
3738 [pbn_ni8430_2] = {
3739 .flags = FL_BASE0,
3740 .num_ports = 2,
3741 .base_baud = 3686400,
3742 .uart_offset = 0x10,
3743 .first_offset = 0x800,
3744 },
3745 /*
3746 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3747 */
3748 [pbn_ADDIDATA_PCIe_1_3906250] = {
3749 .flags = FL_BASE0,
3750 .num_ports = 1,
3751 .base_baud = 3906250,
3752 .uart_offset = 0x200,
3753 .first_offset = 0x1000,
3754 },
3755 [pbn_ADDIDATA_PCIe_2_3906250] = {
3756 .flags = FL_BASE0,
3757 .num_ports = 2,
3758 .base_baud = 3906250,
3759 .uart_offset = 0x200,
3760 .first_offset = 0x1000,
3761 },
3762 [pbn_ADDIDATA_PCIe_4_3906250] = {
3763 .flags = FL_BASE0,
3764 .num_ports = 4,
3765 .base_baud = 3906250,
3766 .uart_offset = 0x200,
3767 .first_offset = 0x1000,
3768 },
3769 [pbn_ADDIDATA_PCIe_8_3906250] = {
3770 .flags = FL_BASE0,
3771 .num_ports = 8,
3772 .base_baud = 3906250,
3773 .uart_offset = 0x200,
3774 .first_offset = 0x1000,
3775 },
3776 [pbn_ce4100_1_115200] = {
3777 .flags = FL_BASE_BARS,
3778 .num_ports = 2,
3779 .base_baud = 921600,
3780 .reg_shift = 2,
3781 },
3782 [pbn_omegapci] = {
3783 .flags = FL_BASE0,
3784 .num_ports = 8,
3785 .base_baud = 115200,
3786 .uart_offset = 0x200,
3787 },
3788 [pbn_NETMOS9900_2s_115200] = {
3789 .flags = FL_BASE0,
3790 .num_ports = 2,
3791 .base_baud = 115200,
3792 },
3793 [pbn_brcm_trumanage] = {
3794 .flags = FL_BASE0,
3795 .num_ports = 1,
3796 .reg_shift = 2,
3797 .base_baud = 115200,
3798 },
3799 [pbn_fintek_4] = {
3800 .num_ports = 4,
3801 .uart_offset = 8,
3802 .base_baud = 115200,
3803 .first_offset = 0x40,
3804 },
3805 [pbn_fintek_8] = {
3806 .num_ports = 8,
3807 .uart_offset = 8,
3808 .base_baud = 115200,
3809 .first_offset = 0x40,
3810 },
3811 [pbn_fintek_12] = {
3812 .num_ports = 12,
3813 .uart_offset = 8,
3814 .base_baud = 115200,
3815 .first_offset = 0x40,
3816 },
3817 [pbn_fintek_F81504A] = {
3818 .num_ports = 4,
3819 .uart_offset = 8,
3820 .base_baud = 115200,
3821 },
3822 [pbn_fintek_F81508A] = {
3823 .num_ports = 8,
3824 .uart_offset = 8,
3825 .base_baud = 115200,
3826 },
3827 [pbn_fintek_F81512A] = {
3828 .num_ports = 12,
3829 .uart_offset = 8,
3830 .base_baud = 115200,
3831 },
3832 [pbn_wch382_2] = {
3833 .flags = FL_BASE0,
3834 .num_ports = 2,
3835 .base_baud = 115200,
3836 .uart_offset = 8,
3837 .first_offset = 0xC0,
3838 },
3839 [pbn_wch384_4] = {
3840 .flags = FL_BASE0,
3841 .num_ports = 4,
3842 .base_baud = 115200,
3843 .uart_offset = 8,
3844 .first_offset = 0xC0,
3845 },
3846 [pbn_wch384_8] = {
3847 .flags = FL_BASE0,
3848 .num_ports = 8,
3849 .base_baud = 115200,
3850 .uart_offset = 8,
3851 .first_offset = 0x00,
3852 },
3853 [pbn_sunix_pci_1s] = {
3854 .num_ports = 1,
3855 .base_baud = 921600,
3856 .uart_offset = 0x8,
3857 },
3858 [pbn_sunix_pci_2s] = {
3859 .num_ports = 2,
3860 .base_baud = 921600,
3861 .uart_offset = 0x8,
3862 },
3863 [pbn_sunix_pci_4s] = {
3864 .num_ports = 4,
3865 .base_baud = 921600,
3866 .uart_offset = 0x8,
3867 },
3868 [pbn_sunix_pci_8s] = {
3869 .num_ports = 8,
3870 .base_baud = 921600,
3871 .uart_offset = 0x8,
3872 },
3873 [pbn_sunix_pci_16s] = {
3874 .num_ports = 16,
3875 .base_baud = 921600,
3876 .uart_offset = 0x8,
3877 },
3878 [pbn_titan_1_4000000] = {
3879 .flags = FL_BASE0,
3880 .num_ports = 1,
3881 .base_baud = 4000000,
3882 .uart_offset = 0x200,
3883 .first_offset = 0x1000,
3884 },
3885 [pbn_titan_2_4000000] = {
3886 .flags = FL_BASE0,
3887 .num_ports = 2,
3888 .base_baud = 4000000,
3889 .uart_offset = 0x200,
3890 .first_offset = 0x1000,
3891 },
3892 [pbn_titan_4_4000000] = {
3893 .flags = FL_BASE0,
3894 .num_ports = 4,
3895 .base_baud = 4000000,
3896 .uart_offset = 0x200,
3897 .first_offset = 0x1000,
3898 },
3899 [pbn_titan_8_4000000] = {
3900 .flags = FL_BASE0,
3901 .num_ports = 8,
3902 .base_baud = 4000000,
3903 .uart_offset = 0x200,
3904 .first_offset = 0x1000,
3905 },
3906 [pbn_moxa_2] = {
3907 .flags = FL_BASE1,
3908 .num_ports = 2,
3909 .base_baud = 921600,
3910 .uart_offset = 0x200,
3911 },
3912 [pbn_moxa_4] = {
3913 .flags = FL_BASE1,
3914 .num_ports = 4,
3915 .base_baud = 921600,
3916 .uart_offset = 0x200,
3917 },
3918 [pbn_moxa_8] = {
3919 .flags = FL_BASE1,
3920 .num_ports = 8,
3921 .base_baud = 921600,
3922 .uart_offset = 0x200,
3923 },
3924 };
3925
3926 #define REPORT_CONFIG(option) \
3927 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3928 #define REPORT_8250_CONFIG(option) \
3929 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3930 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3931
3932 static const struct pci_device_id blacklist[] = {
3933 /* softmodems */
3934 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3935 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3936 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3937
3938 /* multi-io cards handled by parport_serial */
3939 /* WCH CH353 2S1P */
3940 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3941 /* WCH CH353 1S1P */
3942 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3943 /* WCH CH382 2S1P */
3944 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
3945
3946 /* Intel platforms with MID UART */
3947 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3948 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3949 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3950 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3951 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3952 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3953
3954 /* Intel platforms with DesignWare UART */
3955 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3956 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3957 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3958 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3959 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3960 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3961 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3962 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3963 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3964 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3965 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3966 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3967 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
3968
3969 /* Exar devices */
3970 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3971 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3972
3973 /* Pericom devices */
3974 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3975 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3976
3977 /* End of the black list */
3978 { }
3979 };
3980
serial_pci_is_class_communication(struct pci_dev * dev)3981 static int serial_pci_is_class_communication(struct pci_dev *dev)
3982 {
3983 /*
3984 * If it is not a communications device or the programming
3985 * interface is greater than 6, give up.
3986 */
3987 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3988 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3989 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3990 (dev->class & 0xff) > 6)
3991 return -ENODEV;
3992
3993 return 0;
3994 }
3995
3996 /*
3997 * Given a complete unknown PCI device, try to use some heuristics to
3998 * guess what the configuration might be, based on the pitiful PCI
3999 * serial specs. Returns 0 on success, -ENODEV on failure.
4000 */
4001 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4002 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4003 {
4004 int num_iomem, num_port, first_port = -1, i;
4005 int rc;
4006
4007 rc = serial_pci_is_class_communication(dev);
4008 if (rc)
4009 return rc;
4010
4011 /*
4012 * Should we try to make guesses for multiport serial devices later?
4013 */
4014 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4015 return -ENODEV;
4016
4017 num_iomem = num_port = 0;
4018 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4019 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4020 num_port++;
4021 if (first_port == -1)
4022 first_port = i;
4023 }
4024 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4025 num_iomem++;
4026 }
4027
4028 /*
4029 * If there is 1 or 0 iomem regions, and exactly one port,
4030 * use it. We guess the number of ports based on the IO
4031 * region size.
4032 */
4033 if (num_iomem <= 1 && num_port == 1) {
4034 board->flags = first_port;
4035 board->num_ports = pci_resource_len(dev, first_port) / 8;
4036 return 0;
4037 }
4038
4039 /*
4040 * Now guess if we've got a board which indexes by BARs.
4041 * Each IO BAR should be 8 bytes, and they should follow
4042 * consecutively.
4043 */
4044 first_port = -1;
4045 num_port = 0;
4046 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4047 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4048 pci_resource_len(dev, i) == 8 &&
4049 (first_port == -1 || (first_port + num_port) == i)) {
4050 num_port++;
4051 if (first_port == -1)
4052 first_port = i;
4053 }
4054 }
4055
4056 if (num_port > 1) {
4057 board->flags = first_port | FL_BASE_BARS;
4058 board->num_ports = num_port;
4059 return 0;
4060 }
4061
4062 return -ENODEV;
4063 }
4064
4065 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4066 serial_pci_matches(const struct pciserial_board *board,
4067 const struct pciserial_board *guessed)
4068 {
4069 return
4070 board->num_ports == guessed->num_ports &&
4071 board->base_baud == guessed->base_baud &&
4072 board->uart_offset == guessed->uart_offset &&
4073 board->reg_shift == guessed->reg_shift &&
4074 board->first_offset == guessed->first_offset;
4075 }
4076
4077 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4078 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4079 {
4080 struct uart_8250_port uart;
4081 struct serial_private *priv;
4082 struct pci_serial_quirk *quirk;
4083 int rc, nr_ports, i;
4084
4085 nr_ports = board->num_ports;
4086
4087 /*
4088 * Find an init and setup quirks.
4089 */
4090 quirk = find_quirk(dev);
4091
4092 /*
4093 * Run the new-style initialization function.
4094 * The initialization function returns:
4095 * <0 - error
4096 * 0 - use board->num_ports
4097 * >0 - number of ports
4098 */
4099 if (quirk->init) {
4100 rc = quirk->init(dev);
4101 if (rc < 0) {
4102 priv = ERR_PTR(rc);
4103 goto err_out;
4104 }
4105 if (rc)
4106 nr_ports = rc;
4107 }
4108
4109 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
4110 if (!priv) {
4111 priv = ERR_PTR(-ENOMEM);
4112 goto err_deinit;
4113 }
4114
4115 priv->dev = dev;
4116 priv->quirk = quirk;
4117
4118 memset(&uart, 0, sizeof(uart));
4119 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4120 uart.port.uartclk = board->base_baud * 16;
4121
4122 if (board->flags & FL_NOIRQ) {
4123 uart.port.irq = 0;
4124 } else {
4125 if (pci_match_id(pci_use_msi, dev)) {
4126 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4127 pci_set_master(dev);
4128 uart.port.flags &= ~UPF_SHARE_IRQ;
4129 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4130 } else {
4131 pci_dbg(dev, "Using legacy interrupts\n");
4132 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4133 }
4134 if (rc < 0) {
4135 kfree(priv);
4136 priv = ERR_PTR(rc);
4137 goto err_deinit;
4138 }
4139
4140 uart.port.irq = pci_irq_vector(dev, 0);
4141 }
4142
4143 uart.port.dev = &dev->dev;
4144
4145 for (i = 0; i < nr_ports; i++) {
4146 if (quirk->setup(priv, board, &uart, i))
4147 break;
4148
4149 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4150 uart.port.iobase, uart.port.irq, uart.port.iotype);
4151
4152 priv->line[i] = serial8250_register_8250_port(&uart);
4153 if (priv->line[i] < 0) {
4154 pci_err(dev,
4155 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4156 uart.port.iobase, uart.port.irq,
4157 uart.port.iotype, priv->line[i]);
4158 break;
4159 }
4160 }
4161 priv->nr = i;
4162 priv->board = board;
4163 return priv;
4164
4165 err_deinit:
4166 if (quirk->exit)
4167 quirk->exit(dev);
4168 err_out:
4169 return priv;
4170 }
4171 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4172
pciserial_detach_ports(struct serial_private * priv)4173 static void pciserial_detach_ports(struct serial_private *priv)
4174 {
4175 struct pci_serial_quirk *quirk;
4176 int i;
4177
4178 for (i = 0; i < priv->nr; i++)
4179 serial8250_unregister_port(priv->line[i]);
4180
4181 /*
4182 * Find the exit quirks.
4183 */
4184 quirk = find_quirk(priv->dev);
4185 if (quirk->exit)
4186 quirk->exit(priv->dev);
4187 }
4188
pciserial_remove_ports(struct serial_private * priv)4189 void pciserial_remove_ports(struct serial_private *priv)
4190 {
4191 pciserial_detach_ports(priv);
4192 kfree(priv);
4193 }
4194 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4195
pciserial_suspend_ports(struct serial_private * priv)4196 void pciserial_suspend_ports(struct serial_private *priv)
4197 {
4198 int i;
4199
4200 for (i = 0; i < priv->nr; i++)
4201 if (priv->line[i] >= 0)
4202 serial8250_suspend_port(priv->line[i]);
4203
4204 /*
4205 * Ensure that every init quirk is properly torn down
4206 */
4207 if (priv->quirk->exit)
4208 priv->quirk->exit(priv->dev);
4209 }
4210 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4211
pciserial_resume_ports(struct serial_private * priv)4212 void pciserial_resume_ports(struct serial_private *priv)
4213 {
4214 int i;
4215
4216 /*
4217 * Ensure that the board is correctly configured.
4218 */
4219 if (priv->quirk->init)
4220 priv->quirk->init(priv->dev);
4221
4222 for (i = 0; i < priv->nr; i++)
4223 if (priv->line[i] >= 0)
4224 serial8250_resume_port(priv->line[i]);
4225 }
4226 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4227
4228 /*
4229 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4230 * to the arrangement of serial ports on a PCI card.
4231 */
4232 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4233 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4234 {
4235 struct pci_serial_quirk *quirk;
4236 struct serial_private *priv;
4237 const struct pciserial_board *board;
4238 const struct pci_device_id *exclude;
4239 struct pciserial_board tmp;
4240 int rc;
4241
4242 quirk = find_quirk(dev);
4243 if (quirk->probe) {
4244 rc = quirk->probe(dev);
4245 if (rc)
4246 return rc;
4247 }
4248
4249 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4250 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4251 return -EINVAL;
4252 }
4253
4254 board = &pci_boards[ent->driver_data];
4255
4256 exclude = pci_match_id(blacklist, dev);
4257 if (exclude) {
4258 if (exclude->driver_data)
4259 pci_warn(dev, "ignoring port, enable %s to handle\n",
4260 (const char *)exclude->driver_data);
4261 return -ENODEV;
4262 }
4263
4264 rc = pcim_enable_device(dev);
4265 pci_save_state(dev);
4266 if (rc)
4267 return rc;
4268
4269 if (ent->driver_data == pbn_default) {
4270 /*
4271 * Use a copy of the pci_board entry for this;
4272 * avoid changing entries in the table.
4273 */
4274 memcpy(&tmp, board, sizeof(struct pciserial_board));
4275 board = &tmp;
4276
4277 /*
4278 * We matched one of our class entries. Try to
4279 * determine the parameters of this board.
4280 */
4281 rc = serial_pci_guess_board(dev, &tmp);
4282 if (rc)
4283 return rc;
4284 } else {
4285 /*
4286 * We matched an explicit entry. If we are able to
4287 * detect this boards settings with our heuristic,
4288 * then we no longer need this entry.
4289 */
4290 memcpy(&tmp, &pci_boards[pbn_default],
4291 sizeof(struct pciserial_board));
4292 rc = serial_pci_guess_board(dev, &tmp);
4293 if (rc == 0 && serial_pci_matches(board, &tmp))
4294 moan_device("Redundant entry in serial pci_table.",
4295 dev);
4296 }
4297
4298 priv = pciserial_init_ports(dev, board);
4299 if (IS_ERR(priv))
4300 return PTR_ERR(priv);
4301
4302 pci_set_drvdata(dev, priv);
4303 return 0;
4304 }
4305
pciserial_remove_one(struct pci_dev * dev)4306 static void pciserial_remove_one(struct pci_dev *dev)
4307 {
4308 struct serial_private *priv = pci_get_drvdata(dev);
4309
4310 pciserial_remove_ports(priv);
4311 }
4312
4313 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4314 static int pciserial_suspend_one(struct device *dev)
4315 {
4316 struct serial_private *priv = dev_get_drvdata(dev);
4317
4318 if (priv)
4319 pciserial_suspend_ports(priv);
4320
4321 return 0;
4322 }
4323
pciserial_resume_one(struct device * dev)4324 static int pciserial_resume_one(struct device *dev)
4325 {
4326 struct pci_dev *pdev = to_pci_dev(dev);
4327 struct serial_private *priv = pci_get_drvdata(pdev);
4328 int err;
4329
4330 if (priv) {
4331 /*
4332 * The device may have been disabled. Re-enable it.
4333 */
4334 err = pci_enable_device(pdev);
4335 /* FIXME: We cannot simply error out here */
4336 if (err)
4337 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4338 pciserial_resume_ports(priv);
4339 }
4340 return 0;
4341 }
4342 #endif
4343
4344 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4345 pciserial_resume_one);
4346
4347 static const struct pci_device_id serial_pci_tbl[] = {
4348 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4349 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4350 pbn_b0_4_921600 },
4351 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4352 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4353 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4354 pbn_b2_8_921600 },
4355 /* Advantech also use 0x3618 and 0xf618 */
4356 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4357 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4358 pbn_b0_4_921600 },
4359 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4360 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4361 pbn_b0_4_921600 },
4362 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4363 PCI_SUBVENDOR_ID_CONNECT_TECH,
4364 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4365 pbn_b1_8_1382400 },
4366 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4367 PCI_SUBVENDOR_ID_CONNECT_TECH,
4368 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4369 pbn_b1_4_1382400 },
4370 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4371 PCI_SUBVENDOR_ID_CONNECT_TECH,
4372 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4373 pbn_b1_2_1382400 },
4374 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4375 PCI_SUBVENDOR_ID_CONNECT_TECH,
4376 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4377 pbn_b1_8_1382400 },
4378 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4379 PCI_SUBVENDOR_ID_CONNECT_TECH,
4380 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4381 pbn_b1_4_1382400 },
4382 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4383 PCI_SUBVENDOR_ID_CONNECT_TECH,
4384 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4385 pbn_b1_2_1382400 },
4386 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4387 PCI_SUBVENDOR_ID_CONNECT_TECH,
4388 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4389 pbn_b1_8_921600 },
4390 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4391 PCI_SUBVENDOR_ID_CONNECT_TECH,
4392 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4393 pbn_b1_8_921600 },
4394 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4395 PCI_SUBVENDOR_ID_CONNECT_TECH,
4396 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4397 pbn_b1_4_921600 },
4398 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4399 PCI_SUBVENDOR_ID_CONNECT_TECH,
4400 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4401 pbn_b1_4_921600 },
4402 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4403 PCI_SUBVENDOR_ID_CONNECT_TECH,
4404 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4405 pbn_b1_2_921600 },
4406 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4407 PCI_SUBVENDOR_ID_CONNECT_TECH,
4408 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4409 pbn_b1_8_921600 },
4410 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4411 PCI_SUBVENDOR_ID_CONNECT_TECH,
4412 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4413 pbn_b1_8_921600 },
4414 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4415 PCI_SUBVENDOR_ID_CONNECT_TECH,
4416 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4417 pbn_b1_4_921600 },
4418 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4419 PCI_SUBVENDOR_ID_CONNECT_TECH,
4420 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4421 pbn_b1_2_1250000 },
4422 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4423 PCI_SUBVENDOR_ID_CONNECT_TECH,
4424 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4425 pbn_b0_2_1843200 },
4426 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4427 PCI_SUBVENDOR_ID_CONNECT_TECH,
4428 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4429 pbn_b0_4_1843200 },
4430 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4431 PCI_VENDOR_ID_AFAVLAB,
4432 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4433 pbn_b0_4_1152000 },
4434 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b2_bt_1_115200 },
4437 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b2_bt_2_115200 },
4440 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b2_bt_4_115200 },
4443 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_b2_bt_2_115200 },
4446 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_b2_bt_4_115200 },
4449 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b2_8_115200 },
4452 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b2_8_460800 },
4455 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b2_8_115200 },
4458
4459 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 pbn_b2_bt_2_115200 },
4462 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 pbn_b2_bt_2_921600 },
4465 /*
4466 * VScom SPCOM800, from sl@s.pl
4467 */
4468 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 pbn_b2_8_921600 },
4471 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 pbn_b2_4_921600 },
4474 /* Unknown card - subdevice 0x1584 */
4475 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4476 PCI_VENDOR_ID_PLX,
4477 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4478 pbn_b2_4_115200 },
4479 /* Unknown card - subdevice 0x1588 */
4480 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4481 PCI_VENDOR_ID_PLX,
4482 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4483 pbn_b2_8_115200 },
4484 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4485 PCI_SUBVENDOR_ID_KEYSPAN,
4486 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4487 pbn_panacom },
4488 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_panacom4 },
4491 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_panacom2 },
4494 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4495 PCI_VENDOR_ID_ESDGMBH,
4496 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4497 pbn_b2_4_115200 },
4498 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4499 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4500 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4501 pbn_b2_4_460800 },
4502 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4503 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4504 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4505 pbn_b2_8_460800 },
4506 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4507 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4508 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4509 pbn_b2_16_460800 },
4510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4511 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4512 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4513 pbn_b2_16_460800 },
4514 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4515 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4516 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4517 pbn_b2_4_460800 },
4518 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4519 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4520 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4521 pbn_b2_8_460800 },
4522 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4523 PCI_SUBVENDOR_ID_EXSYS,
4524 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4525 pbn_b2_4_115200 },
4526 /*
4527 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4528 * (Exoray@isys.ca)
4529 */
4530 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4531 0x10b5, 0x106a, 0, 0,
4532 pbn_plx_romulus },
4533 /*
4534 * Quatech cards. These actually have configurable clocks but for
4535 * now we just use the default.
4536 *
4537 * 100 series are RS232, 200 series RS422,
4538 */
4539 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_b1_4_115200 },
4542 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_b1_2_115200 },
4545 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_b2_2_115200 },
4548 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_b1_2_115200 },
4551 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_b2_2_115200 },
4554 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_b1_4_115200 },
4557 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_b1_8_115200 },
4560 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 pbn_b1_8_115200 },
4563 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_b1_4_115200 },
4566 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_b1_2_115200 },
4569 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_b1_4_115200 },
4572 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_b1_2_115200 },
4575 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_b2_4_115200 },
4578 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b2_2_115200 },
4581 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b2_1_115200 },
4584 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b2_4_115200 },
4587 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b2_2_115200 },
4590 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b2_1_115200 },
4593 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b0_8_115200 },
4596
4597 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4598 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4599 0, 0,
4600 pbn_b0_4_921600 },
4601 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4602 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4603 0, 0,
4604 pbn_b0_4_1152000 },
4605 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b0_bt_2_921600 },
4608
4609 /*
4610 * The below card is a little controversial since it is the
4611 * subject of a PCI vendor/device ID clash. (See
4612 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4613 * For now just used the hex ID 0x950a.
4614 */
4615 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4616 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4617 0, 0, pbn_b0_2_115200 },
4618 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4619 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4620 0, 0, pbn_b0_2_115200 },
4621 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b0_2_1130000 },
4624 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4625 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4626 pbn_b0_1_921600 },
4627 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b0_4_115200 },
4630 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b0_bt_2_921600 },
4633 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b2_8_1152000 },
4636
4637 /*
4638 * Oxford Semiconductor Inc. Tornado PCI express device range.
4639 */
4640 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b0_1_15625000 },
4643 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b0_1_15625000 },
4646 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_oxsemi_1_15625000 },
4649 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_oxsemi_1_15625000 },
4652 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_b0_1_15625000 },
4655 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_b0_1_15625000 },
4658 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_oxsemi_1_15625000 },
4661 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_oxsemi_1_15625000 },
4664 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_b0_1_15625000 },
4667 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b0_1_15625000 },
4670 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b0_1_15625000 },
4673 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b0_1_15625000 },
4676 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_oxsemi_2_15625000 },
4679 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_oxsemi_2_15625000 },
4682 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_oxsemi_4_15625000 },
4685 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_oxsemi_4_15625000 },
4688 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_oxsemi_8_15625000 },
4691 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_oxsemi_8_15625000 },
4694 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_oxsemi_1_15625000 },
4697 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_oxsemi_1_15625000 },
4700 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_oxsemi_1_15625000 },
4703 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_oxsemi_1_15625000 },
4706 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_oxsemi_1_15625000 },
4709 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_oxsemi_1_15625000 },
4712 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_oxsemi_1_15625000 },
4715 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_oxsemi_1_15625000 },
4718 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_oxsemi_1_15625000 },
4721 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_oxsemi_1_15625000 },
4724 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_oxsemi_1_15625000 },
4727 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_oxsemi_1_15625000 },
4730 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_oxsemi_1_15625000 },
4733 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_oxsemi_1_15625000 },
4736 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_15625000 },
4739 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_1_15625000 },
4742 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_1_15625000 },
4745 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_1_15625000 },
4748 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_1_15625000 },
4751 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_oxsemi_1_15625000 },
4754 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_oxsemi_1_15625000 },
4757 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_oxsemi_1_15625000 },
4760 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_oxsemi_1_15625000 },
4763 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_oxsemi_1_15625000 },
4766 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_oxsemi_1_15625000 },
4769 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_oxsemi_1_15625000 },
4772 /*
4773 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4774 */
4775 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4776 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4777 pbn_oxsemi_1_15625000 },
4778 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4779 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4780 pbn_oxsemi_2_15625000 },
4781 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4782 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4783 pbn_oxsemi_4_15625000 },
4784 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4785 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4786 pbn_oxsemi_8_15625000 },
4787
4788 /*
4789 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4790 */
4791 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4792 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4793 pbn_oxsemi_2_15625000 },
4794 /*
4795 * EndRun Technologies. PCI express device range.
4796 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4797 */
4798 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_oxsemi_2_15625000 },
4801
4802 /*
4803 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4804 * from skokodyn@yahoo.com
4805 */
4806 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4807 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4808 pbn_sbsxrsio },
4809 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4810 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4811 pbn_sbsxrsio },
4812 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4813 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4814 pbn_sbsxrsio },
4815 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4816 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4817 pbn_sbsxrsio },
4818
4819 /*
4820 * Digitan DS560-558, from jimd@esoft.com
4821 */
4822 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824 pbn_b1_1_115200 },
4825
4826 /*
4827 * Titan Electronic cards
4828 * The 400L and 800L have a custom setup quirk.
4829 */
4830 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_b0_1_921600 },
4833 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 pbn_b0_2_921600 },
4836 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 pbn_b0_4_921600 },
4839 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 pbn_b0_4_921600 },
4842 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844 pbn_b1_1_921600 },
4845 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_b1_bt_2_921600 },
4848 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850 pbn_b0_bt_4_921600 },
4851 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_b0_bt_8_921600 },
4854 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856 pbn_b4_bt_2_921600 },
4857 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_b4_bt_4_921600 },
4860 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b4_bt_8_921600 },
4863 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865 pbn_b0_4_921600 },
4866 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_b0_4_921600 },
4869 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871 pbn_b0_4_921600 },
4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 pbn_titan_1_4000000 },
4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 pbn_titan_2_4000000 },
4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 pbn_titan_4_4000000 },
4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 pbn_titan_8_4000000 },
4884 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_titan_2_4000000 },
4887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_titan_2_4000000 },
4890 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_b0_bt_2_921600 },
4893 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_4_921600 },
4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_4_921600 },
4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b0_4_921600 },
4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b0_4_921600 },
4905
4906 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b2_1_460800 },
4909 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b2_1_460800 },
4912 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_b2_1_460800 },
4915 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_b2_bt_2_921600 },
4918 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_b2_bt_2_921600 },
4921 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b2_bt_2_921600 },
4924 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b2_bt_4_921600 },
4927 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_b2_bt_4_921600 },
4930 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_b2_bt_4_921600 },
4933 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_1_921600 },
4936 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b0_1_921600 },
4939 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b0_1_921600 },
4942 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b0_bt_2_921600 },
4945 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b0_bt_2_921600 },
4948 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b0_bt_2_921600 },
4951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b0_bt_4_921600 },
4954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b0_bt_4_921600 },
4957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b0_bt_4_921600 },
4960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b0_bt_8_921600 },
4963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b0_bt_8_921600 },
4966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b0_bt_8_921600 },
4969
4970 /*
4971 * Computone devices submitted by Doug McNash dmcnash@computone.com
4972 */
4973 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4974 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4975 0, 0, pbn_computone_4 },
4976 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4977 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4978 0, 0, pbn_computone_8 },
4979 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4980 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4981 0, 0, pbn_computone_6 },
4982
4983 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_oxsemi },
4986 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4987 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4988 pbn_b0_bt_1_921600 },
4989
4990 /*
4991 * Sunix PCI serial boards
4992 */
4993 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4994 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4995 pbn_sunix_pci_1s },
4996 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4997 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4998 pbn_sunix_pci_2s },
4999 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5000 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5001 pbn_sunix_pci_4s },
5002 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5003 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5004 pbn_sunix_pci_4s },
5005 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5006 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5007 pbn_sunix_pci_8s },
5008 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5009 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5010 pbn_sunix_pci_8s },
5011 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5012 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5013 pbn_sunix_pci_16s },
5014
5015 /*
5016 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5017 */
5018 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_b0_bt_8_115200 },
5021 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_b0_bt_8_115200 },
5024
5025 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 pbn_b0_bt_2_115200 },
5028 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5030 pbn_b0_bt_2_115200 },
5031 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5033 pbn_b0_bt_2_115200 },
5034 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5036 pbn_b0_bt_4_460800 },
5037 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5039 pbn_b0_bt_4_460800 },
5040 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5042 pbn_b0_bt_2_460800 },
5043 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5045 pbn_b0_bt_2_460800 },
5046 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5048 pbn_b0_bt_2_460800 },
5049 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5051 pbn_b0_bt_1_115200 },
5052 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5054 pbn_b0_bt_1_460800 },
5055
5056 /*
5057 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5058 * Cards are identified by their subsystem vendor IDs, which
5059 * (in hex) match the model number.
5060 *
5061 * Note that JC140x are RS422/485 cards which require ox950
5062 * ACR = 0x10, and as such are not currently fully supported.
5063 */
5064 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5065 0x1204, 0x0004, 0, 0,
5066 pbn_b0_4_921600 },
5067 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5068 0x1208, 0x0004, 0, 0,
5069 pbn_b0_4_921600 },
5070 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5071 0x1402, 0x0002, 0, 0,
5072 pbn_b0_2_921600 }, */
5073 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5074 0x1404, 0x0004, 0, 0,
5075 pbn_b0_4_921600 }, */
5076 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5077 0x1208, 0x0004, 0, 0,
5078 pbn_b0_4_921600 },
5079
5080 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5081 0x1204, 0x0004, 0, 0,
5082 pbn_b0_4_921600 },
5083 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5084 0x1208, 0x0004, 0, 0,
5085 pbn_b0_4_921600 },
5086 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5087 0x1208, 0x0004, 0, 0,
5088 pbn_b0_4_921600 },
5089 /*
5090 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5091 */
5092 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_b1_1_1382400 },
5095
5096 /*
5097 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5098 */
5099 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101 pbn_b1_1_1382400 },
5102
5103 /*
5104 * RAStel 2 port modem, gerg@moreton.com.au
5105 */
5106 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5108 pbn_b2_bt_2_115200 },
5109
5110 /*
5111 * EKF addition for i960 Boards form EKF with serial port
5112 */
5113 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5114 0xE4BF, PCI_ANY_ID, 0, 0,
5115 pbn_intel_i960 },
5116
5117 /*
5118 * Xircom Cardbus/Ethernet combos
5119 */
5120 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5122 pbn_b0_1_115200 },
5123 /*
5124 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5125 */
5126 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5128 pbn_b0_1_115200 },
5129
5130 /*
5131 * Untested PCI modems, sent in from various folks...
5132 */
5133
5134 /*
5135 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5136 */
5137 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5138 0x1048, 0x1500, 0, 0,
5139 pbn_b1_1_115200 },
5140
5141 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5142 0xFF00, 0, 0, 0,
5143 pbn_sgi_ioc3 },
5144
5145 /*
5146 * HP Diva card
5147 */
5148 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5149 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5150 pbn_b1_1_115200 },
5151 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153 pbn_b0_5_115200 },
5154 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5156 pbn_b2_1_115200 },
5157 /* HPE PCI serial device */
5158 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 pbn_b1_1_115200 },
5161
5162 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164 pbn_b3_2_115200 },
5165 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5167 pbn_b3_4_115200 },
5168 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5170 pbn_b3_8_115200 },
5171 /*
5172 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5173 */
5174 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5176 pbn_b0_1_115200 },
5177 /*
5178 * ITE
5179 */
5180 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5181 PCI_ANY_ID, PCI_ANY_ID,
5182 0, 0,
5183 pbn_b1_bt_1_115200 },
5184
5185 /*
5186 * IntaShield IS-100
5187 */
5188 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5190 pbn_b2_1_115200 },
5191 /*
5192 * IntaShield IS-200
5193 */
5194 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5196 pbn_b2_2_115200 },
5197 /*
5198 * IntaShield IS-400
5199 */
5200 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5202 pbn_b2_4_115200 },
5203 /*
5204 * IntaShield IX-100
5205 */
5206 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5207 PCI_ANY_ID, PCI_ANY_ID,
5208 0, 0,
5209 pbn_oxsemi_1_15625000 },
5210 /*
5211 * IntaShield IX-200
5212 */
5213 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5214 PCI_ANY_ID, PCI_ANY_ID,
5215 0, 0,
5216 pbn_oxsemi_2_15625000 },
5217 /*
5218 * IntaShield IX-400
5219 */
5220 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5221 PCI_ANY_ID, PCI_ANY_ID,
5222 0, 0,
5223 pbn_oxsemi_4_15625000 },
5224 /* Brainboxes Devices */
5225 /*
5226 * Brainboxes UC-101
5227 */
5228 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5229 PCI_ANY_ID, PCI_ANY_ID,
5230 0, 0,
5231 pbn_b2_2_115200 },
5232 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5233 PCI_ANY_ID, PCI_ANY_ID,
5234 0, 0,
5235 pbn_b2_2_115200 },
5236 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5237 PCI_ANY_ID, PCI_ANY_ID,
5238 0, 0,
5239 pbn_b2_2_115200 },
5240 /*
5241 * Brainboxes UC-235/246
5242 */
5243 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5244 PCI_ANY_ID, PCI_ANY_ID,
5245 0, 0,
5246 pbn_b2_1_115200 },
5247 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5248 PCI_ANY_ID, PCI_ANY_ID,
5249 0, 0,
5250 pbn_b2_1_115200 },
5251 /*
5252 * Brainboxes UC-253/UC-734
5253 */
5254 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5255 PCI_ANY_ID, PCI_ANY_ID,
5256 0, 0,
5257 pbn_b2_2_115200 },
5258 /*
5259 * Brainboxes UC-260/271/701/756
5260 */
5261 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5262 PCI_ANY_ID, PCI_ANY_ID,
5263 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5264 pbn_b2_4_115200 },
5265 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5266 PCI_ANY_ID, PCI_ANY_ID,
5267 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5268 pbn_b2_4_115200 },
5269 /*
5270 * Brainboxes UC-268
5271 */
5272 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5273 PCI_ANY_ID, PCI_ANY_ID,
5274 0, 0,
5275 pbn_b2_4_115200 },
5276 /*
5277 * Brainboxes UC-275/279
5278 */
5279 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5280 PCI_ANY_ID, PCI_ANY_ID,
5281 0, 0,
5282 pbn_b2_8_115200 },
5283 /*
5284 * Brainboxes UC-302
5285 */
5286 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5287 PCI_ANY_ID, PCI_ANY_ID,
5288 0, 0,
5289 pbn_b2_2_115200 },
5290 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5291 PCI_ANY_ID, PCI_ANY_ID,
5292 0, 0,
5293 pbn_b2_2_115200 },
5294 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5295 PCI_ANY_ID, PCI_ANY_ID,
5296 0, 0,
5297 pbn_b2_2_115200 },
5298 /*
5299 * Brainboxes UC-310
5300 */
5301 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5302 PCI_ANY_ID, PCI_ANY_ID,
5303 0, 0,
5304 pbn_b2_2_115200 },
5305 /*
5306 * Brainboxes UC-313
5307 */
5308 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5309 PCI_ANY_ID, PCI_ANY_ID,
5310 0, 0,
5311 pbn_b2_2_115200 },
5312 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5313 PCI_ANY_ID, PCI_ANY_ID,
5314 0, 0,
5315 pbn_b2_2_115200 },
5316 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5317 PCI_ANY_ID, PCI_ANY_ID,
5318 0, 0,
5319 pbn_b2_2_115200 },
5320 /*
5321 * Brainboxes UC-320/324
5322 */
5323 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5324 PCI_ANY_ID, PCI_ANY_ID,
5325 0, 0,
5326 pbn_b2_1_115200 },
5327 /*
5328 * Brainboxes UC-346
5329 */
5330 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5331 PCI_ANY_ID, PCI_ANY_ID,
5332 0, 0,
5333 pbn_b2_4_115200 },
5334 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5335 PCI_ANY_ID, PCI_ANY_ID,
5336 0, 0,
5337 pbn_b2_4_115200 },
5338 /*
5339 * Brainboxes UC-357
5340 */
5341 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5342 PCI_ANY_ID, PCI_ANY_ID,
5343 0, 0,
5344 pbn_b2_2_115200 },
5345 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5346 PCI_ANY_ID, PCI_ANY_ID,
5347 0, 0,
5348 pbn_b2_2_115200 },
5349 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5350 PCI_ANY_ID, PCI_ANY_ID,
5351 0, 0,
5352 pbn_b2_2_115200 },
5353 /*
5354 * Brainboxes UC-368
5355 */
5356 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 0, 0,
5359 pbn_b2_4_115200 },
5360 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5361 PCI_ANY_ID, PCI_ANY_ID,
5362 0, 0,
5363 pbn_b2_4_115200 },
5364 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5365 PCI_ANY_ID, PCI_ANY_ID,
5366 0, 0,
5367 pbn_b2_4_115200 },
5368 /*
5369 * Brainboxes UC-420
5370 */
5371 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5372 PCI_ANY_ID, PCI_ANY_ID,
5373 0, 0,
5374 pbn_b2_4_115200 },
5375 /*
5376 * Brainboxes UC-607
5377 */
5378 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5379 PCI_ANY_ID, PCI_ANY_ID,
5380 0, 0,
5381 pbn_b2_2_115200 },
5382 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5383 PCI_ANY_ID, PCI_ANY_ID,
5384 0, 0,
5385 pbn_b2_2_115200 },
5386 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5387 PCI_ANY_ID, PCI_ANY_ID,
5388 0, 0,
5389 pbn_b2_2_115200 },
5390 /*
5391 * Brainboxes UC-836
5392 */
5393 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5394 PCI_ANY_ID, PCI_ANY_ID,
5395 0, 0,
5396 pbn_b2_4_115200 },
5397 /*
5398 * Brainboxes UP-189
5399 */
5400 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5401 PCI_ANY_ID, PCI_ANY_ID,
5402 0, 0,
5403 pbn_b2_2_115200 },
5404 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5405 PCI_ANY_ID, PCI_ANY_ID,
5406 0, 0,
5407 pbn_b2_2_115200 },
5408 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5409 PCI_ANY_ID, PCI_ANY_ID,
5410 0, 0,
5411 pbn_b2_2_115200 },
5412 /*
5413 * Brainboxes UP-200
5414 */
5415 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5416 PCI_ANY_ID, PCI_ANY_ID,
5417 0, 0,
5418 pbn_b2_2_115200 },
5419 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5420 PCI_ANY_ID, PCI_ANY_ID,
5421 0, 0,
5422 pbn_b2_2_115200 },
5423 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5424 PCI_ANY_ID, PCI_ANY_ID,
5425 0, 0,
5426 pbn_b2_2_115200 },
5427 /*
5428 * Brainboxes UP-869
5429 */
5430 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5431 PCI_ANY_ID, PCI_ANY_ID,
5432 0, 0,
5433 pbn_b2_2_115200 },
5434 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5435 PCI_ANY_ID, PCI_ANY_ID,
5436 0, 0,
5437 pbn_b2_2_115200 },
5438 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5439 PCI_ANY_ID, PCI_ANY_ID,
5440 0, 0,
5441 pbn_b2_2_115200 },
5442 /*
5443 * Brainboxes UP-880
5444 */
5445 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5446 PCI_ANY_ID, PCI_ANY_ID,
5447 0, 0,
5448 pbn_b2_2_115200 },
5449 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5450 PCI_ANY_ID, PCI_ANY_ID,
5451 0, 0,
5452 pbn_b2_2_115200 },
5453 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5454 PCI_ANY_ID, PCI_ANY_ID,
5455 0, 0,
5456 pbn_b2_2_115200 },
5457 /*
5458 * Brainboxes PX-101
5459 */
5460 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5461 PCI_ANY_ID, PCI_ANY_ID,
5462 0, 0,
5463 pbn_b0_2_115200 },
5464 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5465 PCI_ANY_ID, PCI_ANY_ID,
5466 0, 0,
5467 pbn_oxsemi_2_15625000 },
5468 /*
5469 * Brainboxes PX-235/246
5470 */
5471 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5472 PCI_ANY_ID, PCI_ANY_ID,
5473 0, 0,
5474 pbn_b0_1_115200 },
5475 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5476 PCI_ANY_ID, PCI_ANY_ID,
5477 0, 0,
5478 pbn_oxsemi_1_15625000 },
5479 /*
5480 * Brainboxes PX-203/PX-257
5481 */
5482 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5483 PCI_ANY_ID, PCI_ANY_ID,
5484 0, 0,
5485 pbn_b0_2_115200 },
5486 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5487 PCI_ANY_ID, PCI_ANY_ID,
5488 0, 0,
5489 pbn_oxsemi_2_15625000 },
5490 /*
5491 * Brainboxes PX-260/PX-701
5492 */
5493 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5494 PCI_ANY_ID, PCI_ANY_ID,
5495 0, 0,
5496 pbn_oxsemi_4_15625000 },
5497 /*
5498 * Brainboxes PX-275/279
5499 */
5500 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5501 PCI_ANY_ID, PCI_ANY_ID,
5502 0, 0,
5503 pbn_b2_8_115200 },
5504 /*
5505 * Brainboxes PX-310
5506 */
5507 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5508 PCI_ANY_ID, PCI_ANY_ID,
5509 0, 0,
5510 pbn_oxsemi_2_15625000 },
5511 /*
5512 * Brainboxes PX-313
5513 */
5514 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5515 PCI_ANY_ID, PCI_ANY_ID,
5516 0, 0,
5517 pbn_oxsemi_2_15625000 },
5518 /*
5519 * Brainboxes PX-320/324/PX-376/PX-387
5520 */
5521 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5522 PCI_ANY_ID, PCI_ANY_ID,
5523 0, 0,
5524 pbn_oxsemi_1_15625000 },
5525 /*
5526 * Brainboxes PX-335/346
5527 */
5528 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5529 PCI_ANY_ID, PCI_ANY_ID,
5530 0, 0,
5531 pbn_oxsemi_4_15625000 },
5532 /*
5533 * Brainboxes PX-368
5534 */
5535 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5536 PCI_ANY_ID, PCI_ANY_ID,
5537 0, 0,
5538 pbn_oxsemi_4_15625000 },
5539 /*
5540 * Brainboxes PX-420
5541 */
5542 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5543 PCI_ANY_ID, PCI_ANY_ID,
5544 0, 0,
5545 pbn_b0_4_115200 },
5546 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5547 PCI_ANY_ID, PCI_ANY_ID,
5548 0, 0,
5549 pbn_oxsemi_4_15625000 },
5550 /*
5551 * Brainboxes PX-475
5552 */
5553 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5554 PCI_ANY_ID, PCI_ANY_ID,
5555 0, 0,
5556 pbn_oxsemi_1_15625000 },
5557 /*
5558 * Brainboxes PX-803/PX-857
5559 */
5560 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5561 PCI_ANY_ID, PCI_ANY_ID,
5562 0, 0,
5563 pbn_b0_2_115200 },
5564 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5565 PCI_ANY_ID, PCI_ANY_ID,
5566 0, 0,
5567 pbn_oxsemi_2_15625000 },
5568 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5569 PCI_ANY_ID, PCI_ANY_ID,
5570 0, 0,
5571 pbn_oxsemi_2_15625000 },
5572 /*
5573 * Brainboxes PX-820
5574 */
5575 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5576 PCI_ANY_ID, PCI_ANY_ID,
5577 0, 0,
5578 pbn_b0_4_115200 },
5579 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5580 PCI_ANY_ID, PCI_ANY_ID,
5581 0, 0,
5582 pbn_oxsemi_4_15625000 },
5583 /*
5584 * Brainboxes PX-835/PX-846
5585 */
5586 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5587 PCI_ANY_ID, PCI_ANY_ID,
5588 0, 0,
5589 pbn_b0_1_115200 },
5590 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5591 PCI_ANY_ID, PCI_ANY_ID,
5592 0, 0,
5593 pbn_oxsemi_1_15625000 },
5594 /*
5595 * Brainboxes XC-235
5596 */
5597 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5598 PCI_ANY_ID, PCI_ANY_ID,
5599 0, 0,
5600 pbn_oxsemi_1_15625000 },
5601 /*
5602 * Brainboxes XC-475
5603 */
5604 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5605 PCI_ANY_ID, PCI_ANY_ID,
5606 0, 0,
5607 pbn_oxsemi_1_15625000 },
5608
5609 /*
5610 * Perle PCI-RAS cards
5611 */
5612 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5613 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5614 0, 0, pbn_b2_4_921600 },
5615 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5616 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5617 0, 0, pbn_b2_8_921600 },
5618
5619 /*
5620 * Mainpine series cards: Fairly standard layout but fools
5621 * parts of the autodetect in some cases and uses otherwise
5622 * unmatched communications subclasses in the PCI Express case
5623 */
5624
5625 { /* RockForceDUO */
5626 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5627 PCI_VENDOR_ID_MAINPINE, 0x0200,
5628 0, 0, pbn_b0_2_115200 },
5629 { /* RockForceQUATRO */
5630 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5631 PCI_VENDOR_ID_MAINPINE, 0x0300,
5632 0, 0, pbn_b0_4_115200 },
5633 { /* RockForceDUO+ */
5634 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5635 PCI_VENDOR_ID_MAINPINE, 0x0400,
5636 0, 0, pbn_b0_2_115200 },
5637 { /* RockForceQUATRO+ */
5638 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5639 PCI_VENDOR_ID_MAINPINE, 0x0500,
5640 0, 0, pbn_b0_4_115200 },
5641 { /* RockForce+ */
5642 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5643 PCI_VENDOR_ID_MAINPINE, 0x0600,
5644 0, 0, pbn_b0_2_115200 },
5645 { /* RockForce+ */
5646 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5647 PCI_VENDOR_ID_MAINPINE, 0x0700,
5648 0, 0, pbn_b0_4_115200 },
5649 { /* RockForceOCTO+ */
5650 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5651 PCI_VENDOR_ID_MAINPINE, 0x0800,
5652 0, 0, pbn_b0_8_115200 },
5653 { /* RockForceDUO+ */
5654 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5655 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5656 0, 0, pbn_b0_2_115200 },
5657 { /* RockForceQUARTRO+ */
5658 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5659 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5660 0, 0, pbn_b0_4_115200 },
5661 { /* RockForceOCTO+ */
5662 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5663 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5664 0, 0, pbn_b0_8_115200 },
5665 { /* RockForceD1 */
5666 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5667 PCI_VENDOR_ID_MAINPINE, 0x2000,
5668 0, 0, pbn_b0_1_115200 },
5669 { /* RockForceF1 */
5670 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5671 PCI_VENDOR_ID_MAINPINE, 0x2100,
5672 0, 0, pbn_b0_1_115200 },
5673 { /* RockForceD2 */
5674 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5675 PCI_VENDOR_ID_MAINPINE, 0x2200,
5676 0, 0, pbn_b0_2_115200 },
5677 { /* RockForceF2 */
5678 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5679 PCI_VENDOR_ID_MAINPINE, 0x2300,
5680 0, 0, pbn_b0_2_115200 },
5681 { /* RockForceD4 */
5682 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5683 PCI_VENDOR_ID_MAINPINE, 0x2400,
5684 0, 0, pbn_b0_4_115200 },
5685 { /* RockForceF4 */
5686 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5687 PCI_VENDOR_ID_MAINPINE, 0x2500,
5688 0, 0, pbn_b0_4_115200 },
5689 { /* RockForceD8 */
5690 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5691 PCI_VENDOR_ID_MAINPINE, 0x2600,
5692 0, 0, pbn_b0_8_115200 },
5693 { /* RockForceF8 */
5694 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5695 PCI_VENDOR_ID_MAINPINE, 0x2700,
5696 0, 0, pbn_b0_8_115200 },
5697 { /* IQ Express D1 */
5698 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5699 PCI_VENDOR_ID_MAINPINE, 0x3000,
5700 0, 0, pbn_b0_1_115200 },
5701 { /* IQ Express F1 */
5702 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5703 PCI_VENDOR_ID_MAINPINE, 0x3100,
5704 0, 0, pbn_b0_1_115200 },
5705 { /* IQ Express D2 */
5706 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5707 PCI_VENDOR_ID_MAINPINE, 0x3200,
5708 0, 0, pbn_b0_2_115200 },
5709 { /* IQ Express F2 */
5710 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5711 PCI_VENDOR_ID_MAINPINE, 0x3300,
5712 0, 0, pbn_b0_2_115200 },
5713 { /* IQ Express D4 */
5714 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5715 PCI_VENDOR_ID_MAINPINE, 0x3400,
5716 0, 0, pbn_b0_4_115200 },
5717 { /* IQ Express F4 */
5718 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5719 PCI_VENDOR_ID_MAINPINE, 0x3500,
5720 0, 0, pbn_b0_4_115200 },
5721 { /* IQ Express D8 */
5722 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5723 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5724 0, 0, pbn_b0_8_115200 },
5725 { /* IQ Express F8 */
5726 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5727 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5728 0, 0, pbn_b0_8_115200 },
5729
5730
5731 /*
5732 * PA Semi PA6T-1682M on-chip UART
5733 */
5734 { PCI_VENDOR_ID_PASEMI, 0xa004,
5735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5736 pbn_pasemi_1682M },
5737
5738 /*
5739 * National Instruments
5740 */
5741 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5743 pbn_b1_16_115200 },
5744 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5746 pbn_b1_8_115200 },
5747 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5749 pbn_b1_bt_4_115200 },
5750 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5752 pbn_b1_bt_2_115200 },
5753 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5755 pbn_b1_bt_4_115200 },
5756 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5758 pbn_b1_bt_2_115200 },
5759 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5761 pbn_b1_16_115200 },
5762 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5764 pbn_b1_8_115200 },
5765 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5767 pbn_b1_bt_4_115200 },
5768 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5770 pbn_b1_bt_2_115200 },
5771 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5773 pbn_b1_bt_4_115200 },
5774 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5776 pbn_b1_bt_2_115200 },
5777 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5779 pbn_ni8430_2 },
5780 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5782 pbn_ni8430_2 },
5783 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5785 pbn_ni8430_4 },
5786 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5788 pbn_ni8430_4 },
5789 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5791 pbn_ni8430_8 },
5792 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5794 pbn_ni8430_8 },
5795 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5797 pbn_ni8430_16 },
5798 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5800 pbn_ni8430_16 },
5801 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5803 pbn_ni8430_2 },
5804 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5806 pbn_ni8430_2 },
5807 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5809 pbn_ni8430_4 },
5810 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5812 pbn_ni8430_4 },
5813
5814 /*
5815 * MOXA
5816 */
5817 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5818 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5819 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5820 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5821 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5822 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5823 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5824 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5825 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5826 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5827 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5828 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5829 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5830 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5831 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5832 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5833 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5834 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5835
5836 /*
5837 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5838 */
5839 { PCI_VENDOR_ID_ADDIDATA,
5840 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5841 PCI_ANY_ID,
5842 PCI_ANY_ID,
5843 0,
5844 0,
5845 pbn_b0_4_115200 },
5846
5847 { PCI_VENDOR_ID_ADDIDATA,
5848 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5849 PCI_ANY_ID,
5850 PCI_ANY_ID,
5851 0,
5852 0,
5853 pbn_b0_2_115200 },
5854
5855 { PCI_VENDOR_ID_ADDIDATA,
5856 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5857 PCI_ANY_ID,
5858 PCI_ANY_ID,
5859 0,
5860 0,
5861 pbn_b0_1_115200 },
5862
5863 { PCI_VENDOR_ID_AMCC,
5864 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5865 PCI_ANY_ID,
5866 PCI_ANY_ID,
5867 0,
5868 0,
5869 pbn_b1_8_115200 },
5870
5871 { PCI_VENDOR_ID_ADDIDATA,
5872 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5873 PCI_ANY_ID,
5874 PCI_ANY_ID,
5875 0,
5876 0,
5877 pbn_b0_4_115200 },
5878
5879 { PCI_VENDOR_ID_ADDIDATA,
5880 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5881 PCI_ANY_ID,
5882 PCI_ANY_ID,
5883 0,
5884 0,
5885 pbn_b0_2_115200 },
5886
5887 { PCI_VENDOR_ID_ADDIDATA,
5888 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5889 PCI_ANY_ID,
5890 PCI_ANY_ID,
5891 0,
5892 0,
5893 pbn_b0_1_115200 },
5894
5895 { PCI_VENDOR_ID_ADDIDATA,
5896 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5897 PCI_ANY_ID,
5898 PCI_ANY_ID,
5899 0,
5900 0,
5901 pbn_b0_4_115200 },
5902
5903 { PCI_VENDOR_ID_ADDIDATA,
5904 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5905 PCI_ANY_ID,
5906 PCI_ANY_ID,
5907 0,
5908 0,
5909 pbn_b0_2_115200 },
5910
5911 { PCI_VENDOR_ID_ADDIDATA,
5912 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5913 PCI_ANY_ID,
5914 PCI_ANY_ID,
5915 0,
5916 0,
5917 pbn_b0_1_115200 },
5918
5919 { PCI_VENDOR_ID_ADDIDATA,
5920 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5921 PCI_ANY_ID,
5922 PCI_ANY_ID,
5923 0,
5924 0,
5925 pbn_b0_8_115200 },
5926
5927 { PCI_VENDOR_ID_ADDIDATA,
5928 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5929 PCI_ANY_ID,
5930 PCI_ANY_ID,
5931 0,
5932 0,
5933 pbn_ADDIDATA_PCIe_4_3906250 },
5934
5935 { PCI_VENDOR_ID_ADDIDATA,
5936 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5937 PCI_ANY_ID,
5938 PCI_ANY_ID,
5939 0,
5940 0,
5941 pbn_ADDIDATA_PCIe_2_3906250 },
5942
5943 { PCI_VENDOR_ID_ADDIDATA,
5944 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5945 PCI_ANY_ID,
5946 PCI_ANY_ID,
5947 0,
5948 0,
5949 pbn_ADDIDATA_PCIe_1_3906250 },
5950
5951 { PCI_VENDOR_ID_ADDIDATA,
5952 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5953 PCI_ANY_ID,
5954 PCI_ANY_ID,
5955 0,
5956 0,
5957 pbn_ADDIDATA_PCIe_8_3906250 },
5958
5959 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5960 PCI_VENDOR_ID_IBM, 0x0299,
5961 0, 0, pbn_b0_bt_2_115200 },
5962
5963 /*
5964 * other NetMos 9835 devices are most likely handled by the
5965 * parport_serial driver, check drivers/parport/parport_serial.c
5966 * before adding them here.
5967 */
5968
5969 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5970 0xA000, 0x1000,
5971 0, 0, pbn_b0_1_115200 },
5972
5973 /* the 9901 is a rebranded 9912 */
5974 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5975 0xA000, 0x1000,
5976 0, 0, pbn_b0_1_115200 },
5977
5978 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5979 0xA000, 0x1000,
5980 0, 0, pbn_b0_1_115200 },
5981
5982 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5983 0xA000, 0x1000,
5984 0, 0, pbn_b0_1_115200 },
5985
5986 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5987 0xA000, 0x1000,
5988 0, 0, pbn_b0_1_115200 },
5989
5990 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5991 0xA000, 0x3002,
5992 0, 0, pbn_NETMOS9900_2s_115200 },
5993
5994 /*
5995 * Best Connectivity and Rosewill PCI Multi I/O cards
5996 */
5997
5998 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5999 0xA000, 0x1000,
6000 0, 0, pbn_b0_1_115200 },
6001
6002 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6003 0xA000, 0x3002,
6004 0, 0, pbn_b0_bt_2_115200 },
6005
6006 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6007 0xA000, 0x3004,
6008 0, 0, pbn_b0_bt_4_115200 },
6009
6010 /*
6011 * ASIX AX99100 PCIe to Multi I/O Controller
6012 */
6013 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6014 0xA000, 0x1000,
6015 0, 0, pbn_b0_1_115200 },
6016
6017 /* Intel CE4100 */
6018 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6020 pbn_ce4100_1_115200 },
6021
6022 /*
6023 * Cronyx Omega PCI
6024 */
6025 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6027 pbn_omegapci },
6028
6029 /*
6030 * Broadcom TruManage
6031 */
6032 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6034 pbn_brcm_trumanage },
6035
6036 /*
6037 * AgeStar as-prs2-009
6038 */
6039 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6040 PCI_ANY_ID, PCI_ANY_ID,
6041 0, 0, pbn_b0_bt_2_115200 },
6042
6043 /*
6044 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6045 * so not listed here.
6046 */
6047 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
6048 PCI_ANY_ID, PCI_ANY_ID,
6049 0, 0, pbn_b0_bt_4_115200 },
6050
6051 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
6052 PCI_ANY_ID, PCI_ANY_ID,
6053 0, 0, pbn_b0_bt_2_115200 },
6054
6055 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
6056 PCI_ANY_ID, PCI_ANY_ID,
6057 0, 0, pbn_b0_bt_4_115200 },
6058
6059 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
6060 PCI_ANY_ID, PCI_ANY_ID,
6061 0, 0, pbn_wch382_2 },
6062
6063 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
6064 PCI_ANY_ID, PCI_ANY_ID,
6065 0, 0, pbn_wch384_4 },
6066
6067 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
6068 PCI_ANY_ID, PCI_ANY_ID,
6069 0, 0, pbn_wch384_8 },
6070 /*
6071 * Realtek RealManage
6072 */
6073 { PCI_VENDOR_ID_REALTEK, 0x816a,
6074 PCI_ANY_ID, PCI_ANY_ID,
6075 0, 0, pbn_b0_1_115200 },
6076
6077 { PCI_VENDOR_ID_REALTEK, 0x816b,
6078 PCI_ANY_ID, PCI_ANY_ID,
6079 0, 0, pbn_b0_1_115200 },
6080
6081 /* Fintek PCI serial cards */
6082 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6083 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6084 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6085 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6086 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6087 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6088
6089 /* MKS Tenta SCOM-080x serial cards */
6090 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6091 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6092
6093 /* Amazon PCI serial device */
6094 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6095
6096 /*
6097 * These entries match devices with class COMMUNICATION_SERIAL,
6098 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6099 */
6100 { PCI_ANY_ID, PCI_ANY_ID,
6101 PCI_ANY_ID, PCI_ANY_ID,
6102 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6103 0xffff00, pbn_default },
6104 { PCI_ANY_ID, PCI_ANY_ID,
6105 PCI_ANY_ID, PCI_ANY_ID,
6106 PCI_CLASS_COMMUNICATION_MODEM << 8,
6107 0xffff00, pbn_default },
6108 { PCI_ANY_ID, PCI_ANY_ID,
6109 PCI_ANY_ID, PCI_ANY_ID,
6110 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6111 0xffff00, pbn_default },
6112 { 0, }
6113 };
6114
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6115 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6116 pci_channel_state_t state)
6117 {
6118 struct serial_private *priv = pci_get_drvdata(dev);
6119
6120 if (state == pci_channel_io_perm_failure)
6121 return PCI_ERS_RESULT_DISCONNECT;
6122
6123 if (priv)
6124 pciserial_detach_ports(priv);
6125
6126 pci_disable_device(dev);
6127
6128 return PCI_ERS_RESULT_NEED_RESET;
6129 }
6130
serial8250_io_slot_reset(struct pci_dev * dev)6131 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6132 {
6133 int rc;
6134
6135 rc = pci_enable_device(dev);
6136
6137 if (rc)
6138 return PCI_ERS_RESULT_DISCONNECT;
6139
6140 pci_restore_state(dev);
6141 pci_save_state(dev);
6142
6143 return PCI_ERS_RESULT_RECOVERED;
6144 }
6145
serial8250_io_resume(struct pci_dev * dev)6146 static void serial8250_io_resume(struct pci_dev *dev)
6147 {
6148 struct serial_private *priv = pci_get_drvdata(dev);
6149 struct serial_private *new;
6150
6151 if (!priv)
6152 return;
6153
6154 new = pciserial_init_ports(dev, priv->board);
6155 if (!IS_ERR(new)) {
6156 pci_set_drvdata(dev, new);
6157 kfree(priv);
6158 }
6159 }
6160
6161 static const struct pci_error_handlers serial8250_err_handler = {
6162 .error_detected = serial8250_io_error_detected,
6163 .slot_reset = serial8250_io_slot_reset,
6164 .resume = serial8250_io_resume,
6165 };
6166
6167 static struct pci_driver serial_pci_driver = {
6168 .name = "serial",
6169 .probe = pciserial_init_one,
6170 .remove = pciserial_remove_one,
6171 .driver = {
6172 .pm = &pciserial_pm_ops,
6173 },
6174 .id_table = serial_pci_tbl,
6175 .err_handler = &serial8250_err_handler,
6176 };
6177
6178 module_pci_driver(serial_pci_driver);
6179
6180 MODULE_LICENSE("GPL");
6181 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6182 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6183 MODULE_IMPORT_NS(SERIAL_8250_PCI);
6184