1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/circ_buf.h>
12 #include <linux/module.h>
13 #include <linux/ioport.h>
14 #include <linux/init.h>
15 #include <linux/console.h>
16 #include <linux/sysrq.h>
17 #include <linux/platform_device.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/ktime.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/rational.h>
27 #include <linux/slab.h>
28 #include <linux/of.h>
29 #include <linux/io.h>
30 #include <linux/iopoll.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/irq.h>
34 #include <linux/dma/imx-dma.h>
35
36 #include "serial_mctrl_gpio.h"
37
38 /* Register definitions */
39 #define URXD0 0x0 /* Receiver Register */
40 #define URTX0 0x40 /* Transmitter Register */
41 #define UCR1 0x80 /* Control Register 1 */
42 #define UCR2 0x84 /* Control Register 2 */
43 #define UCR3 0x88 /* Control Register 3 */
44 #define UCR4 0x8c /* Control Register 4 */
45 #define UFCR 0x90 /* FIFO Control Register */
46 #define USR1 0x94 /* Status Register 1 */
47 #define USR2 0x98 /* Status Register 2 */
48 #define UESC 0x9c /* Escape Character Register */
49 #define UTIM 0xa0 /* Escape Timer Register */
50 #define UBIR 0xa4 /* BRM Incremental Register */
51 #define UBMR 0xa8 /* BRM Modulator Register */
52 #define UBRC 0xac /* Baud Rate Count Register */
53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57 /* UART Control Register Bit Fields.*/
58 #define URXD_DUMMY_READ (1<<16)
59 #define URXD_CHARRDY (1<<15)
60 #define URXD_ERR (1<<14)
61 #define URXD_OVRRUN (1<<13)
62 #define URXD_FRMERR (1<<12)
63 #define URXD_BRK (1<<11)
64 #define URXD_PRERR (1<<10)
65 #define URXD_RX_DATA (0xFF<<0)
66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73 #define UCR1_IREN (1<<7) /* Infrared interface enable */
74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76 #define UCR1_SNDBRK (1<<4) /* Send break */
77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80 #define UCR1_DOZE (1<<1) /* Doze */
81 #define UCR1_UARTEN (1<<0) /* UART enabled */
82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84 #define UCR2_CTSC (1<<13) /* CTS pin control */
85 #define UCR2_CTS (1<<12) /* Clear to send */
86 #define UCR2_ESCEN (1<<11) /* Escape enable */
87 #define UCR2_PREN (1<<8) /* Parity enable */
88 #define UCR2_PROE (1<<7) /* Parity odd/even */
89 #define UCR2_STPB (1<<6) /* Stop */
90 #define UCR2_WS (1<<5) /* Word size */
91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
94 #define UCR2_RXEN (1<<1) /* Receiver enabled */
95 #define UCR2_SRST (1<<0) /* SW reset */
96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97 #define UCR3_PARERREN (1<<12) /* Parity enable */
98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99 #define UCR3_DSR (1<<10) /* Data set ready */
100 #define UCR3_DCD (1<<9) /* Data carrier detect */
101 #define UCR3_RI (1<<8) /* Ring indicator */
102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR3_BPEN (1<<0) /* Preset registers enable */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117 #define UCR4_IRSC (1<<5) /* IR special case */
118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123 #define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
124 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
125 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
127 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
128 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
129 #define USR1_RTSS (1<<14) /* RTS pin status */
130 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
131 #define USR1_RTSD (1<<12) /* RTS delta */
132 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
133 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
134 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
135 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
136 #define USR1_DTRD (1<<7) /* DTR Delta */
137 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
138 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
139 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
140 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
141 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
142 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
143 #define USR2_IDLE (1<<12) /* Idle condition */
144 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
145 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
146 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
147 #define USR2_WAKE (1<<7) /* Wake */
148 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
149 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
150 #define USR2_TXDC (1<<3) /* Transmitter complete */
151 #define USR2_BRCD (1<<2) /* Break condition */
152 #define USR2_ORE (1<<1) /* Overrun error */
153 #define USR2_RDR (1<<0) /* Recv data ready */
154 #define UTS_FRCPERR (1<<13) /* Force parity error */
155 #define UTS_LOOP (1<<12) /* Loop tx and rx */
156 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
157 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
158 #define UTS_TXFULL (1<<4) /* TxFIFO full */
159 #define UTS_RXFULL (1<<3) /* RxFIFO full */
160 #define UTS_SOFTRST (1<<0) /* Software reset */
161
162 /* We've been assigned a range on the "Low-density serial ports" major */
163 #define SERIAL_IMX_MAJOR 207
164 #define MINOR_START 16
165 #define DEV_NAME "ttymxc"
166
167 /*
168 * This determines how often we check the modem status signals
169 * for any change. They generally aren't connected to an IRQ
170 * so we have to poll them. We also check immediately before
171 * filling the TX fifo incase CTS has been dropped.
172 */
173 #define MCTRL_TIMEOUT (250*HZ/1000)
174
175 #define DRIVER_NAME "IMX-uart"
176
177 #define UART_NR 8
178
179 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
180 enum imx_uart_type {
181 IMX1_UART,
182 IMX21_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* counter to stop 0xff flood */
214 int idle_counter;
215
216 /* DMA fields */
217 unsigned int dma_is_enabled:1;
218 unsigned int dma_is_rxing:1;
219 unsigned int dma_is_txing:1;
220 struct dma_chan *dma_chan_rx, *dma_chan_tx;
221 struct scatterlist rx_sgl, tx_sgl[2];
222 void *rx_buf;
223 struct circ_buf rx_ring;
224 unsigned int rx_buf_size;
225 unsigned int rx_period_length;
226 unsigned int rx_periods;
227 dma_cookie_t rx_cookie;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 unsigned int saved_reg[10];
231 bool context_saved;
232
233 enum imx_tx_state tx_state;
234 struct hrtimer trigger_start_tx;
235 struct hrtimer trigger_stop_tx;
236 unsigned int rxtl;
237 };
238
239 struct imx_port_ucrs {
240 unsigned int ucr1;
241 unsigned int ucr2;
242 unsigned int ucr3;
243 };
244
245 static const struct imx_uart_data imx_uart_imx1_devdata = {
246 .uts_reg = IMX1_UTS,
247 .devtype = IMX1_UART,
248 };
249
250 static const struct imx_uart_data imx_uart_imx21_devdata = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 };
254
255 static const struct of_device_id imx_uart_dt_ids[] = {
256 /*
257 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
258 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
259 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
260 * doesn't make any distinction between these two variants.
261 */
262 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
263 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
264 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
265 { /* sentinel */ }
266 };
267 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
268
to_imx_port(struct uart_port * port)269 static inline struct imx_port *to_imx_port(struct uart_port *port)
270 {
271 return container_of(port, struct imx_port, port);
272 }
273
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)274 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
275 {
276 writel(val, sport->port.membase + offset);
277 }
278
imx_uart_readl(struct imx_port * sport,u32 offset)279 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
280 {
281 return readl(sport->port.membase + offset);
282 }
283
imx_uart_uts_reg(struct imx_port * sport)284 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
285 {
286 return sport->devdata->uts_reg;
287 }
288
imx_uart_is_imx1(struct imx_port * sport)289 static inline int imx_uart_is_imx1(struct imx_port *sport)
290 {
291 return sport->devdata->devtype == IMX1_UART;
292 }
293
294 /*
295 * Save and restore functions for UCR1, UCR2 and UCR3 registers
296 */
297 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)298 static void imx_uart_ucrs_save(struct imx_port *sport,
299 struct imx_port_ucrs *ucr)
300 {
301 /* save control registers */
302 ucr->ucr1 = imx_uart_readl(sport, UCR1);
303 ucr->ucr2 = imx_uart_readl(sport, UCR2);
304 ucr->ucr3 = imx_uart_readl(sport, UCR3);
305 }
306
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)307 static void imx_uart_ucrs_restore(struct imx_port *sport,
308 struct imx_port_ucrs *ucr)
309 {
310 /* restore control registers */
311 imx_uart_writel(sport, ucr->ucr1, UCR1);
312 imx_uart_writel(sport, ucr->ucr2, UCR2);
313 imx_uart_writel(sport, ucr->ucr3, UCR3);
314 }
315 #endif
316
317 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)318 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
319 {
320 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
321
322 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
323 }
324
325 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)326 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
327 {
328 *ucr2 &= ~UCR2_CTSC;
329 *ucr2 |= UCR2_CTS;
330
331 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
332 }
333
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)334 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
335 {
336 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
337 }
338
339 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)340 static void imx_uart_soft_reset(struct imx_port *sport)
341 {
342 int i = 10;
343 u32 ucr2, ubir, ubmr, uts;
344
345 /*
346 * According to the Reference Manual description of the UART SRST bit:
347 *
348 * "Reset the transmit and receive state machines,
349 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
350 * and UTS[6-3]".
351 *
352 * We don't need to restore the old values from USR1, USR2, URXD and
353 * UTXD. UBRC is read only, so only save/restore the other three
354 * registers.
355 */
356 ubir = imx_uart_readl(sport, UBIR);
357 ubmr = imx_uart_readl(sport, UBMR);
358 uts = imx_uart_readl(sport, IMX21_UTS);
359
360 ucr2 = imx_uart_readl(sport, UCR2);
361 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
362
363 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
364 udelay(1);
365
366 /* Restore the registers */
367 imx_uart_writel(sport, ubir, UBIR);
368 imx_uart_writel(sport, ubmr, UBMR);
369 imx_uart_writel(sport, uts, IMX21_UTS);
370
371 sport->idle_counter = 0;
372 }
373
imx_uart_disable_loopback_rs485(struct imx_port * sport)374 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
375 {
376 unsigned int uts;
377
378 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
379 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
380 uts &= ~UTS_LOOP;
381 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
382 }
383
384 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)385 static void imx_uart_start_rx(struct uart_port *port)
386 {
387 struct imx_port *sport = to_imx_port(port);
388 unsigned int ucr1, ucr2;
389
390 ucr1 = imx_uart_readl(sport, UCR1);
391 ucr2 = imx_uart_readl(sport, UCR2);
392
393 ucr2 |= UCR2_RXEN;
394
395 if (sport->dma_is_enabled) {
396 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
397 } else {
398 ucr1 |= UCR1_RRDYEN;
399 ucr2 |= UCR2_ATEN;
400 }
401
402 /* Write UCR2 first as it includes RXEN */
403 imx_uart_writel(sport, ucr2, UCR2);
404 imx_uart_writel(sport, ucr1, UCR1);
405 imx_uart_disable_loopback_rs485(sport);
406 }
407
408 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)409 static void imx_uart_stop_tx(struct uart_port *port)
410 {
411 struct imx_port *sport = to_imx_port(port);
412 u32 ucr1, ucr4, usr2;
413
414 if (sport->tx_state == OFF)
415 return;
416
417 /*
418 * We are maybe in the SMP context, so if the DMA TX thread is running
419 * on other cpu, we have to wait for it to finish.
420 */
421 if (sport->dma_is_txing)
422 return;
423
424 ucr1 = imx_uart_readl(sport, UCR1);
425 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
426
427 ucr4 = imx_uart_readl(sport, UCR4);
428 usr2 = imx_uart_readl(sport, USR2);
429 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
430 /* The shifter is still busy, so retry once TC triggers */
431 return;
432 }
433
434 ucr4 &= ~UCR4_TCEN;
435 imx_uart_writel(sport, ucr4, UCR4);
436
437 /* in rs485 mode disable transmitter */
438 if (port->rs485.flags & SER_RS485_ENABLED) {
439 if (sport->tx_state == SEND) {
440 sport->tx_state = WAIT_AFTER_SEND;
441
442 if (port->rs485.delay_rts_after_send > 0) {
443 start_hrtimer_ms(&sport->trigger_stop_tx,
444 port->rs485.delay_rts_after_send);
445 return;
446 }
447
448 /* continue without any delay */
449 }
450
451 if (sport->tx_state == WAIT_AFTER_RTS ||
452 sport->tx_state == WAIT_AFTER_SEND) {
453 u32 ucr2;
454
455 hrtimer_try_to_cancel(&sport->trigger_start_tx);
456
457 ucr2 = imx_uart_readl(sport, UCR2);
458 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
459 imx_uart_rts_active(sport, &ucr2);
460 else
461 imx_uart_rts_inactive(sport, &ucr2);
462 imx_uart_writel(sport, ucr2, UCR2);
463
464 if (!port->rs485_rx_during_tx_gpio)
465 imx_uart_start_rx(port);
466
467 sport->tx_state = OFF;
468 }
469 } else {
470 sport->tx_state = OFF;
471 }
472 }
473
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)474 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
475 {
476 struct imx_port *sport = to_imx_port(port);
477 u32 ucr1, ucr2, ucr4, uts;
478
479 ucr1 = imx_uart_readl(sport, UCR1);
480 ucr2 = imx_uart_readl(sport, UCR2);
481 ucr4 = imx_uart_readl(sport, UCR4);
482
483 if (sport->dma_is_enabled) {
484 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
485 } else {
486 ucr1 &= ~UCR1_RRDYEN;
487 ucr2 &= ~UCR2_ATEN;
488 ucr4 &= ~UCR4_OREN;
489 }
490 imx_uart_writel(sport, ucr1, UCR1);
491 imx_uart_writel(sport, ucr4, UCR4);
492
493 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
494 if (port->rs485.flags & SER_RS485_ENABLED &&
495 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
496 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
497 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
498 uts |= UTS_LOOP;
499 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
500 ucr2 |= UCR2_RXEN;
501 } else {
502 ucr2 &= ~UCR2_RXEN;
503 }
504
505 imx_uart_writel(sport, ucr2, UCR2);
506 }
507
508 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)509 static void imx_uart_stop_rx(struct uart_port *port)
510 {
511 /*
512 * Stop RX and enable loopback in order to make sure RS485 bus
513 * is not blocked. Se comment in imx_uart_probe().
514 */
515 imx_uart_stop_rx_with_loopback_ctrl(port, true);
516 }
517
518 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)519 static void imx_uart_enable_ms(struct uart_port *port)
520 {
521 struct imx_port *sport = to_imx_port(port);
522
523 mod_timer(&sport->timer, jiffies);
524
525 mctrl_gpio_enable_ms(sport->gpios);
526 }
527
528 static void imx_uart_dma_tx(struct imx_port *sport);
529
530 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)531 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
532 {
533 struct tty_port *tport = &sport->port.state->port;
534 unsigned char c;
535
536 if (sport->port.x_char) {
537 /* Send next char */
538 imx_uart_writel(sport, sport->port.x_char, URTX0);
539 sport->port.icount.tx++;
540 sport->port.x_char = 0;
541 return;
542 }
543
544 if (kfifo_is_empty(&tport->xmit_fifo) ||
545 uart_tx_stopped(&sport->port)) {
546 imx_uart_stop_tx(&sport->port);
547 return;
548 }
549
550 if (sport->dma_is_enabled) {
551 u32 ucr1;
552 /*
553 * We've just sent a X-char Ensure the TX DMA is enabled
554 * and the TX IRQ is disabled.
555 **/
556 ucr1 = imx_uart_readl(sport, UCR1);
557 ucr1 &= ~UCR1_TRDYEN;
558 if (sport->dma_is_txing) {
559 ucr1 |= UCR1_TXDMAEN;
560 imx_uart_writel(sport, ucr1, UCR1);
561 } else {
562 imx_uart_writel(sport, ucr1, UCR1);
563 imx_uart_dma_tx(sport);
564 }
565
566 return;
567 }
568
569 while (!(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) &&
570 uart_fifo_get(&sport->port, &c))
571 imx_uart_writel(sport, c, URTX0);
572
573 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
574 uart_write_wakeup(&sport->port);
575
576 if (kfifo_is_empty(&tport->xmit_fifo))
577 imx_uart_stop_tx(&sport->port);
578 }
579
imx_uart_dma_tx_callback(void * data)580 static void imx_uart_dma_tx_callback(void *data)
581 {
582 struct imx_port *sport = data;
583 struct tty_port *tport = &sport->port.state->port;
584 struct scatterlist *sgl = &sport->tx_sgl[0];
585 unsigned long flags;
586 u32 ucr1;
587
588 uart_port_lock_irqsave(&sport->port, &flags);
589
590 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
591
592 ucr1 = imx_uart_readl(sport, UCR1);
593 ucr1 &= ~UCR1_TXDMAEN;
594 imx_uart_writel(sport, ucr1, UCR1);
595
596 uart_xmit_advance(&sport->port, sport->tx_bytes);
597
598 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
599
600 sport->dma_is_txing = 0;
601
602 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
603 uart_write_wakeup(&sport->port);
604
605 if (!kfifo_is_empty(&tport->xmit_fifo) &&
606 !uart_tx_stopped(&sport->port))
607 imx_uart_dma_tx(sport);
608 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
609 u32 ucr4 = imx_uart_readl(sport, UCR4);
610 ucr4 |= UCR4_TCEN;
611 imx_uart_writel(sport, ucr4, UCR4);
612 }
613
614 uart_port_unlock_irqrestore(&sport->port, flags);
615 }
616
617 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)618 static void imx_uart_dma_tx(struct imx_port *sport)
619 {
620 struct tty_port *tport = &sport->port.state->port;
621 struct scatterlist *sgl = sport->tx_sgl;
622 struct dma_async_tx_descriptor *desc;
623 struct dma_chan *chan = sport->dma_chan_tx;
624 struct device *dev = sport->port.dev;
625 u32 ucr1, ucr4;
626 int ret;
627
628 if (sport->dma_is_txing)
629 return;
630
631 ucr4 = imx_uart_readl(sport, UCR4);
632 ucr4 &= ~UCR4_TCEN;
633 imx_uart_writel(sport, ucr4, UCR4);
634
635 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl));
636 sport->tx_bytes = kfifo_len(&tport->xmit_fifo);
637 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl,
638 ARRAY_SIZE(sport->tx_sgl), sport->tx_bytes);
639
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
641 if (ret == 0) {
642 dev_err(dev, "DMA mapping error for TX.\n");
643 return;
644 }
645 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
647 if (!desc) {
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
649 DMA_TO_DEVICE);
650 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
651 return;
652 }
653 desc->callback = imx_uart_dma_tx_callback;
654 desc->callback_param = sport;
655
656 dev_dbg(dev, "TX: prepare to send %u bytes by DMA.\n", sport->tx_bytes);
657
658 ucr1 = imx_uart_readl(sport, UCR1);
659 ucr1 |= UCR1_TXDMAEN;
660 imx_uart_writel(sport, ucr1, UCR1);
661
662 /* fire it */
663 sport->dma_is_txing = 1;
664 dmaengine_submit(desc);
665 dma_async_issue_pending(chan);
666 return;
667 }
668
669 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)670 static void imx_uart_start_tx(struct uart_port *port)
671 {
672 struct imx_port *sport = to_imx_port(port);
673 struct tty_port *tport = &sport->port.state->port;
674 u32 ucr1;
675
676 if (!sport->port.x_char && kfifo_is_empty(&tport->xmit_fifo))
677 return;
678
679 /*
680 * We cannot simply do nothing here if sport->tx_state == SEND already
681 * because UCR1_TXMPTYEN might already have been cleared in
682 * imx_uart_stop_tx(), but tx_state is still SEND.
683 */
684
685 if (port->rs485.flags & SER_RS485_ENABLED) {
686 if (sport->tx_state == OFF) {
687 u32 ucr2 = imx_uart_readl(sport, UCR2);
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
689 imx_uart_rts_active(sport, &ucr2);
690 else
691 imx_uart_rts_inactive(sport, &ucr2);
692 imx_uart_writel(sport, ucr2, UCR2);
693
694 /*
695 * Since we are about to transmit we can not stop RX
696 * with loopback enabled because that will make our
697 * transmitted data being just looped to RX.
698 */
699 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
700 !port->rs485_rx_during_tx_gpio)
701 imx_uart_stop_rx_with_loopback_ctrl(port, false);
702
703 sport->tx_state = WAIT_AFTER_RTS;
704
705 if (port->rs485.delay_rts_before_send > 0) {
706 start_hrtimer_ms(&sport->trigger_start_tx,
707 port->rs485.delay_rts_before_send);
708 return;
709 }
710
711 /* continue without any delay */
712 }
713
714 if (sport->tx_state == WAIT_AFTER_SEND
715 || sport->tx_state == WAIT_AFTER_RTS) {
716
717 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
718
719 /*
720 * Enable transmitter and shifter empty irq only if DMA
721 * is off. In the DMA case this is done in the
722 * tx-callback.
723 */
724 if (!sport->dma_is_enabled) {
725 u32 ucr4 = imx_uart_readl(sport, UCR4);
726 ucr4 |= UCR4_TCEN;
727 imx_uart_writel(sport, ucr4, UCR4);
728 }
729
730 sport->tx_state = SEND;
731 }
732 } else {
733 sport->tx_state = SEND;
734 }
735
736 if (!sport->dma_is_enabled) {
737 ucr1 = imx_uart_readl(sport, UCR1);
738 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
739 }
740
741 if (sport->dma_is_enabled) {
742 if (sport->port.x_char) {
743 /* We have X-char to send, so enable TX IRQ and
744 * disable TX DMA to let TX interrupt to send X-char */
745 ucr1 = imx_uart_readl(sport, UCR1);
746 ucr1 &= ~UCR1_TXDMAEN;
747 ucr1 |= UCR1_TRDYEN;
748 imx_uart_writel(sport, ucr1, UCR1);
749 return;
750 }
751
752 if (!kfifo_is_empty(&tport->xmit_fifo) &&
753 !uart_tx_stopped(port))
754 imx_uart_dma_tx(sport);
755 return;
756 }
757 }
758
__imx_uart_rtsint(int irq,void * dev_id)759 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
760 {
761 struct imx_port *sport = dev_id;
762 u32 usr1;
763
764 imx_uart_writel(sport, USR1_RTSD, USR1);
765 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
766 /*
767 * Update sport->old_status here, so any follow-up calls to
768 * imx_uart_mctrl_check() will be able to recognize that RTS
769 * state changed since last imx_uart_mctrl_check() call.
770 *
771 * In case RTS has been detected as asserted here and later on
772 * deasserted by the time imx_uart_mctrl_check() was called,
773 * imx_uart_mctrl_check() can detect the RTS state change and
774 * trigger uart_handle_cts_change() to unblock the port for
775 * further TX transfers.
776 */
777 if (usr1 & USR1_RTSS)
778 sport->old_status |= TIOCM_CTS;
779 else
780 sport->old_status &= ~TIOCM_CTS;
781 uart_handle_cts_change(&sport->port, usr1);
782 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
783
784 return IRQ_HANDLED;
785 }
786
imx_uart_rtsint(int irq,void * dev_id)787 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
788 {
789 struct imx_port *sport = dev_id;
790 irqreturn_t ret;
791
792 uart_port_lock(&sport->port);
793
794 ret = __imx_uart_rtsint(irq, dev_id);
795
796 uart_port_unlock(&sport->port);
797
798 return ret;
799 }
800
imx_uart_txint(int irq,void * dev_id)801 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
802 {
803 struct imx_port *sport = dev_id;
804
805 uart_port_lock(&sport->port);
806 imx_uart_transmit_buffer(sport);
807 uart_port_unlock(&sport->port);
808 return IRQ_HANDLED;
809 }
810
811 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
812 * This is to be called from Rx ISRs only when some bytes were actually
813 * received.
814 *
815 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
816 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
817 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
818 * that is terminated by any activity on RxD line, or could be stopped by
819 * issuing soft reset to the UART (just stop/start of RX does not help). Note
820 * that what we do here is sending isolated start bit about 2.4 times shorter
821 * than it is to be on UART configured baud rate.
822 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)823 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
824 {
825 /* To detect hardware 0xff flood we monitor RxD line between RX
826 * interrupts to isolate "receiving" of char(s) with no activity
827 * on RxD line, that'd never happen on actual data transfers.
828 *
829 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
830 * race here if we clear USR2_WAKE when receiving of a char is in
831 * progress, so we might get RX interrupt later with USR2_WAKE bit
832 * cleared. Note though that as we don't try to clear USR2_WAKE when we
833 * detected no activity, this race may hide actual activity only once.
834 *
835 * Yet another case where receive interrupt may occur without RxD
836 * activity is expiration of aging timer, so we consider this as well.
837 *
838 * We use 'idle_counter' to ensure that we got at least so many RX
839 * interrupts without any detected activity on RxD line. 2 cases
840 * described plus 1 to be on the safe side gives us a margin of 3,
841 * below. In practice I was not able to produce a false positive to
842 * induce soft reset at regular data transfers even using 1 as the
843 * margin, so 3 is actually very strong.
844 *
845 * We count interrupts, not chars in 'idle-counter' for simplicity.
846 */
847
848 if (usr2 & USR2_WAKE) {
849 imx_uart_writel(sport, USR2_WAKE, USR2);
850 sport->idle_counter = 0;
851 } else if (++sport->idle_counter > 3) {
852 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
853 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
854 }
855 }
856
__imx_uart_rxint(int irq,void * dev_id)857 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
858 {
859 struct imx_port *sport = dev_id;
860 struct tty_port *port = &sport->port.state->port;
861 u32 usr2, rx;
862
863 /* If we received something, check for 0xff flood */
864 usr2 = imx_uart_readl(sport, USR2);
865 if (usr2 & USR2_RDR)
866 imx_uart_check_flood(sport, usr2);
867
868 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
869 unsigned int flg = TTY_NORMAL;
870 sport->port.icount.rx++;
871
872 if (unlikely(rx & URXD_ERR)) {
873 if (rx & URXD_BRK) {
874 sport->port.icount.brk++;
875 if (uart_handle_break(&sport->port))
876 continue;
877 }
878 else if (rx & URXD_PRERR)
879 sport->port.icount.parity++;
880 else if (rx & URXD_FRMERR)
881 sport->port.icount.frame++;
882 if (rx & URXD_OVRRUN)
883 sport->port.icount.overrun++;
884
885 if (rx & sport->port.ignore_status_mask)
886 continue;
887
888 rx &= (sport->port.read_status_mask | 0xFF);
889
890 if (rx & URXD_BRK)
891 flg = TTY_BREAK;
892 else if (rx & URXD_PRERR)
893 flg = TTY_PARITY;
894 else if (rx & URXD_FRMERR)
895 flg = TTY_FRAME;
896 if (rx & URXD_OVRRUN)
897 flg = TTY_OVERRUN;
898
899 sport->port.sysrq = 0;
900 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
901 continue;
902 }
903
904 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
905 continue;
906
907 if (tty_insert_flip_char(port, rx, flg) == 0)
908 sport->port.icount.buf_overrun++;
909 }
910
911 tty_flip_buffer_push(port);
912
913 return IRQ_HANDLED;
914 }
915
imx_uart_rxint(int irq,void * dev_id)916 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
917 {
918 struct imx_port *sport = dev_id;
919 irqreturn_t ret;
920
921 uart_port_lock(&sport->port);
922
923 ret = __imx_uart_rxint(irq, dev_id);
924
925 uart_port_unlock(&sport->port);
926
927 return ret;
928 }
929
930 static void imx_uart_clear_rx_errors(struct imx_port *sport);
931
932 /*
933 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
934 */
imx_uart_get_hwmctrl(struct imx_port * sport)935 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
936 {
937 unsigned int tmp = TIOCM_DSR;
938 unsigned usr1 = imx_uart_readl(sport, USR1);
939 unsigned usr2 = imx_uart_readl(sport, USR2);
940
941 if (usr1 & USR1_RTSS)
942 tmp |= TIOCM_CTS;
943
944 /* in DCE mode DCDIN is always 0 */
945 if (!(usr2 & USR2_DCDIN))
946 tmp |= TIOCM_CAR;
947
948 if (sport->dte_mode)
949 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
950 tmp |= TIOCM_RI;
951
952 return tmp;
953 }
954
955 /*
956 * Handle any change of modem status signal since we were last called.
957 */
imx_uart_mctrl_check(struct imx_port * sport)958 static void imx_uart_mctrl_check(struct imx_port *sport)
959 {
960 unsigned int status, changed;
961
962 status = imx_uart_get_hwmctrl(sport);
963 changed = status ^ sport->old_status;
964
965 if (changed == 0)
966 return;
967
968 sport->old_status = status;
969
970 if (changed & TIOCM_RI && status & TIOCM_RI)
971 sport->port.icount.rng++;
972 if (changed & TIOCM_DSR)
973 sport->port.icount.dsr++;
974 if (changed & TIOCM_CAR)
975 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
976 if (changed & TIOCM_CTS)
977 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
978
979 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
980 }
981
imx_uart_int(int irq,void * dev_id)982 static irqreturn_t imx_uart_int(int irq, void *dev_id)
983 {
984 struct imx_port *sport = dev_id;
985 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
986 irqreturn_t ret = IRQ_NONE;
987
988 uart_port_lock(&sport->port);
989
990 usr1 = imx_uart_readl(sport, USR1);
991 usr2 = imx_uart_readl(sport, USR2);
992 ucr1 = imx_uart_readl(sport, UCR1);
993 ucr2 = imx_uart_readl(sport, UCR2);
994 ucr3 = imx_uart_readl(sport, UCR3);
995 ucr4 = imx_uart_readl(sport, UCR4);
996
997 /*
998 * Even if a condition is true that can trigger an irq only handle it if
999 * the respective irq source is enabled. This prevents some undesired
1000 * actions, for example if a character that sits in the RX FIFO and that
1001 * should be fetched via DMA is tried to be fetched using PIO. Or the
1002 * receiver is currently off and so reading from URXD0 results in an
1003 * exception. So just mask the (raw) status bits for disabled irqs.
1004 */
1005 if ((ucr1 & UCR1_RRDYEN) == 0)
1006 usr1 &= ~USR1_RRDY;
1007 if ((ucr2 & UCR2_ATEN) == 0)
1008 usr1 &= ~USR1_AGTIM;
1009 if ((ucr1 & UCR1_TRDYEN) == 0)
1010 usr1 &= ~USR1_TRDY;
1011 if ((ucr4 & UCR4_TCEN) == 0)
1012 usr2 &= ~USR2_TXDC;
1013 if ((ucr3 & UCR3_DTRDEN) == 0)
1014 usr1 &= ~USR1_DTRD;
1015 if ((ucr1 & UCR1_RTSDEN) == 0)
1016 usr1 &= ~USR1_RTSD;
1017 if ((ucr3 & UCR3_AWAKEN) == 0)
1018 usr1 &= ~USR1_AWAKE;
1019 if ((ucr4 & UCR4_OREN) == 0)
1020 usr2 &= ~USR2_ORE;
1021
1022 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1023 imx_uart_writel(sport, USR1_AGTIM, USR1);
1024
1025 __imx_uart_rxint(irq, dev_id);
1026 ret = IRQ_HANDLED;
1027 }
1028
1029 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1030 imx_uart_transmit_buffer(sport);
1031 ret = IRQ_HANDLED;
1032 }
1033
1034 if (usr1 & USR1_DTRD) {
1035 imx_uart_writel(sport, USR1_DTRD, USR1);
1036
1037 imx_uart_mctrl_check(sport);
1038
1039 ret = IRQ_HANDLED;
1040 }
1041
1042 if (usr1 & USR1_RTSD) {
1043 __imx_uart_rtsint(irq, dev_id);
1044 ret = IRQ_HANDLED;
1045 }
1046
1047 if (usr1 & USR1_AWAKE) {
1048 imx_uart_writel(sport, USR1_AWAKE, USR1);
1049 ret = IRQ_HANDLED;
1050 }
1051
1052 if (usr2 & USR2_ORE) {
1053 sport->port.icount.overrun++;
1054 imx_uart_writel(sport, USR2_ORE, USR2);
1055 ret = IRQ_HANDLED;
1056 }
1057
1058 uart_port_unlock(&sport->port);
1059
1060 return ret;
1061 }
1062
1063 /*
1064 * Return TIOCSER_TEMT when transmitter is not busy.
1065 */
imx_uart_tx_empty(struct uart_port * port)1066 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1067 {
1068 struct imx_port *sport = to_imx_port(port);
1069 unsigned int ret;
1070
1071 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1072
1073 /* If the TX DMA is working, return 0. */
1074 if (sport->dma_is_txing)
1075 ret = 0;
1076
1077 return ret;
1078 }
1079
1080 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1081 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1082 {
1083 struct imx_port *sport = to_imx_port(port);
1084 unsigned int ret = imx_uart_get_hwmctrl(sport);
1085
1086 mctrl_gpio_get(sport->gpios, &ret);
1087
1088 return ret;
1089 }
1090
1091 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1092 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1093 {
1094 struct imx_port *sport = to_imx_port(port);
1095 u32 ucr3, uts;
1096
1097 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1098 u32 ucr2;
1099
1100 /*
1101 * Turn off autoRTS if RTS is lowered and restore autoRTS
1102 * setting if RTS is raised.
1103 */
1104 ucr2 = imx_uart_readl(sport, UCR2);
1105 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1106 if (mctrl & TIOCM_RTS) {
1107 ucr2 |= UCR2_CTS;
1108 /*
1109 * UCR2_IRTS is unset if and only if the port is
1110 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1111 * to get the state to restore to.
1112 */
1113 if (!(ucr2 & UCR2_IRTS))
1114 ucr2 |= UCR2_CTSC;
1115 }
1116 imx_uart_writel(sport, ucr2, UCR2);
1117 }
1118
1119 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1120 if (!(mctrl & TIOCM_DTR))
1121 ucr3 |= UCR3_DSR;
1122 imx_uart_writel(sport, ucr3, UCR3);
1123
1124 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1125 if (mctrl & TIOCM_LOOP)
1126 uts |= UTS_LOOP;
1127 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1128
1129 mctrl_gpio_set(sport->gpios, mctrl);
1130 }
1131
1132 /*
1133 * Interrupts always disabled.
1134 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1135 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1136 {
1137 struct imx_port *sport = to_imx_port(port);
1138 unsigned long flags;
1139 u32 ucr1;
1140
1141 uart_port_lock_irqsave(&sport->port, &flags);
1142
1143 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1144
1145 if (break_state != 0)
1146 ucr1 |= UCR1_SNDBRK;
1147
1148 imx_uart_writel(sport, ucr1, UCR1);
1149
1150 uart_port_unlock_irqrestore(&sport->port, flags);
1151 }
1152
1153 /*
1154 * This is our per-port timeout handler, for checking the
1155 * modem status signals.
1156 */
imx_uart_timeout(struct timer_list * t)1157 static void imx_uart_timeout(struct timer_list *t)
1158 {
1159 struct imx_port *sport = from_timer(sport, t, timer);
1160 unsigned long flags;
1161
1162 if (sport->port.state) {
1163 uart_port_lock_irqsave(&sport->port, &flags);
1164 imx_uart_mctrl_check(sport);
1165 uart_port_unlock_irqrestore(&sport->port, flags);
1166
1167 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1168 }
1169 }
1170
1171 /*
1172 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1173 * [1] the RX DMA buffer is full.
1174 * [2] the aging timer expires
1175 *
1176 * Condition [2] is triggered when a character has been sitting in the FIFO
1177 * for at least 8 byte durations.
1178 */
imx_uart_dma_rx_callback(void * data)1179 static void imx_uart_dma_rx_callback(void *data)
1180 {
1181 struct imx_port *sport = data;
1182 struct dma_chan *chan = sport->dma_chan_rx;
1183 struct scatterlist *sgl = &sport->rx_sgl;
1184 struct tty_port *port = &sport->port.state->port;
1185 struct dma_tx_state state;
1186 struct circ_buf *rx_ring = &sport->rx_ring;
1187 enum dma_status status;
1188 unsigned int w_bytes = 0;
1189 unsigned int r_bytes;
1190 unsigned int bd_size;
1191
1192 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1193
1194 if (status == DMA_ERROR) {
1195 uart_port_lock(&sport->port);
1196 imx_uart_clear_rx_errors(sport);
1197 uart_port_unlock(&sport->port);
1198 return;
1199 }
1200
1201 /*
1202 * The state-residue variable represents the empty space
1203 * relative to the entire buffer. Taking this in consideration
1204 * the head is always calculated base on the buffer total
1205 * length - DMA transaction residue. The UART script from the
1206 * SDMA firmware will jump to the next buffer descriptor,
1207 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1208 * Taking this in consideration the tail is always at the
1209 * beginning of the buffer descriptor that contains the head.
1210 */
1211
1212 /* Calculate the head */
1213 rx_ring->head = sg_dma_len(sgl) - state.residue;
1214
1215 /* Calculate the tail. */
1216 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1217 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1218
1219 if (rx_ring->head <= sg_dma_len(sgl) &&
1220 rx_ring->head > rx_ring->tail) {
1221
1222 /* Move data from tail to head */
1223 r_bytes = rx_ring->head - rx_ring->tail;
1224
1225 /* If we received something, check for 0xff flood */
1226 uart_port_lock(&sport->port);
1227 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1228 uart_port_unlock(&sport->port);
1229
1230 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1231
1232 /* CPU claims ownership of RX DMA buffer */
1233 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1234 DMA_FROM_DEVICE);
1235
1236 w_bytes = tty_insert_flip_string(port,
1237 sport->rx_buf + rx_ring->tail, r_bytes);
1238
1239 /* UART retrieves ownership of RX DMA buffer */
1240 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1241 DMA_FROM_DEVICE);
1242
1243 if (w_bytes != r_bytes)
1244 sport->port.icount.buf_overrun++;
1245
1246 sport->port.icount.rx += w_bytes;
1247 }
1248 } else {
1249 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1250 WARN_ON(rx_ring->head <= rx_ring->tail);
1251 }
1252
1253 if (w_bytes) {
1254 tty_flip_buffer_push(port);
1255 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1256 }
1257 }
1258
imx_uart_start_rx_dma(struct imx_port * sport)1259 static int imx_uart_start_rx_dma(struct imx_port *sport)
1260 {
1261 struct scatterlist *sgl = &sport->rx_sgl;
1262 struct dma_chan *chan = sport->dma_chan_rx;
1263 struct device *dev = sport->port.dev;
1264 struct dma_async_tx_descriptor *desc;
1265 int ret;
1266
1267 sport->rx_ring.head = 0;
1268 sport->rx_ring.tail = 0;
1269
1270 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1271 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1272 if (ret == 0) {
1273 dev_err(dev, "DMA mapping error for RX.\n");
1274 return -EINVAL;
1275 }
1276
1277 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1278 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1279 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1280
1281 if (!desc) {
1282 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1283 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1284 return -EINVAL;
1285 }
1286 desc->callback = imx_uart_dma_rx_callback;
1287 desc->callback_param = sport;
1288
1289 dev_dbg(dev, "RX: prepare for the DMA.\n");
1290 sport->dma_is_rxing = 1;
1291 sport->rx_cookie = dmaengine_submit(desc);
1292 dma_async_issue_pending(chan);
1293 return 0;
1294 }
1295
imx_uart_clear_rx_errors(struct imx_port * sport)1296 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1297 {
1298 struct tty_port *port = &sport->port.state->port;
1299 u32 usr1, usr2;
1300
1301 usr1 = imx_uart_readl(sport, USR1);
1302 usr2 = imx_uart_readl(sport, USR2);
1303
1304 if (usr2 & USR2_BRCD) {
1305 sport->port.icount.brk++;
1306 imx_uart_writel(sport, USR2_BRCD, USR2);
1307 uart_handle_break(&sport->port);
1308 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1309 sport->port.icount.buf_overrun++;
1310 tty_flip_buffer_push(port);
1311 } else {
1312 if (usr1 & USR1_FRAMERR) {
1313 sport->port.icount.frame++;
1314 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1315 } else if (usr1 & USR1_PARITYERR) {
1316 sport->port.icount.parity++;
1317 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1318 }
1319 }
1320
1321 if (usr2 & USR2_ORE) {
1322 sport->port.icount.overrun++;
1323 imx_uart_writel(sport, USR2_ORE, USR2);
1324 }
1325
1326 sport->idle_counter = 0;
1327
1328 }
1329
1330 #define TXTL_DEFAULT 8
1331 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1332 #define RXTL_CONSOLE_DEFAULT 1
1333 #define TXTL_DMA 8 /* DMA burst setting */
1334 #define RXTL_DMA 9 /* DMA burst setting */
1335
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1336 static void imx_uart_setup_ufcr(struct imx_port *sport,
1337 unsigned char txwl, unsigned char rxwl)
1338 {
1339 unsigned int val;
1340
1341 /* set receiver / transmitter trigger level */
1342 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1343 val |= txwl << UFCR_TXTL_SHF | rxwl;
1344 imx_uart_writel(sport, val, UFCR);
1345 }
1346
imx_uart_dma_exit(struct imx_port * sport)1347 static void imx_uart_dma_exit(struct imx_port *sport)
1348 {
1349 if (sport->dma_chan_rx) {
1350 dmaengine_terminate_sync(sport->dma_chan_rx);
1351 dma_release_channel(sport->dma_chan_rx);
1352 sport->dma_chan_rx = NULL;
1353 sport->rx_cookie = -EINVAL;
1354 kfree(sport->rx_buf);
1355 sport->rx_buf = NULL;
1356 }
1357
1358 if (sport->dma_chan_tx) {
1359 dmaengine_terminate_sync(sport->dma_chan_tx);
1360 dma_release_channel(sport->dma_chan_tx);
1361 sport->dma_chan_tx = NULL;
1362 }
1363 }
1364
imx_uart_dma_init(struct imx_port * sport)1365 static int imx_uart_dma_init(struct imx_port *sport)
1366 {
1367 struct dma_slave_config slave_config = {};
1368 struct device *dev = sport->port.dev;
1369 struct dma_chan *chan;
1370 int ret;
1371
1372 /* Prepare for RX : */
1373 chan = dma_request_chan(dev, "rx");
1374 if (IS_ERR(chan)) {
1375 dev_dbg(dev, "cannot get the DMA channel.\n");
1376 sport->dma_chan_rx = NULL;
1377 ret = PTR_ERR(chan);
1378 goto err;
1379 }
1380 sport->dma_chan_rx = chan;
1381
1382 slave_config.direction = DMA_DEV_TO_MEM;
1383 slave_config.src_addr = sport->port.mapbase + URXD0;
1384 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1385 /* one byte less than the watermark level to enable the aging timer */
1386 slave_config.src_maxburst = RXTL_DMA - 1;
1387 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1388 if (ret) {
1389 dev_err(dev, "error in RX dma configuration.\n");
1390 goto err;
1391 }
1392
1393 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1394 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1395 if (!sport->rx_buf) {
1396 ret = -ENOMEM;
1397 goto err;
1398 }
1399 sport->rx_ring.buf = sport->rx_buf;
1400
1401 /* Prepare for TX : */
1402 chan = dma_request_chan(dev, "tx");
1403 if (IS_ERR(chan)) {
1404 dev_err(dev, "cannot get the TX DMA channel!\n");
1405 sport->dma_chan_tx = NULL;
1406 ret = PTR_ERR(chan);
1407 goto err;
1408 }
1409 sport->dma_chan_tx = chan;
1410
1411 slave_config.direction = DMA_MEM_TO_DEV;
1412 slave_config.dst_addr = sport->port.mapbase + URTX0;
1413 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1414 slave_config.dst_maxburst = TXTL_DMA;
1415 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1416 if (ret) {
1417 dev_err(dev, "error in TX dma configuration.");
1418 goto err;
1419 }
1420
1421 return 0;
1422 err:
1423 imx_uart_dma_exit(sport);
1424 return ret;
1425 }
1426
imx_uart_enable_dma(struct imx_port * sport)1427 static void imx_uart_enable_dma(struct imx_port *sport)
1428 {
1429 u32 ucr1;
1430
1431 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1432
1433 /* set UCR1 */
1434 ucr1 = imx_uart_readl(sport, UCR1);
1435 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1436 imx_uart_writel(sport, ucr1, UCR1);
1437
1438 sport->dma_is_enabled = 1;
1439 }
1440
imx_uart_disable_dma(struct imx_port * sport)1441 static void imx_uart_disable_dma(struct imx_port *sport)
1442 {
1443 u32 ucr1;
1444
1445 /* clear UCR1 */
1446 ucr1 = imx_uart_readl(sport, UCR1);
1447 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1448 imx_uart_writel(sport, ucr1, UCR1);
1449
1450 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1451
1452 sport->dma_is_enabled = 0;
1453 }
1454
1455 /* half the RX buffer size */
1456 #define CTSTL 16
1457
imx_uart_startup(struct uart_port * port)1458 static int imx_uart_startup(struct uart_port *port)
1459 {
1460 struct imx_port *sport = to_imx_port(port);
1461 int retval;
1462 unsigned long flags;
1463 int dma_is_inited = 0;
1464 u32 ucr1, ucr2, ucr3, ucr4;
1465
1466 retval = clk_prepare_enable(sport->clk_per);
1467 if (retval)
1468 return retval;
1469 retval = clk_prepare_enable(sport->clk_ipg);
1470 if (retval) {
1471 clk_disable_unprepare(sport->clk_per);
1472 return retval;
1473 }
1474
1475 if (uart_console(&sport->port))
1476 sport->rxtl = RXTL_CONSOLE_DEFAULT;
1477 else
1478 sport->rxtl = RXTL_DEFAULT;
1479
1480 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1481
1482 /* disable the DREN bit (Data Ready interrupt enable) before
1483 * requesting IRQs
1484 */
1485 ucr4 = imx_uart_readl(sport, UCR4);
1486
1487 /* set the trigger level for CTS */
1488 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1489 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1490
1491 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1492
1493 /* Can we enable the DMA support? */
1494 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1495 lockdep_set_subclass(&port->lock, 1);
1496 dma_is_inited = 1;
1497 }
1498
1499 uart_port_lock_irqsave(&sport->port, &flags);
1500
1501 /* Reset fifo's and state machines */
1502 imx_uart_soft_reset(sport);
1503
1504 /*
1505 * Finally, clear and enable interrupts
1506 */
1507 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1508 imx_uart_writel(sport, USR2_ORE, USR2);
1509
1510 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1511 ucr1 |= UCR1_UARTEN;
1512 if (sport->have_rtscts)
1513 ucr1 |= UCR1_RTSDEN;
1514
1515 imx_uart_writel(sport, ucr1, UCR1);
1516
1517 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1518 if (!dma_is_inited)
1519 ucr4 |= UCR4_OREN;
1520 if (sport->inverted_rx)
1521 ucr4 |= UCR4_INVR;
1522 imx_uart_writel(sport, ucr4, UCR4);
1523
1524 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1525 /*
1526 * configure tx polarity before enabling tx
1527 */
1528 if (sport->inverted_tx)
1529 ucr3 |= UCR3_INVT;
1530
1531 if (!imx_uart_is_imx1(sport)) {
1532 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1533
1534 if (sport->dte_mode)
1535 /* disable broken interrupts */
1536 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1537 }
1538 imx_uart_writel(sport, ucr3, UCR3);
1539
1540 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1541 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1542 if (!sport->have_rtscts)
1543 ucr2 |= UCR2_IRTS;
1544 /*
1545 * make sure the edge sensitive RTS-irq is disabled,
1546 * we're using RTSD instead.
1547 */
1548 if (!imx_uart_is_imx1(sport))
1549 ucr2 &= ~UCR2_RTSEN;
1550 imx_uart_writel(sport, ucr2, UCR2);
1551
1552 /*
1553 * Enable modem status interrupts
1554 */
1555 imx_uart_enable_ms(&sport->port);
1556
1557 if (dma_is_inited) {
1558 imx_uart_enable_dma(sport);
1559 imx_uart_start_rx_dma(sport);
1560 } else {
1561 ucr1 = imx_uart_readl(sport, UCR1);
1562 ucr1 |= UCR1_RRDYEN;
1563 imx_uart_writel(sport, ucr1, UCR1);
1564
1565 ucr2 = imx_uart_readl(sport, UCR2);
1566 ucr2 |= UCR2_ATEN;
1567 imx_uart_writel(sport, ucr2, UCR2);
1568 }
1569
1570 imx_uart_disable_loopback_rs485(sport);
1571
1572 uart_port_unlock_irqrestore(&sport->port, flags);
1573
1574 return 0;
1575 }
1576
imx_uart_shutdown(struct uart_port * port)1577 static void imx_uart_shutdown(struct uart_port *port)
1578 {
1579 struct imx_port *sport = to_imx_port(port);
1580 unsigned long flags;
1581 u32 ucr1, ucr2, ucr4, uts;
1582 int loops;
1583
1584 if (sport->dma_is_enabled) {
1585 dmaengine_terminate_sync(sport->dma_chan_tx);
1586 if (sport->dma_is_txing) {
1587 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1588 sport->dma_tx_nents, DMA_TO_DEVICE);
1589 sport->dma_is_txing = 0;
1590 }
1591 dmaengine_terminate_sync(sport->dma_chan_rx);
1592 if (sport->dma_is_rxing) {
1593 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1594 1, DMA_FROM_DEVICE);
1595 sport->dma_is_rxing = 0;
1596 }
1597
1598 uart_port_lock_irqsave(&sport->port, &flags);
1599 imx_uart_stop_tx(port);
1600 imx_uart_stop_rx(port);
1601 imx_uart_disable_dma(sport);
1602 uart_port_unlock_irqrestore(&sport->port, flags);
1603 imx_uart_dma_exit(sport);
1604 }
1605
1606 mctrl_gpio_disable_ms(sport->gpios);
1607
1608 uart_port_lock_irqsave(&sport->port, &flags);
1609 ucr2 = imx_uart_readl(sport, UCR2);
1610 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1611 imx_uart_writel(sport, ucr2, UCR2);
1612 uart_port_unlock_irqrestore(&sport->port, flags);
1613
1614 /*
1615 * Stop our timer.
1616 */
1617 del_timer_sync(&sport->timer);
1618
1619 /*
1620 * Disable all interrupts, port and break condition.
1621 */
1622
1623 uart_port_lock_irqsave(&sport->port, &flags);
1624
1625 ucr1 = imx_uart_readl(sport, UCR1);
1626 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1627 UCR1_ATDMAEN | UCR1_SNDBRK);
1628 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1629 if (port->rs485.flags & SER_RS485_ENABLED &&
1630 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1631 sport->have_rtscts && !sport->have_rtsgpio) {
1632 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1633 uts |= UTS_LOOP;
1634 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1635 ucr1 |= UCR1_UARTEN;
1636 } else {
1637 ucr1 &= ~UCR1_UARTEN;
1638 }
1639 imx_uart_writel(sport, ucr1, UCR1);
1640
1641 ucr4 = imx_uart_readl(sport, UCR4);
1642 ucr4 &= ~UCR4_TCEN;
1643 imx_uart_writel(sport, ucr4, UCR4);
1644
1645 /*
1646 * We have to ensure the tx state machine ends up in OFF. This
1647 * is especially important for rs485 where we must not leave
1648 * the RTS signal high, blocking the bus indefinitely.
1649 *
1650 * All interrupts are now disabled, so imx_uart_stop_tx() will
1651 * no longer be called from imx_uart_transmit_buffer(). It may
1652 * still be called via the hrtimers, and if those are in play,
1653 * we have to honour the delays.
1654 */
1655 if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1656 imx_uart_stop_tx(port);
1657
1658 /*
1659 * In many cases (rs232 mode, or if tx_state was
1660 * WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1661 * delay_rts_after_send), this will have moved directly to
1662 * OFF. In rs485 mode, tx_state might already have been
1663 * WAIT_AFTER_SEND and the hrtimer thus already started, or
1664 * the above imx_uart_stop_tx() call could have started it. In
1665 * those cases, we have to wait for the hrtimer to fire and
1666 * complete the transition to OFF.
1667 */
1668 loops = port->rs485.flags & SER_RS485_ENABLED ?
1669 port->rs485.delay_rts_after_send : 0;
1670 while (sport->tx_state != OFF && loops--) {
1671 uart_port_unlock_irqrestore(&sport->port, flags);
1672 msleep(1);
1673 uart_port_lock_irqsave(&sport->port, &flags);
1674 }
1675
1676 if (sport->tx_state != OFF) {
1677 dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1678 sport->tx_state);
1679 /*
1680 * This machine may be busted, but ensure the RTS
1681 * signal is inactive in order not to block other
1682 * devices.
1683 */
1684 if (port->rs485.flags & SER_RS485_ENABLED) {
1685 ucr2 = imx_uart_readl(sport, UCR2);
1686 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1687 imx_uart_rts_active(sport, &ucr2);
1688 else
1689 imx_uart_rts_inactive(sport, &ucr2);
1690 imx_uart_writel(sport, ucr2, UCR2);
1691 }
1692 sport->tx_state = OFF;
1693 }
1694
1695 uart_port_unlock_irqrestore(&sport->port, flags);
1696
1697 clk_disable_unprepare(sport->clk_per);
1698 clk_disable_unprepare(sport->clk_ipg);
1699 }
1700
1701 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1702 static void imx_uart_flush_buffer(struct uart_port *port)
1703 {
1704 struct imx_port *sport = to_imx_port(port);
1705 struct scatterlist *sgl = &sport->tx_sgl[0];
1706
1707 if (!sport->dma_chan_tx)
1708 return;
1709
1710 sport->tx_bytes = 0;
1711 dmaengine_terminate_all(sport->dma_chan_tx);
1712 if (sport->dma_is_txing) {
1713 u32 ucr1;
1714
1715 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1716 DMA_TO_DEVICE);
1717 ucr1 = imx_uart_readl(sport, UCR1);
1718 ucr1 &= ~UCR1_TXDMAEN;
1719 imx_uart_writel(sport, ucr1, UCR1);
1720 sport->dma_is_txing = 0;
1721 }
1722
1723 imx_uart_soft_reset(sport);
1724
1725 }
1726
1727 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1728 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1729 const struct ktermios *old)
1730 {
1731 struct imx_port *sport = to_imx_port(port);
1732 unsigned long flags;
1733 u32 ucr2, old_ucr2, ufcr;
1734 unsigned int baud, quot;
1735 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1736 unsigned long div;
1737 unsigned long num, denom, old_ubir, old_ubmr;
1738 uint64_t tdiv64;
1739
1740 /*
1741 * We only support CS7 and CS8.
1742 */
1743 while ((termios->c_cflag & CSIZE) != CS7 &&
1744 (termios->c_cflag & CSIZE) != CS8) {
1745 termios->c_cflag &= ~CSIZE;
1746 termios->c_cflag |= old_csize;
1747 old_csize = CS8;
1748 }
1749
1750 del_timer_sync(&sport->timer);
1751
1752 /*
1753 * Ask the core to calculate the divisor for us.
1754 */
1755 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1756 quot = uart_get_divisor(port, baud);
1757
1758 uart_port_lock_irqsave(&sport->port, &flags);
1759
1760 /*
1761 * Read current UCR2 and save it for future use, then clear all the bits
1762 * except those we will or may need to preserve.
1763 */
1764 old_ucr2 = imx_uart_readl(sport, UCR2);
1765 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1766
1767 ucr2 |= UCR2_SRST | UCR2_IRTS;
1768 if ((termios->c_cflag & CSIZE) == CS8)
1769 ucr2 |= UCR2_WS;
1770
1771 if (!sport->have_rtscts)
1772 termios->c_cflag &= ~CRTSCTS;
1773
1774 if (port->rs485.flags & SER_RS485_ENABLED) {
1775 /*
1776 * RTS is mandatory for rs485 operation, so keep
1777 * it under manual control and keep transmitter
1778 * disabled.
1779 */
1780 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1781 imx_uart_rts_active(sport, &ucr2);
1782 else
1783 imx_uart_rts_inactive(sport, &ucr2);
1784
1785 } else if (termios->c_cflag & CRTSCTS) {
1786 /*
1787 * Only let receiver control RTS output if we were not requested
1788 * to have RTS inactive (which then should take precedence).
1789 */
1790 if (ucr2 & UCR2_CTS)
1791 ucr2 |= UCR2_CTSC;
1792 }
1793
1794 if (termios->c_cflag & CRTSCTS)
1795 ucr2 &= ~UCR2_IRTS;
1796 if (termios->c_cflag & CSTOPB)
1797 ucr2 |= UCR2_STPB;
1798 if (termios->c_cflag & PARENB) {
1799 ucr2 |= UCR2_PREN;
1800 if (termios->c_cflag & PARODD)
1801 ucr2 |= UCR2_PROE;
1802 }
1803
1804 sport->port.read_status_mask = 0;
1805 if (termios->c_iflag & INPCK)
1806 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1807 if (termios->c_iflag & (BRKINT | PARMRK))
1808 sport->port.read_status_mask |= URXD_BRK;
1809
1810 /*
1811 * Characters to ignore
1812 */
1813 sport->port.ignore_status_mask = 0;
1814 if (termios->c_iflag & IGNPAR)
1815 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1816 if (termios->c_iflag & IGNBRK) {
1817 sport->port.ignore_status_mask |= URXD_BRK;
1818 /*
1819 * If we're ignoring parity and break indicators,
1820 * ignore overruns too (for real raw support).
1821 */
1822 if (termios->c_iflag & IGNPAR)
1823 sport->port.ignore_status_mask |= URXD_OVRRUN;
1824 }
1825
1826 if ((termios->c_cflag & CREAD) == 0)
1827 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1828
1829 /*
1830 * Update the per-port timeout.
1831 */
1832 uart_update_timeout(port, termios->c_cflag, baud);
1833
1834 /* custom-baudrate handling */
1835 div = sport->port.uartclk / (baud * 16);
1836 if (baud == 38400 && quot != div)
1837 baud = sport->port.uartclk / (quot * 16);
1838
1839 div = sport->port.uartclk / (baud * 16);
1840 if (div > 7)
1841 div = 7;
1842 if (!div)
1843 div = 1;
1844
1845 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1846 1 << 16, 1 << 16, &num, &denom);
1847
1848 tdiv64 = sport->port.uartclk;
1849 tdiv64 *= num;
1850 do_div(tdiv64, denom * 16 * div);
1851 tty_termios_encode_baud_rate(termios,
1852 (speed_t)tdiv64, (speed_t)tdiv64);
1853
1854 num -= 1;
1855 denom -= 1;
1856
1857 ufcr = imx_uart_readl(sport, UFCR);
1858 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1859 imx_uart_writel(sport, ufcr, UFCR);
1860
1861 /*
1862 * Two registers below should always be written both and in this
1863 * particular order. One consequence is that we need to check if any of
1864 * them changes and then update both. We do need the check for change
1865 * as even writing the same values seem to "restart"
1866 * transmission/receiving logic in the hardware, that leads to data
1867 * breakage even when rate doesn't in fact change. E.g., user switches
1868 * RTS/CTS handshake and suddenly gets broken bytes.
1869 */
1870 old_ubir = imx_uart_readl(sport, UBIR);
1871 old_ubmr = imx_uart_readl(sport, UBMR);
1872 if (old_ubir != num || old_ubmr != denom) {
1873 imx_uart_writel(sport, num, UBIR);
1874 imx_uart_writel(sport, denom, UBMR);
1875 }
1876
1877 if (!imx_uart_is_imx1(sport))
1878 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1879 IMX21_ONEMS);
1880
1881 imx_uart_writel(sport, ucr2, UCR2);
1882
1883 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1884 imx_uart_enable_ms(&sport->port);
1885
1886 uart_port_unlock_irqrestore(&sport->port, flags);
1887 }
1888
imx_uart_type(struct uart_port * port)1889 static const char *imx_uart_type(struct uart_port *port)
1890 {
1891 return port->type == PORT_IMX ? "IMX" : NULL;
1892 }
1893
1894 /*
1895 * Configure/autoconfigure the port.
1896 */
imx_uart_config_port(struct uart_port * port,int flags)1897 static void imx_uart_config_port(struct uart_port *port, int flags)
1898 {
1899 if (flags & UART_CONFIG_TYPE)
1900 port->type = PORT_IMX;
1901 }
1902
1903 /*
1904 * Verify the new serial_struct (for TIOCSSERIAL).
1905 * The only change we allow are to the flags and type, and
1906 * even then only between PORT_IMX and PORT_UNKNOWN
1907 */
1908 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1909 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1910 {
1911 int ret = 0;
1912
1913 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1914 ret = -EINVAL;
1915 if (port->irq != ser->irq)
1916 ret = -EINVAL;
1917 if (ser->io_type != UPIO_MEM)
1918 ret = -EINVAL;
1919 if (port->uartclk / 16 != ser->baud_base)
1920 ret = -EINVAL;
1921 if (port->mapbase != (unsigned long)ser->iomem_base)
1922 ret = -EINVAL;
1923 if (port->iobase != ser->port)
1924 ret = -EINVAL;
1925 if (ser->hub6 != 0)
1926 ret = -EINVAL;
1927 return ret;
1928 }
1929
1930 #if defined(CONFIG_CONSOLE_POLL)
1931
imx_uart_poll_init(struct uart_port * port)1932 static int imx_uart_poll_init(struct uart_port *port)
1933 {
1934 struct imx_port *sport = to_imx_port(port);
1935 unsigned long flags;
1936 u32 ucr1, ucr2;
1937 int retval;
1938
1939 retval = clk_prepare_enable(sport->clk_ipg);
1940 if (retval)
1941 return retval;
1942 retval = clk_prepare_enable(sport->clk_per);
1943 if (retval)
1944 clk_disable_unprepare(sport->clk_ipg);
1945
1946 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1947
1948 uart_port_lock_irqsave(&sport->port, &flags);
1949
1950 /*
1951 * Be careful about the order of enabling bits here. First enable the
1952 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1953 * This prevents that a character that already sits in the RX fifo is
1954 * triggering an irq but the try to fetch it from there results in an
1955 * exception because UARTEN or RXEN is still off.
1956 */
1957 ucr1 = imx_uart_readl(sport, UCR1);
1958 ucr2 = imx_uart_readl(sport, UCR2);
1959
1960 if (imx_uart_is_imx1(sport))
1961 ucr1 |= IMX1_UCR1_UARTCLKEN;
1962
1963 ucr1 |= UCR1_UARTEN;
1964 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1965
1966 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1967 ucr2 &= ~UCR2_ATEN;
1968
1969 imx_uart_writel(sport, ucr1, UCR1);
1970 imx_uart_writel(sport, ucr2, UCR2);
1971
1972 /* now enable irqs */
1973 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1974 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1975
1976 uart_port_unlock_irqrestore(&sport->port, flags);
1977
1978 return 0;
1979 }
1980
imx_uart_poll_get_char(struct uart_port * port)1981 static int imx_uart_poll_get_char(struct uart_port *port)
1982 {
1983 struct imx_port *sport = to_imx_port(port);
1984 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1985 return NO_POLL_CHAR;
1986
1987 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1988 }
1989
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1990 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1991 {
1992 struct imx_port *sport = to_imx_port(port);
1993 unsigned int status;
1994
1995 /* drain */
1996 do {
1997 status = imx_uart_readl(sport, USR1);
1998 } while (~status & USR1_TRDY);
1999
2000 /* write */
2001 imx_uart_writel(sport, c, URTX0);
2002
2003 /* flush */
2004 do {
2005 status = imx_uart_readl(sport, USR2);
2006 } while (~status & USR2_TXDC);
2007 }
2008 #endif
2009
2010 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)2011 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
2012 struct serial_rs485 *rs485conf)
2013 {
2014 struct imx_port *sport = to_imx_port(port);
2015 u32 ucr2, ufcr;
2016
2017 if (rs485conf->flags & SER_RS485_ENABLED) {
2018 /* Enable receiver if low-active RTS signal is requested */
2019 if (sport->have_rtscts && !sport->have_rtsgpio &&
2020 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
2021 rs485conf->flags |= SER_RS485_RX_DURING_TX;
2022
2023 /* disable transmitter */
2024 ucr2 = imx_uart_readl(sport, UCR2);
2025 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
2026 imx_uart_rts_active(sport, &ucr2);
2027 else
2028 imx_uart_rts_inactive(sport, &ucr2);
2029 imx_uart_writel(sport, ucr2, UCR2);
2030 }
2031
2032 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
2033 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2034 rs485conf->flags & SER_RS485_RX_DURING_TX) {
2035 /* If the receiver trigger is 0, set it to a default value */
2036 ufcr = imx_uart_readl(sport, UFCR);
2037 if ((ufcr & UFCR_RXTL_MASK) == 0)
2038 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2039 imx_uart_start_rx(port);
2040 }
2041
2042 return 0;
2043 }
2044
2045 static const struct uart_ops imx_uart_pops = {
2046 .tx_empty = imx_uart_tx_empty,
2047 .set_mctrl = imx_uart_set_mctrl,
2048 .get_mctrl = imx_uart_get_mctrl,
2049 .stop_tx = imx_uart_stop_tx,
2050 .start_tx = imx_uart_start_tx,
2051 .stop_rx = imx_uart_stop_rx,
2052 .enable_ms = imx_uart_enable_ms,
2053 .break_ctl = imx_uart_break_ctl,
2054 .startup = imx_uart_startup,
2055 .shutdown = imx_uart_shutdown,
2056 .flush_buffer = imx_uart_flush_buffer,
2057 .set_termios = imx_uart_set_termios,
2058 .type = imx_uart_type,
2059 .config_port = imx_uart_config_port,
2060 .verify_port = imx_uart_verify_port,
2061 #if defined(CONFIG_CONSOLE_POLL)
2062 .poll_init = imx_uart_poll_init,
2063 .poll_get_char = imx_uart_poll_get_char,
2064 .poll_put_char = imx_uart_poll_put_char,
2065 #endif
2066 };
2067
2068 static struct imx_port *imx_uart_ports[UART_NR];
2069
2070 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)2071 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2072 {
2073 struct imx_port *sport = to_imx_port(port);
2074
2075 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2076 barrier();
2077
2078 imx_uart_writel(sport, ch, URTX0);
2079 }
2080
2081 /*
2082 * Interrupts are disabled on entering
2083 */
2084 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2085 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2086 {
2087 struct imx_port *sport = imx_uart_ports[co->index];
2088 struct imx_port_ucrs old_ucr;
2089 unsigned long flags;
2090 unsigned int ucr1, usr2;
2091 int locked = 1;
2092
2093 if (sport->port.sysrq)
2094 locked = 0;
2095 else if (oops_in_progress)
2096 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2097 else
2098 uart_port_lock_irqsave(&sport->port, &flags);
2099
2100 /*
2101 * First, save UCR1/2/3 and then disable interrupts
2102 */
2103 imx_uart_ucrs_save(sport, &old_ucr);
2104 ucr1 = old_ucr.ucr1;
2105
2106 if (imx_uart_is_imx1(sport))
2107 ucr1 |= IMX1_UCR1_UARTCLKEN;
2108 ucr1 |= UCR1_UARTEN;
2109 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2110
2111 imx_uart_writel(sport, ucr1, UCR1);
2112
2113 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2114
2115 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2116
2117 /*
2118 * Finally, wait for transmitter to become empty
2119 * and restore UCR1/2/3
2120 */
2121 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2122 0, USEC_PER_SEC, false, sport, USR2);
2123 imx_uart_ucrs_restore(sport, &old_ucr);
2124
2125 if (locked)
2126 uart_port_unlock_irqrestore(&sport->port, flags);
2127 }
2128
2129 /*
2130 * If the port was already initialised (eg, by a boot loader),
2131 * try to determine the current setup.
2132 */
2133 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2134 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2135 int *parity, int *bits)
2136 {
2137
2138 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2139 /* ok, the port was enabled */
2140 unsigned int ucr2, ubir, ubmr, uartclk;
2141 unsigned int baud_raw;
2142 unsigned int ucfr_rfdiv;
2143
2144 ucr2 = imx_uart_readl(sport, UCR2);
2145
2146 *parity = 'n';
2147 if (ucr2 & UCR2_PREN) {
2148 if (ucr2 & UCR2_PROE)
2149 *parity = 'o';
2150 else
2151 *parity = 'e';
2152 }
2153
2154 if (ucr2 & UCR2_WS)
2155 *bits = 8;
2156 else
2157 *bits = 7;
2158
2159 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2160 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2161
2162 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2163 if (ucfr_rfdiv == 6)
2164 ucfr_rfdiv = 7;
2165 else
2166 ucfr_rfdiv = 6 - ucfr_rfdiv;
2167
2168 uartclk = clk_get_rate(sport->clk_per);
2169 uartclk /= ucfr_rfdiv;
2170
2171 { /*
2172 * The next code provides exact computation of
2173 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2174 * without need of float support or long long division,
2175 * which would be required to prevent 32bit arithmetic overflow
2176 */
2177 unsigned int mul = ubir + 1;
2178 unsigned int div = 16 * (ubmr + 1);
2179 unsigned int rem = uartclk % div;
2180
2181 baud_raw = (uartclk / div) * mul;
2182 baud_raw += (rem * mul + div / 2) / div;
2183 *baud = (baud_raw + 50) / 100 * 100;
2184 }
2185
2186 if (*baud != baud_raw)
2187 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2188 baud_raw, *baud);
2189 }
2190 }
2191
2192 static int
imx_uart_console_setup(struct console * co,char * options)2193 imx_uart_console_setup(struct console *co, char *options)
2194 {
2195 struct imx_port *sport;
2196 int baud = 9600;
2197 int bits = 8;
2198 int parity = 'n';
2199 int flow = 'n';
2200 int retval;
2201
2202 /*
2203 * Check whether an invalid uart number has been specified, and
2204 * if so, search for the first available port that does have
2205 * console support.
2206 */
2207 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2208 co->index = 0;
2209 sport = imx_uart_ports[co->index];
2210 if (sport == NULL)
2211 return -ENODEV;
2212
2213 /* For setting the registers, we only need to enable the ipg clock. */
2214 retval = clk_prepare_enable(sport->clk_ipg);
2215 if (retval)
2216 goto error_console;
2217
2218 if (options)
2219 uart_parse_options(options, &baud, &parity, &bits, &flow);
2220 else
2221 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2222
2223 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2224
2225 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2226
2227 if (retval) {
2228 clk_disable_unprepare(sport->clk_ipg);
2229 goto error_console;
2230 }
2231
2232 retval = clk_prepare_enable(sport->clk_per);
2233 if (retval)
2234 clk_disable_unprepare(sport->clk_ipg);
2235
2236 error_console:
2237 return retval;
2238 }
2239
2240 static int
imx_uart_console_exit(struct console * co)2241 imx_uart_console_exit(struct console *co)
2242 {
2243 struct imx_port *sport = imx_uart_ports[co->index];
2244
2245 clk_disable_unprepare(sport->clk_per);
2246 clk_disable_unprepare(sport->clk_ipg);
2247
2248 return 0;
2249 }
2250
2251 static struct uart_driver imx_uart_uart_driver;
2252 static struct console imx_uart_console = {
2253 .name = DEV_NAME,
2254 .write = imx_uart_console_write,
2255 .device = uart_console_device,
2256 .setup = imx_uart_console_setup,
2257 .exit = imx_uart_console_exit,
2258 .flags = CON_PRINTBUFFER,
2259 .index = -1,
2260 .data = &imx_uart_uart_driver,
2261 };
2262
2263 #define IMX_CONSOLE &imx_uart_console
2264
2265 #else
2266 #define IMX_CONSOLE NULL
2267 #endif
2268
2269 static struct uart_driver imx_uart_uart_driver = {
2270 .owner = THIS_MODULE,
2271 .driver_name = DRIVER_NAME,
2272 .dev_name = DEV_NAME,
2273 .major = SERIAL_IMX_MAJOR,
2274 .minor = MINOR_START,
2275 .nr = ARRAY_SIZE(imx_uart_ports),
2276 .cons = IMX_CONSOLE,
2277 };
2278
imx_trigger_start_tx(struct hrtimer * t)2279 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2280 {
2281 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2282 unsigned long flags;
2283
2284 uart_port_lock_irqsave(&sport->port, &flags);
2285 if (sport->tx_state == WAIT_AFTER_RTS)
2286 imx_uart_start_tx(&sport->port);
2287 uart_port_unlock_irqrestore(&sport->port, flags);
2288
2289 return HRTIMER_NORESTART;
2290 }
2291
imx_trigger_stop_tx(struct hrtimer * t)2292 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2293 {
2294 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2295 unsigned long flags;
2296
2297 uart_port_lock_irqsave(&sport->port, &flags);
2298 if (sport->tx_state == WAIT_AFTER_SEND)
2299 imx_uart_stop_tx(&sport->port);
2300 uart_port_unlock_irqrestore(&sport->port, flags);
2301
2302 return HRTIMER_NORESTART;
2303 }
2304
2305 static const struct serial_rs485 imx_rs485_supported = {
2306 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2307 SER_RS485_RX_DURING_TX,
2308 .delay_rts_before_send = 1,
2309 .delay_rts_after_send = 1,
2310 };
2311
2312 /* Default RX DMA buffer configuration */
2313 #define RX_DMA_PERIODS 16
2314 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2315
imx_uart_probe(struct platform_device * pdev)2316 static int imx_uart_probe(struct platform_device *pdev)
2317 {
2318 struct device_node *np = pdev->dev.of_node;
2319 struct imx_port *sport;
2320 void __iomem *base;
2321 u32 dma_buf_conf[2];
2322 int ret = 0;
2323 u32 ucr1, ucr2, uts;
2324 struct resource *res;
2325 int txirq, rxirq, rtsirq;
2326
2327 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2328 if (!sport)
2329 return -ENOMEM;
2330
2331 sport->devdata = of_device_get_match_data(&pdev->dev);
2332
2333 ret = of_alias_get_id(np, "serial");
2334 if (ret < 0) {
2335 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2336 return ret;
2337 }
2338 sport->port.line = ret;
2339
2340 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2341 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2342
2343 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2344
2345 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2346
2347 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2348
2349 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2350
2351 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2352 sport->rx_period_length = dma_buf_conf[0];
2353 sport->rx_periods = dma_buf_conf[1];
2354 } else {
2355 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2356 sport->rx_periods = RX_DMA_PERIODS;
2357 }
2358
2359 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2360 dev_err(&pdev->dev, "serial%d out of range\n",
2361 sport->port.line);
2362 return -EINVAL;
2363 }
2364
2365 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2366 if (IS_ERR(base))
2367 return PTR_ERR(base);
2368
2369 rxirq = platform_get_irq(pdev, 0);
2370 if (rxirq < 0)
2371 return rxirq;
2372 txirq = platform_get_irq_optional(pdev, 1);
2373 rtsirq = platform_get_irq_optional(pdev, 2);
2374
2375 sport->port.dev = &pdev->dev;
2376 sport->port.mapbase = res->start;
2377 sport->port.membase = base;
2378 sport->port.type = PORT_IMX;
2379 sport->port.iotype = UPIO_MEM;
2380 sport->port.irq = rxirq;
2381 sport->port.fifosize = 32;
2382 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2383 sport->port.ops = &imx_uart_pops;
2384 sport->port.rs485_config = imx_uart_rs485_config;
2385 /* RTS is required to control the RS485 transmitter */
2386 if (sport->have_rtscts || sport->have_rtsgpio)
2387 sport->port.rs485_supported = imx_rs485_supported;
2388 sport->port.flags = UPF_BOOT_AUTOCONF;
2389 timer_setup(&sport->timer, imx_uart_timeout, 0);
2390
2391 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2392 if (IS_ERR(sport->gpios))
2393 return PTR_ERR(sport->gpios);
2394
2395 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2396 if (IS_ERR(sport->clk_ipg)) {
2397 ret = PTR_ERR(sport->clk_ipg);
2398 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2399 return ret;
2400 }
2401
2402 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2403 if (IS_ERR(sport->clk_per)) {
2404 ret = PTR_ERR(sport->clk_per);
2405 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2406 return ret;
2407 }
2408
2409 sport->port.uartclk = clk_get_rate(sport->clk_per);
2410
2411 /* For register access, we only need to enable the ipg clock. */
2412 ret = clk_prepare_enable(sport->clk_ipg);
2413 if (ret) {
2414 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2415 return ret;
2416 }
2417
2418 ret = uart_get_rs485_mode(&sport->port);
2419 if (ret)
2420 goto err_clk;
2421
2422 /*
2423 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2424 * signal cannot be set low during transmission in case the
2425 * receiver is off (limitation of the i.MX UART IP).
2426 */
2427 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2428 sport->have_rtscts && !sport->have_rtsgpio &&
2429 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2430 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2431 dev_err(&pdev->dev,
2432 "low-active RTS not possible when receiver is off, enabling receiver\n");
2433
2434 /* Disable interrupts before requesting them */
2435 ucr1 = imx_uart_readl(sport, UCR1);
2436 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2437 imx_uart_writel(sport, ucr1, UCR1);
2438
2439 /* Disable Ageing Timer interrupt */
2440 ucr2 = imx_uart_readl(sport, UCR2);
2441 ucr2 &= ~UCR2_ATEN;
2442 imx_uart_writel(sport, ucr2, UCR2);
2443
2444 /*
2445 * In case RS485 is enabled without GPIO RTS control, the UART IP
2446 * is used to control CTS signal. Keep both the UART and Receiver
2447 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2448 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2449 * data from being fed into the RX FIFO, enable loopback mode in
2450 * UTS register, which disconnects the RX path from external RXD
2451 * pin and connects it to the Transceiver, which is disabled, so
2452 * no data can be fed to the RX FIFO that way.
2453 */
2454 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2455 sport->have_rtscts && !sport->have_rtsgpio) {
2456 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2457 uts |= UTS_LOOP;
2458 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2459
2460 ucr1 = imx_uart_readl(sport, UCR1);
2461 ucr1 |= UCR1_UARTEN;
2462 imx_uart_writel(sport, ucr1, UCR1);
2463
2464 ucr2 = imx_uart_readl(sport, UCR2);
2465 ucr2 |= UCR2_RXEN;
2466 imx_uart_writel(sport, ucr2, UCR2);
2467 }
2468
2469 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2470 /*
2471 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2472 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2473 * and DCD (when they are outputs) or enables the respective
2474 * irqs. So set this bit early, i.e. before requesting irqs.
2475 */
2476 u32 ufcr = imx_uart_readl(sport, UFCR);
2477 if (!(ufcr & UFCR_DCEDTE))
2478 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2479
2480 /*
2481 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2482 * enabled later because they cannot be cleared
2483 * (confirmed on i.MX25) which makes them unusable.
2484 */
2485 imx_uart_writel(sport,
2486 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2487 UCR3);
2488
2489 } else {
2490 u32 ucr3 = UCR3_DSR;
2491 u32 ufcr = imx_uart_readl(sport, UFCR);
2492 if (ufcr & UFCR_DCEDTE)
2493 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2494
2495 if (!imx_uart_is_imx1(sport))
2496 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2497 imx_uart_writel(sport, ucr3, UCR3);
2498 }
2499
2500 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2501 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2502 sport->trigger_start_tx.function = imx_trigger_start_tx;
2503 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2504
2505 /*
2506 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2507 * chips only have one interrupt.
2508 */
2509 if (txirq > 0) {
2510 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2511 dev_name(&pdev->dev), sport);
2512 if (ret) {
2513 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2514 ret);
2515 goto err_clk;
2516 }
2517
2518 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2519 dev_name(&pdev->dev), sport);
2520 if (ret) {
2521 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2522 ret);
2523 goto err_clk;
2524 }
2525
2526 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2527 dev_name(&pdev->dev), sport);
2528 if (ret) {
2529 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2530 ret);
2531 goto err_clk;
2532 }
2533 } else {
2534 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2535 dev_name(&pdev->dev), sport);
2536 if (ret) {
2537 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2538 goto err_clk;
2539 }
2540 }
2541
2542 imx_uart_ports[sport->port.line] = sport;
2543
2544 platform_set_drvdata(pdev, sport);
2545
2546 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2547
2548 err_clk:
2549 clk_disable_unprepare(sport->clk_ipg);
2550
2551 return ret;
2552 }
2553
imx_uart_remove(struct platform_device * pdev)2554 static void imx_uart_remove(struct platform_device *pdev)
2555 {
2556 struct imx_port *sport = platform_get_drvdata(pdev);
2557
2558 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2559 }
2560
imx_uart_restore_context(struct imx_port * sport)2561 static void imx_uart_restore_context(struct imx_port *sport)
2562 {
2563 unsigned long flags;
2564
2565 uart_port_lock_irqsave(&sport->port, &flags);
2566 if (!sport->context_saved) {
2567 uart_port_unlock_irqrestore(&sport->port, flags);
2568 return;
2569 }
2570
2571 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2572 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2573 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2574 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2575 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2576 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2577 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2578 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2579 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2580 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2581 sport->context_saved = false;
2582 uart_port_unlock_irqrestore(&sport->port, flags);
2583 }
2584
imx_uart_save_context(struct imx_port * sport)2585 static void imx_uart_save_context(struct imx_port *sport)
2586 {
2587 unsigned long flags;
2588
2589 /* Save necessary regs */
2590 uart_port_lock_irqsave(&sport->port, &flags);
2591 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2592 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2593 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2594 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2595 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2596 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2597 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2598 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2599 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2600 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2601 sport->context_saved = true;
2602 uart_port_unlock_irqrestore(&sport->port, flags);
2603 }
2604
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2605 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2606 {
2607 u32 ucr3;
2608
2609 ucr3 = imx_uart_readl(sport, UCR3);
2610 if (on) {
2611 imx_uart_writel(sport, USR1_AWAKE, USR1);
2612 ucr3 |= UCR3_AWAKEN;
2613 } else {
2614 ucr3 &= ~UCR3_AWAKEN;
2615 }
2616 imx_uart_writel(sport, ucr3, UCR3);
2617
2618 if (sport->have_rtscts) {
2619 u32 ucr1 = imx_uart_readl(sport, UCR1);
2620 if (on) {
2621 imx_uart_writel(sport, USR1_RTSD, USR1);
2622 ucr1 |= UCR1_RTSDEN;
2623 } else {
2624 ucr1 &= ~UCR1_RTSDEN;
2625 }
2626 imx_uart_writel(sport, ucr1, UCR1);
2627 }
2628 }
2629
imx_uart_suspend_noirq(struct device * dev)2630 static int imx_uart_suspend_noirq(struct device *dev)
2631 {
2632 struct imx_port *sport = dev_get_drvdata(dev);
2633
2634 imx_uart_save_context(sport);
2635
2636 clk_disable(sport->clk_ipg);
2637
2638 pinctrl_pm_select_sleep_state(dev);
2639
2640 return 0;
2641 }
2642
imx_uart_resume_noirq(struct device * dev)2643 static int imx_uart_resume_noirq(struct device *dev)
2644 {
2645 struct imx_port *sport = dev_get_drvdata(dev);
2646 int ret;
2647
2648 pinctrl_pm_select_default_state(dev);
2649
2650 ret = clk_enable(sport->clk_ipg);
2651 if (ret)
2652 return ret;
2653
2654 imx_uart_restore_context(sport);
2655
2656 return 0;
2657 }
2658
imx_uart_suspend(struct device * dev)2659 static int imx_uart_suspend(struct device *dev)
2660 {
2661 struct imx_port *sport = dev_get_drvdata(dev);
2662 int ret;
2663
2664 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2665 disable_irq(sport->port.irq);
2666
2667 ret = clk_prepare_enable(sport->clk_ipg);
2668 if (ret)
2669 return ret;
2670
2671 /* enable wakeup from i.MX UART */
2672 imx_uart_enable_wakeup(sport, true);
2673
2674 return 0;
2675 }
2676
imx_uart_resume(struct device * dev)2677 static int imx_uart_resume(struct device *dev)
2678 {
2679 struct imx_port *sport = dev_get_drvdata(dev);
2680
2681 /* disable wakeup from i.MX UART */
2682 imx_uart_enable_wakeup(sport, false);
2683
2684 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2685 enable_irq(sport->port.irq);
2686
2687 clk_disable_unprepare(sport->clk_ipg);
2688
2689 return 0;
2690 }
2691
imx_uart_freeze(struct device * dev)2692 static int imx_uart_freeze(struct device *dev)
2693 {
2694 struct imx_port *sport = dev_get_drvdata(dev);
2695
2696 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2697
2698 return clk_prepare_enable(sport->clk_ipg);
2699 }
2700
imx_uart_thaw(struct device * dev)2701 static int imx_uart_thaw(struct device *dev)
2702 {
2703 struct imx_port *sport = dev_get_drvdata(dev);
2704
2705 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2706
2707 clk_disable_unprepare(sport->clk_ipg);
2708
2709 return 0;
2710 }
2711
2712 static const struct dev_pm_ops imx_uart_pm_ops = {
2713 .suspend_noirq = imx_uart_suspend_noirq,
2714 .resume_noirq = imx_uart_resume_noirq,
2715 .freeze_noirq = imx_uart_suspend_noirq,
2716 .thaw_noirq = imx_uart_resume_noirq,
2717 .restore_noirq = imx_uart_resume_noirq,
2718 .suspend = imx_uart_suspend,
2719 .resume = imx_uart_resume,
2720 .freeze = imx_uart_freeze,
2721 .thaw = imx_uart_thaw,
2722 .restore = imx_uart_thaw,
2723 };
2724
2725 static struct platform_driver imx_uart_platform_driver = {
2726 .probe = imx_uart_probe,
2727 .remove_new = imx_uart_remove,
2728
2729 .driver = {
2730 .name = "imx-uart",
2731 .of_match_table = imx_uart_dt_ids,
2732 .pm = &imx_uart_pm_ops,
2733 },
2734 };
2735
imx_uart_init(void)2736 static int __init imx_uart_init(void)
2737 {
2738 int ret = uart_register_driver(&imx_uart_uart_driver);
2739
2740 if (ret)
2741 return ret;
2742
2743 ret = platform_driver_register(&imx_uart_platform_driver);
2744 if (ret != 0)
2745 uart_unregister_driver(&imx_uart_uart_driver);
2746
2747 return ret;
2748 }
2749
imx_uart_exit(void)2750 static void __exit imx_uart_exit(void)
2751 {
2752 platform_driver_unregister(&imx_uart_platform_driver);
2753 uart_unregister_driver(&imx_uart_uart_driver);
2754 }
2755
2756 module_init(imx_uart_init);
2757 module_exit(imx_uart_exit);
2758
2759 MODULE_AUTHOR("Sascha Hauer");
2760 MODULE_DESCRIPTION("IMX generic serial port driver");
2761 MODULE_LICENSE("GPL");
2762 MODULE_ALIAS("platform:imx-uart");
2763