1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 * Author: Seungwon Jeon <essuuj@gmail.com>
7 * Author: Alim Akhtar <alim.akhtar@samsung.com>
8 *
9 */
10
11 #include <linux/unaligned.h>
12 #include <crypto/aes.h>
13 #include <linux/arm-smccc.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23
24 #include <ufs/ufshcd.h>
25 #include "ufshcd-pltfrm.h"
26 #include <ufs/ufshci.h>
27 #include <ufs/unipro.h>
28
29 #include "ufs-exynos.h"
30
31 #define DATA_UNIT_SIZE 4096
32
33 /*
34 * Exynos's Vendor specific registers for UFSHCI
35 */
36 #define HCI_TXPRDT_ENTRY_SIZE 0x00
37 #define PRDT_PREFETCH_EN BIT(31)
38 #define HCI_RXPRDT_ENTRY_SIZE 0x04
39 #define HCI_1US_TO_CNT_VAL 0x0C
40 #define CNT_VAL_1US_MASK 0x3FF
41 #define HCI_UTRL_NEXUS_TYPE 0x40
42 #define HCI_UTMRL_NEXUS_TYPE 0x44
43 #define HCI_SW_RST 0x50
44 #define UFS_LINK_SW_RST BIT(0)
45 #define UFS_UNIPRO_SW_RST BIT(1)
46 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST)
47 #define HCI_DATA_REORDER 0x60
48 #define HCI_UNIPRO_APB_CLK_CTRL 0x68
49 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
50 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C
51 #define HCI_GPIO_OUT 0x70
52 #define HCI_ERR_EN_PA_LAYER 0x78
53 #define HCI_ERR_EN_DL_LAYER 0x7C
54 #define HCI_ERR_EN_N_LAYER 0x80
55 #define HCI_ERR_EN_T_LAYER 0x84
56 #define HCI_ERR_EN_DME_LAYER 0x88
57 #define HCI_V2P1_CTRL 0x8C
58 #define IA_TICK_SEL BIT(16)
59 #define HCI_CLKSTOP_CTRL 0xB0
60 #define REFCLKOUT_STOP BIT(4)
61 #define MPHY_APBCLK_STOP BIT(3)
62 #define REFCLK_STOP BIT(2)
63 #define UNIPRO_MCLK_STOP BIT(1)
64 #define UNIPRO_PCLK_STOP BIT(0)
65 #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
66 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
67 UNIPRO_PCLK_STOP)
68 /* HCI_MISC is also known as HCI_FORCE_HCS */
69 #define HCI_MISC 0xB4
70 #define REFCLK_CTRL_EN BIT(7)
71 #define UNIPRO_PCLK_CTRL_EN BIT(6)
72 #define UNIPRO_MCLK_CTRL_EN BIT(5)
73 #define HCI_CORECLK_CTRL_EN BIT(4)
74 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
75 UNIPRO_PCLK_CTRL_EN |\
76 UNIPRO_MCLK_CTRL_EN)
77 /* Device fatal error */
78 #define DFES_ERR_EN BIT(31)
79 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
80 UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
81 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\
82 UIC_NETWORK_BAD_DEVICEID_ENC |\
83 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING)
84 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\
85 UIC_TRANSPORT_UNKNOWN_CPORTID |\
86 UIC_TRANSPORT_NO_CONNECTION_RX |\
87 UIC_TRANSPORT_BAD_TC)
88
89 /* UFS Shareability */
90 #define UFS_EXYNOSAUTO_WR_SHARABLE BIT(2)
91 #define UFS_EXYNOSAUTO_RD_SHARABLE BIT(1)
92 #define UFS_EXYNOSAUTO_SHARABLE (UFS_EXYNOSAUTO_WR_SHARABLE | \
93 UFS_EXYNOSAUTO_RD_SHARABLE)
94 #define UFS_GS101_WR_SHARABLE BIT(1)
95 #define UFS_GS101_RD_SHARABLE BIT(0)
96 #define UFS_GS101_SHARABLE (UFS_GS101_WR_SHARABLE | \
97 UFS_GS101_RD_SHARABLE)
98 #define UFS_SHAREABILITY_OFFSET 0x710
99
100 /* Multi-host registers */
101 #define MHCTRL 0xC4
102 #define MHCTRL_EN_VH_MASK (0xE)
103 #define MHCTRL_EN_VH(vh) (vh << 1)
104 #define PH2VH_MBOX 0xD8
105
106 #define MH_MSG_MASK (0xFF)
107
108 #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF))
109 #define MH_MSG_PH_READY 0x1
110 #define MH_MSG_VH_READY 0x2
111
112 #define ALLOW_INQUIRY BIT(25)
113 #define ALLOW_MODE_SELECT BIT(24)
114 #define ALLOW_MODE_SENSE BIT(23)
115 #define ALLOW_PRE_FETCH GENMASK(22, 21)
116 #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */
117 #define ALLOW_READ_BUFFER BIT(17)
118 #define ALLOW_READ_CAPACITY GENMASK(16, 15)
119 #define ALLOW_REPORT_LUNS BIT(14)
120 #define ALLOW_REQUEST_SENSE BIT(13)
121 #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7)
122 #define ALLOW_TEST_UNIT_READY BIT(6)
123 #define ALLOW_UNMAP BIT(5)
124 #define ALLOW_VERIFY BIT(4)
125 #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */
126
127 #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \
128 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \
129 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \
130 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \
131 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \
132 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \
133 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL)
134
135 #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C
136 #define HCI_MH_IID_IN_TASK_TAG 0X308
137
138 #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC)
139
140 enum {
141 UNIPRO_L1_5 = 0,/* PHY Adapter */
142 UNIPRO_L2, /* Data Link */
143 UNIPRO_L3, /* Network */
144 UNIPRO_L4, /* Transport */
145 UNIPRO_DME, /* DME */
146 };
147
148 /*
149 * UNIPRO registers
150 */
151 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888
152 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c
153 #define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890
154 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
155 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
156 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
157
158 /*
159 * UFS Protector registers
160 */
161 #define UFSPRSECURITY 0x010
162 #define NSSMU BIT(14)
163 #define UFSPSBEGIN0 0x200
164 #define UFSPSEND0 0x204
165 #define UFSPSLUN0 0x208
166 #define UFSPSCTRL0 0x20C
167
168 #define CNTR_DIV_VAL 40
169
170 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
171 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
172
exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs * ufs)173 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
174 {
175 exynos_ufs_auto_ctrl_hcc(ufs, true);
176 }
177
exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs * ufs)178 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
179 {
180 exynos_ufs_auto_ctrl_hcc(ufs, false);
181 }
182
exynos_ufs_disable_auto_ctrl_hcc_save(struct exynos_ufs * ufs,u32 * val)183 static inline void exynos_ufs_disable_auto_ctrl_hcc_save(
184 struct exynos_ufs *ufs, u32 *val)
185 {
186 *val = hci_readl(ufs, HCI_MISC);
187 exynos_ufs_auto_ctrl_hcc(ufs, false);
188 }
189
exynos_ufs_auto_ctrl_hcc_restore(struct exynos_ufs * ufs,u32 * val)190 static inline void exynos_ufs_auto_ctrl_hcc_restore(
191 struct exynos_ufs *ufs, u32 *val)
192 {
193 hci_writel(ufs, *val, HCI_MISC);
194 }
195
exynos_ufs_gate_clks(struct exynos_ufs * ufs)196 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
197 {
198 exynos_ufs_ctrl_clkstop(ufs, true);
199 }
200
exynos_ufs_ungate_clks(struct exynos_ufs * ufs)201 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
202 {
203 exynos_ufs_ctrl_clkstop(ufs, false);
204 }
205
exynos_ufs_shareability(struct exynos_ufs * ufs)206 static int exynos_ufs_shareability(struct exynos_ufs *ufs)
207 {
208 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
209
210 /* IO Coherency setting */
211 if (ufs->sysreg) {
212 return regmap_update_bits(ufs->sysreg,
213 ufs->iocc_offset,
214 ufs->iocc_mask, ufs->iocc_val);
215 }
216
217 attr->tx_dif_p_nsec = 3200000;
218
219 return 0;
220 }
221
gs101_ufs_drv_init(struct exynos_ufs * ufs)222 static int gs101_ufs_drv_init(struct exynos_ufs *ufs)
223 {
224 struct ufs_hba *hba = ufs->hba;
225
226 /* Enable WriteBooster */
227 hba->caps |= UFSHCD_CAP_WB_EN;
228
229 return exynos_ufs_shareability(ufs);
230 }
231
exynosauto_ufs_drv_init(struct exynos_ufs * ufs)232 static int exynosauto_ufs_drv_init(struct exynos_ufs *ufs)
233 {
234 return exynos_ufs_shareability(ufs);
235 }
236
exynosauto_ufs_post_hce_enable(struct exynos_ufs * ufs)237 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
238 {
239 struct ufs_hba *hba = ufs->hba;
240
241 /* Enable Virtual Host #1 */
242 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
243 /* Default VH Transfer permissions */
244 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH);
245 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
246 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
247
248 return 0;
249 }
250
exynosauto_ufs_pre_link(struct exynos_ufs * ufs)251 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
252 {
253 struct ufs_hba *hba = ufs->hba;
254 int i;
255 u32 tx_line_reset_period, rx_line_reset_period;
256
257 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
258 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
259
260 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
261 for_each_ufs_rx_lane(ufs, i) {
262 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
263 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
264 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
265
266 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
267 (rx_line_reset_period >> 16) & 0xFF);
268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
269 (rx_line_reset_period >> 8) & 0xFF);
270 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
271 (rx_line_reset_period) & 0xFF);
272
273 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
275 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
276 }
277
278 for_each_ufs_tx_lane(ufs, i) {
279 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
280 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
281 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */
282 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
283 0x02);
284
285 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
286 (tx_line_reset_period >> 16) & 0xFF);
287 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
288 (tx_line_reset_period >> 8) & 0xFF);
289 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
290 (tx_line_reset_period) & 0xFF);
291
292 /* TX PWM Gear Capability / PWM_G1_ONLY */
293 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
294 }
295
296 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
297
298 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
299
300 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
301
302 return 0;
303 }
304
exynosauto_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)305 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
306 struct ufs_pa_layer_attr *pwr)
307 {
308 struct ufs_hba *hba = ufs->hba;
309
310 /* PACP_PWR_req and delivered to the remote DME */
311 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
312 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
313 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
314
315 return 0;
316 }
317
exynosauto_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)318 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
319 struct ufs_pa_layer_attr *pwr)
320 {
321 struct ufs_hba *hba = ufs->hba;
322 u32 enabled_vh;
323
324 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
325
326 /* Send physical host ready message to virtual hosts */
327 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
328
329 return 0;
330 }
331
exynos7_ufs_pre_link(struct exynos_ufs * ufs)332 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
333 {
334 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
335 u32 val = attr->pa_dbg_opt_suite1_val;
336 struct ufs_hba *hba = ufs->hba;
337 int i;
338
339 exynos_ufs_enable_ov_tm(hba);
340 for_each_ufs_tx_lane(ufs, i)
341 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
342 for_each_ufs_rx_lane(ufs, i) {
343 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
344 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
345 }
346 exynos_ufs_disable_ov_tm(hba);
347
348 for_each_ufs_tx_lane(ufs, i)
349 ufshcd_dme_set(hba,
350 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
351 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
352 udelay(1);
353 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
354 val | (1 << 12));
355 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
356 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
357 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
358 udelay(1600);
359 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val);
360
361 return 0;
362 }
363
exynos7_ufs_post_link(struct exynos_ufs * ufs)364 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
365 {
366 struct ufs_hba *hba = ufs->hba;
367 int i;
368
369 exynos_ufs_enable_ov_tm(hba);
370 for_each_ufs_tx_lane(ufs, i) {
371 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83);
372 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07);
373 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i),
374 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
375 }
376 exynos_ufs_disable_ov_tm(hba);
377
378 exynos_ufs_enable_dbg_mode(hba);
379 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);
380 exynos_ufs_disable_dbg_mode(hba);
381
382 return 0;
383 }
384
exynos7_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)385 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
386 struct ufs_pa_layer_attr *pwr)
387 {
388 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
389
390 return 0;
391 }
392
exynos7_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)393 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
394 struct ufs_pa_layer_attr *pwr)
395 {
396 struct ufs_hba *hba = ufs->hba;
397 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx);
398
399 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);
400
401 if (lanes == 1) {
402 exynos_ufs_enable_dbg_mode(hba);
403 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);
404 exynos_ufs_disable_dbg_mode(hba);
405 }
406
407 return 0;
408 }
409
410 /*
411 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
412 * Control should be disabled in the below cases
413 * - Before host controller S/W reset
414 * - Access to UFS protector's register
415 */
exynos_ufs_auto_ctrl_hcc(struct exynos_ufs * ufs,bool en)416 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
417 {
418 u32 misc = hci_readl(ufs, HCI_MISC);
419
420 if (en)
421 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
422 else
423 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
424 }
425
exynos_ufs_ctrl_clkstop(struct exynos_ufs * ufs,bool en)426 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
427 {
428 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
429 u32 misc = hci_readl(ufs, HCI_MISC);
430
431 if (en) {
432 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
433 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
434 } else {
435 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
436 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
437 }
438 }
439
exynos_ufs_get_clk_info(struct exynos_ufs * ufs)440 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
441 {
442 struct ufs_hba *hba = ufs->hba;
443 struct list_head *head = &hba->clk_list_head;
444 struct ufs_clk_info *clki;
445 unsigned long pclk_rate;
446 u32 f_min, f_max;
447 u8 div = 0;
448 int ret = 0;
449
450 if (list_empty(head))
451 goto out;
452
453 list_for_each_entry(clki, head, list) {
454 if (!IS_ERR(clki->clk)) {
455 if (!strcmp(clki->name, "core_clk"))
456 ufs->clk_hci_core = clki->clk;
457 else if (!strcmp(clki->name, "sclk_unipro_main"))
458 ufs->clk_unipro_main = clki->clk;
459 }
460 }
461
462 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
463 dev_err(hba->dev, "failed to get clk info\n");
464 ret = -EINVAL;
465 goto out;
466 }
467
468 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
469 pclk_rate = clk_get_rate(ufs->clk_hci_core);
470 f_min = ufs->pclk_avail_min;
471 f_max = ufs->pclk_avail_max;
472
473 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
474 do {
475 pclk_rate /= (div + 1);
476
477 if (pclk_rate <= f_max)
478 break;
479 div++;
480 } while (pclk_rate >= f_min);
481 }
482
483 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
484 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate);
485 ret = -EINVAL;
486 goto out;
487 }
488
489 ufs->pclk_rate = pclk_rate;
490 ufs->pclk_div = div;
491
492 out:
493 return ret;
494 }
495
exynos_ufs_set_unipro_pclk_div(struct exynos_ufs * ufs)496 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
497 {
498 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
499 u32 val;
500
501 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
502 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
503 HCI_UNIPRO_APB_CLK_CTRL);
504 }
505 }
506
exynos_ufs_set_pwm_clk_div(struct exynos_ufs * ufs)507 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
508 {
509 struct ufs_hba *hba = ufs->hba;
510 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
511
512 ufshcd_dme_set(hba,
513 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);
514 }
515
exynos_ufs_calc_pwm_clk_div(struct exynos_ufs * ufs)516 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
517 {
518 struct ufs_hba *hba = ufs->hba;
519 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
520 const unsigned int div = 30, mult = 20;
521 const unsigned long pwm_min = 3 * 1000 * 1000;
522 const unsigned long pwm_max = 9 * 1000 * 1000;
523 const int divs[] = {32, 16, 8, 4};
524 unsigned long clk = 0, _clk, clk_period;
525 int i = 0, clk_idx = -1;
526
527 clk_period = UNIPRO_PCLK_PERIOD(ufs);
528 for (i = 0; i < ARRAY_SIZE(divs); i++) {
529 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div);
530 if (_clk >= pwm_min && _clk <= pwm_max) {
531 if (_clk > clk) {
532 clk_idx = i;
533 clk = _clk;
534 }
535 }
536 }
537
538 if (clk_idx == -1) {
539 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);
540 dev_err(hba->dev,
541 "failed to decide pwm clock divider, will not change\n");
542 }
543
544 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK;
545 }
546
exynos_ufs_calc_time_cntr(struct exynos_ufs * ufs,long period)547 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
548 {
549 const int precise = 10;
550 long pclk_rate = ufs->pclk_rate;
551 long clk_period, fraction;
552
553 clk_period = UNIPRO_PCLK_PERIOD(ufs);
554 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate;
555
556 return (period * precise) / ((clk_period * precise) + fraction);
557 }
558
exynos_ufs_specify_phy_time_attr(struct exynos_ufs * ufs)559 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
560 {
561 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
562 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
563
564 t_cfg->tx_linereset_p =
565 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
566 t_cfg->tx_linereset_n =
567 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
568 t_cfg->tx_high_z_cnt =
569 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
570 t_cfg->tx_base_n_val =
571 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
572 t_cfg->tx_gran_n_val =
573 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
574 t_cfg->tx_sleep_cnt =
575 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
576
577 t_cfg->rx_linereset =
578 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
579 t_cfg->rx_hibern8_wait =
580 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
581 t_cfg->rx_base_n_val =
582 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
583 t_cfg->rx_gran_n_val =
584 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
585 t_cfg->rx_sleep_cnt =
586 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
587 t_cfg->rx_stall_cnt =
588 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
589 }
590
exynos_ufs_config_phy_time_attr(struct exynos_ufs * ufs)591 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
592 {
593 struct ufs_hba *hba = ufs->hba;
594 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
595 int i;
596
597 exynos_ufs_set_pwm_clk_div(ufs);
598
599 exynos_ufs_enable_ov_tm(hba);
600
601 for_each_ufs_rx_lane(ufs, i) {
602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i),
603 ufs->drv_data->uic_attr->rx_filler_enable);
604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i),
605 RX_LINERESET(t_cfg->rx_linereset));
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i),
607 RX_BASE_NVAL_L(t_cfg->rx_base_n_val));
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i),
609 RX_BASE_NVAL_H(t_cfg->rx_base_n_val));
610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i),
611 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val));
612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i),
613 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val));
614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i),
615 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt));
616 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i),
617 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt));
618 }
619
620 for_each_ufs_tx_lane(ufs, i) {
621 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i),
622 TX_LINERESET_P(t_cfg->tx_linereset_p));
623 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i),
624 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt));
625 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i),
626 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt));
627 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i),
628 TX_BASE_NVAL_L(t_cfg->tx_base_n_val));
629 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i),
630 TX_BASE_NVAL_H(t_cfg->tx_base_n_val));
631 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i),
632 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val));
633 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i),
634 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val));
635 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i),
636 TX_OV_H8_ENTER_EN |
637 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt));
638 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i),
639 ufs->drv_data->uic_attr->tx_min_activatetime);
640 }
641
642 exynos_ufs_disable_ov_tm(hba);
643 }
644
exynos_ufs_config_phy_cap_attr(struct exynos_ufs * ufs)645 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
646 {
647 struct ufs_hba *hba = ufs->hba;
648 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
649 int i;
650
651 exynos_ufs_enable_ov_tm(hba);
652
653 for_each_ufs_rx_lane(ufs, i) {
654 ufshcd_dme_set(hba,
655 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i),
656 attr->rx_hs_g1_sync_len_cap);
657 ufshcd_dme_set(hba,
658 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i),
659 attr->rx_hs_g2_sync_len_cap);
660 ufshcd_dme_set(hba,
661 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i),
662 attr->rx_hs_g3_sync_len_cap);
663 ufshcd_dme_set(hba,
664 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i),
665 attr->rx_hs_g1_prep_sync_len_cap);
666 ufshcd_dme_set(hba,
667 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i),
668 attr->rx_hs_g2_prep_sync_len_cap);
669 ufshcd_dme_set(hba,
670 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i),
671 attr->rx_hs_g3_prep_sync_len_cap);
672 }
673
674 if (attr->rx_adv_fine_gran_sup_en == 0) {
675 for_each_ufs_rx_lane(ufs, i) {
676 ufshcd_dme_set(hba,
677 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0);
678
679 if (attr->rx_min_actv_time_cap)
680 ufshcd_dme_set(hba,
681 UIC_ARG_MIB_SEL(
682 RX_MIN_ACTIVATETIME_CAPABILITY, i),
683 attr->rx_min_actv_time_cap);
684
685 if (attr->rx_hibern8_time_cap)
686 ufshcd_dme_set(hba,
687 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i),
688 attr->rx_hibern8_time_cap);
689 }
690 } else if (attr->rx_adv_fine_gran_sup_en == 1) {
691 for_each_ufs_rx_lane(ufs, i) {
692 if (attr->rx_adv_fine_gran_step)
693 ufshcd_dme_set(hba,
694 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP,
695 i), RX_ADV_FINE_GRAN_STEP(
696 attr->rx_adv_fine_gran_step));
697
698 if (attr->rx_adv_min_actv_time_cap)
699 ufshcd_dme_set(hba,
700 UIC_ARG_MIB_SEL(
701 RX_ADV_MIN_ACTIVATETIME_CAP, i),
702 attr->rx_adv_min_actv_time_cap);
703
704 if (attr->rx_adv_hibern8_time_cap)
705 ufshcd_dme_set(hba,
706 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP,
707 i),
708 attr->rx_adv_hibern8_time_cap);
709 }
710 }
711
712 exynos_ufs_disable_ov_tm(hba);
713 }
714
exynos_ufs_establish_connt(struct exynos_ufs * ufs)715 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
716 {
717 struct ufs_hba *hba = ufs->hba;
718 enum {
719 DEV_ID = 0x00,
720 PEER_DEV_ID = 0x01,
721 PEER_CPORT_ID = 0x00,
722 TRAFFIC_CLASS = 0x00,
723 };
724
725 /* allow cport attributes to be set */
726 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);
727
728 /* local unipro attributes */
729 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);
730 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true);
731 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);
732 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);
733 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);
734 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);
735 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
736 }
737
exynos_ufs_config_smu(struct exynos_ufs * ufs)738 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
739 {
740 u32 reg, val;
741
742 if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)
743 return;
744
745 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
746
747 /* make encryption disabled by default */
748 reg = ufsp_readl(ufs, UFSPRSECURITY);
749 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
750 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
751 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
752 ufsp_writel(ufs, 0xff, UFSPSLUN0);
753 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
754
755 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
756 }
757
exynos_ufs_config_sync_pattern_mask(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)758 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
759 struct ufs_pa_layer_attr *pwr)
760 {
761 struct ufs_hba *hba = ufs->hba;
762 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx);
763 u32 mask, sync_len;
764 enum {
765 SYNC_LEN_G1 = 80 * 1000, /* 80us */
766 SYNC_LEN_G2 = 40 * 1000, /* 44us */
767 SYNC_LEN_G3 = 20 * 1000, /* 20us */
768 };
769 int i;
770
771 if (g == 1)
772 sync_len = SYNC_LEN_G1;
773 else if (g == 2)
774 sync_len = SYNC_LEN_G2;
775 else if (g == 3)
776 sync_len = SYNC_LEN_G3;
777 else
778 return;
779
780 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
781 mask = (mask >> 8) & 0xff;
782
783 exynos_ufs_enable_ov_tm(hba);
784
785 for_each_ufs_rx_lane(ufs, i)
786 ufshcd_dme_set(hba,
787 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask);
788
789 exynos_ufs_disable_ov_tm(hba);
790 }
791
exynos_ufs_pre_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)792 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
793 struct ufs_pa_layer_attr *dev_max_params,
794 struct ufs_pa_layer_attr *dev_req_params)
795 {
796 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
797 struct phy *generic_phy = ufs->phy;
798 struct ufs_host_params host_params;
799 int ret;
800
801 if (!dev_req_params) {
802 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
803 ret = -EINVAL;
804 goto out;
805 }
806
807 ufshcd_init_host_params(&host_params);
808
809 ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params);
810 if (ret) {
811 pr_err("%s: failed to determine capabilities\n", __func__);
812 goto out;
813 }
814
815 if (ufs->drv_data->pre_pwr_change)
816 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
817
818 if (ufshcd_is_hs_mode(dev_req_params)) {
819 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
820
821 switch (dev_req_params->hs_rate) {
822 case PA_HS_MODE_A:
823 case PA_HS_MODE_B:
824 phy_calibrate(generic_phy);
825 break;
826 }
827 }
828
829 /* setting for three timeout values for traffic class #0 */
830 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
831 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
832 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
833
834 return 0;
835 out:
836 return ret;
837 }
838
839 #define PWR_MODE_STR_LEN 64
exynos_ufs_post_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_req)840 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
841 struct ufs_pa_layer_attr *pwr_req)
842 {
843 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
844 struct phy *generic_phy = ufs->phy;
845 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx);
846 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx);
847 char pwr_str[PWR_MODE_STR_LEN] = "";
848
849 /* let default be PWM Gear 1, Lane 1 */
850 if (!gear)
851 gear = 1;
852
853 if (!lanes)
854 lanes = 1;
855
856 if (ufs->drv_data->post_pwr_change)
857 ufs->drv_data->post_pwr_change(ufs, pwr_req);
858
859 if ((ufshcd_is_hs_mode(pwr_req))) {
860 switch (pwr_req->hs_rate) {
861 case PA_HS_MODE_A:
862 case PA_HS_MODE_B:
863 phy_calibrate(generic_phy);
864 break;
865 }
866
867 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d",
868 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B",
869 gear, lanes);
870 } else {
871 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d",
872 "SLOW", gear, lanes);
873 }
874
875 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str);
876
877 return 0;
878 }
879
exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba * hba,int tag,bool is_scsi_cmd)880 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
881 int tag, bool is_scsi_cmd)
882 {
883 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
884 u32 type;
885
886 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
887
888 if (is_scsi_cmd)
889 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
890 else
891 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
892 }
893
exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba * hba,int tag,u8 func)894 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
895 int tag, u8 func)
896 {
897 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
898 u32 type;
899
900 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
901
902 switch (func) {
903 case UFS_ABORT_TASK:
904 case UFS_QUERY_TASK:
905 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
906 break;
907 case UFS_ABORT_TASK_SET:
908 case UFS_CLEAR_TASK_SET:
909 case UFS_LOGICAL_RESET:
910 case UFS_QUERY_TASK_SET:
911 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
912 break;
913 }
914 }
915
exynos_ufs_phy_init(struct exynos_ufs * ufs)916 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
917 {
918 struct ufs_hba *hba = ufs->hba;
919 struct phy *generic_phy = ufs->phy;
920 int ret = 0;
921
922 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
923 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
924 &ufs->avail_ln_rx);
925 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
926 &ufs->avail_ln_tx);
927 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
928 "available data lane is not equal(rx:%d, tx:%d)\n",
929 ufs->avail_ln_rx, ufs->avail_ln_tx);
930 }
931
932 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
933
934 if (generic_phy->power_count) {
935 phy_power_off(generic_phy);
936 phy_exit(generic_phy);
937 }
938
939 ret = phy_init(generic_phy);
940 if (ret) {
941 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
942 __func__, ret);
943 return ret;
944 }
945
946 ret = phy_power_on(generic_phy);
947 if (ret)
948 goto out_exit_phy;
949
950 return 0;
951
952 out_exit_phy:
953 phy_exit(generic_phy);
954
955 return ret;
956 }
957
exynos_ufs_config_unipro(struct exynos_ufs * ufs)958 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
959 {
960 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
961 struct ufs_hba *hba = ufs->hba;
962
963 if (attr->pa_dbg_clk_period_off)
964 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off),
965 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
966
967 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
968 ufs->drv_data->uic_attr->tx_trailingclks);
969
970 if (attr->pa_dbg_opt_suite1_off)
971 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
972 attr->pa_dbg_opt_suite1_val);
973
974 if (attr->pa_dbg_opt_suite2_off)
975 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off),
976 attr->pa_dbg_opt_suite2_val);
977 }
978
exynos_ufs_config_intr(struct exynos_ufs * ufs,u32 errs,u8 index)979 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
980 {
981 switch (index) {
982 case UNIPRO_L1_5:
983 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
984 break;
985 case UNIPRO_L2:
986 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
987 break;
988 case UNIPRO_L3:
989 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
990 break;
991 case UNIPRO_L4:
992 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
993 break;
994 case UNIPRO_DME:
995 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
996 break;
997 }
998 }
999
exynos_ufs_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)1000 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
1001 enum ufs_notify_change_status status)
1002 {
1003 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1004
1005 if (!ufs)
1006 return 0;
1007
1008 if (on && status == PRE_CHANGE) {
1009 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1010 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1011 exynos_ufs_ungate_clks(ufs);
1012 } else if (!on && status == POST_CHANGE) {
1013 exynos_ufs_gate_clks(ufs);
1014 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1015 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1016 }
1017
1018 return 0;
1019 }
1020
exynos_ufs_pre_link(struct ufs_hba * hba)1021 static int exynos_ufs_pre_link(struct ufs_hba *hba)
1022 {
1023 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1024
1025 /* hci */
1026 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
1027 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
1028 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
1029 exynos_ufs_set_unipro_pclk_div(ufs);
1030
1031 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE);
1032
1033 /* unipro */
1034 exynos_ufs_config_unipro(ufs);
1035
1036 if (ufs->drv_data->pre_link)
1037 ufs->drv_data->pre_link(ufs);
1038
1039 /* m-phy */
1040 exynos_ufs_phy_init(ufs);
1041 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
1042 exynos_ufs_config_phy_time_attr(ufs);
1043 exynos_ufs_config_phy_cap_attr(ufs);
1044 }
1045
1046 return 0;
1047 }
1048
exynos_ufs_fit_aggr_timeout(struct exynos_ufs * ufs)1049 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
1050 {
1051 u32 val;
1052
1053 /* Select function clock (mclk) for timer tick */
1054 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) {
1055 val = hci_readl(ufs, HCI_V2P1_CTRL);
1056 val |= IA_TICK_SEL;
1057 hci_writel(ufs, val, HCI_V2P1_CTRL);
1058 }
1059
1060 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
1061 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
1062 }
1063
exynos_ufs_post_link(struct ufs_hba * hba)1064 static int exynos_ufs_post_link(struct ufs_hba *hba)
1065 {
1066 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1067 struct phy *generic_phy = ufs->phy;
1068 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1069 u32 val = ilog2(DATA_UNIT_SIZE);
1070
1071 exynos_ufs_establish_connt(ufs);
1072 exynos_ufs_fit_aggr_timeout(ufs);
1073
1074 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
1075
1076 if (hba->caps & UFSHCD_CAP_CRYPTO)
1077 val |= PRDT_PREFETCH_EN;
1078 hci_writel(ufs, val, HCI_TXPRDT_ENTRY_SIZE);
1079
1080 hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE);
1081 hci_writel(ufs, BIT(hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
1082 hci_writel(ufs, BIT(hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
1083 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
1084
1085 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
1086 ufshcd_dme_set(hba,
1087 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true);
1088
1089 if (attr->pa_granularity) {
1090 exynos_ufs_enable_dbg_mode(hba);
1091 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),
1092 attr->pa_granularity);
1093 exynos_ufs_disable_dbg_mode(hba);
1094
1095 if (attr->pa_tactivate)
1096 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1097 attr->pa_tactivate);
1098 if (attr->pa_hibern8time &&
1099 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
1100 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1101 attr->pa_hibern8time);
1102 }
1103
1104 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1105 if (!attr->pa_granularity)
1106 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
1107 &attr->pa_granularity);
1108 if (!attr->pa_hibern8time)
1109 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1110 &attr->pa_hibern8time);
1111 /*
1112 * not wait for HIBERN8 time to exit hibernation
1113 */
1114 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);
1115
1116 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
1117 /* Valid range for granularity: 1 ~ 6 */
1118 dev_warn(hba->dev,
1119 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n",
1120 __func__,
1121 attr->pa_granularity);
1122 attr->pa_granularity = 6;
1123 }
1124 }
1125
1126 phy_calibrate(generic_phy);
1127
1128 if (ufs->drv_data->post_link)
1129 ufs->drv_data->post_link(ufs);
1130
1131 return 0;
1132 }
1133
exynos_ufs_parse_dt(struct device * dev,struct exynos_ufs * ufs)1134 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
1135 {
1136 struct device_node *np = dev->of_node;
1137 struct exynos_ufs_uic_attr *attr;
1138 int ret = 0;
1139
1140 ufs->drv_data = device_get_match_data(dev);
1141
1142 if (ufs->drv_data && ufs->drv_data->uic_attr) {
1143 attr = ufs->drv_data->uic_attr;
1144 } else {
1145 dev_err(dev, "failed to get uic attributes\n");
1146 ret = -EINVAL;
1147 goto out;
1148 }
1149
1150 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");
1151 if (IS_ERR(ufs->sysreg))
1152 ufs->sysreg = NULL;
1153 else {
1154 if (of_property_read_u32_index(np, "samsung,sysreg", 1,
1155 &ufs->iocc_offset)) {
1156 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n");
1157 ufs->iocc_offset = UFS_SHAREABILITY_OFFSET;
1158 }
1159 }
1160
1161 ufs->iocc_mask = ufs->drv_data->iocc_mask;
1162 /*
1163 * no 'dma-coherent' property means the descriptors are
1164 * non-cacheable so iocc shareability should be disabled.
1165 */
1166 if (of_dma_is_coherent(dev->of_node))
1167 ufs->iocc_val = ufs->iocc_mask;
1168 else
1169 ufs->iocc_val = 0;
1170
1171 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
1172 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
1173
1174 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN;
1175 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL;
1176 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP;
1177 attr->pa_granularity = PA_GRANULARITY_VAL;
1178 attr->pa_tactivate = PA_TACTIVATE_VAL;
1179 attr->pa_hibern8time = PA_HIBERN8TIME_VAL;
1180
1181 out:
1182 return ret;
1183 }
1184
exynos_ufs_priv_init(struct ufs_hba * hba,struct exynos_ufs * ufs)1185 static inline void exynos_ufs_priv_init(struct ufs_hba *hba,
1186 struct exynos_ufs *ufs)
1187 {
1188 ufs->hba = hba;
1189 ufs->opts = ufs->drv_data->opts;
1190 ufs->rx_sel_idx = PA_MAXDATALANES;
1191 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
1192 ufs->rx_sel_idx = 0;
1193 hba->priv = (void *)ufs;
1194 hba->quirks = ufs->drv_data->quirks;
1195 }
1196
1197 #ifdef CONFIG_SCSI_UFS_CRYPTO
1198
1199 /*
1200 * Support for Flash Memory Protector (FMP), which is the inline encryption
1201 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is
1202 * not compatible with the standard UFS crypto. It requires that encryption be
1203 * configured in the PRDT using a nonstandard extension.
1204 */
1205
1206 enum fmp_crypto_algo_mode {
1207 FMP_BYPASS_MODE = 0,
1208 FMP_ALGO_MODE_AES_CBC = 1,
1209 FMP_ALGO_MODE_AES_XTS = 2,
1210 };
1211 enum fmp_crypto_key_length {
1212 FMP_KEYLEN_256BIT = 1,
1213 };
1214
1215 /**
1216 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled
1217 *
1218 * @base: The standard PRDT entry, but with nonstandard bitfields in the high
1219 * bits of the 'size' field, i.e. the last 32-bit word. When these
1220 * nonstandard bitfields are zero, the data segment won't be encrypted or
1221 * decrypted. Otherwise they specify the algorithm and key length with
1222 * which the data segment will be encrypted or decrypted.
1223 * @file_iv: The initialization vector (IV) with all bytes reversed
1224 * @file_enckey: The first half of the AES-XTS key with all bytes reserved
1225 * @file_twkey: The second half of the AES-XTS key with all bytes reserved
1226 * @disk_iv: Unused
1227 * @reserved: Unused
1228 */
1229 struct fmp_sg_entry {
1230 struct ufshcd_sg_entry base;
1231 __be64 file_iv[2];
1232 __be64 file_enckey[4];
1233 __be64 file_twkey[4];
1234 __be64 disk_iv[2];
1235 __be64 reserved[2];
1236 };
1237
1238 #define SMC_CMD_FMP_SECURITY \
1239 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
1240 ARM_SMCCC_OWNER_SIP, 0x1810)
1241 #define SMC_CMD_SMU \
1242 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
1243 ARM_SMCCC_OWNER_SIP, 0x1850)
1244 #define SMC_CMD_FMP_SMU_RESUME \
1245 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
1246 ARM_SMCCC_OWNER_SIP, 0x1860)
1247 #define SMU_EMBEDDED 0
1248 #define SMU_INIT 0
1249 #define CFG_DESCTYPE_3 3
1250
exynos_ufs_fmp_init(struct ufs_hba * hba,struct exynos_ufs * ufs)1251 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs)
1252 {
1253 struct blk_crypto_profile *profile = &hba->crypto_profile;
1254 struct arm_smccc_res res;
1255 int err;
1256
1257 /*
1258 * Check for the standard crypto support bit, since it's available even
1259 * though the rest of the interface to FMP is nonstandard.
1260 *
1261 * This check should have the effect of preventing the driver from
1262 * trying to use FMP on old Exynos SoCs that don't have FMP.
1263 */
1264 if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) &
1265 MASK_CRYPTO_SUPPORT))
1266 return;
1267
1268 /*
1269 * The below sequence of SMC calls to enable FMP can be found in the
1270 * downstream driver source for gs101 and other Exynos-based SoCs. It
1271 * is the only way to enable FMP that works on SoCs such as gs101 that
1272 * don't make the FMP registers accessible to Linux. It probably works
1273 * on other Exynos-based SoCs too, and might even still be the only way
1274 * that works. But this hasn't been properly tested, and this code is
1275 * mutually exclusive with exynos_ufs_config_smu(). So for now only
1276 * enable FMP support on SoCs with EXYNOS_UFS_OPT_UFSPR_SECURE.
1277 */
1278 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
1279 return;
1280
1281 /*
1282 * This call (which sets DESCTYPE to 0x3 in the FMPSECURITY0 register)
1283 * is needed to make the hardware use the larger PRDT entry size.
1284 */
1285 BUILD_BUG_ON(sizeof(struct fmp_sg_entry) != 128);
1286 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3,
1287 0, 0, 0, 0, &res);
1288 if (res.a0) {
1289 dev_warn(hba->dev,
1290 "SMC_CMD_FMP_SECURITY failed on init: %ld. Disabling FMP support.\n",
1291 res.a0);
1292 return;
1293 }
1294 ufshcd_set_sg_entry_size(hba, sizeof(struct fmp_sg_entry));
1295
1296 /*
1297 * This is needed to initialize FMP. Without it, errors occur when
1298 * inline encryption is used.
1299 */
1300 arm_smccc_smc(SMC_CMD_SMU, SMU_INIT, SMU_EMBEDDED, 0, 0, 0, 0, 0, &res);
1301 if (res.a0) {
1302 dev_err(hba->dev,
1303 "SMC_CMD_SMU(SMU_INIT) failed: %ld. Disabling FMP support.\n",
1304 res.a0);
1305 return;
1306 }
1307
1308 /* Advertise crypto capabilities to the block layer. */
1309 err = devm_blk_crypto_profile_init(hba->dev, profile, 0);
1310 if (err) {
1311 /* Only ENOMEM should be possible here. */
1312 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n",
1313 err);
1314 return;
1315 }
1316 profile->max_dun_bytes_supported = AES_BLOCK_SIZE;
1317 profile->dev = hba->dev;
1318 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] =
1319 DATA_UNIT_SIZE;
1320
1321 /* Advertise crypto support to ufshcd-core. */
1322 hba->caps |= UFSHCD_CAP_CRYPTO;
1323
1324 /* Advertise crypto quirks to ufshcd-core. */
1325 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE |
1326 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE |
1327 UFSHCD_QUIRK_KEYS_IN_PRDT;
1328
1329 }
1330
exynos_ufs_fmp_resume(struct ufs_hba * hba)1331 static void exynos_ufs_fmp_resume(struct ufs_hba *hba)
1332 {
1333 struct arm_smccc_res res;
1334
1335 if (!(hba->caps & UFSHCD_CAP_CRYPTO))
1336 return;
1337
1338 arm_smccc_smc(SMC_CMD_FMP_SECURITY, 0, SMU_EMBEDDED, CFG_DESCTYPE_3,
1339 0, 0, 0, 0, &res);
1340 if (res.a0)
1341 dev_err(hba->dev,
1342 "SMC_CMD_FMP_SECURITY failed on resume: %ld\n", res.a0);
1343
1344 arm_smccc_smc(SMC_CMD_FMP_SMU_RESUME, 0, SMU_EMBEDDED, 0, 0, 0, 0, 0,
1345 &res);
1346 if (res.a0)
1347 dev_err(hba->dev,
1348 "SMC_CMD_FMP_SMU_RESUME failed: %ld\n", res.a0);
1349 }
1350
fmp_key_word(const u8 * key,int j)1351 static inline __be64 fmp_key_word(const u8 *key, int j)
1352 {
1353 return cpu_to_be64(get_unaligned_le64(
1354 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64)));
1355 }
1356
1357 /* Fill the PRDT for a request according to the given encryption context. */
exynos_ufs_fmp_fill_prdt(struct ufs_hba * hba,const struct bio_crypt_ctx * crypt_ctx,void * prdt,unsigned int num_segments)1358 static int exynos_ufs_fmp_fill_prdt(struct ufs_hba *hba,
1359 const struct bio_crypt_ctx *crypt_ctx,
1360 void *prdt, unsigned int num_segments)
1361 {
1362 struct fmp_sg_entry *fmp_prdt = prdt;
1363 const u8 *enckey = crypt_ctx->bc_key->raw;
1364 const u8 *twkey = enckey + AES_KEYSIZE_256;
1365 u64 dun_lo = crypt_ctx->bc_dun[0];
1366 u64 dun_hi = crypt_ctx->bc_dun[1];
1367 unsigned int i;
1368
1369 /* If FMP wasn't enabled, we shouldn't get any encrypted requests. */
1370 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO)))
1371 return -EIO;
1372
1373 /* Configure FMP on each segment of the request. */
1374 for (i = 0; i < num_segments; i++) {
1375 struct fmp_sg_entry *prd = &fmp_prdt[i];
1376 int j;
1377
1378 /* Each segment must be exactly one data unit. */
1379 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) {
1380 dev_err(hba->dev,
1381 "data segment is misaligned for FMP\n");
1382 return -EIO;
1383 }
1384
1385 /* Set the algorithm and key length. */
1386 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) |
1387 (FMP_KEYLEN_256BIT << 26));
1388
1389 /* Set the IV. */
1390 prd->file_iv[0] = cpu_to_be64(dun_hi);
1391 prd->file_iv[1] = cpu_to_be64(dun_lo);
1392
1393 /* Set the key. */
1394 for (j = 0; j < AES_KEYSIZE_256 / sizeof(u64); j++) {
1395 prd->file_enckey[j] = fmp_key_word(enckey, j);
1396 prd->file_twkey[j] = fmp_key_word(twkey, j);
1397 }
1398
1399 /* Increment the data unit number. */
1400 dun_lo++;
1401 if (dun_lo == 0)
1402 dun_hi++;
1403 }
1404 return 0;
1405 }
1406
1407 #else /* CONFIG_SCSI_UFS_CRYPTO */
1408
exynos_ufs_fmp_init(struct ufs_hba * hba,struct exynos_ufs * ufs)1409 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs)
1410 {
1411 }
1412
exynos_ufs_fmp_resume(struct ufs_hba * hba)1413 static void exynos_ufs_fmp_resume(struct ufs_hba *hba)
1414 {
1415 }
1416
1417 #define exynos_ufs_fmp_fill_prdt NULL
1418
1419 #endif /* !CONFIG_SCSI_UFS_CRYPTO */
1420
exynos_ufs_init(struct ufs_hba * hba)1421 static int exynos_ufs_init(struct ufs_hba *hba)
1422 {
1423 struct device *dev = hba->dev;
1424 struct platform_device *pdev = to_platform_device(dev);
1425 struct exynos_ufs *ufs;
1426 int ret;
1427
1428 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1429 if (!ufs)
1430 return -ENOMEM;
1431
1432 /* exynos-specific hci */
1433 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1434 if (IS_ERR(ufs->reg_hci)) {
1435 dev_err(dev, "cannot ioremap for hci vendor register\n");
1436 return PTR_ERR(ufs->reg_hci);
1437 }
1438
1439 /* unipro */
1440 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
1441 if (IS_ERR(ufs->reg_unipro)) {
1442 dev_err(dev, "cannot ioremap for unipro register\n");
1443 return PTR_ERR(ufs->reg_unipro);
1444 }
1445
1446 /* ufs protector */
1447 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
1448 if (IS_ERR(ufs->reg_ufsp)) {
1449 dev_err(dev, "cannot ioremap for ufs protector register\n");
1450 return PTR_ERR(ufs->reg_ufsp);
1451 }
1452
1453 ret = exynos_ufs_parse_dt(dev, ufs);
1454 if (ret) {
1455 dev_err(dev, "failed to get dt info.\n");
1456 goto out;
1457 }
1458
1459 ufs->phy = devm_phy_get(dev, "ufs-phy");
1460 if (IS_ERR(ufs->phy)) {
1461 ret = PTR_ERR(ufs->phy);
1462 dev_err(dev, "failed to get ufs-phy\n");
1463 goto out;
1464 }
1465
1466 exynos_ufs_priv_init(hba, ufs);
1467
1468 exynos_ufs_fmp_init(hba, ufs);
1469
1470 if (ufs->drv_data->drv_init) {
1471 ret = ufs->drv_data->drv_init(ufs);
1472 if (ret) {
1473 dev_err(dev, "failed to init drv-data\n");
1474 goto out;
1475 }
1476 }
1477
1478 ret = exynos_ufs_get_clk_info(ufs);
1479 if (ret)
1480 goto out;
1481 exynos_ufs_specify_phy_time_attr(ufs);
1482
1483 exynos_ufs_config_smu(ufs);
1484
1485 hba->host->dma_alignment = DATA_UNIT_SIZE - 1;
1486 return 0;
1487
1488 out:
1489 hba->priv = NULL;
1490 return ret;
1491 }
1492
exynos_ufs_exit(struct ufs_hba * hba)1493 static void exynos_ufs_exit(struct ufs_hba *hba)
1494 {
1495 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1496
1497 phy_power_off(ufs->phy);
1498 phy_exit(ufs->phy);
1499 }
1500
exynos_ufs_host_reset(struct ufs_hba * hba)1501 static int exynos_ufs_host_reset(struct ufs_hba *hba)
1502 {
1503 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1504 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1505 u32 val;
1506 int ret = 0;
1507
1508 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1509
1510 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1511
1512 do {
1513 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1514 goto out;
1515 } while (time_before(jiffies, timeout));
1516
1517 dev_err(hba->dev, "timeout host sw-reset\n");
1518 ret = -ETIMEDOUT;
1519
1520 out:
1521 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1522 return ret;
1523 }
1524
exynos_ufs_dev_hw_reset(struct ufs_hba * hba)1525 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba)
1526 {
1527 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1528
1529 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1530 udelay(5);
1531 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1532 }
1533
exynos_ufs_pre_hibern8(struct ufs_hba * hba,enum uic_cmd_dme cmd)1534 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd)
1535 {
1536 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1537 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1538
1539 if (cmd == UIC_CMD_DME_HIBER_EXIT) {
1540 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1541 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1542 exynos_ufs_ungate_clks(ufs);
1543
1544 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1545 static const unsigned int granularity_tbl[] = {
1546 1, 4, 8, 16, 32, 100
1547 };
1548 int h8_time = attr->pa_hibern8time *
1549 granularity_tbl[attr->pa_granularity - 1];
1550 unsigned long us;
1551 s64 delta;
1552
1553 do {
1554 delta = h8_time - ktime_us_delta(ktime_get(),
1555 ufs->entry_hibern8_t);
1556 if (delta <= 0)
1557 break;
1558
1559 us = min_t(s64, delta, USEC_PER_MSEC);
1560 if (us >= 10)
1561 usleep_range(us, us + 10);
1562 } while (1);
1563 }
1564 }
1565 }
1566
exynos_ufs_post_hibern8(struct ufs_hba * hba,enum uic_cmd_dme cmd)1567 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd)
1568 {
1569 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1570
1571 if (cmd == UIC_CMD_DME_HIBER_EXIT) {
1572 u32 cur_mode = 0;
1573 u32 pwrmode;
1574
1575 if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1576 pwrmode = FAST_MODE;
1577 else
1578 pwrmode = SLOW_MODE;
1579
1580 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
1581 if (cur_mode != (pwrmode << 4 | pwrmode)) {
1582 dev_warn(hba->dev, "%s: power mode change\n", __func__);
1583 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
1584 hba->pwr_info.pwr_tx = cur_mode & 0xf;
1585 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
1586 }
1587
1588 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1589 exynos_ufs_establish_connt(ufs);
1590 } else if (cmd == UIC_CMD_DME_HIBER_ENTER) {
1591 ufs->entry_hibern8_t = ktime_get();
1592 exynos_ufs_gate_clks(ufs);
1593 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1594 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1595 }
1596 }
1597
exynos_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1598 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
1599 enum ufs_notify_change_status status)
1600 {
1601 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1602 int ret = 0;
1603
1604 switch (status) {
1605 case PRE_CHANGE:
1606 /*
1607 * The maximum segment size must be set after scsi_host_alloc()
1608 * has been called and before LUN scanning starts
1609 * (ufshcd_async_scan()). Note: this callback may also be called
1610 * from other functions than ufshcd_init().
1611 */
1612 hba->host->max_segment_size = DATA_UNIT_SIZE;
1613
1614 if (ufs->drv_data->pre_hce_enable) {
1615 ret = ufs->drv_data->pre_hce_enable(ufs);
1616 if (ret)
1617 return ret;
1618 }
1619
1620 ret = exynos_ufs_host_reset(hba);
1621 if (ret)
1622 return ret;
1623 exynos_ufs_dev_hw_reset(hba);
1624 break;
1625 case POST_CHANGE:
1626 exynos_ufs_calc_pwm_clk_div(ufs);
1627 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1628 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1629
1630 if (ufs->drv_data->post_hce_enable)
1631 ret = ufs->drv_data->post_hce_enable(ufs);
1632
1633 break;
1634 }
1635
1636 return ret;
1637 }
1638
exynos_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1639 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba,
1640 enum ufs_notify_change_status status)
1641 {
1642 int ret = 0;
1643
1644 switch (status) {
1645 case PRE_CHANGE:
1646 ret = exynos_ufs_pre_link(hba);
1647 break;
1648 case POST_CHANGE:
1649 ret = exynos_ufs_post_link(hba);
1650 break;
1651 }
1652
1653 return ret;
1654 }
1655
exynos_ufs_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1656 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba,
1657 enum ufs_notify_change_status status,
1658 struct ufs_pa_layer_attr *dev_max_params,
1659 struct ufs_pa_layer_attr *dev_req_params)
1660 {
1661 int ret = 0;
1662
1663 switch (status) {
1664 case PRE_CHANGE:
1665 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params,
1666 dev_req_params);
1667 break;
1668 case POST_CHANGE:
1669 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params);
1670 break;
1671 }
1672
1673 return ret;
1674 }
1675
exynos_ufs_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme cmd,enum ufs_notify_change_status notify)1676 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba,
1677 enum uic_cmd_dme cmd,
1678 enum ufs_notify_change_status notify)
1679 {
1680 switch ((u8)notify) {
1681 case PRE_CHANGE:
1682 exynos_ufs_pre_hibern8(hba, cmd);
1683 break;
1684 case POST_CHANGE:
1685 exynos_ufs_post_hibern8(hba, cmd);
1686 break;
1687 }
1688 }
1689
gs101_ufs_suspend(struct exynos_ufs * ufs)1690 static int gs101_ufs_suspend(struct exynos_ufs *ufs)
1691 {
1692 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1693 return 0;
1694 }
1695
exynos_ufs_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)1696 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1697 enum ufs_notify_change_status status)
1698 {
1699 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1700
1701 if (status == PRE_CHANGE)
1702 return 0;
1703
1704 if (ufs->drv_data->suspend)
1705 ufs->drv_data->suspend(ufs);
1706
1707 if (!ufshcd_is_link_active(hba))
1708 phy_power_off(ufs->phy);
1709
1710 return 0;
1711 }
1712
exynos_ufs_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1713 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1714 {
1715 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1716
1717 if (!ufshcd_is_link_active(hba))
1718 phy_power_on(ufs->phy);
1719
1720 exynos_ufs_config_smu(ufs);
1721 exynos_ufs_fmp_resume(hba);
1722 return 0;
1723 }
1724
exynosauto_ufs_vh_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1725 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba,
1726 enum ufs_notify_change_status status)
1727 {
1728 if (status == POST_CHANGE) {
1729 ufshcd_set_link_active(hba);
1730 ufshcd_set_ufs_dev_active(hba);
1731 }
1732
1733 return 0;
1734 }
1735
exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba * hba)1736 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba)
1737 {
1738 u32 mbox;
1739 ktime_t start, stop;
1740
1741 start = ktime_get();
1742 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS));
1743
1744 do {
1745 mbox = ufshcd_readl(hba, PH2VH_MBOX);
1746 /* TODO: Mailbox message protocols between the PH and VHs are
1747 * not implemented yet. This will be supported later
1748 */
1749 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY)
1750 return 0;
1751
1752 usleep_range(40, 50);
1753 } while (ktime_before(ktime_get(), stop));
1754
1755 return -ETIME;
1756 }
1757
exynosauto_ufs_vh_init(struct ufs_hba * hba)1758 static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
1759 {
1760 struct device *dev = hba->dev;
1761 struct platform_device *pdev = to_platform_device(dev);
1762 struct exynos_ufs *ufs;
1763 int ret;
1764
1765 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1766 if (!ufs)
1767 return -ENOMEM;
1768
1769 /* exynos-specific hci */
1770 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1771 if (IS_ERR(ufs->reg_hci)) {
1772 dev_err(dev, "cannot ioremap for hci vendor register\n");
1773 return PTR_ERR(ufs->reg_hci);
1774 }
1775
1776 ret = exynosauto_ufs_vh_wait_ph_ready(hba);
1777 if (ret)
1778 return ret;
1779
1780 ufs->drv_data = device_get_match_data(dev);
1781 if (!ufs->drv_data)
1782 return -ENODEV;
1783
1784 exynos_ufs_priv_init(hba, ufs);
1785
1786 return 0;
1787 }
1788
fsd_ufs_pre_link(struct exynos_ufs * ufs)1789 static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
1790 {
1791 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1792 struct ufs_hba *hba = ufs->hba;
1793 int i;
1794
1795 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off),
1796 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1797 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
1798 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1799
1800 for_each_ufs_tx_lane(ufs, i) {
1801 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
1802 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1803 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
1804 }
1805
1806 for_each_ufs_rx_lane(ufs, i) {
1807 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
1808 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1809 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
1810 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
1811 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
1812 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
1813 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
1814 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
1815 }
1816
1817 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1818 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
1819
1820 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
1821 0x2e820183);
1822 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
1823
1824 exynos_ufs_establish_connt(ufs);
1825
1826 return 0;
1827 }
1828
fsd_ufs_post_link(struct exynos_ufs * ufs)1829 static int fsd_ufs_post_link(struct exynos_ufs *ufs)
1830 {
1831 int i;
1832 struct ufs_hba *hba = ufs->hba;
1833 u32 hw_cap_min_tactivate;
1834 u32 peer_rx_min_actv_time_cap;
1835 u32 max_rx_hibern8_time_cap;
1836
1837 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
1838 &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
1839 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
1840 &peer_rx_min_actv_time_cap); /* PA_TActivate */
1841 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1842 &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
1843
1844 if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
1845 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1846 peer_rx_min_actv_time_cap + 1);
1847 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1);
1848
1849 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01);
1850 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA);
1851 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00);
1852
1853 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1854
1855 for_each_ufs_rx_lane(ufs, i) {
1856 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
1857 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
1858 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
1859 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
1860 }
1861
1862 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1863
1864 return 0;
1865 }
1866
fsd_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)1867 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
1868 struct ufs_pa_layer_attr *pwr)
1869 {
1870 struct ufs_hba *hba = ufs->hba;
1871
1872 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
1873 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
1874 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
1875 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
1876 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
1877
1878 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
1879 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
1880 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
1881
1882 return 0;
1883 }
1884
get_mclk_period_unipro_18(struct exynos_ufs * ufs)1885 static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs)
1886 {
1887 return (16 * 1000 * 1000000UL / ufs->mclk_rate);
1888 }
1889
gs101_ufs_pre_link(struct exynos_ufs * ufs)1890 static int gs101_ufs_pre_link(struct exynos_ufs *ufs)
1891 {
1892 struct ufs_hba *hba = ufs->hba;
1893 int i;
1894 u32 tx_line_reset_period, rx_line_reset_period;
1895
1896 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate)
1897 / NSEC_PER_MSEC;
1898 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate)
1899 / NSEC_PER_MSEC;
1900
1901 unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD);
1902
1903 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1904
1905 for_each_ufs_rx_lane(ufs, i) {
1906 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
1907 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1908 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
1909 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
1910 (rx_line_reset_period >> 16) & 0xFF);
1911 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
1912 (rx_line_reset_period >> 8) & 0xFF);
1913 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
1914 (rx_line_reset_period) & 0xFF);
1915 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69);
1916 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
1917 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
1918 }
1919
1920 for_each_ufs_tx_lane(ufs, i) {
1921 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
1922 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1923 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
1924 0x02);
1925 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
1926 (tx_line_reset_period >> 16) & 0xFF);
1927 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
1928 (tx_line_reset_period >> 8) & 0xFF);
1929 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
1930 (tx_line_reset_period) & 0xFF);
1931 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1);
1932 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0);
1933 }
1934
1935 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1936 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
1937 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0);
1938 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1);
1939 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1);
1940 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
1941 ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000);
1942
1943 return 0;
1944 }
1945
gs101_ufs_post_link(struct exynos_ufs * ufs)1946 static int gs101_ufs_post_link(struct exynos_ufs *ufs)
1947 {
1948 struct ufs_hba *hba = ufs->hba;
1949
1950 exynos_ufs_enable_dbg_mode(hba);
1951 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8);
1952 exynos_ufs_disable_dbg_mode(hba);
1953
1954 return 0;
1955 }
1956
gs101_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)1957 static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs,
1958 struct ufs_pa_layer_attr *pwr)
1959 {
1960 struct ufs_hba *hba = ufs->hba;
1961
1962 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
1963 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
1964 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
1965 unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0);
1966 unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1);
1967 unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2);
1968 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
1969 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
1970 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
1971
1972 return 0;
1973 }
1974
1975 static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
1976 .name = "exynos_ufs",
1977 .init = exynos_ufs_init,
1978 .exit = exynos_ufs_exit,
1979 .hce_enable_notify = exynos_ufs_hce_enable_notify,
1980 .link_startup_notify = exynos_ufs_link_startup_notify,
1981 .pwr_change_notify = exynos_ufs_pwr_change_notify,
1982 .setup_clocks = exynos_ufs_setup_clocks,
1983 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req,
1984 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req,
1985 .hibern8_notify = exynos_ufs_hibern8_notify,
1986 .suspend = exynos_ufs_suspend,
1987 .resume = exynos_ufs_resume,
1988 .fill_crypto_prdt = exynos_ufs_fmp_fill_prdt,
1989 };
1990
1991 static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
1992 .name = "exynosauto_ufs_vh",
1993 .init = exynosauto_ufs_vh_init,
1994 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify,
1995 };
1996
exynos_ufs_probe(struct platform_device * pdev)1997 static int exynos_ufs_probe(struct platform_device *pdev)
1998 {
1999 int err;
2000 struct device *dev = &pdev->dev;
2001 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
2002 const struct exynos_ufs_drv_data *drv_data =
2003 device_get_match_data(dev);
2004
2005 if (drv_data && drv_data->vops)
2006 vops = drv_data->vops;
2007
2008 err = ufshcd_pltfrm_init(pdev, vops);
2009 if (err)
2010 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
2011
2012 return err;
2013 }
2014
exynos_ufs_remove(struct platform_device * pdev)2015 static void exynos_ufs_remove(struct platform_device *pdev)
2016 {
2017 ufshcd_pltfrm_remove(pdev);
2018 }
2019
2020 static struct exynos_ufs_uic_attr exynos7_uic_attr = {
2021 .tx_trailingclks = 0x10,
2022 .tx_dif_p_nsec = 3000000, /* unit: ns */
2023 .tx_dif_n_nsec = 1000000, /* unit: ns */
2024 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
2025 .tx_base_unit_nsec = 100000, /* unit: ns */
2026 .tx_gran_unit_nsec = 4000, /* unit: ns */
2027 .tx_sleep_cnt = 1000, /* unit: ns */
2028 .tx_min_activatetime = 0xa,
2029 .rx_filler_enable = 0x2,
2030 .rx_dif_p_nsec = 1000000, /* unit: ns */
2031 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
2032 .rx_base_unit_nsec = 100000, /* unit: ns */
2033 .rx_gran_unit_nsec = 4000, /* unit: ns */
2034 .rx_sleep_cnt = 1280, /* unit: ns */
2035 .rx_stall_cnt = 320, /* unit: ns */
2036 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
2037 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
2038 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
2039 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
2040 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
2041 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
2042 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD,
2043 .pa_dbg_opt_suite1_val = 0x30103,
2044 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE,
2045 };
2046
2047 static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
2048 .uic_attr = &exynos7_uic_attr,
2049 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
2050 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
2051 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
2052 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
2053 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
2054 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
2055 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
2056 .iocc_mask = UFS_EXYNOSAUTO_SHARABLE,
2057 .drv_init = exynosauto_ufs_drv_init,
2058 .post_hce_enable = exynosauto_ufs_post_hce_enable,
2059 .pre_link = exynosauto_ufs_pre_link,
2060 .pre_pwr_change = exynosauto_ufs_pre_pwr_change,
2061 .post_pwr_change = exynosauto_ufs_post_pwr_change,
2062 };
2063
2064 static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = {
2065 .vops = &ufs_hba_exynosauto_vh_ops,
2066 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
2067 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
2068 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
2069 UFSHCI_QUIRK_BROKEN_HCE |
2070 UFSHCD_QUIRK_BROKEN_UIC_CMD |
2071 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION |
2072 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
2073 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
2074 };
2075
2076 static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
2077 .uic_attr = &exynos7_uic_attr,
2078 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
2079 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
2080 UFSHCI_QUIRK_BROKEN_HCE |
2081 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
2082 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
2083 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
2084 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
2085 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
2086 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
2087 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
2088 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
2089 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
2090 .pre_link = exynos7_ufs_pre_link,
2091 .post_link = exynos7_ufs_post_link,
2092 .pre_pwr_change = exynos7_ufs_pre_pwr_change,
2093 .post_pwr_change = exynos7_ufs_post_pwr_change,
2094 };
2095
2096 static struct exynos_ufs_uic_attr gs101_uic_attr = {
2097 .tx_trailingclks = 0xff,
2098 .tx_dif_p_nsec = 3000000, /* unit: ns */
2099 .tx_dif_n_nsec = 1000000, /* unit: ns */
2100 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
2101 .tx_base_unit_nsec = 100000, /* unit: ns */
2102 .tx_gran_unit_nsec = 4000, /* unit: ns */
2103 .tx_sleep_cnt = 1000, /* unit: ns */
2104 .tx_min_activatetime = 0xa,
2105 .rx_filler_enable = 0x2,
2106 .rx_dif_p_nsec = 1000000, /* unit: ns */
2107 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
2108 .rx_base_unit_nsec = 100000, /* unit: ns */
2109 .rx_gran_unit_nsec = 4000, /* unit: ns */
2110 .rx_sleep_cnt = 1280, /* unit: ns */
2111 .rx_stall_cnt = 320, /* unit: ns */
2112 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
2113 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
2114 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
2115 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
2116 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
2117 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
2118 .pa_dbg_opt_suite1_val = 0x90913C1C,
2119 .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1,
2120 .pa_dbg_opt_suite2_val = 0xE01C115F,
2121 .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2,
2122 };
2123
2124 static struct exynos_ufs_uic_attr fsd_uic_attr = {
2125 .tx_trailingclks = 0x10,
2126 .tx_dif_p_nsec = 3000000, /* unit: ns */
2127 .tx_dif_n_nsec = 1000000, /* unit: ns */
2128 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
2129 .tx_base_unit_nsec = 100000, /* unit: ns */
2130 .tx_gran_unit_nsec = 4000, /* unit: ns */
2131 .tx_sleep_cnt = 1000, /* unit: ns */
2132 .tx_min_activatetime = 0xa,
2133 .rx_filler_enable = 0x2,
2134 .rx_dif_p_nsec = 1000000, /* unit: ns */
2135 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
2136 .rx_base_unit_nsec = 100000, /* unit: ns */
2137 .rx_gran_unit_nsec = 4000, /* unit: ns */
2138 .rx_sleep_cnt = 1280, /* unit: ns */
2139 .rx_stall_cnt = 320, /* unit: ns */
2140 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
2141 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
2142 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
2143 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
2144 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
2145 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
2146 .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD,
2147 .pa_dbg_opt_suite1_val = 0x2E820183,
2148 .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE,
2149 };
2150
2151 static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
2152 .uic_attr = &fsd_uic_attr,
2153 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
2154 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
2155 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
2156 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
2157 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
2158 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
2159 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
2160 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
2161 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
2162 .pre_link = fsd_ufs_pre_link,
2163 .post_link = fsd_ufs_post_link,
2164 .pre_pwr_change = fsd_ufs_pre_pwr_change,
2165 };
2166
2167 static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
2168 .uic_attr = &gs101_uic_attr,
2169 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
2170 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
2171 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
2172 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
2173 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
2174 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
2175 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
2176 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
2177 EXYNOS_UFS_OPT_UFSPR_SECURE |
2178 EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
2179 .iocc_mask = UFS_GS101_SHARABLE,
2180 .drv_init = gs101_ufs_drv_init,
2181 .pre_link = gs101_ufs_pre_link,
2182 .post_link = gs101_ufs_post_link,
2183 .pre_pwr_change = gs101_ufs_pre_pwr_change,
2184 .suspend = gs101_ufs_suspend,
2185 };
2186
2187 static const struct of_device_id exynos_ufs_of_match[] = {
2188 { .compatible = "google,gs101-ufs",
2189 .data = &gs101_ufs_drvs },
2190 { .compatible = "samsung,exynos7-ufs",
2191 .data = &exynos_ufs_drvs },
2192 { .compatible = "samsung,exynosautov9-ufs",
2193 .data = &exynosauto_ufs_drvs },
2194 { .compatible = "samsung,exynosautov9-ufs-vh",
2195 .data = &exynosauto_ufs_vh_drvs },
2196 { .compatible = "tesla,fsd-ufs",
2197 .data = &fsd_ufs_drvs },
2198 {},
2199 };
2200 MODULE_DEVICE_TABLE(of, exynos_ufs_of_match);
2201
2202 static const struct dev_pm_ops exynos_ufs_pm_ops = {
2203 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
2204 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
2205 .prepare = ufshcd_suspend_prepare,
2206 .complete = ufshcd_resume_complete,
2207 };
2208
2209 static struct platform_driver exynos_ufs_pltform = {
2210 .probe = exynos_ufs_probe,
2211 .remove_new = exynos_ufs_remove,
2212 .driver = {
2213 .name = "exynos-ufshc",
2214 .pm = &exynos_ufs_pm_ops,
2215 .of_match_table = exynos_ufs_of_match,
2216 },
2217 };
2218 module_platform_driver(exynos_ufs_pltform);
2219
2220 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
2221 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
2222 MODULE_DESCRIPTION("Exynos UFS HCI Driver");
2223 MODULE_LICENSE("GPL v2");
2224