1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/devfreq.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interconnect.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
18 #include <linux/units.h>
19
20 #include <soc/qcom/ice.h>
21
22 #include <ufs/ufshcd.h>
23 #include <ufs/ufshci.h>
24 #include <ufs/ufs_quirks.h>
25 #include <ufs/unipro.h>
26 #include "ufshcd-pltfrm.h"
27 #include "ufs-qcom.h"
28
29 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
30 #define MCQ_QCFGPTR_UNIT 0x200
31 #define MCQ_SQATTR_OFFSET(c) \
32 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
33 #define MCQ_QCFG_SIZE 0x40
34
35 enum {
36 TSTBUS_UAWM,
37 TSTBUS_UARM,
38 TSTBUS_TXUC,
39 TSTBUS_RXUC,
40 TSTBUS_DFC,
41 TSTBUS_TRLUT,
42 TSTBUS_TMRLUT,
43 TSTBUS_OCSC,
44 TSTBUS_UTP_HCI,
45 TSTBUS_COMBINED,
46 TSTBUS_WRAPPER,
47 TSTBUS_UNIPRO,
48 TSTBUS_MAX,
49 };
50
51 #define QCOM_UFS_MAX_GEAR 5
52 #define QCOM_UFS_MAX_LANE 2
53
54 enum {
55 MODE_MIN,
56 MODE_PWM,
57 MODE_HS_RA,
58 MODE_HS_RB,
59 MODE_MAX,
60 };
61
62 static const struct __ufs_qcom_bw_table {
63 u32 mem_bw;
64 u32 cfg_bw;
65 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
66 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
67 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
68 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
69 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
70 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
71 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 },
72 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
73 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
74 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
75 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
76 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 },
77 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
78 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
79 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
80 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
81 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
82 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
83 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
84 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
85 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
86 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
87 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
88 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
89 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
90 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
91 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
92 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
93 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
94 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
95 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
96 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
97 [MODE_MAX][0][0] = { 7643136, 819200 },
98 };
99
100 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
101 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq);
102
rcdev_to_ufs_host(struct reset_controller_dev * rcd)103 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
104 {
105 return container_of(rcd, struct ufs_qcom_host, rcdev);
106 }
107
108 #ifdef CONFIG_SCSI_UFS_CRYPTO
109
ufs_qcom_ice_enable(struct ufs_qcom_host * host)110 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
111 {
112 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
113 qcom_ice_enable(host->ice);
114 }
115
ufs_qcom_ice_init(struct ufs_qcom_host * host)116 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
117 {
118 struct ufs_hba *hba = host->hba;
119 struct device *dev = hba->dev;
120 struct qcom_ice *ice;
121
122 ice = devm_of_qcom_ice_get(dev);
123 if (ice == ERR_PTR(-EOPNOTSUPP)) {
124 dev_warn(dev, "Disabling inline encryption support\n");
125 ice = NULL;
126 }
127
128 if (IS_ERR_OR_NULL(ice))
129 return PTR_ERR_OR_ZERO(ice);
130
131 host->ice = ice;
132 hba->caps |= UFSHCD_CAP_CRYPTO;
133
134 return 0;
135 }
136
ufs_qcom_ice_resume(struct ufs_qcom_host * host)137 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
138 {
139 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
140 return qcom_ice_resume(host->ice);
141
142 return 0;
143 }
144
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)145 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
146 {
147 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
148 return qcom_ice_suspend(host->ice);
149
150 return 0;
151 }
152
ufs_qcom_ice_program_key(struct ufs_hba * hba,const union ufs_crypto_cfg_entry * cfg,int slot)153 static int ufs_qcom_ice_program_key(struct ufs_hba *hba,
154 const union ufs_crypto_cfg_entry *cfg,
155 int slot)
156 {
157 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
158 union ufs_crypto_cap_entry cap;
159
160 if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE))
161 return qcom_ice_evict_key(host->ice, slot);
162
163 /* Only AES-256-XTS has been tested so far. */
164 cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
165 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
166 cap.key_size != UFS_CRYPTO_KEY_SIZE_256)
167 return -EOPNOTSUPP;
168
169 return qcom_ice_program_key(host->ice,
170 QCOM_ICE_CRYPTO_ALG_AES_XTS,
171 QCOM_ICE_CRYPTO_KEY_SIZE_256,
172 cfg->crypto_key,
173 cfg->data_unit_size, slot);
174 }
175
176 #else
177
178 #define ufs_qcom_ice_program_key NULL
179
ufs_qcom_ice_enable(struct ufs_qcom_host * host)180 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
181 {
182 }
183
ufs_qcom_ice_init(struct ufs_qcom_host * host)184 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
185 {
186 return 0;
187 }
188
ufs_qcom_ice_resume(struct ufs_qcom_host * host)189 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
190 {
191 return 0;
192 }
193
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)194 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
195 {
196 return 0;
197 }
198 #endif
199
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)200 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
201 {
202 if (!host->is_lane_clks_enabled)
203 return;
204
205 clk_bulk_disable_unprepare(host->num_clks, host->clks);
206
207 host->is_lane_clks_enabled = false;
208 }
209
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)210 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
211 {
212 int err;
213
214 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
215 if (err)
216 return err;
217
218 host->is_lane_clks_enabled = true;
219
220 return 0;
221 }
222
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)223 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
224 {
225 int err;
226 struct device *dev = host->hba->dev;
227
228 if (has_acpi_companion(dev))
229 return 0;
230
231 err = devm_clk_bulk_get_all(dev, &host->clks);
232 if (err <= 0)
233 return err;
234
235 host->num_clks = err;
236
237 return 0;
238 }
239
ufs_qcom_check_hibern8(struct ufs_hba * hba)240 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
241 {
242 int err;
243 u32 tx_fsm_val;
244 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
245
246 do {
247 err = ufshcd_dme_get(hba,
248 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
249 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
250 &tx_fsm_val);
251 if (err || tx_fsm_val == TX_FSM_HIBERN8)
252 break;
253
254 /* sleep for max. 200us */
255 usleep_range(100, 200);
256 } while (time_before(jiffies, timeout));
257
258 /*
259 * we might have scheduled out for long during polling so
260 * check the state again.
261 */
262 if (time_after(jiffies, timeout))
263 err = ufshcd_dme_get(hba,
264 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
265 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
266 &tx_fsm_val);
267
268 if (err) {
269 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
270 __func__, err);
271 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
272 err = tx_fsm_val;
273 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
274 __func__, err);
275 }
276
277 return err;
278 }
279
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)280 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
281 {
282 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
283
284 if (host->hw_ver.major >= 0x05)
285 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
286 }
287
288 /*
289 * ufs_qcom_host_reset - reset host controller and PHY
290 */
ufs_qcom_host_reset(struct ufs_hba * hba)291 static int ufs_qcom_host_reset(struct ufs_hba *hba)
292 {
293 int ret;
294 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
295 bool reenable_intr;
296
297 if (!host->core_reset)
298 return 0;
299
300 reenable_intr = hba->is_irq_enabled;
301 ufshcd_disable_irq(hba);
302
303 ret = reset_control_assert(host->core_reset);
304 if (ret) {
305 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
306 __func__, ret);
307 return ret;
308 }
309
310 /*
311 * The hardware requirement for delay between assert/deassert
312 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
313 * ~125us (4/32768). To be on the safe side add 200us delay.
314 */
315 usleep_range(200, 210);
316
317 ret = reset_control_deassert(host->core_reset);
318 if (ret) {
319 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
320 __func__, ret);
321 return ret;
322 }
323
324 usleep_range(1000, 1100);
325
326 if (reenable_intr)
327 ufshcd_enable_irq(hba);
328
329 return 0;
330 }
331
ufs_qcom_get_hs_gear(struct ufs_hba * hba)332 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
333 {
334 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
335
336 if (host->hw_ver.major >= 0x4)
337 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
338
339 /* Default is HS-G3 */
340 return UFS_HS_G3;
341 }
342
ufs_qcom_power_up_sequence(struct ufs_hba * hba)343 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
344 {
345 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
346 struct ufs_host_params *host_params = &host->host_params;
347 struct phy *phy = host->generic_phy;
348 enum phy_mode mode;
349 int ret;
350
351 /*
352 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
353 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
354 * so that the subsequent power mode change shall stick to Rate-A.
355 */
356 if (host->hw_ver.major == 0x5) {
357 if (host->phy_gear == UFS_HS_G5)
358 host_params->hs_rate = PA_HS_MODE_A;
359 else
360 host_params->hs_rate = PA_HS_MODE_B;
361 }
362
363 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
364
365 /* Reset UFS Host Controller and PHY */
366 ret = ufs_qcom_host_reset(hba);
367 if (ret)
368 return ret;
369
370 if (phy->power_count)
371 phy_power_off(phy);
372
373
374 /* phy initialization - calibrate the phy */
375 ret = phy_init(phy);
376 if (ret) {
377 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
378 __func__, ret);
379 return ret;
380 }
381
382 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
383 if (ret)
384 goto out_disable_phy;
385
386 /* power on phy - start serdes and phy's power and clocks */
387 ret = phy_power_on(phy);
388 if (ret) {
389 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
390 __func__, ret);
391 goto out_disable_phy;
392 }
393
394 ufs_qcom_select_unipro_mode(host);
395
396 return 0;
397
398 out_disable_phy:
399 phy_exit(phy);
400
401 return ret;
402 }
403
404 /*
405 * The UTP controller has a number of internal clock gating cells (CGCs).
406 * Internal hardware sub-modules within the UTP controller control the CGCs.
407 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
408 * in a specific operation, UTP controller CGCs are by default disabled and
409 * this function enables them (after every UFS link startup) to save some power
410 * leakage.
411 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)412 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
413 {
414 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
415 REG_UFS_CFG2);
416
417 /* Ensure that HW clock gating is enabled before next operations */
418 ufshcd_readl(hba, REG_UFS_CFG2);
419 }
420
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)421 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
422 enum ufs_notify_change_status status)
423 {
424 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
425 int err;
426
427 switch (status) {
428 case PRE_CHANGE:
429 err = ufs_qcom_power_up_sequence(hba);
430 if (err)
431 return err;
432
433 /*
434 * The PHY PLL output is the source of tx/rx lane symbol
435 * clocks, hence, enable the lane clocks only after PHY
436 * is initialized.
437 */
438 err = ufs_qcom_enable_lane_clks(host);
439 break;
440 case POST_CHANGE:
441 /* check if UFS PHY moved from DISABLED to HIBERN8 */
442 err = ufs_qcom_check_hibern8(hba);
443 ufs_qcom_enable_hw_clk_gating(hba);
444 ufs_qcom_ice_enable(host);
445 break;
446 default:
447 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
448 err = -EINVAL;
449 break;
450 }
451 return err;
452 }
453
454 /**
455 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
456 *
457 * @hba: host controller instance
458 * @gear: Current operating gear
459 * @hs: current power mode
460 * @rate: current operating rate (A or B)
461 * @update_link_startup_timer: indicate if link_start ongoing
462 * @is_pre_scale_up: flag to check if pre scale up condition.
463 * Return: zero for success and non-zero in case of a failure.
464 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,u32 gear,u32 hs,u32 rate,bool update_link_startup_timer,bool is_pre_scale_up)465 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
466 u32 hs, u32 rate, bool update_link_startup_timer,
467 bool is_pre_scale_up)
468 {
469 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
470 struct ufs_clk_info *clki;
471 unsigned long core_clk_rate = 0;
472 u32 core_clk_cycles_per_us;
473
474 /*
475 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
476 * Aggregation logic.
477 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
478 * controller V4.0.0 onwards.
479 */
480 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
481 return 0;
482
483 if (gear == 0) {
484 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
485 return -EINVAL;
486 }
487
488 list_for_each_entry(clki, &hba->clk_list_head, list) {
489 if (!strcmp(clki->name, "core_clk")) {
490 if (is_pre_scale_up)
491 core_clk_rate = clki->max_freq;
492 else
493 core_clk_rate = clk_get_rate(clki->clk);
494 break;
495 }
496
497 }
498
499 /* If frequency is smaller than 1MHz, set to 1MHz */
500 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
501 core_clk_rate = DEFAULT_CLK_RATE_HZ;
502
503 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
504 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
505 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
506 /*
507 * make sure above write gets applied before we return from
508 * this function.
509 */
510 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
511 }
512
513 return 0;
514 }
515
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)516 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
517 enum ufs_notify_change_status status)
518 {
519 int err = 0;
520
521 switch (status) {
522 case PRE_CHANGE:
523 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
524 0, true, false)) {
525 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
526 __func__);
527 return -EINVAL;
528 }
529
530 err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX);
531 if (err)
532 dev_err(hba->dev, "cfg core clk ctrl failed\n");
533 /*
534 * Some UFS devices (and may be host) have issues if LCC is
535 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
536 * before link startup which will make sure that both host
537 * and device TX LCC are disabled once link startup is
538 * completed.
539 */
540 err = ufshcd_disable_host_tx_lcc(hba);
541
542 break;
543 default:
544 break;
545 }
546
547 return err;
548 }
549
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)550 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
551 {
552 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
553
554 /* reset gpio is optional */
555 if (!host->device_reset)
556 return;
557
558 gpiod_set_value_cansleep(host->device_reset, asserted);
559 }
560
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)561 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
562 enum ufs_notify_change_status status)
563 {
564 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
565 struct phy *phy = host->generic_phy;
566
567 if (status == PRE_CHANGE)
568 return 0;
569
570 if (ufs_qcom_is_link_off(hba)) {
571 /*
572 * Disable the tx/rx lane symbol clocks before PHY is
573 * powered down as the PLL source should be disabled
574 * after downstream clocks are disabled.
575 */
576 ufs_qcom_disable_lane_clks(host);
577 phy_power_off(phy);
578
579 /* reset the connected UFS device during power down */
580 ufs_qcom_device_reset_ctrl(hba, true);
581
582 } else if (!ufs_qcom_is_link_active(hba)) {
583 ufs_qcom_disable_lane_clks(host);
584 }
585
586 return ufs_qcom_ice_suspend(host);
587 }
588
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)589 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
590 {
591 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
592 struct phy *phy = host->generic_phy;
593 int err;
594
595 if (ufs_qcom_is_link_off(hba)) {
596 err = phy_power_on(phy);
597 if (err) {
598 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
599 __func__, err);
600 return err;
601 }
602
603 err = ufs_qcom_enable_lane_clks(host);
604 if (err)
605 return err;
606
607 } else if (!ufs_qcom_is_link_active(hba)) {
608 err = ufs_qcom_enable_lane_clks(host);
609 if (err)
610 return err;
611 }
612
613 return ufs_qcom_ice_resume(host);
614 }
615
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)616 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
617 {
618 if (host->dev_ref_clk_ctrl_mmio &&
619 (enable ^ host->is_dev_ref_clk_enabled)) {
620 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
621
622 if (enable)
623 temp |= host->dev_ref_clk_en_mask;
624 else
625 temp &= ~host->dev_ref_clk_en_mask;
626
627 /*
628 * If we are here to disable this clock it might be immediately
629 * after entering into hibern8 in which case we need to make
630 * sure that device ref_clk is active for specific time after
631 * hibern8 enter.
632 */
633 if (!enable) {
634 unsigned long gating_wait;
635
636 gating_wait = host->hba->dev_info.clk_gating_wait_us;
637 if (!gating_wait) {
638 udelay(1);
639 } else {
640 /*
641 * bRefClkGatingWaitTime defines the minimum
642 * time for which the reference clock is
643 * required by device during transition from
644 * HS-MODE to LS-MODE or HIBERN8 state. Give it
645 * more delay to be on the safe side.
646 */
647 gating_wait += 10;
648 usleep_range(gating_wait, gating_wait + 10);
649 }
650 }
651
652 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
653
654 /*
655 * Make sure the write to ref_clk reaches the destination and
656 * not stored in a Write Buffer (WB).
657 */
658 readl(host->dev_ref_clk_ctrl_mmio);
659
660 /*
661 * If we call hibern8 exit after this, we need to make sure that
662 * device ref_clk is stable for at least 1us before the hibern8
663 * exit command.
664 */
665 if (enable)
666 udelay(1);
667
668 host->is_dev_ref_clk_enabled = enable;
669 }
670 }
671
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)672 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
673 {
674 struct device *dev = host->hba->dev;
675 int ret;
676
677 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
678 if (ret < 0) {
679 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
680 return ret;
681 }
682
683 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
684 if (ret < 0) {
685 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
686 return ret;
687 }
688
689 return 0;
690 }
691
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)692 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
693 {
694 struct ufs_pa_layer_attr *p = &host->dev_req_params;
695 int gear = max_t(u32, p->gear_rx, p->gear_tx);
696 int lane = max_t(u32, p->lane_rx, p->lane_tx);
697
698 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR,
699 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n",
700 gear, QCOM_UFS_MAX_GEAR))
701 gear = QCOM_UFS_MAX_GEAR;
702
703 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE,
704 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n",
705 lane, QCOM_UFS_MAX_LANE))
706 lane = QCOM_UFS_MAX_LANE;
707
708 if (ufshcd_is_hs_mode(p)) {
709 if (p->hs_rate == PA_HS_MODE_B)
710 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
711 else
712 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
713 } else {
714 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
715 }
716 }
717
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)718 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
719 {
720 struct __ufs_qcom_bw_table bw_table;
721
722 bw_table = ufs_qcom_get_bw_table(host);
723
724 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
725 }
726
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)727 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
728 enum ufs_notify_change_status status,
729 struct ufs_pa_layer_attr *dev_max_params,
730 struct ufs_pa_layer_attr *dev_req_params)
731 {
732 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
733 struct ufs_host_params *host_params = &host->host_params;
734 int ret = 0;
735
736 if (!dev_req_params) {
737 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
738 return -EINVAL;
739 }
740
741 switch (status) {
742 case PRE_CHANGE:
743 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
744 if (ret) {
745 dev_err(hba->dev, "%s: failed to determine capabilities\n",
746 __func__);
747 return ret;
748 }
749
750 /*
751 * During UFS driver probe, always update the PHY gear to match the negotiated
752 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
753 * the second init can program the optimal PHY settings. This allows one to start
754 * the first init with either the minimum or the maximum support gear.
755 */
756 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
757 /*
758 * Skip REINIT if the negotiated gear matches with the
759 * initial phy_gear. Otherwise, update the phy_gear to
760 * program the optimal gear setting during REINIT.
761 */
762 if (host->phy_gear == dev_req_params->gear_tx)
763 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
764 else
765 host->phy_gear = dev_req_params->gear_tx;
766 }
767
768 /* enable the device ref clock before changing to HS mode */
769 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
770 ufshcd_is_hs_mode(dev_req_params))
771 ufs_qcom_dev_ref_clk_ctrl(host, true);
772
773 if (host->hw_ver.major >= 0x4) {
774 ufshcd_dme_configure_adapt(hba,
775 dev_req_params->gear_tx,
776 PA_INITIAL_ADAPT);
777 }
778 break;
779 case POST_CHANGE:
780 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
781 dev_req_params->pwr_rx,
782 dev_req_params->hs_rate, false, false)) {
783 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
784 __func__);
785 /*
786 * we return error code at the end of the routine,
787 * but continue to configure UFS_PHY_TX_LANE_ENABLE
788 * and bus voting as usual
789 */
790 ret = -EINVAL;
791 }
792
793 /* cache the power mode parameters to use internally */
794 memcpy(&host->dev_req_params,
795 dev_req_params, sizeof(*dev_req_params));
796
797 ufs_qcom_icc_update_bw(host);
798
799 /* disable the device ref clock if entered PWM mode */
800 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
801 !ufshcd_is_hs_mode(dev_req_params))
802 ufs_qcom_dev_ref_clk_ctrl(host, false);
803 break;
804 default:
805 ret = -EINVAL;
806 break;
807 }
808
809 return ret;
810 }
811
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)812 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
813 {
814 int err;
815 u32 pa_vs_config_reg1;
816
817 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
818 &pa_vs_config_reg1);
819 if (err)
820 return err;
821
822 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
823 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
824 (pa_vs_config_reg1 | (1 << 12)));
825 }
826
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)827 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
828 {
829 int err = 0;
830
831 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
832 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
833
834 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
835 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
836
837 return err;
838 }
839
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)840 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
841 {
842 return ufshci_version(2, 0);
843 }
844
845 /**
846 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
847 * @hba: host controller instance
848 *
849 * QCOM UFS host controller might have some non standard behaviours (quirks)
850 * than what is specified by UFSHCI specification. Advertise all such
851 * quirks to standard UFS host controller driver so standard takes them into
852 * account.
853 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)854 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
855 {
856 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
857
858 if (host->hw_ver.major == 0x2)
859 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
860
861 if (host->hw_ver.major > 0x3)
862 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
863
864 if (of_device_is_compatible(hba->dev->of_node, "qcom,sm8550-ufshc"))
865 hba->quirks |= UFSHCD_QUIRK_BROKEN_LSDBS_CAP;
866 }
867
ufs_qcom_set_phy_gear(struct ufs_qcom_host * host)868 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
869 {
870 struct ufs_host_params *host_params = &host->host_params;
871 u32 val, dev_major;
872
873 /*
874 * Default to powering up the PHY to the max gear possible, which is
875 * backwards compatible with lower gears but not optimal from
876 * a power usage point of view. After device negotiation, if the
877 * gear is lower a reinit will be performed to program the PHY
878 * to the ideal gear for this combo of controller and device.
879 */
880 host->phy_gear = host_params->hs_tx_gear;
881
882 if (host->hw_ver.major < 0x4) {
883 /*
884 * These controllers only have one PHY init sequence,
885 * let's power up the PHY using that (the minimum supported
886 * gear, UFS_HS_G2).
887 */
888 host->phy_gear = UFS_HS_G2;
889 } else if (host->hw_ver.major >= 0x5) {
890 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
891 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
892
893 /*
894 * Since the UFS device version is populated, let's remove the
895 * REINIT quirk as the negotiated gear won't change during boot.
896 * So there is no need to do reinit.
897 */
898 if (dev_major != 0x0)
899 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
900
901 /*
902 * For UFS 3.1 device and older, power up the PHY using HS-G4
903 * PHY gear to save power.
904 */
905 if (dev_major > 0x0 && dev_major < 0x4)
906 host->phy_gear = UFS_HS_G4;
907 }
908 }
909
ufs_qcom_set_host_params(struct ufs_hba * hba)910 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
911 {
912 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
913 struct ufs_host_params *host_params = &host->host_params;
914
915 ufshcd_init_host_params(host_params);
916
917 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
918 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
919 }
920
ufs_qcom_set_caps(struct ufs_hba * hba)921 static void ufs_qcom_set_caps(struct ufs_hba *hba)
922 {
923 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
924 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
925 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
926 hba->caps |= UFSHCD_CAP_WB_EN;
927 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
928 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
929 }
930
931 /**
932 * ufs_qcom_setup_clocks - enables/disable clocks
933 * @hba: host controller instance
934 * @on: If true, enable clocks else disable them.
935 * @status: PRE_CHANGE or POST_CHANGE notify
936 *
937 * Return: 0 on success, non-zero on failure.
938 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)939 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
940 enum ufs_notify_change_status status)
941 {
942 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
943
944 /*
945 * In case ufs_qcom_init() is not yet done, simply ignore.
946 * This ufs_qcom_setup_clocks() shall be called from
947 * ufs_qcom_init() after init is done.
948 */
949 if (!host)
950 return 0;
951
952 switch (status) {
953 case PRE_CHANGE:
954 if (on) {
955 ufs_qcom_icc_update_bw(host);
956 } else {
957 if (!ufs_qcom_is_link_active(hba)) {
958 /* disable device ref_clk */
959 ufs_qcom_dev_ref_clk_ctrl(host, false);
960 }
961 }
962 break;
963 case POST_CHANGE:
964 if (on) {
965 /* enable the device ref clock for HS mode*/
966 if (ufshcd_is_hs_mode(&hba->pwr_info))
967 ufs_qcom_dev_ref_clk_ctrl(host, true);
968 } else {
969 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
970 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
971 }
972 break;
973 }
974
975 return 0;
976 }
977
978 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)979 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
980 {
981 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
982
983 ufs_qcom_assert_reset(host->hba);
984 /* provide 1ms delay to let the reset pulse propagate. */
985 usleep_range(1000, 1100);
986 return 0;
987 }
988
989 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)990 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
991 {
992 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
993
994 ufs_qcom_deassert_reset(host->hba);
995
996 /*
997 * after reset deassertion, phy will need all ref clocks,
998 * voltage, current to settle down before starting serdes.
999 */
1000 usleep_range(1000, 1100);
1001 return 0;
1002 }
1003
1004 static const struct reset_control_ops ufs_qcom_reset_ops = {
1005 .assert = ufs_qcom_reset_assert,
1006 .deassert = ufs_qcom_reset_deassert,
1007 };
1008
ufs_qcom_icc_init(struct ufs_qcom_host * host)1009 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1010 {
1011 struct device *dev = host->hba->dev;
1012 int ret;
1013
1014 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1015 if (IS_ERR(host->icc_ddr))
1016 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1017 "failed to acquire interconnect path\n");
1018
1019 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1020 if (IS_ERR(host->icc_cpu))
1021 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1022 "failed to acquire interconnect path\n");
1023
1024 /*
1025 * Set Maximum bandwidth vote before initializing the UFS controller and
1026 * device. Ideally, a minimal interconnect vote would suffice for the
1027 * initialization, but a max vote would allow faster initialization.
1028 */
1029 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1030 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1031 if (ret < 0)
1032 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1033
1034 return 0;
1035 }
1036
1037 /**
1038 * ufs_qcom_init - bind phy with controller
1039 * @hba: host controller instance
1040 *
1041 * Binds PHY with controller and powers up PHY enabling clocks
1042 * and regulators.
1043 *
1044 * Return: -EPROBE_DEFER if binding fails, returns negative error
1045 * on phy power up failure and returns zero on success.
1046 */
ufs_qcom_init(struct ufs_hba * hba)1047 static int ufs_qcom_init(struct ufs_hba *hba)
1048 {
1049 int err;
1050 struct device *dev = hba->dev;
1051 struct ufs_qcom_host *host;
1052 struct ufs_clk_info *clki;
1053
1054 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1055 if (!host)
1056 return -ENOMEM;
1057
1058 /* Make a two way bind between the qcom host and the hba */
1059 host->hba = hba;
1060 ufshcd_set_variant(hba, host);
1061
1062 /* Setup the optional reset control of HCI */
1063 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1064 if (IS_ERR(host->core_reset)) {
1065 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1066 "Failed to get reset control\n");
1067 goto out_variant_clear;
1068 }
1069
1070 /* Fire up the reset controller. Failure here is non-fatal. */
1071 host->rcdev.of_node = dev->of_node;
1072 host->rcdev.ops = &ufs_qcom_reset_ops;
1073 host->rcdev.owner = dev->driver->owner;
1074 host->rcdev.nr_resets = 1;
1075 err = devm_reset_controller_register(dev, &host->rcdev);
1076 if (err)
1077 dev_warn(dev, "Failed to register reset controller\n");
1078
1079 if (!has_acpi_companion(dev)) {
1080 host->generic_phy = devm_phy_get(dev, "ufsphy");
1081 if (IS_ERR(host->generic_phy)) {
1082 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1083 goto out_variant_clear;
1084 }
1085 }
1086
1087 err = ufs_qcom_icc_init(host);
1088 if (err)
1089 goto out_variant_clear;
1090
1091 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1092 GPIOD_OUT_HIGH);
1093 if (IS_ERR(host->device_reset)) {
1094 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1095 "Failed to acquire device reset gpio\n");
1096 goto out_variant_clear;
1097 }
1098
1099 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1100 &host->hw_ver.minor, &host->hw_ver.step);
1101
1102 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1103 host->dev_ref_clk_en_mask = BIT(26);
1104
1105 list_for_each_entry(clki, &hba->clk_list_head, list) {
1106 if (!strcmp(clki->name, "core_clk_unipro"))
1107 clki->keep_link_active = true;
1108 }
1109
1110 err = ufs_qcom_init_lane_clks(host);
1111 if (err)
1112 goto out_variant_clear;
1113
1114 ufs_qcom_set_caps(hba);
1115 ufs_qcom_advertise_quirks(hba);
1116 ufs_qcom_set_host_params(hba);
1117 ufs_qcom_set_phy_gear(host);
1118
1119 err = ufs_qcom_ice_init(host);
1120 if (err)
1121 goto out_variant_clear;
1122
1123 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1124
1125 ufs_qcom_get_default_testbus_cfg(host);
1126 err = ufs_qcom_testbus_config(host);
1127 if (err)
1128 /* Failure is non-fatal */
1129 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1130 __func__, err);
1131
1132 return 0;
1133
1134 out_variant_clear:
1135 ufshcd_set_variant(hba, NULL);
1136
1137 return err;
1138 }
1139
ufs_qcom_exit(struct ufs_hba * hba)1140 static void ufs_qcom_exit(struct ufs_hba *hba)
1141 {
1142 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1143
1144 ufs_qcom_disable_lane_clks(host);
1145 phy_power_off(host->generic_phy);
1146 phy_exit(host->generic_phy);
1147 }
1148
1149 /**
1150 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1151 *
1152 * @hba: host controller instance
1153 * @cycles_in_1us: No of cycles in 1us to be configured
1154 *
1155 * Returns error if dme get/set configuration for 40ns fails
1156 * and returns zero on success.
1157 */
ufs_qcom_set_clk_40ns_cycles(struct ufs_hba * hba,u32 cycles_in_1us)1158 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1159 u32 cycles_in_1us)
1160 {
1161 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1162 u32 cycles_in_40ns;
1163 u32 reg;
1164 int err;
1165
1166 /*
1167 * UFS host controller V4.0.0 onwards needs to program
1168 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1169 * frequency of unipro core clk of UFS host controller.
1170 */
1171 if (host->hw_ver.major < 4)
1172 return 0;
1173
1174 /*
1175 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1176 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1177 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1178 * specification expect to be 16. Hence use exact hardware spec
1179 * mandated value for cycles_in_40ns instead of calculating using
1180 * generic formulae.
1181 */
1182 switch (cycles_in_1us) {
1183 case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1184 cycles_in_40ns = 16;
1185 break;
1186 case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1187 cycles_in_40ns = 12;
1188 break;
1189 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1190 cycles_in_40ns = 8;
1191 break;
1192 case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1193 cycles_in_40ns = 6;
1194 break;
1195 case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1196 cycles_in_40ns = 4;
1197 break;
1198 case UNIPRO_CORE_CLK_FREQ_75_MHZ:
1199 cycles_in_40ns = 3;
1200 break;
1201 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1202 cycles_in_40ns = 2;
1203 break;
1204 default:
1205 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1206 cycles_in_1us);
1207 return -EINVAL;
1208 }
1209
1210 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®);
1211 if (err)
1212 return err;
1213
1214 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1215 reg |= cycles_in_40ns;
1216
1217 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1218 }
1219
ufs_qcom_set_core_clk_ctrl(struct ufs_hba * hba,unsigned long freq)1220 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq)
1221 {
1222 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1223 struct list_head *head = &hba->clk_list_head;
1224 struct ufs_clk_info *clki;
1225 u32 cycles_in_1us = 0;
1226 u32 core_clk_ctrl_reg;
1227 int err;
1228
1229 list_for_each_entry(clki, head, list) {
1230 if (!IS_ERR_OR_NULL(clki->clk) &&
1231 !strcmp(clki->name, "core_clk_unipro")) {
1232 if (!clki->max_freq)
1233 cycles_in_1us = 150; /* default for backwards compatibility */
1234 else if (freq == ULONG_MAX)
1235 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ);
1236 else
1237 cycles_in_1us = ceil(freq, HZ_PER_MHZ);
1238
1239 break;
1240 }
1241 }
1242
1243 err = ufshcd_dme_get(hba,
1244 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1245 &core_clk_ctrl_reg);
1246 if (err)
1247 return err;
1248
1249 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1250 if (host->hw_ver.major >= 4) {
1251 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1252 return -ERANGE;
1253 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1254 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1255 } else {
1256 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1257 return -ERANGE;
1258 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1259 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1260 }
1261
1262 /* Clear CORE_CLK_DIV_EN */
1263 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1264
1265 err = ufshcd_dme_set(hba,
1266 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1267 core_clk_ctrl_reg);
1268 if (err)
1269 return err;
1270
1271 /* Configure unipro core clk 40ns attribute */
1272 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1273 }
1274
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba,unsigned long freq)1275 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq)
1276 {
1277 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1278 struct ufs_pa_layer_attr *attr = &host->dev_req_params;
1279 int ret;
1280
1281 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,
1282 attr->hs_rate, false, true);
1283 if (ret) {
1284 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1285 return ret;
1286 }
1287 /* set unipro core clock attributes and clear clock divider */
1288 return ufs_qcom_set_core_clk_ctrl(hba, freq);
1289 }
1290
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1291 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1292 {
1293 return 0;
1294 }
1295
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1296 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1297 {
1298 int err;
1299 u32 core_clk_ctrl_reg;
1300
1301 err = ufshcd_dme_get(hba,
1302 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1303 &core_clk_ctrl_reg);
1304
1305 /* make sure CORE_CLK_DIV_EN is cleared */
1306 if (!err &&
1307 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1308 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1309 err = ufshcd_dme_set(hba,
1310 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1311 core_clk_ctrl_reg);
1312 }
1313
1314 return err;
1315 }
1316
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba,unsigned long freq)1317 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq)
1318 {
1319 /* set unipro core clock attributes and clear clock divider */
1320 return ufs_qcom_set_core_clk_ctrl(hba, freq);
1321 }
1322
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,unsigned long target_freq,enum ufs_notify_change_status status)1323 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
1324 unsigned long target_freq,
1325 enum ufs_notify_change_status status)
1326 {
1327 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1328 int err;
1329
1330 /* check the host controller state before sending hibern8 cmd */
1331 if (!ufshcd_is_hba_active(hba))
1332 return 0;
1333
1334 if (status == PRE_CHANGE) {
1335 err = ufshcd_uic_hibern8_enter(hba);
1336 if (err)
1337 return err;
1338 if (scale_up)
1339 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq);
1340 else
1341 err = ufs_qcom_clk_scale_down_pre_change(hba);
1342
1343 if (err) {
1344 ufshcd_uic_hibern8_exit(hba);
1345 return err;
1346 }
1347 } else {
1348 if (scale_up)
1349 err = ufs_qcom_clk_scale_up_post_change(hba);
1350 else
1351 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq);
1352
1353
1354 if (err) {
1355 ufshcd_uic_hibern8_exit(hba);
1356 return err;
1357 }
1358
1359 ufs_qcom_icc_update_bw(host);
1360 ufshcd_uic_hibern8_exit(hba);
1361 }
1362
1363 return 0;
1364 }
1365
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1366 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1367 {
1368 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1369 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1370 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1371 }
1372
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1373 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1374 {
1375 /* provide a legal default configuration */
1376 host->testbus.select_major = TSTBUS_UNIPRO;
1377 host->testbus.select_minor = 37;
1378 }
1379
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1380 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1381 {
1382 if (host->testbus.select_major >= TSTBUS_MAX) {
1383 dev_err(host->hba->dev,
1384 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1385 __func__, host->testbus.select_major);
1386 return false;
1387 }
1388
1389 return true;
1390 }
1391
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1392 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1393 {
1394 int reg;
1395 int offset;
1396 u32 mask = TEST_BUS_SUB_SEL_MASK;
1397
1398 if (!host)
1399 return -EINVAL;
1400
1401 if (!ufs_qcom_testbus_cfg_is_ok(host))
1402 return -EPERM;
1403
1404 switch (host->testbus.select_major) {
1405 case TSTBUS_UAWM:
1406 reg = UFS_TEST_BUS_CTRL_0;
1407 offset = 24;
1408 break;
1409 case TSTBUS_UARM:
1410 reg = UFS_TEST_BUS_CTRL_0;
1411 offset = 16;
1412 break;
1413 case TSTBUS_TXUC:
1414 reg = UFS_TEST_BUS_CTRL_0;
1415 offset = 8;
1416 break;
1417 case TSTBUS_RXUC:
1418 reg = UFS_TEST_BUS_CTRL_0;
1419 offset = 0;
1420 break;
1421 case TSTBUS_DFC:
1422 reg = UFS_TEST_BUS_CTRL_1;
1423 offset = 24;
1424 break;
1425 case TSTBUS_TRLUT:
1426 reg = UFS_TEST_BUS_CTRL_1;
1427 offset = 16;
1428 break;
1429 case TSTBUS_TMRLUT:
1430 reg = UFS_TEST_BUS_CTRL_1;
1431 offset = 8;
1432 break;
1433 case TSTBUS_OCSC:
1434 reg = UFS_TEST_BUS_CTRL_1;
1435 offset = 0;
1436 break;
1437 case TSTBUS_WRAPPER:
1438 reg = UFS_TEST_BUS_CTRL_2;
1439 offset = 16;
1440 break;
1441 case TSTBUS_COMBINED:
1442 reg = UFS_TEST_BUS_CTRL_2;
1443 offset = 8;
1444 break;
1445 case TSTBUS_UTP_HCI:
1446 reg = UFS_TEST_BUS_CTRL_2;
1447 offset = 0;
1448 break;
1449 case TSTBUS_UNIPRO:
1450 reg = UFS_UNIPRO_CFG;
1451 offset = 20;
1452 mask = 0xFFF;
1453 break;
1454 /*
1455 * No need for a default case, since
1456 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1457 * is legal
1458 */
1459 }
1460 mask <<= offset;
1461 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1462 (u32)host->testbus.select_major << 19,
1463 REG_UFS_CFG1);
1464 ufshcd_rmwl(host->hba, mask,
1465 (u32)host->testbus.select_minor << offset,
1466 reg);
1467 ufs_qcom_enable_test_bus(host);
1468
1469 return 0;
1470 }
1471
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1472 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1473 {
1474 u32 reg;
1475 struct ufs_qcom_host *host;
1476
1477 host = ufshcd_get_variant(hba);
1478
1479 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1480 "HCI Vendor Specific Registers ");
1481
1482 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1483 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1484
1485 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1486 reg |= UTP_DBG_RAMS_EN;
1487 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1488
1489 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1490 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1491
1492 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1493 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1494
1495 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1496 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1497
1498 /* clear bit 17 - UTP_DBG_RAMS_EN */
1499 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1500
1501 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1502 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1503
1504 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1505 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1506
1507 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1508 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1509
1510 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1511 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1512
1513 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1514 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1515
1516 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1517 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1518
1519 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1520 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1521 }
1522
1523 /**
1524 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1525 * @hba: per-adapter instance
1526 *
1527 * Toggles the (optional) reset line to reset the attached device.
1528 */
ufs_qcom_device_reset(struct ufs_hba * hba)1529 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1530 {
1531 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1532
1533 /* reset gpio is optional */
1534 if (!host->device_reset)
1535 return -EOPNOTSUPP;
1536
1537 /*
1538 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1539 * be on the safe side.
1540 */
1541 ufs_qcom_device_reset_ctrl(hba, true);
1542 usleep_range(10, 15);
1543
1544 ufs_qcom_device_reset_ctrl(hba, false);
1545 usleep_range(10, 15);
1546
1547 return 0;
1548 }
1549
1550 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1551 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1552 struct devfreq_dev_profile *p,
1553 struct devfreq_simple_ondemand_data *d)
1554 {
1555 p->polling_ms = 60;
1556 p->timer = DEVFREQ_TIMER_DELAYED;
1557 d->upthreshold = 70;
1558 d->downdifferential = 5;
1559
1560 hba->clk_scaling.suspend_on_no_request = true;
1561 }
1562 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * data)1563 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1564 struct devfreq_dev_profile *p,
1565 struct devfreq_simple_ondemand_data *data)
1566 {
1567 }
1568 #endif
1569
1570 /* Resources */
1571 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1572 {.name = "ufs_mem",},
1573 {.name = "mcq",},
1574 /* Submission Queue DAO */
1575 {.name = "mcq_sqd",},
1576 /* Submission Queue Interrupt Status */
1577 {.name = "mcq_sqis",},
1578 /* Completion Queue DAO */
1579 {.name = "mcq_cqd",},
1580 /* Completion Queue Interrupt Status */
1581 {.name = "mcq_cqis",},
1582 /* MCQ vendor specific */
1583 {.name = "mcq_vs",},
1584 };
1585
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1586 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1587 {
1588 struct platform_device *pdev = to_platform_device(hba->dev);
1589 struct ufshcd_res_info *res;
1590 struct resource *res_mem, *res_mcq;
1591 int i, ret;
1592
1593 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1594
1595 for (i = 0; i < RES_MAX; i++) {
1596 res = &hba->res[i];
1597 res->resource = platform_get_resource_byname(pdev,
1598 IORESOURCE_MEM,
1599 res->name);
1600 if (!res->resource) {
1601 dev_info(hba->dev, "Resource %s not provided\n", res->name);
1602 if (i == RES_UFS)
1603 return -ENODEV;
1604 continue;
1605 } else if (i == RES_UFS) {
1606 res_mem = res->resource;
1607 res->base = hba->mmio_base;
1608 continue;
1609 }
1610
1611 res->base = devm_ioremap_resource(hba->dev, res->resource);
1612 if (IS_ERR(res->base)) {
1613 dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1614 res->name, (int)PTR_ERR(res->base));
1615 ret = PTR_ERR(res->base);
1616 res->base = NULL;
1617 return ret;
1618 }
1619 }
1620
1621 /* MCQ resource provided in DT */
1622 res = &hba->res[RES_MCQ];
1623 /* Bail if MCQ resource is provided */
1624 if (res->base)
1625 goto out;
1626
1627 /* Explicitly allocate MCQ resource from ufs_mem */
1628 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1629 if (!res_mcq)
1630 return -ENOMEM;
1631
1632 res_mcq->start = res_mem->start +
1633 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1634 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1635 res_mcq->flags = res_mem->flags;
1636 res_mcq->name = "mcq";
1637
1638 ret = insert_resource(&iomem_resource, res_mcq);
1639 if (ret) {
1640 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1641 ret);
1642 return ret;
1643 }
1644
1645 res->base = devm_ioremap_resource(hba->dev, res_mcq);
1646 if (IS_ERR(res->base)) {
1647 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1648 (int)PTR_ERR(res->base));
1649 ret = PTR_ERR(res->base);
1650 goto ioremap_err;
1651 }
1652
1653 out:
1654 hba->mcq_base = res->base;
1655 return 0;
1656 ioremap_err:
1657 res->base = NULL;
1658 remove_resource(res_mcq);
1659 return ret;
1660 }
1661
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1662 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1663 {
1664 struct ufshcd_res_info *mem_res, *sqdao_res;
1665 struct ufshcd_mcq_opr_info_t *opr;
1666 int i;
1667
1668 mem_res = &hba->res[RES_UFS];
1669 sqdao_res = &hba->res[RES_MCQ_SQD];
1670
1671 if (!mem_res->base || !sqdao_res->base)
1672 return -EINVAL;
1673
1674 for (i = 0; i < OPR_MAX; i++) {
1675 opr = &hba->mcq_opr[i];
1676 opr->offset = sqdao_res->resource->start -
1677 mem_res->resource->start + 0x40 * i;
1678 opr->stride = 0x100;
1679 opr->base = sqdao_res->base + 0x40 * i;
1680 }
1681
1682 return 0;
1683 }
1684
ufs_qcom_get_hba_mac(struct ufs_hba * hba)1685 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1686 {
1687 /* Qualcomm HC supports up to 64 */
1688 return MAX_SUPP_MAC;
1689 }
1690
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)1691 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1692 unsigned long *ocqs)
1693 {
1694 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1695
1696 if (!mcq_vs_res->base)
1697 return -EINVAL;
1698
1699 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1700
1701 return 0;
1702 }
1703
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)1704 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1705 {
1706 struct device *dev = msi_desc_to_dev(desc);
1707 struct ufs_hba *hba = dev_get_drvdata(dev);
1708
1709 ufshcd_mcq_config_esi(hba, msg);
1710 }
1711
ufs_qcom_mcq_esi_handler(int irq,void * data)1712 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1713 {
1714 struct msi_desc *desc = data;
1715 struct device *dev = msi_desc_to_dev(desc);
1716 struct ufs_hba *hba = dev_get_drvdata(dev);
1717 u32 id = desc->msi_index;
1718 struct ufs_hw_queue *hwq = &hba->uhq[id];
1719
1720 ufshcd_mcq_write_cqis(hba, 0x1, id);
1721 ufshcd_mcq_poll_cqe_lock(hba, hwq);
1722
1723 return IRQ_HANDLED;
1724 }
1725
ufs_qcom_config_esi(struct ufs_hba * hba)1726 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1727 {
1728 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1729 struct msi_desc *desc;
1730 struct msi_desc *failed_desc = NULL;
1731 int nr_irqs, ret;
1732
1733 if (host->esi_enabled)
1734 return 0;
1735
1736 /*
1737 * 1. We only handle CQs as of now.
1738 * 2. Poll queues do not need ESI.
1739 */
1740 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1741 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
1742 ufs_qcom_write_msi_msg);
1743 if (ret) {
1744 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1745 return ret;
1746 }
1747
1748 msi_lock_descs(hba->dev);
1749 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1750 ret = devm_request_irq(hba->dev, desc->irq,
1751 ufs_qcom_mcq_esi_handler,
1752 IRQF_SHARED, "qcom-mcq-esi", desc);
1753 if (ret) {
1754 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1755 __func__, desc->irq, ret);
1756 failed_desc = desc;
1757 break;
1758 }
1759 }
1760 msi_unlock_descs(hba->dev);
1761
1762 if (ret) {
1763 /* Rewind */
1764 msi_lock_descs(hba->dev);
1765 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1766 if (desc == failed_desc)
1767 break;
1768 devm_free_irq(hba->dev, desc->irq, hba);
1769 }
1770 msi_unlock_descs(hba->dev);
1771 platform_device_msi_free_irqs_all(hba->dev);
1772 } else {
1773 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1774 host->hw_ver.step == 0)
1775 ufshcd_rmwl(hba, ESI_VEC_MASK,
1776 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
1777 REG_UFS_CFG3);
1778 ufshcd_mcq_enable_esi(hba);
1779 host->esi_enabled = true;
1780 }
1781
1782 return ret;
1783 }
1784
ufs_qcom_freq_to_gear_speed(struct ufs_hba * hba,unsigned long freq)1785 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq)
1786 {
1787 u32 gear = UFS_HS_DONT_CHANGE;
1788
1789 switch (freq) {
1790 case 403000000:
1791 gear = UFS_HS_G5;
1792 break;
1793 case 300000000:
1794 gear = UFS_HS_G4;
1795 break;
1796 case 201500000:
1797 gear = UFS_HS_G3;
1798 break;
1799 case 150000000:
1800 case 100000000:
1801 gear = UFS_HS_G2;
1802 break;
1803 case 75000000:
1804 case 37500000:
1805 gear = UFS_HS_G1;
1806 break;
1807 default:
1808 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq);
1809 return UFS_HS_DONT_CHANGE;
1810 }
1811
1812 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx);
1813 }
1814
1815 /*
1816 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1817 *
1818 * The variant operations configure the necessary controller and PHY
1819 * handshake during initialization.
1820 */
1821 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1822 .name = "qcom",
1823 .init = ufs_qcom_init,
1824 .exit = ufs_qcom_exit,
1825 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1826 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1827 .setup_clocks = ufs_qcom_setup_clocks,
1828 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1829 .link_startup_notify = ufs_qcom_link_startup_notify,
1830 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1831 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1832 .suspend = ufs_qcom_suspend,
1833 .resume = ufs_qcom_resume,
1834 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1835 .device_reset = ufs_qcom_device_reset,
1836 .config_scaling_param = ufs_qcom_config_scaling_param,
1837 .program_key = ufs_qcom_ice_program_key,
1838 .mcq_config_resource = ufs_qcom_mcq_config_resource,
1839 .get_hba_mac = ufs_qcom_get_hba_mac,
1840 .op_runtime_config = ufs_qcom_op_runtime_config,
1841 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
1842 .config_esi = ufs_qcom_config_esi,
1843 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed,
1844 };
1845
1846 /**
1847 * ufs_qcom_probe - probe routine of the driver
1848 * @pdev: pointer to Platform device handle
1849 *
1850 * Return: zero for success and non-zero for failure.
1851 */
ufs_qcom_probe(struct platform_device * pdev)1852 static int ufs_qcom_probe(struct platform_device *pdev)
1853 {
1854 int err;
1855 struct device *dev = &pdev->dev;
1856
1857 /* Perform generic probe */
1858 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1859 if (err)
1860 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
1861
1862 return 0;
1863 }
1864
1865 /**
1866 * ufs_qcom_remove - set driver_data of the device to NULL
1867 * @pdev: pointer to platform device handle
1868 *
1869 * Always returns 0
1870 */
ufs_qcom_remove(struct platform_device * pdev)1871 static void ufs_qcom_remove(struct platform_device *pdev)
1872 {
1873 struct ufs_hba *hba = platform_get_drvdata(pdev);
1874 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1875
1876 ufshcd_pltfrm_remove(pdev);
1877 if (host->esi_enabled)
1878 platform_device_msi_free_irqs_all(hba->dev);
1879 }
1880
1881 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
1882 { .compatible = "qcom,ufshc" },
1883 { .compatible = "qcom,sm8550-ufshc" },
1884 {},
1885 };
1886 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1887
1888 #ifdef CONFIG_ACPI
1889 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1890 { "QCOM24A5" },
1891 { },
1892 };
1893 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1894 #endif
1895
1896 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1897 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1898 .prepare = ufshcd_suspend_prepare,
1899 .complete = ufshcd_resume_complete,
1900 #ifdef CONFIG_PM_SLEEP
1901 .suspend = ufshcd_system_suspend,
1902 .resume = ufshcd_system_resume,
1903 .freeze = ufshcd_system_freeze,
1904 .restore = ufshcd_system_restore,
1905 .thaw = ufshcd_system_thaw,
1906 #endif
1907 };
1908
1909 static struct platform_driver ufs_qcom_pltform = {
1910 .probe = ufs_qcom_probe,
1911 .remove_new = ufs_qcom_remove,
1912 .driver = {
1913 .name = "ufshcd-qcom",
1914 .pm = &ufs_qcom_pm_ops,
1915 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1916 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1917 },
1918 };
1919 module_platform_driver(ufs_qcom_pltform);
1920
1921 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");
1922 MODULE_LICENSE("GPL v2");
1923