1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Universal Flash Storage Host controller PCI glue driver
4 *
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #include <ufs/ufshcd.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/pm_qos.h>
18 #include <linux/debugfs.h>
19 #include <linux/uuid.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio/consumer.h>
22
23 #define MAX_SUPP_MAC 64
24
25 struct ufs_host {
26 void (*late_init)(struct ufs_hba *hba);
27 };
28
29 enum intel_ufs_dsm_func_id {
30 INTEL_DSM_FNS = 0,
31 INTEL_DSM_RESET = 1,
32 };
33
34 struct intel_host {
35 struct ufs_host ufs_host;
36 u32 dsm_fns;
37 u32 active_ltr;
38 u32 idle_ltr;
39 struct dentry *debugfs_root;
40 struct gpio_desc *reset_gpio;
41 };
42
43 static const guid_t intel_dsm_guid =
44 GUID_INIT(0x1A4832A0, 0x7D03, 0x43CA,
45 0xB0, 0x20, 0xF6, 0xDC, 0xD1, 0x2A, 0x19, 0x50);
46
__intel_dsm_supported(struct intel_host * host,enum intel_ufs_dsm_func_id fn)47 static bool __intel_dsm_supported(struct intel_host *host,
48 enum intel_ufs_dsm_func_id fn)
49 {
50 return fn < 32 && fn >= 0 && (host->dsm_fns & (1u << fn));
51 }
52
53 #define INTEL_DSM_SUPPORTED(host, name) \
54 __intel_dsm_supported(host, INTEL_DSM_##name)
55
__intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)56 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
57 unsigned int fn, u32 *result)
58 {
59 union acpi_object *obj;
60 int err = 0;
61 size_t len;
62
63 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL,
64 ACPI_TYPE_BUFFER);
65 if (!obj)
66 return -EOPNOTSUPP;
67
68 if (obj->buffer.length < 1) {
69 err = -EINVAL;
70 goto out;
71 }
72
73 len = min_t(size_t, obj->buffer.length, 4);
74
75 *result = 0;
76 memcpy(result, obj->buffer.pointer, len);
77 out:
78 ACPI_FREE(obj);
79
80 return err;
81 }
82
intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)83 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
84 unsigned int fn, u32 *result)
85 {
86 if (!__intel_dsm_supported(intel_host, fn))
87 return -EOPNOTSUPP;
88
89 return __intel_dsm(intel_host, dev, fn, result);
90 }
91
intel_dsm_init(struct intel_host * intel_host,struct device * dev)92 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev)
93 {
94 int err;
95
96 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
97 dev_dbg(dev, "DSM fns %#x, error %d\n", intel_host->dsm_fns, err);
98 }
99
ufs_intel_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)100 static int ufs_intel_hce_enable_notify(struct ufs_hba *hba,
101 enum ufs_notify_change_status status)
102 {
103 /* Cannot enable ICE until after HC enable */
104 if (status == POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) {
105 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
106
107 hce |= CRYPTO_GENERAL_ENABLE;
108 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE);
109 }
110
111 return 0;
112 }
113
ufs_intel_disable_lcc(struct ufs_hba * hba)114 static int ufs_intel_disable_lcc(struct ufs_hba *hba)
115 {
116 u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
117 u32 lcc_enable = 0;
118
119 ufshcd_dme_get(hba, attr, &lcc_enable);
120 if (lcc_enable)
121 ufshcd_disable_host_tx_lcc(hba);
122
123 return 0;
124 }
125
ufs_intel_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)126 static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
127 enum ufs_notify_change_status status)
128 {
129 int err = 0;
130
131 switch (status) {
132 case PRE_CHANGE:
133 err = ufs_intel_disable_lcc(hba);
134 break;
135 case POST_CHANGE:
136 break;
137 default:
138 break;
139 }
140
141 return err;
142 }
143
ufs_intel_set_lanes(struct ufs_hba * hba,u32 lanes)144 static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes)
145 {
146 struct ufs_pa_layer_attr pwr_info = hba->pwr_info;
147 int ret;
148
149 pwr_info.lane_rx = lanes;
150 pwr_info.lane_tx = lanes;
151 ret = ufshcd_config_pwr_mode(hba, &pwr_info);
152 if (ret)
153 dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n",
154 __func__, lanes, ret);
155 return ret;
156 }
157
ufs_intel_lkf_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)158 static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba,
159 enum ufs_notify_change_status status,
160 struct ufs_pa_layer_attr *dev_max_params,
161 struct ufs_pa_layer_attr *dev_req_params)
162 {
163 int err = 0;
164
165 switch (status) {
166 case PRE_CHANGE:
167 if (ufshcd_is_hs_mode(dev_max_params) &&
168 (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2))
169 ufs_intel_set_lanes(hba, 2);
170 memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params));
171 break;
172 case POST_CHANGE:
173 if (ufshcd_is_hs_mode(dev_req_params)) {
174 u32 peer_granularity;
175
176 usleep_range(1000, 1250);
177 err = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
178 &peer_granularity);
179 }
180 break;
181 default:
182 break;
183 }
184
185 return err;
186 }
187
ufs_intel_lkf_apply_dev_quirks(struct ufs_hba * hba)188 static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba)
189 {
190 u32 granularity, peer_granularity;
191 u32 pa_tactivate, peer_pa_tactivate;
192 int ret;
193
194 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &granularity);
195 if (ret)
196 goto out;
197
198 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &peer_granularity);
199 if (ret)
200 goto out;
201
202 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
203 if (ret)
204 goto out;
205
206 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &peer_pa_tactivate);
207 if (ret)
208 goto out;
209
210 if (granularity == peer_granularity) {
211 u32 new_peer_pa_tactivate = pa_tactivate + 2;
212
213 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), new_peer_pa_tactivate);
214 }
215 out:
216 return ret;
217 }
218
ufs_intel_ctrl_uic_compl(struct ufs_hba * hba,bool enable)219 static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable)
220 {
221 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
222
223 if (enable)
224 set |= UIC_COMMAND_COMPL;
225 else
226 set &= ~UIC_COMMAND_COMPL;
227 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
228 }
229
ufs_intel_mtl_h8_notify(struct ufs_hba * hba,enum uic_cmd_dme cmd,enum ufs_notify_change_status status)230 static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba,
231 enum uic_cmd_dme cmd,
232 enum ufs_notify_change_status status)
233 {
234 /*
235 * Disable UIC COMPL INTR to prevent access to UFSHCI after
236 * checking HCS.UPMCRS
237 */
238 if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER)
239 ufs_intel_ctrl_uic_compl(hba, false);
240
241 if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT)
242 ufs_intel_ctrl_uic_compl(hba, true);
243 }
244
245 #define INTEL_ACTIVELTR 0x804
246 #define INTEL_IDLELTR 0x808
247
248 #define INTEL_LTR_REQ BIT(15)
249 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
250 #define INTEL_LTR_SCALE_1US (2 << 10)
251 #define INTEL_LTR_SCALE_32US (3 << 10)
252 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
253
intel_cache_ltr(struct ufs_hba * hba)254 static void intel_cache_ltr(struct ufs_hba *hba)
255 {
256 struct intel_host *host = ufshcd_get_variant(hba);
257
258 host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
259 host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
260 }
261
intel_ltr_set(struct device * dev,s32 val)262 static void intel_ltr_set(struct device *dev, s32 val)
263 {
264 struct ufs_hba *hba = dev_get_drvdata(dev);
265 struct intel_host *host = ufshcd_get_variant(hba);
266 u32 ltr;
267
268 pm_runtime_get_sync(dev);
269
270 /*
271 * Program latency tolerance (LTR) accordingly what has been asked
272 * by the PM QoS layer or disable it in case we were passed
273 * negative value or PM_QOS_LATENCY_ANY.
274 */
275 ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
276
277 if (val == PM_QOS_LATENCY_ANY || val < 0) {
278 ltr &= ~INTEL_LTR_REQ;
279 } else {
280 ltr |= INTEL_LTR_REQ;
281 ltr &= ~INTEL_LTR_SCALE_MASK;
282 ltr &= ~INTEL_LTR_VALUE_MASK;
283
284 if (val > INTEL_LTR_VALUE_MASK) {
285 val >>= 5;
286 if (val > INTEL_LTR_VALUE_MASK)
287 val = INTEL_LTR_VALUE_MASK;
288 ltr |= INTEL_LTR_SCALE_32US | val;
289 } else {
290 ltr |= INTEL_LTR_SCALE_1US | val;
291 }
292 }
293
294 if (ltr == host->active_ltr)
295 goto out;
296
297 writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
298 writel(ltr, hba->mmio_base + INTEL_IDLELTR);
299
300 /* Cache the values into intel_host structure */
301 intel_cache_ltr(hba);
302 out:
303 pm_runtime_put(dev);
304 }
305
intel_ltr_expose(struct device * dev)306 static void intel_ltr_expose(struct device *dev)
307 {
308 dev->power.set_latency_tolerance = intel_ltr_set;
309 dev_pm_qos_expose_latency_tolerance(dev);
310 }
311
intel_ltr_hide(struct device * dev)312 static void intel_ltr_hide(struct device *dev)
313 {
314 dev_pm_qos_hide_latency_tolerance(dev);
315 dev->power.set_latency_tolerance = NULL;
316 }
317
intel_add_debugfs(struct ufs_hba * hba)318 static void intel_add_debugfs(struct ufs_hba *hba)
319 {
320 struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
321 struct intel_host *host = ufshcd_get_variant(hba);
322
323 intel_cache_ltr(hba);
324
325 host->debugfs_root = dir;
326 debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
327 debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
328 }
329
intel_remove_debugfs(struct ufs_hba * hba)330 static void intel_remove_debugfs(struct ufs_hba *hba)
331 {
332 struct intel_host *host = ufshcd_get_variant(hba);
333
334 debugfs_remove_recursive(host->debugfs_root);
335 }
336
ufs_intel_device_reset(struct ufs_hba * hba)337 static int ufs_intel_device_reset(struct ufs_hba *hba)
338 {
339 struct intel_host *host = ufshcd_get_variant(hba);
340
341 if (INTEL_DSM_SUPPORTED(host, RESET)) {
342 u32 result = 0;
343 int err;
344
345 err = intel_dsm(host, hba->dev, INTEL_DSM_RESET, &result);
346 if (!err && !result)
347 err = -EIO;
348 if (err)
349 dev_err(hba->dev, "%s: DSM error %d result %u\n",
350 __func__, err, result);
351 return err;
352 }
353
354 if (!host->reset_gpio)
355 return -EOPNOTSUPP;
356
357 gpiod_set_value_cansleep(host->reset_gpio, 1);
358 usleep_range(10, 15);
359
360 gpiod_set_value_cansleep(host->reset_gpio, 0);
361 usleep_range(10, 15);
362
363 return 0;
364 }
365
ufs_intel_get_reset_gpio(struct device * dev)366 static struct gpio_desc *ufs_intel_get_reset_gpio(struct device *dev)
367 {
368 /* GPIO in _DSD has active low setting */
369 return devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
370 }
371
ufs_intel_common_init(struct ufs_hba * hba)372 static int ufs_intel_common_init(struct ufs_hba *hba)
373 {
374 struct intel_host *host;
375
376 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
377
378 host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
379 if (!host)
380 return -ENOMEM;
381 ufshcd_set_variant(hba, host);
382 intel_dsm_init(host, hba->dev);
383 if (INTEL_DSM_SUPPORTED(host, RESET)) {
384 if (hba->vops->device_reset)
385 hba->caps |= UFSHCD_CAP_DEEPSLEEP;
386 } else {
387 if (hba->vops->device_reset)
388 host->reset_gpio = ufs_intel_get_reset_gpio(hba->dev);
389 if (IS_ERR(host->reset_gpio)) {
390 dev_err(hba->dev, "%s: failed to get reset GPIO, error %ld\n",
391 __func__, PTR_ERR(host->reset_gpio));
392 host->reset_gpio = NULL;
393 }
394 if (host->reset_gpio) {
395 gpiod_set_value_cansleep(host->reset_gpio, 0);
396 hba->caps |= UFSHCD_CAP_DEEPSLEEP;
397 }
398 }
399 intel_ltr_expose(hba->dev);
400 intel_add_debugfs(hba);
401 return 0;
402 }
403
ufs_intel_common_exit(struct ufs_hba * hba)404 static void ufs_intel_common_exit(struct ufs_hba *hba)
405 {
406 intel_remove_debugfs(hba);
407 intel_ltr_hide(hba->dev);
408 }
409
ufs_intel_resume(struct ufs_hba * hba,enum ufs_pm_op op)410 static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op)
411 {
412 if (ufshcd_is_link_hibern8(hba)) {
413 int ret = ufshcd_uic_hibern8_exit(hba);
414
415 if (!ret) {
416 ufshcd_set_link_active(hba);
417 } else {
418 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
419 __func__, ret);
420 /*
421 * Force reset and restore. Any other actions can lead
422 * to an unrecoverable state.
423 */
424 ufshcd_set_link_off(hba);
425 }
426 }
427
428 return 0;
429 }
430
ufs_intel_ehl_init(struct ufs_hba * hba)431 static int ufs_intel_ehl_init(struct ufs_hba *hba)
432 {
433 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
434 return ufs_intel_common_init(hba);
435 }
436
ufs_intel_lkf_late_init(struct ufs_hba * hba)437 static void ufs_intel_lkf_late_init(struct ufs_hba *hba)
438 {
439 /* LKF always needs a full reset, so set PM accordingly */
440 if (hba->caps & UFSHCD_CAP_DEEPSLEEP) {
441 hba->spm_lvl = UFS_PM_LVL_6;
442 hba->rpm_lvl = UFS_PM_LVL_6;
443 } else {
444 hba->spm_lvl = UFS_PM_LVL_5;
445 hba->rpm_lvl = UFS_PM_LVL_5;
446 }
447 }
448
ufs_intel_lkf_init(struct ufs_hba * hba)449 static int ufs_intel_lkf_init(struct ufs_hba *hba)
450 {
451 struct ufs_host *ufs_host;
452 int err;
453
454 hba->nop_out_timeout = 200;
455 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
456 hba->caps |= UFSHCD_CAP_CRYPTO;
457 err = ufs_intel_common_init(hba);
458 ufs_host = ufshcd_get_variant(hba);
459 ufs_host->late_init = ufs_intel_lkf_late_init;
460 return err;
461 }
462
ufs_intel_adl_init(struct ufs_hba * hba)463 static int ufs_intel_adl_init(struct ufs_hba *hba)
464 {
465 hba->nop_out_timeout = 200;
466 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
467 hba->caps |= UFSHCD_CAP_WB_EN;
468 return ufs_intel_common_init(hba);
469 }
470
ufs_intel_mtl_late_init(struct ufs_hba * hba)471 static void ufs_intel_mtl_late_init(struct ufs_hba *hba)
472 {
473 hba->rpm_lvl = UFS_PM_LVL_2;
474 hba->spm_lvl = UFS_PM_LVL_2;
475 }
476
ufs_intel_mtl_init(struct ufs_hba * hba)477 static int ufs_intel_mtl_init(struct ufs_hba *hba)
478 {
479 struct ufs_host *ufs_host;
480 int err;
481
482 hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN;
483 err = ufs_intel_common_init(hba);
484 /* Get variant after it is set in ufs_intel_common_init() */
485 ufs_host = ufshcd_get_variant(hba);
486 ufs_host->late_init = ufs_intel_mtl_late_init;
487 return err;
488 }
489
ufs_qemu_get_hba_mac(struct ufs_hba * hba)490 static int ufs_qemu_get_hba_mac(struct ufs_hba *hba)
491 {
492 return MAX_SUPP_MAC;
493 }
494
ufs_qemu_mcq_config_resource(struct ufs_hba * hba)495 static int ufs_qemu_mcq_config_resource(struct ufs_hba *hba)
496 {
497 hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba);
498
499 return 0;
500 }
501
ufs_qemu_op_runtime_config(struct ufs_hba * hba)502 static int ufs_qemu_op_runtime_config(struct ufs_hba *hba)
503 {
504 struct ufshcd_mcq_opr_info_t *opr;
505 int i;
506
507 u32 sqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQDAO, 0));
508 u32 sqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQISAO, 0));
509 u32 cqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQDAO, 0));
510 u32 cqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQISAO, 0));
511
512 hba->mcq_opr[OPR_SQD].offset = sqdao;
513 hba->mcq_opr[OPR_SQIS].offset = sqisao;
514 hba->mcq_opr[OPR_CQD].offset = cqdao;
515 hba->mcq_opr[OPR_CQIS].offset = cqisao;
516
517 for (i = 0; i < OPR_MAX; i++) {
518 opr = &hba->mcq_opr[i];
519 opr->stride = 48;
520 opr->base = hba->mmio_base + opr->offset;
521 }
522
523 return 0;
524 }
525
526 static struct ufs_hba_variant_ops ufs_qemu_hba_vops = {
527 .name = "qemu-pci",
528 .get_hba_mac = ufs_qemu_get_hba_mac,
529 .mcq_config_resource = ufs_qemu_mcq_config_resource,
530 .op_runtime_config = ufs_qemu_op_runtime_config,
531 };
532
533 static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
534 .name = "intel-pci",
535 .init = ufs_intel_common_init,
536 .exit = ufs_intel_common_exit,
537 .link_startup_notify = ufs_intel_link_startup_notify,
538 .resume = ufs_intel_resume,
539 };
540
541 static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
542 .name = "intel-pci",
543 .init = ufs_intel_ehl_init,
544 .exit = ufs_intel_common_exit,
545 .link_startup_notify = ufs_intel_link_startup_notify,
546 .resume = ufs_intel_resume,
547 };
548
549 static struct ufs_hba_variant_ops ufs_intel_lkf_hba_vops = {
550 .name = "intel-pci",
551 .init = ufs_intel_lkf_init,
552 .exit = ufs_intel_common_exit,
553 .hce_enable_notify = ufs_intel_hce_enable_notify,
554 .link_startup_notify = ufs_intel_link_startup_notify,
555 .pwr_change_notify = ufs_intel_lkf_pwr_change_notify,
556 .apply_dev_quirks = ufs_intel_lkf_apply_dev_quirks,
557 .resume = ufs_intel_resume,
558 .device_reset = ufs_intel_device_reset,
559 };
560
561 static struct ufs_hba_variant_ops ufs_intel_adl_hba_vops = {
562 .name = "intel-pci",
563 .init = ufs_intel_adl_init,
564 .exit = ufs_intel_common_exit,
565 .link_startup_notify = ufs_intel_link_startup_notify,
566 .resume = ufs_intel_resume,
567 .device_reset = ufs_intel_device_reset,
568 };
569
570 static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
571 .name = "intel-pci",
572 .init = ufs_intel_mtl_init,
573 .exit = ufs_intel_common_exit,
574 .hce_enable_notify = ufs_intel_hce_enable_notify,
575 .hibern8_notify = ufs_intel_mtl_h8_notify,
576 .link_startup_notify = ufs_intel_link_startup_notify,
577 .resume = ufs_intel_resume,
578 .device_reset = ufs_intel_device_reset,
579 };
580
581 #ifdef CONFIG_PM_SLEEP
ufshcd_pci_restore(struct device * dev)582 static int ufshcd_pci_restore(struct device *dev)
583 {
584 struct ufs_hba *hba = dev_get_drvdata(dev);
585
586 /* Force a full reset and restore */
587 ufshcd_set_link_off(hba);
588
589 return ufshcd_system_resume(dev);
590 }
591 #endif
592
593 /**
594 * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
595 * data structure memory
596 * @pdev: pointer to PCI handle
597 */
ufshcd_pci_remove(struct pci_dev * pdev)598 static void ufshcd_pci_remove(struct pci_dev *pdev)
599 {
600 struct ufs_hba *hba = pci_get_drvdata(pdev);
601
602 pm_runtime_forbid(&pdev->dev);
603 pm_runtime_get_noresume(&pdev->dev);
604 ufshcd_remove(hba);
605 }
606
607 /**
608 * ufshcd_pci_probe - probe routine of the driver
609 * @pdev: pointer to PCI device handle
610 * @id: PCI device id
611 *
612 * Return: 0 on success, non-zero value on failure.
613 */
614 static int
ufshcd_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)615 ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
616 {
617 struct ufs_host *ufs_host;
618 struct ufs_hba *hba;
619 void __iomem *mmio_base;
620 int err;
621
622 err = pcim_enable_device(pdev);
623 if (err) {
624 dev_err(&pdev->dev, "pcim_enable_device failed\n");
625 return err;
626 }
627
628 pci_set_master(pdev);
629
630 err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD);
631 if (err < 0) {
632 dev_err(&pdev->dev, "request and iomap failed\n");
633 return err;
634 }
635
636 mmio_base = pcim_iomap_table(pdev)[0];
637
638 err = ufshcd_alloc_host(&pdev->dev, &hba);
639 if (err) {
640 dev_err(&pdev->dev, "Allocation failed\n");
641 return err;
642 }
643
644 hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
645
646 err = ufshcd_init(hba, mmio_base, pdev->irq);
647 if (err) {
648 dev_err(&pdev->dev, "Initialization failed\n");
649 return err;
650 }
651
652 ufs_host = ufshcd_get_variant(hba);
653 if (ufs_host && ufs_host->late_init)
654 ufs_host->late_init(hba);
655
656 pm_runtime_put_noidle(&pdev->dev);
657 pm_runtime_allow(&pdev->dev);
658
659 return 0;
660 }
661
662 static const struct dev_pm_ops ufshcd_pci_pm_ops = {
663 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
664 #ifdef CONFIG_PM_SLEEP
665 .suspend = ufshcd_system_suspend,
666 .resume = ufshcd_system_resume,
667 .freeze = ufshcd_system_suspend,
668 .thaw = ufshcd_system_resume,
669 .poweroff = ufshcd_system_suspend,
670 .restore = ufshcd_pci_restore,
671 .prepare = ufshcd_suspend_prepare,
672 .complete = ufshcd_resume_complete,
673 #endif
674 };
675
676 static const struct pci_device_id ufshcd_pci_tbl[] = {
677 { PCI_VENDOR_ID_REDHAT, 0x0013, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
678 (kernel_ulong_t)&ufs_qemu_hba_vops },
679 { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
680 { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
681 { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
682 { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
683 { PCI_VDEVICE(INTEL, 0x98FA), (kernel_ulong_t)&ufs_intel_lkf_hba_vops },
684 { PCI_VDEVICE(INTEL, 0x51FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops },
685 { PCI_VDEVICE(INTEL, 0x54FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops },
686 { PCI_VDEVICE(INTEL, 0x7E47), (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
687 { PCI_VDEVICE(INTEL, 0xA847), (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
688 { PCI_VDEVICE(INTEL, 0x7747), (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
689 { PCI_VDEVICE(INTEL, 0xE447), (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
690 { } /* terminate list */
691 };
692
693 MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
694
695 static struct pci_driver ufshcd_pci_driver = {
696 .name = UFSHCD,
697 .id_table = ufshcd_pci_tbl,
698 .probe = ufshcd_pci_probe,
699 .remove = ufshcd_pci_remove,
700 .driver = {
701 .pm = &ufshcd_pci_pm_ops
702 },
703 };
704
705 module_pci_driver(ufshcd_pci_driver);
706
707 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
708 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
709 MODULE_DESCRIPTION("UFS host controller PCI glue driver");
710 MODULE_LICENSE("GPL");
711