1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16 #include <linux/suspend.h>
17
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-pci.h"
21
22 #define SSIC_PORT_NUM 2
23 #define SSIC_PORT_CFG2 0x880c
24 #define SSIC_PORT_CFG2_OFFSET 0x30
25 #define PROG_DONE (1 << 30)
26 #define SSIC_PORT_UNUSED (1 << 31)
27 #define SPARSE_DISABLE_BIT 17
28 #define SPARSE_CNTL_ENABLE 0xC12C
29
30 /* Device for a quirk */
31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36
37 #define PCI_VENDOR_ID_ETRON 0x1b6f
38 #define PCI_DEVICE_ID_EJ168 0x7023
39 #define PCI_DEVICE_ID_EJ188 0x7052
40
41 #define PCI_DEVICE_ID_VIA_VL805 0x3483
42
43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
45 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
46 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
47 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
49 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
50 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
51 #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8
52 #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0
53 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
54 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
55 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed
56 #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af
57 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
58 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
59
60 #define PCI_VENDOR_ID_PHYTIUM 0x1db7
61 #define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27
62
63 /* Thunderbolt */
64 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
65 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
66 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
67 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
68 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
69 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
70 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
71 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
72 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
73
74 #define PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI 0x13ed
75 #define PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI 0x13ee
76 #define PCI_DEVICE_ID_AMD_STARSHIP_XHCI 0x148c
77 #define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI 0x15d4
78 #define PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI 0x15d5
79 #define PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI 0x15e0
80 #define PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI 0x15e1
81 #define PCI_DEVICE_ID_AMD_RAVEN2_XHCI 0x15e5
82 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
83 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
84 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
85 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
86 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
87
88 #define PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI 0x7316
89
90 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
91 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
92 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
93 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
94 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042
95 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
96
97 #define PCI_DEVICE_ID_CADENCE 0x17CD
98 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200
99
100 static const char hcd_name[] = "xhci_hcd";
101
102 static struct hc_driver __read_mostly xhci_pci_hc_driver;
103
104 static int xhci_pci_setup(struct usb_hcd *hcd);
105 static int xhci_pci_run(struct usb_hcd *hcd);
106 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
107 struct usb_tt *tt, gfp_t mem_flags);
108
109 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
110 .reset = xhci_pci_setup,
111 .start = xhci_pci_run,
112 .update_hub_device = xhci_pci_update_hub_device,
113 };
114
115 /*
116 * Primary Legacy and MSI IRQ are synced in suspend_common().
117 * All MSI-X IRQs and secondary MSI IRQs should be synced here.
118 */
xhci_msix_sync_irqs(struct xhci_hcd * xhci)119 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
120 {
121 struct usb_hcd *hcd = xhci_to_hcd(xhci);
122
123 if (hcd->msix_enabled) {
124 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
125
126 /* for now, the driver only supports one primary interrupter */
127 synchronize_irq(pci_irq_vector(pdev, 0));
128 }
129 }
130
131 /* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */
xhci_cleanup_msix(struct xhci_hcd * xhci)132 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
133 {
134 struct usb_hcd *hcd = xhci_to_hcd(xhci);
135 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
136
137 if (hcd->irq > 0)
138 return;
139
140 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
141 pci_free_irq_vectors(pdev);
142 hcd->msix_enabled = 0;
143 }
144
145 /* Try enabling MSI-X with MSI and legacy IRQ as fallback */
xhci_try_enable_msi(struct usb_hcd * hcd)146 static int xhci_try_enable_msi(struct usb_hcd *hcd)
147 {
148 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
149 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
150 int ret;
151
152 /*
153 * Some Fresco Logic host controllers advertise MSI, but fail to
154 * generate interrupts. Don't even try to enable MSI.
155 */
156 if (xhci->quirks & XHCI_BROKEN_MSI)
157 goto legacy_irq;
158
159 /* unregister the legacy interrupt */
160 if (hcd->irq)
161 free_irq(hcd->irq, hcd);
162 hcd->irq = 0;
163
164 /*
165 * calculate number of MSI-X vectors supported.
166 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
167 * with max number of interrupters based on the xhci HCSPARAMS1.
168 * - num_online_cpus: maximum MSI-X vectors per CPUs core.
169 * Add additional 1 vector to ensure always available interrupt.
170 */
171 xhci->nvecs = min(num_online_cpus() + 1,
172 HCS_MAX_INTRS(xhci->hcs_params1));
173
174 /* TODO: Check with MSI Soc for sysdev */
175 xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs,
176 PCI_IRQ_MSIX | PCI_IRQ_MSI);
177 if (xhci->nvecs < 0) {
178 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
179 "failed to allocate IRQ vectors");
180 goto legacy_irq;
181 }
182
183 ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd",
184 xhci_to_hcd(xhci));
185 if (ret)
186 goto free_irq_vectors;
187
188 hcd->msi_enabled = 1;
189 hcd->msix_enabled = pdev->msix_enabled;
190 return 0;
191
192 free_irq_vectors:
193 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt",
194 pdev->msix_enabled ? "MSI-X" : "MSI");
195 pci_free_irq_vectors(pdev);
196
197 legacy_irq:
198 if (!pdev->irq) {
199 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
200 return -EINVAL;
201 }
202
203 if (!strlen(hcd->irq_descr))
204 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
205 hcd->driver->description, hcd->self.busnum);
206
207 /* fall back to legacy interrupt */
208 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd);
209 if (ret) {
210 xhci_err(xhci, "request interrupt %d failed\n", pdev->irq);
211 return ret;
212 }
213 hcd->irq = pdev->irq;
214 return 0;
215 }
216
xhci_pci_run(struct usb_hcd * hcd)217 static int xhci_pci_run(struct usb_hcd *hcd)
218 {
219 int ret;
220
221 if (usb_hcd_is_primary_hcd(hcd)) {
222 ret = xhci_try_enable_msi(hcd);
223 if (ret)
224 return ret;
225 }
226
227 return xhci_run(hcd);
228 }
229
xhci_pci_stop(struct usb_hcd * hcd)230 static void xhci_pci_stop(struct usb_hcd *hcd)
231 {
232 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
233
234 xhci_stop(hcd);
235
236 if (usb_hcd_is_primary_hcd(hcd))
237 xhci_cleanup_msix(xhci);
238 }
239
240 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)241 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
242 {
243 /*
244 * TODO: Implement finding debug ports later.
245 * TODO: see if there are any quirks that need to be added to handle
246 * new extended capabilities.
247 */
248
249 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
250 if (!pci_set_mwi(pdev))
251 xhci_dbg(xhci, "MWI active\n");
252
253 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
254 return 0;
255 }
256
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)257 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
258 {
259 struct pci_dev *pdev = to_pci_dev(dev);
260
261 /* Look for vendor-specific quirks */
262 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
263 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
264 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
265 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
266 pdev->revision == 0x0) {
267 xhci->quirks |= XHCI_RESET_EP_QUIRK;
268 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
269 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
270 }
271 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
272 pdev->revision == 0x4) {
273 xhci->quirks |= XHCI_SLOW_SUSPEND;
274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
275 "QUIRK: Fresco Logic xHC revision %u"
276 "must be suspended extra slowly",
277 pdev->revision);
278 }
279 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
280 xhci->quirks |= XHCI_BROKEN_STREAMS;
281 /* Fresco Logic confirms: all revisions of this chip do not
282 * support MSI, even though some of them claim to in their PCI
283 * capabilities.
284 */
285 xhci->quirks |= XHCI_BROKEN_MSI;
286 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
287 "QUIRK: Fresco Logic revision %u "
288 "has broken MSI implementation",
289 pdev->revision);
290 }
291
292 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
293 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
294 xhci->quirks |= XHCI_BROKEN_STREAMS;
295
296 if (pdev->vendor == PCI_VENDOR_ID_NEC)
297 xhci->quirks |= XHCI_NEC_HOST;
298
299 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
300 (pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEC_XHCI ||
301 pdev->device == PCI_DEVICE_ID_AMD_ARIEL_TYPEA_XHCI ||
302 pdev->device == PCI_DEVICE_ID_AMD_STARSHIP_XHCI ||
303 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D4_XHCI ||
304 pdev->device == PCI_DEVICE_ID_AMD_FIREFLIGHT_15D5_XHCI ||
305 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E0_XHCI ||
306 pdev->device == PCI_DEVICE_ID_AMD_RAVEN_15E1_XHCI ||
307 pdev->device == PCI_DEVICE_ID_AMD_RAVEN2_XHCI))
308 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9;
309
310 if (pdev->vendor == PCI_VENDOR_ID_ATI &&
311 pdev->device == PCI_DEVICE_ID_ATI_NAVI10_7316_XHCI)
312 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_9;
313
314 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
315 xhci->quirks |= XHCI_AMD_0x96_HOST;
316
317 /* AMD PLL quirk */
318 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
319 xhci->quirks |= XHCI_AMD_PLL_FIX;
320
321 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
322 (pdev->device == 0x145c ||
323 pdev->device == 0x15e0 ||
324 pdev->device == 0x15e1 ||
325 pdev->device == 0x43bb))
326 xhci->quirks |= XHCI_SUSPEND_DELAY;
327
328 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
329 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
330 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
331
332 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
333 xhci->quirks |= XHCI_DISABLE_SPARSE;
334 xhci->quirks |= XHCI_RESET_ON_RESUME;
335 }
336
337 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7)
338 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
339
340 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
341 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
342 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
343 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
344 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
345 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
346
347 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
348 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
349 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
350
351 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
352 xhci->quirks |= XHCI_LPM_SUPPORT;
353 xhci->quirks |= XHCI_INTEL_HOST;
354 xhci->quirks |= XHCI_AVOID_BEI;
355 }
356 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
357 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
358 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
359 xhci->limit_active_eps = 64;
360 xhci->quirks |= XHCI_SW_BW_CHECKING;
361 /*
362 * PPT desktop boards DH77EB and DH77DF will power back on after
363 * a few seconds of being shutdown. The fix for this is to
364 * switch the ports from xHCI to EHCI on shutdown. We can't use
365 * DMI information to find those particular boards (since each
366 * vendor will change the board name), so we have to key off all
367 * PPT chipsets.
368 */
369 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
370 }
371 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
372 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
373 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
374 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
375 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
376 }
377 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
378 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
379 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
380 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
381 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
382 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
383 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI ||
384 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI ||
385 pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) {
386 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
387 }
388 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
389 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
390 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
391 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
392 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
393 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
394 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI))
395 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
396 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
397 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
398 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
399 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
400 pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI ||
401 pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI))
402 xhci->quirks |= XHCI_MISSING_CAS;
403
404 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
405 (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI ||
406 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
407 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
408 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
409
410 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
411 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
412 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
413 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
414 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
415 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
416 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
417 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
418 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
419 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
420 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
421 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
422 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
423
424 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
425 (pdev->device == PCI_DEVICE_ID_EJ168 ||
426 pdev->device == PCI_DEVICE_ID_EJ188)) {
427 xhci->quirks |= XHCI_ETRON_HOST;
428 xhci->quirks |= XHCI_RESET_ON_RESUME;
429 xhci->quirks |= XHCI_BROKEN_STREAMS;
430 xhci->quirks |= XHCI_NO_SOFT_RETRY;
431 }
432
433 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
434 pdev->device == 0x0014) {
435 xhci->quirks |= XHCI_ZERO_64B_REGS;
436 }
437 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
438 pdev->device == 0x0015) {
439 xhci->quirks |= XHCI_RESET_ON_RESUME;
440 xhci->quirks |= XHCI_ZERO_64B_REGS;
441 }
442 if (pdev->vendor == PCI_VENDOR_ID_VIA)
443 xhci->quirks |= XHCI_RESET_ON_RESUME;
444
445 if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM &&
446 pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI)
447 xhci->quirks |= XHCI_RESET_ON_RESUME;
448
449 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
450 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
451 pdev->device == 0x3432)
452 xhci->quirks |= XHCI_BROKEN_STREAMS;
453
454 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) {
455 xhci->quirks |= XHCI_LPM_SUPPORT;
456 xhci->quirks |= XHCI_TRB_OVERFETCH;
457 }
458
459 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
460 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
461 /*
462 * try to tame the ASMedia 1042 controller which reports 0.96
463 * but appears to behave more like 1.0
464 */
465 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
466 xhci->quirks |= XHCI_BROKEN_STREAMS;
467 }
468 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
469 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
470 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
471 }
472 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
473 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
474 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
475 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
476 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
477
478 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
479 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
480 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
481
482 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
483 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI)
484 xhci->quirks |= XHCI_RESET_ON_RESUME;
485
486 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
487 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
488
489 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
490 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
491 pdev->device == 0x9026)
492 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
493
494 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
495 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
496 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
497 xhci->quirks |= XHCI_NO_SOFT_RETRY;
498
499 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
500 xhci->quirks |= XHCI_ZHAOXIN_HOST;
501 xhci->quirks |= XHCI_LPM_SUPPORT;
502
503 if (pdev->device == 0x9202) {
504 xhci->quirks |= XHCI_RESET_ON_RESUME;
505 xhci->quirks |= XHCI_TRB_OVERFETCH;
506 }
507
508 if (pdev->device == 0x9203)
509 xhci->quirks |= XHCI_TRB_OVERFETCH;
510 }
511
512 if (pdev->vendor == PCI_DEVICE_ID_CADENCE &&
513 pdev->device == PCI_DEVICE_ID_CADENCE_SSP)
514 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK;
515
516 /* xHC spec requires PCI devices to support D3hot and D3cold */
517 if (xhci->hci_version >= 0x120)
518 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
519
520 if (xhci->quirks & XHCI_RESET_ON_RESUME)
521 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
522 "QUIRK: Resetting on resume");
523 }
524
525 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)526 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
527 {
528 static const guid_t intel_dsm_guid =
529 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
530 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
531 union acpi_object *obj;
532
533 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
534 NULL);
535 ACPI_FREE(obj);
536 }
537
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)538 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
539 {
540 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
541 struct xhci_hub *rhub = &xhci->usb3_rhub;
542 int ret;
543 int i;
544
545 /* This is not the usb3 roothub we are looking for */
546 if (hcd != rhub->hcd)
547 return;
548
549 if (hdev->maxchild > rhub->num_ports) {
550 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
551 return;
552 }
553
554 for (i = 0; i < hdev->maxchild; i++) {
555 ret = usb_acpi_port_lpm_incapable(hdev, i);
556
557 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
558
559 if (ret >= 0) {
560 rhub->ports[i]->lpm_incapable = ret;
561 continue;
562 }
563 }
564 }
565
566 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)567 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)568 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
569 #endif /* CONFIG_ACPI */
570
571 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)572 static int xhci_pci_setup(struct usb_hcd *hcd)
573 {
574 struct xhci_hcd *xhci;
575 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
576 int retval;
577 u8 sbrn;
578
579 xhci = hcd_to_xhci(hcd);
580
581 /* imod_interval is the interrupt moderation value in nanoseconds. */
582 xhci->imod_interval = 40000;
583
584 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
585 if (retval)
586 return retval;
587
588 if (!usb_hcd_is_primary_hcd(hcd))
589 return 0;
590
591 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
592 xhci_pme_acpi_rtd3_enable(pdev);
593
594 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &sbrn);
595 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn);
596
597 /* Find any debug ports */
598 return xhci_pci_reinit(xhci, pdev);
599 }
600
xhci_pci_update_hub_device(struct usb_hcd * hcd,struct usb_device * hdev,struct usb_tt * tt,gfp_t mem_flags)601 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
602 struct usb_tt *tt, gfp_t mem_flags)
603 {
604 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
605 if (!hdev->parent)
606 xhci_find_lpm_incapable_ports(hcd, hdev);
607
608 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
609 }
610
611 /*
612 * We need to register our own PCI probe function (instead of the USB core's
613 * function) in order to create a second roothub under xHCI.
614 */
xhci_pci_common_probe(struct pci_dev * dev,const struct pci_device_id * id)615 int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id)
616 {
617 int retval;
618 struct xhci_hcd *xhci;
619 struct usb_hcd *hcd;
620 struct reset_control *reset;
621
622 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
623 if (IS_ERR(reset))
624 return PTR_ERR(reset);
625 reset_control_reset(reset);
626
627 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
628 pm_runtime_get_noresume(&dev->dev);
629
630 /* Register the USB 2.0 roothub.
631 * FIXME: USB core must know to register the USB 2.0 roothub first.
632 * This is sort of silly, because we could just set the HCD driver flags
633 * to say USB 2.0, but I'm not sure what the implications would be in
634 * the other parts of the HCD code.
635 */
636 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
637
638 if (retval)
639 goto put_runtime_pm;
640
641 /* USB 2.0 roothub is stored in the PCI device now. */
642 hcd = dev_get_drvdata(&dev->dev);
643 xhci = hcd_to_xhci(hcd);
644 xhci->reset = reset;
645 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
646 pci_name(dev), hcd);
647 if (!xhci->shared_hcd) {
648 retval = -ENOMEM;
649 goto dealloc_usb2_hcd;
650 }
651
652 retval = xhci_ext_cap_init(xhci);
653 if (retval)
654 goto put_usb3_hcd;
655
656 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
657 IRQF_SHARED);
658 if (retval)
659 goto put_usb3_hcd;
660 /* Roothub already marked as USB 3.0 speed */
661
662 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
663 HCC_MAX_PSA(xhci->hcc_params) >= 4)
664 xhci->shared_hcd->can_do_streams = 1;
665
666 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
667 pm_runtime_put_noidle(&dev->dev);
668
669 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
670 pm_runtime_get(&dev->dev);
671 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
672 pm_runtime_allow(&dev->dev);
673
674 dma_set_max_seg_size(&dev->dev, UINT_MAX);
675
676 return 0;
677
678 put_usb3_hcd:
679 usb_put_hcd(xhci->shared_hcd);
680 dealloc_usb2_hcd:
681 usb_hcd_pci_remove(dev);
682 put_runtime_pm:
683 pm_runtime_put_noidle(&dev->dev);
684 return retval;
685 }
686 EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, xhci);
687
688 /* handled by xhci-pci-renesas if enabled */
689 static const struct pci_device_id pci_ids_renesas[] = {
690 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) },
691 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) },
692 { /* end: all zeroes */ }
693 };
694
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)695 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
696 {
697 if (IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) &&
698 pci_match_id(pci_ids_renesas, dev))
699 return -ENODEV;
700
701 return xhci_pci_common_probe(dev, id);
702 }
703
xhci_pci_remove(struct pci_dev * dev)704 void xhci_pci_remove(struct pci_dev *dev)
705 {
706 struct xhci_hcd *xhci;
707 bool set_power_d3;
708
709 xhci = hcd_to_xhci(pci_get_drvdata(dev));
710 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP;
711
712 xhci->xhc_state |= XHCI_STATE_REMOVING;
713
714 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
715 pm_runtime_put(&dev->dev);
716 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
717 pm_runtime_forbid(&dev->dev);
718
719 if (xhci->shared_hcd) {
720 usb_remove_hcd(xhci->shared_hcd);
721 usb_put_hcd(xhci->shared_hcd);
722 xhci->shared_hcd = NULL;
723 }
724
725 usb_hcd_pci_remove(dev);
726
727 /* Workaround for spurious wakeups at shutdown with HSW */
728 if (set_power_d3)
729 pci_set_power_state(dev, PCI_D3hot);
730 }
731 EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, xhci);
732
733 /*
734 * In some Intel xHCI controllers, in order to get D3 working,
735 * through a vendor specific SSIC CONFIG register at offset 0x883c,
736 * SSIC PORT need to be marked as "unused" before putting xHCI
737 * into D3. After D3 exit, the SSIC port need to be marked as "used".
738 * Without this change, xHCI might not enter D3 state.
739 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)740 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
741 {
742 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
743 u32 val;
744 void __iomem *reg;
745 int i;
746
747 for (i = 0; i < SSIC_PORT_NUM; i++) {
748 reg = (void __iomem *) xhci->cap_regs +
749 SSIC_PORT_CFG2 +
750 i * SSIC_PORT_CFG2_OFFSET;
751
752 /* Notify SSIC that SSIC profile programming is not done. */
753 val = readl(reg) & ~PROG_DONE;
754 writel(val, reg);
755
756 /* Mark SSIC port as unused(suspend) or used(resume) */
757 val = readl(reg);
758 if (suspend)
759 val |= SSIC_PORT_UNUSED;
760 else
761 val &= ~SSIC_PORT_UNUSED;
762 writel(val, reg);
763
764 /* Notify SSIC that SSIC profile programming is done */
765 val = readl(reg) | PROG_DONE;
766 writel(val, reg);
767 readl(reg);
768 }
769 }
770
771 /*
772 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
773 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
774 */
xhci_pme_quirk(struct usb_hcd * hcd)775 static void xhci_pme_quirk(struct usb_hcd *hcd)
776 {
777 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
778 void __iomem *reg;
779 u32 val;
780
781 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
782 val = readl(reg);
783 writel(val | BIT(28), reg);
784 readl(reg);
785 }
786
xhci_sparse_control_quirk(struct usb_hcd * hcd)787 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
788 {
789 u32 reg;
790
791 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
792 reg &= ~BIT(SPARSE_DISABLE_BIT);
793 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
794 }
795
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)796 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
797 {
798 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
799 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
800 int ret;
801
802 /*
803 * Systems with the TI redriver that loses port status change events
804 * need to have the registers polled during D3, so avoid D3cold.
805 */
806 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
807 pci_d3cold_disable(pdev);
808
809 #ifdef CONFIG_SUSPEND
810 /* d3cold is broken, but only when s2idle is used */
811 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
812 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
813 pci_d3cold_disable(pdev);
814 #endif
815
816 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
817 xhci_pme_quirk(hcd);
818
819 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
820 xhci_ssic_port_unused_quirk(hcd, true);
821
822 if (xhci->quirks & XHCI_DISABLE_SPARSE)
823 xhci_sparse_control_quirk(hcd);
824
825 ret = xhci_suspend(xhci, do_wakeup);
826
827 /* synchronize irq when using MSI-X */
828 xhci_msix_sync_irqs(xhci);
829
830 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
831 xhci_ssic_port_unused_quirk(hcd, false);
832
833 return ret;
834 }
835
xhci_pci_resume(struct usb_hcd * hcd,pm_message_t msg)836 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
837 {
838 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
839 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
840
841 reset_control_reset(xhci->reset);
842
843 /* The BIOS on systems with the Intel Panther Point chipset may or may
844 * not support xHCI natively. That means that during system resume, it
845 * may switch the ports back to EHCI so that users can use their
846 * keyboard to select a kernel from GRUB after resume from hibernate.
847 *
848 * The BIOS is supposed to remember whether the OS had xHCI ports
849 * enabled before resume, and switch the ports back to xHCI when the
850 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
851 * writers.
852 *
853 * Unconditionally switch the ports back to xHCI after a system resume.
854 * It should not matter whether the EHCI or xHCI controller is
855 * resumed first. It's enough to do the switchover in xHCI because
856 * USB core won't notice anything as the hub driver doesn't start
857 * running again until after all the devices (including both EHCI and
858 * xHCI host controllers) have been resumed.
859 */
860
861 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
862 usb_enable_intel_xhci_ports(pdev);
863
864 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
865 xhci_ssic_port_unused_quirk(hcd, false);
866
867 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
868 xhci_pme_quirk(hcd);
869
870 return xhci_resume(xhci, msg);
871 }
872
xhci_pci_poweroff_late(struct usb_hcd * hcd,bool do_wakeup)873 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
874 {
875 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
876 struct xhci_port *port;
877 struct usb_device *udev;
878 u32 portsc;
879 int i;
880
881 /*
882 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
883 * cause significant boot delay if usb ports are in suspended U3 state
884 * during boot. Some USB devices survive in U3 state over S4 hibernate
885 *
886 * Disable ports that are in U3 if remote wake is not enabled for either
887 * host controller or connected device
888 */
889
890 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
891 return 0;
892
893 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
894 port = &xhci->hw_ports[i];
895 portsc = readl(port->addr);
896
897 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
898 continue;
899
900 if (!port->slot_id || !xhci->devs[port->slot_id]) {
901 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
902 port->slot_id, port->rhub->hcd->self.busnum,
903 port->hcd_portnum + 1);
904 continue;
905 }
906
907 udev = xhci->devs[port->slot_id]->udev;
908
909 /* if wakeup is enabled then don't disable the port */
910 if (udev->do_remote_wakeup && do_wakeup)
911 continue;
912
913 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
914 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
915 portsc = xhci_port_state_to_neutral(portsc);
916 writel(portsc | PORT_PE, port->addr);
917 }
918
919 return 0;
920 }
921
xhci_pci_shutdown(struct usb_hcd * hcd)922 static void xhci_pci_shutdown(struct usb_hcd *hcd)
923 {
924 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
925 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
926
927 xhci_shutdown(hcd);
928 xhci_cleanup_msix(xhci);
929
930 /* Yet another workaround for spurious wakeups at shutdown with HSW */
931 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
932 pci_set_power_state(pdev, PCI_D3hot);
933 }
934
935 /*-------------------------------------------------------------------------*/
936
937 /* PCI driver selection metadata; PCI hotplugging uses this */
938 static const struct pci_device_id pci_ids[] = {
939 /* handle any USB 3.0 xHCI controller */
940 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
941 },
942 { /* end: all zeroes */ }
943 };
944 MODULE_DEVICE_TABLE(pci, pci_ids);
945
946 /* pci driver glue; this is a "new style" PCI driver module */
947 static struct pci_driver xhci_pci_driver = {
948 .name = hcd_name,
949 .id_table = pci_ids,
950
951 .probe = xhci_pci_probe,
952 .remove = xhci_pci_remove,
953 /* suspend and resume implemented later */
954
955 .shutdown = usb_hcd_pci_shutdown,
956 .driver = {
957 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
958 },
959 };
960
xhci_pci_init(void)961 static int __init xhci_pci_init(void)
962 {
963 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
964 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
965 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
966 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
967 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
968 xhci_pci_hc_driver.stop = xhci_pci_stop;
969 return pci_register_driver(&xhci_pci_driver);
970 }
971 module_init(xhci_pci_init);
972
xhci_pci_exit(void)973 static void __exit xhci_pci_exit(void)
974 {
975 pci_unregister_driver(&xhci_pci_driver);
976 }
977 module_exit(xhci_pci_exit);
978
979 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
980 MODULE_LICENSE("GPL");
981