1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
15
16 /* qm user domain */
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
36
37 /* mailbox */
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_FLUSH_QM 0x9
47 #define QM_MB_CMD_SRC 0xc
48 #define QM_MB_CMD_DST 0xd
49
50 #define QM_MB_CMD_SEND_BASE 0x300
51 #define QM_MB_EVENT_SHIFT 8
52 #define QM_MB_BUSY_SHIFT 13
53 #define QM_MB_OP_SHIFT 14
54 #define QM_MB_CMD_DATA_ADDR_L 0x304
55 #define QM_MB_CMD_DATA_ADDR_H 0x308
56 #define QM_MB_MAX_WAIT_CNT 6000
57
58 /* doorbell */
59 #define QM_DOORBELL_CMD_SQ 0
60 #define QM_DOORBELL_CMD_CQ 1
61 #define QM_DOORBELL_CMD_EQ 2
62 #define QM_DOORBELL_CMD_AEQ 3
63
64 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
65 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
66 #define QM_QP_MAX_NUM_SHIFT 11
67 #define QM_DB_CMD_SHIFT_V2 12
68 #define QM_DB_RAND_SHIFT_V2 16
69 #define QM_DB_INDEX_SHIFT_V2 32
70 #define QM_DB_PRIORITY_SHIFT_V2 48
71 #define QM_VF_STATE 0x60
72
73 /* qm cache */
74 #define QM_CACHE_CTL 0x100050
75 #define SQC_CACHE_ENABLE BIT(0)
76 #define CQC_CACHE_ENABLE BIT(1)
77 #define SQC_CACHE_WB_ENABLE BIT(4)
78 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
79 #define CQC_CACHE_WB_ENABLE BIT(11)
80 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
81 #define QM_AXI_M_CFG 0x1000ac
82 #define AXI_M_CFG 0xffff
83 #define QM_AXI_M_CFG_ENABLE 0x1000b0
84 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
85 #define AXI_M_CFG_ENABLE 0xffffffff
86 #define QM_PEH_AXUSER_CFG 0x1000cc
87 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
88 #define PEH_AXUSER_CFG 0x401001
89 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
90
91 #define QM_MIN_QNUM 2
92 #define HISI_ACC_SGL_SGE_NR_MAX 255
93 #define QM_SHAPER_CFG 0x100164
94 #define QM_SHAPER_ENABLE BIT(30)
95 #define QM_SHAPER_TYPE1_OFFSET 10
96
97 /* page number for queue file region */
98 #define QM_DOORBELL_PAGE_NR 1
99
100 /* uacce mode of the driver */
101 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
102 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
103 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
104
105 enum qm_stop_reason {
106 QM_NORMAL,
107 QM_SOFT_RESET,
108 QM_DOWN,
109 };
110
111 enum qm_state {
112 QM_WORK = 0,
113 QM_STOP,
114 };
115
116 enum qp_state {
117 QP_START = 1,
118 QP_STOP,
119 };
120
121 enum qm_hw_ver {
122 QM_HW_V1 = 0x20,
123 QM_HW_V2 = 0x21,
124 QM_HW_V3 = 0x30,
125 };
126
127 enum qm_fun_type {
128 QM_HW_PF,
129 QM_HW_VF,
130 };
131
132 enum qm_debug_file {
133 CURRENT_QM,
134 CURRENT_Q,
135 CLEAR_ENABLE,
136 DEBUG_FILE_NUM,
137 };
138
139 enum qm_vf_state {
140 QM_READY = 0,
141 QM_NOT_READY,
142 };
143
144 enum qm_misc_ctl_bits {
145 QM_DRIVER_REMOVING = 0x0,
146 QM_RST_SCHED,
147 QM_RESETTING,
148 QM_MODULE_PARAM,
149 };
150
151 enum qm_cap_bits {
152 QM_SUPPORT_DB_ISOLATION = 0x0,
153 QM_SUPPORT_FUNC_QOS,
154 QM_SUPPORT_STOP_QP,
155 QM_SUPPORT_STOP_FUNC,
156 QM_SUPPORT_MB_COMMAND,
157 QM_SUPPORT_SVA_PREFETCH,
158 QM_SUPPORT_RPM,
159 };
160
161 struct qm_dev_alg {
162 u64 alg_msk;
163 const char *alg;
164 };
165
166 struct qm_dev_dfx {
167 u32 dev_state;
168 u32 dev_timeout;
169 };
170
171 struct dfx_diff_registers {
172 u32 *regs;
173 u32 reg_offset;
174 u32 reg_len;
175 };
176
177 struct qm_dfx {
178 atomic64_t err_irq_cnt;
179 atomic64_t aeq_irq_cnt;
180 atomic64_t abnormal_irq_cnt;
181 atomic64_t create_qp_err_cnt;
182 atomic64_t mb_err_cnt;
183 };
184
185 struct debugfs_file {
186 enum qm_debug_file index;
187 struct mutex lock;
188 struct qm_debug *debug;
189 };
190
191 struct qm_debug {
192 u32 curr_qm_qp_num;
193 u32 sqe_mask_offset;
194 u32 sqe_mask_len;
195 struct qm_dfx dfx;
196 struct dentry *debug_root;
197 struct dentry *qm_d;
198 struct debugfs_file files[DEBUG_FILE_NUM];
199 struct qm_dev_dfx dev_dfx;
200 unsigned int *qm_last_words;
201 /* ACC engines recoreding last regs */
202 unsigned int *last_words;
203 struct dfx_diff_registers *qm_diff_regs;
204 struct dfx_diff_registers *acc_diff_regs;
205 };
206
207 struct qm_shaper_factor {
208 u32 func_qos;
209 u64 cir_b;
210 u64 cir_u;
211 u64 cir_s;
212 u64 cbs_s;
213 };
214
215 struct qm_dma {
216 void *va;
217 dma_addr_t dma;
218 size_t size;
219 };
220
221 struct hisi_qm_status {
222 u32 eq_head;
223 bool eqc_phase;
224 u32 aeq_head;
225 bool aeqc_phase;
226 atomic_t flags;
227 int stop_reason;
228 };
229
230 struct hisi_qm;
231
232 enum acc_err_result {
233 ACC_ERR_NONE,
234 ACC_ERR_NEED_RESET,
235 ACC_ERR_RECOVERED,
236 };
237
238 struct hisi_qm_err_info {
239 char *acpi_rst;
240 u32 msi_wr_port;
241 u32 ecc_2bits_mask;
242 u32 qm_shutdown_mask;
243 u32 dev_shutdown_mask;
244 u32 qm_reset_mask;
245 u32 dev_reset_mask;
246 u32 ce;
247 u32 nfe;
248 u32 fe;
249 };
250
251 struct hisi_qm_err_status {
252 u32 is_qm_ecc_mbit;
253 u32 is_dev_ecc_mbit;
254 };
255
256 struct hisi_qm_err_ini {
257 int (*hw_init)(struct hisi_qm *qm);
258 void (*hw_err_enable)(struct hisi_qm *qm);
259 void (*hw_err_disable)(struct hisi_qm *qm);
260 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
261 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
262 void (*open_axi_master_ooo)(struct hisi_qm *qm);
263 void (*close_axi_master_ooo)(struct hisi_qm *qm);
264 void (*open_sva_prefetch)(struct hisi_qm *qm);
265 void (*close_sva_prefetch)(struct hisi_qm *qm);
266 void (*show_last_dfx_regs)(struct hisi_qm *qm);
267 void (*err_info_init)(struct hisi_qm *qm);
268 enum acc_err_result (*get_err_result)(struct hisi_qm *qm);
269 };
270
271 struct hisi_qm_cap_info {
272 u32 type;
273 /* Register offset */
274 u32 offset;
275 /* Bit offset in register */
276 u32 shift;
277 u32 mask;
278 u32 v1_val;
279 u32 v2_val;
280 u32 v3_val;
281 };
282
283 struct hisi_qm_cap_record {
284 u32 type;
285 u32 cap_val;
286 };
287
288 struct hisi_qm_cap_tables {
289 struct hisi_qm_cap_record *qm_cap_table;
290 struct hisi_qm_cap_record *dev_cap_table;
291 };
292
293 struct hisi_qm_list {
294 struct mutex lock;
295 struct list_head list;
296 int (*register_to_crypto)(struct hisi_qm *qm);
297 void (*unregister_from_crypto)(struct hisi_qm *qm);
298 };
299
300 struct hisi_qm_poll_data {
301 struct hisi_qm *qm;
302 struct work_struct work;
303 u16 *qp_finish_id;
304 u16 eqe_num;
305 };
306
307 /**
308 * struct qm_err_isolate
309 * @isolate_lock: protects device error log
310 * @err_threshold: user config error threshold which triggers isolation
311 * @is_isolate: device isolation state
312 * @uacce_hw_errs: index into qm device error list
313 */
314 struct qm_err_isolate {
315 struct mutex isolate_lock;
316 u32 err_threshold;
317 bool is_isolate;
318 struct list_head qm_hw_errs;
319 };
320
321 struct qm_rsv_buf {
322 struct qm_sqc *sqc;
323 struct qm_cqc *cqc;
324 struct qm_eqc *eqc;
325 struct qm_aeqc *aeqc;
326 dma_addr_t sqc_dma;
327 dma_addr_t cqc_dma;
328 dma_addr_t eqc_dma;
329 dma_addr_t aeqc_dma;
330 struct qm_dma qcdma;
331 };
332
333 struct hisi_qm {
334 enum qm_hw_ver ver;
335 enum qm_fun_type fun_type;
336 const char *dev_name;
337 struct pci_dev *pdev;
338 void __iomem *io_base;
339 void __iomem *db_io_base;
340
341 /* Capbility version, 0: not supports */
342 u32 cap_ver;
343 u32 sqe_size;
344 u32 qp_base;
345 u32 qp_num;
346 u32 qp_in_used;
347 u32 ctrl_qp_num;
348 u32 max_qp_num;
349 u32 vfs_num;
350 u32 db_interval;
351 u16 eq_depth;
352 u16 aeq_depth;
353 struct list_head list;
354 struct hisi_qm_list *qm_list;
355
356 struct qm_dma qdma;
357 struct qm_sqc *sqc;
358 struct qm_cqc *cqc;
359 struct qm_eqe *eqe;
360 struct qm_aeqe *aeqe;
361 dma_addr_t sqc_dma;
362 dma_addr_t cqc_dma;
363 dma_addr_t eqe_dma;
364 dma_addr_t aeqe_dma;
365 struct qm_rsv_buf xqc_buf;
366
367 struct hisi_qm_status status;
368 const struct hisi_qm_err_ini *err_ini;
369 struct hisi_qm_err_info err_info;
370 struct hisi_qm_err_status err_status;
371 /* driver removing and reset sched */
372 unsigned long misc_ctl;
373 /* Device capability bit */
374 unsigned long caps;
375
376 struct rw_semaphore qps_lock;
377 struct idr qp_idr;
378 struct hisi_qp *qp_array;
379 struct hisi_qm_poll_data *poll_data;
380
381 struct mutex mailbox_lock;
382
383 const struct hisi_qm_hw_ops *ops;
384
385 struct qm_debug debug;
386
387 u32 error_mask;
388
389 struct workqueue_struct *wq;
390 struct work_struct rst_work;
391 struct work_struct cmd_process;
392
393 bool use_sva;
394
395 resource_size_t phys_base;
396 resource_size_t db_phys_base;
397 struct uacce_device *uacce;
398 int mode;
399 struct qm_shaper_factor *factor;
400 u32 mb_qos;
401 u32 type_rate;
402 struct qm_err_isolate isolate_data;
403
404 struct hisi_qm_cap_tables cap_tables;
405 };
406
407 struct hisi_qp_status {
408 atomic_t used;
409 u16 sq_tail;
410 u16 cq_head;
411 bool cqc_phase;
412 atomic_t flags;
413 };
414
415 struct hisi_qp_ops {
416 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
417 };
418
419 struct hisi_qp {
420 u32 qp_id;
421 u16 sq_depth;
422 u16 cq_depth;
423 u8 alg_type;
424 u8 req_type;
425
426 struct qm_dma qdma;
427 void *sqe;
428 struct qm_cqe *cqe;
429 dma_addr_t sqe_dma;
430 dma_addr_t cqe_dma;
431
432 struct hisi_qp_status qp_status;
433 struct hisi_qp_ops *hw_ops;
434 void *qp_ctx;
435 void (*req_cb)(struct hisi_qp *qp, void *data);
436 void (*event_cb)(struct hisi_qp *qp);
437
438 struct hisi_qm *qm;
439 bool is_resetting;
440 bool is_in_kernel;
441 u16 pasid;
442 struct uacce_queue *uacce_q;
443 };
444
q_num_set(const char * val,const struct kernel_param * kp,unsigned int device)445 static inline int q_num_set(const char *val, const struct kernel_param *kp,
446 unsigned int device)
447 {
448 struct pci_dev *pdev;
449 u32 n, q_num;
450 int ret;
451
452 if (!val)
453 return -EINVAL;
454
455 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, device, NULL);
456 if (!pdev) {
457 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
458 pr_info("No device found currently, suppose queue number is %u\n",
459 q_num);
460 } else {
461 if (pdev->revision == QM_HW_V1)
462 q_num = QM_QNUM_V1;
463 else
464 q_num = QM_QNUM_V2;
465
466 pci_dev_put(pdev);
467 }
468
469 ret = kstrtou32(val, 10, &n);
470 if (ret || n < QM_MIN_QNUM || n > q_num)
471 return -EINVAL;
472
473 return param_set_int(val, kp);
474 }
475
vfs_num_set(const char * val,const struct kernel_param * kp)476 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
477 {
478 u32 n;
479 int ret;
480
481 if (!val)
482 return -EINVAL;
483
484 ret = kstrtou32(val, 10, &n);
485 if (ret < 0)
486 return ret;
487
488 if (n > QM_MAX_VFS_NUM_V2)
489 return -EINVAL;
490
491 return param_set_int(val, kp);
492 }
493
mode_set(const char * val,const struct kernel_param * kp)494 static inline int mode_set(const char *val, const struct kernel_param *kp)
495 {
496 u32 n;
497 int ret;
498
499 if (!val)
500 return -EINVAL;
501
502 ret = kstrtou32(val, 10, &n);
503 if (ret != 0 || (n != UACCE_MODE_SVA &&
504 n != UACCE_MODE_NOUACCE))
505 return -EINVAL;
506
507 return param_set_int(val, kp);
508 }
509
uacce_mode_set(const char * val,const struct kernel_param * kp)510 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
511 {
512 return mode_set(val, kp);
513 }
514
hisi_qm_init_list(struct hisi_qm_list * qm_list)515 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
516 {
517 INIT_LIST_HEAD(&qm_list->list);
518 mutex_init(&qm_list->lock);
519 }
520
hisi_qm_add_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)521 static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
522 {
523 mutex_lock(&qm_list->lock);
524 list_add_tail(&qm->list, &qm_list->list);
525 mutex_unlock(&qm_list->lock);
526 }
527
hisi_qm_del_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)528 static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
529 {
530 mutex_lock(&qm_list->lock);
531 list_del(&qm->list);
532 mutex_unlock(&qm_list->lock);
533 }
534
535 int hisi_qm_init(struct hisi_qm *qm);
536 void hisi_qm_uninit(struct hisi_qm *qm);
537 int hisi_qm_start(struct hisi_qm *qm);
538 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
539 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
540 void hisi_qm_stop_qp(struct hisi_qp *qp);
541 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
542 void hisi_qm_debug_init(struct hisi_qm *qm);
543 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
544 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
545 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
546 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
547 void hisi_qm_dev_err_init(struct hisi_qm *qm);
548 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
549 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
550 struct dfx_diff_registers *dregs, u32 reg_len);
551 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
552 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
553 struct dfx_diff_registers *dregs, u32 regs_len);
554
555 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
556 pci_channel_state_t state);
557 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
558 void hisi_qm_reset_prepare(struct pci_dev *pdev);
559 void hisi_qm_reset_done(struct pci_dev *pdev);
560
561 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
562 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
563 bool op);
564
565 struct hisi_acc_sgl_pool;
566 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
567 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
568 u32 index, dma_addr_t *hw_sgl_dma);
569 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
570 struct hisi_acc_hw_sgl *hw_sgl);
571 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
572 u32 count, u32 sge_nr);
573 void hisi_acc_free_sgl_pool(struct device *dev,
574 struct hisi_acc_sgl_pool *pool);
575 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
576 u8 alg_type, int node, struct hisi_qp **qps);
577 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
578 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
579 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
580 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
581 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
582 int hisi_qm_resume(struct device *dev);
583 int hisi_qm_suspend(struct device *dev);
584 void hisi_qm_pm_uninit(struct hisi_qm *qm);
585 void hisi_qm_pm_init(struct hisi_qm *qm);
586 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
587 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
588 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
589 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
590 const struct hisi_qm_cap_info *info_table,
591 u32 index, bool is_read);
592 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
593 u32 dev_algs_size);
594
595 /* Used by VFIO ACC live migration driver */
596 struct pci_driver *hisi_sec_get_pf_driver(void);
597 struct pci_driver *hisi_hpre_get_pf_driver(void);
598 struct pci_driver *hisi_zip_get_pf_driver(void);
599 #endif
600