1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9#include "imx8mm-overdrive.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 aliases { 17 rtc0 = &rtc_i2c; 18 rtc1 = &snvs_rtc; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 brightness-levels = <0 45 63 88 119 158 203 255>; 24 default-brightness-level = <4>; 25 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 26 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 29 power-supply = <®_3p3v>; 30 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 31 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 32 status = "disabled"; 33 }; 34 35 /* Fixed clock dedicated to SPI CAN controller */ 36 clk40m: oscillator { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <40000000>; 40 }; 41 42 gpio-keys { 43 compatible = "gpio-keys"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_gpio_keys>; 46 47 key-wakeup { 48 debounce-interval = <10>; 49 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 50 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 51 label = "Wake-Up"; 52 linux,code = <KEY_WAKEUP>; 53 wakeup-source; 54 }; 55 }; 56 57 hdmi_connector: hdmi-connector { 58 compatible = "hdmi-connector"; 59 ddc-i2c-bus = <&i2c2>; 60 /* Verdin PWM_3_DSI (SODIMM 19) */ 61 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 62 label = "hdmi"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 65 type = "a"; 66 status = "disabled"; 67 }; 68 69 panel_lvds: panel-lvds { 70 compatible = "panel-lvds"; 71 backlight = <&backlight>; 72 data-mapping = "vesa-24"; 73 status = "disabled"; 74 }; 75 76 /* Carrier Board Supplies */ 77 reg_1p8v: regulator-1p8v { 78 compatible = "regulator-fixed"; 79 regulator-max-microvolt = <1800000>; 80 regulator-min-microvolt = <1800000>; 81 regulator-name = "+V1.8_SW"; 82 }; 83 84 reg_3p3v: regulator-3p3v { 85 compatible = "regulator-fixed"; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "+V3.3_SW"; 89 }; 90 91 reg_5p0v: regulator-5p0v { 92 compatible = "regulator-fixed"; 93 regulator-max-microvolt = <5000000>; 94 regulator-min-microvolt = <5000000>; 95 regulator-name = "+V5_SW"; 96 }; 97 98 /* Non PMIC On-module Supplies */ 99 reg_ethphy: regulator-ethphy { 100 compatible = "regulator-fixed"; 101 enable-active-high; 102 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 103 off-on-delay-us = <500000>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_reg_eth>; 106 regulator-always-on; 107 regulator-boot-on; 108 regulator-max-microvolt = <3300000>; 109 regulator-min-microvolt = <3300000>; 110 regulator-name = "On-module +V3.3_ETH"; 111 startup-delay-us = <200000>; 112 }; 113 114 /* 115 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 116 * peripherals on the carrier board powered. 117 * If more granularity or power saving is required this can be disabled 118 * in the carrier board device tree files. 119 */ 120 reg_force_sleep_moci: regulator-force-sleep-moci { 121 compatible = "regulator-fixed"; 122 enable-active-high; 123 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 124 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 125 regulator-always-on; 126 regulator-boot-on; 127 regulator-name = "CTRL_SLEEP_MOCI#"; 128 }; 129 130 reg_usb_otg1_vbus: regulator-usb-otg1 { 131 compatible = "regulator-fixed"; 132 enable-active-high; 133 /* Verdin USB_1_EN (SODIMM 155) */ 134 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_reg_usb1_en>; 137 regulator-max-microvolt = <5000000>; 138 regulator-min-microvolt = <5000000>; 139 regulator-name = "USB_1_EN"; 140 }; 141 142 reg_usb_otg2_vbus: regulator-usb-otg2 { 143 compatible = "regulator-fixed"; 144 enable-active-high; 145 /* Verdin USB_2_EN (SODIMM 185) */ 146 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_reg_usb2_en>; 149 regulator-max-microvolt = <5000000>; 150 regulator-min-microvolt = <5000000>; 151 regulator-name = "USB_2_EN"; 152 }; 153 154 reg_usdhc2_vmmc: regulator-usdhc2 { 155 compatible = "regulator-fixed"; 156 enable-active-high; 157 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 158 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 159 off-on-delay-us = <100000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 162 regulator-max-microvolt = <3300000>; 163 regulator-min-microvolt = <3300000>; 164 regulator-name = "+V3.3_SD"; 165 startup-delay-us = <20000>; 166 }; 167 168 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 169 compatible = "regulator-gpio"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 172 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 173 regulator-max-microvolt = <3300000>; 174 regulator-min-microvolt = <1800000>; 175 states = <1800000 0x1>, 176 <3300000 0x0>; 177 regulator-name = "PMIC_USDHC_VSELECT"; 178 vin-supply = <®_nvcc_sd>; 179 }; 180 181 reserved-memory { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges; 185 186 /* Use the kernel configuration settings instead */ 187 /delete-node/ linux,cma; 188 }; 189}; 190 191&A53_0 { 192 cpu-supply = <®_vdd_arm>; 193}; 194 195&A53_1 { 196 cpu-supply = <®_vdd_arm>; 197}; 198 199&A53_2 { 200 cpu-supply = <®_vdd_arm>; 201}; 202 203&A53_3 { 204 cpu-supply = <®_vdd_arm>; 205}; 206 207&cpu_alert0 { 208 temperature = <95000>; 209}; 210 211&cpu_crit0 { 212 temperature = <105000>; 213}; 214 215&ddrc { 216 operating-points-v2 = <&ddrc_opp_table>; 217 218 ddrc_opp_table: opp-table { 219 compatible = "operating-points-v2"; 220 221 opp-25000000 { 222 opp-hz = /bits/ 64 <25000000>; 223 }; 224 225 opp-100000000 { 226 opp-hz = /bits/ 64 <100000000>; 227 }; 228 229 opp-750000000 { 230 opp-hz = /bits/ 64 <750000000>; 231 }; 232 }; 233}; 234 235/* Verdin SPI_1 */ 236&ecspi2 { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_ecspi2>; 242}; 243 244/* On-module SPI */ 245&ecspi3 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>; 251 status = "okay"; 252 253 /* Verdin CAN_1 */ 254 can1: can@0 { 255 compatible = "microchip,mcp251xfd"; 256 clocks = <&clk40m>; 257 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_can1_int>; 260 reg = <0>; 261 spi-max-frequency = <8500000>; 262 }; 263 264 verdin_som_tpm: tpm@1 { 265 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 266 reg = <0x1>; 267 spi-max-frequency = <36000000>; 268 }; 269}; 270 271/* Verdin ETH_1 (On-module PHY) */ 272&fec1 { 273 fsl,magic-packet; 274 phy-handle = <ðphy0>; 275 phy-mode = "rgmii-id"; 276 phy-supply = <®_ethphy>; 277 pinctrl-names = "default", "sleep"; 278 pinctrl-0 = <&pinctrl_fec1>; 279 pinctrl-1 = <&pinctrl_fec1_sleep>; 280 281 mdio { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 285 ethphy0: ethernet-phy@7 { 286 compatible = "ethernet-phy-ieee802.3-c22"; 287 interrupt-parent = <&gpio1>; 288 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 289 micrel,led-mode = <0>; 290 reg = <7>; 291 }; 292 }; 293}; 294 295/* Verdin QSPI_1 */ 296&flexspi { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_flexspi0>; 299}; 300 301&gpio1 { 302 gpio-line-names = "SODIMM_216", 303 "SODIMM_19", 304 "", 305 "", 306 "PMIC_USDHC_VSELECT", 307 "", 308 "", 309 "", 310 "SODIMM_220", 311 "SODIMM_222", 312 "", 313 "SODIMM_218", 314 "SODIMM_155", 315 "SODIMM_157", 316 "SODIMM_185", 317 "SODIMM_187"; 318}; 319 320&gpio2 { 321 gpio-line-names = "", 322 "", 323 "", 324 "", 325 "", 326 "", 327 "", 328 "", 329 "", 330 "", 331 "", 332 "", 333 "SODIMM_84", 334 "SODIMM_78", 335 "SODIMM_74", 336 "SODIMM_80", 337 "SODIMM_82", 338 "SODIMM_70", 339 "SODIMM_72"; 340}; 341 342&gpio5 { 343 gpio-line-names = "SODIMM_131", 344 "", 345 "SODIMM_91", 346 "SODIMM_16", 347 "SODIMM_15", 348 "SODIMM_208", 349 "SODIMM_137", 350 "SODIMM_139", 351 "SODIMM_141", 352 "SODIMM_143", 353 "SODIMM_196", 354 "SODIMM_200", 355 "SODIMM_198", 356 "SODIMM_202", 357 "", 358 "", 359 "SODIMM_55", 360 "SODIMM_53", 361 "SODIMM_95", 362 "SODIMM_93", 363 "SODIMM_14", 364 "SODIMM_12", 365 "", 366 "", 367 "", 368 "", 369 "SODIMM_210", 370 "SODIMM_212", 371 "SODIMM_151", 372 "SODIMM_153"; 373}; 374 375/* On-module I2C */ 376&i2c1 { 377 clock-frequency = <400000>; 378 pinctrl-names = "default", "gpio"; 379 pinctrl-0 = <&pinctrl_i2c1>; 380 pinctrl-1 = <&pinctrl_i2c1_gpio>; 381 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 382 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 383 status = "okay"; 384 385 pca9450: pmic@25 { 386 compatible = "nxp,pca9450a"; 387 interrupt-parent = <&gpio1>; 388 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 389 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_pmic>; 392 reg = <0x25>; 393 394 /* 395 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 396 * behind this PMIC. 397 */ 398 399 regulators { 400 reg_vdd_soc: BUCK1 { 401 nxp,dvs-run-voltage = <850000>; 402 nxp,dvs-standby-voltage = <800000>; 403 regulator-always-on; 404 regulator-boot-on; 405 regulator-max-microvolt = <850000>; 406 regulator-min-microvolt = <800000>; 407 regulator-name = "On-module +VDD_SOC (BUCK1)"; 408 regulator-ramp-delay = <3125>; 409 }; 410 411 reg_vdd_arm: BUCK2 { 412 nxp,dvs-run-voltage = <950000>; 413 nxp,dvs-standby-voltage = <850000>; 414 regulator-always-on; 415 regulator-boot-on; 416 regulator-max-microvolt = <1050000>; 417 regulator-min-microvolt = <805000>; 418 regulator-name = "On-module +VDD_ARM (BUCK2)"; 419 regulator-ramp-delay = <3125>; 420 }; 421 422 reg_vdd_dram: BUCK3 { 423 regulator-always-on; 424 regulator-boot-on; 425 regulator-max-microvolt = <1000000>; 426 regulator-min-microvolt = <805000>; 427 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 428 }; 429 430 reg_vdd_3v3: BUCK4 { 431 regulator-always-on; 432 regulator-boot-on; 433 regulator-max-microvolt = <3300000>; 434 regulator-min-microvolt = <3300000>; 435 regulator-name = "On-module +V3.3 (BUCK4)"; 436 }; 437 438 reg_vdd_1v8: BUCK5 { 439 regulator-always-on; 440 regulator-boot-on; 441 regulator-max-microvolt = <1800000>; 442 regulator-min-microvolt = <1800000>; 443 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 444 }; 445 446 reg_nvcc_dram: BUCK6 { 447 regulator-always-on; 448 regulator-boot-on; 449 regulator-max-microvolt = <1100000>; 450 regulator-min-microvolt = <1100000>; 451 regulator-name = "On-module +VDD_DDR (BUCK6)"; 452 }; 453 454 reg_nvcc_snvs: LDO1 { 455 regulator-always-on; 456 regulator-boot-on; 457 regulator-max-microvolt = <1800000>; 458 regulator-min-microvolt = <1800000>; 459 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 460 }; 461 462 reg_vdd_snvs: LDO2 { 463 regulator-always-on; 464 regulator-boot-on; 465 regulator-max-microvolt = <800000>; 466 regulator-min-microvolt = <800000>; 467 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 468 }; 469 470 reg_vdda: LDO3 { 471 regulator-always-on; 472 regulator-boot-on; 473 regulator-max-microvolt = <1800000>; 474 regulator-min-microvolt = <1800000>; 475 regulator-name = "On-module +V1.8A (LDO3)"; 476 }; 477 478 reg_vdd_phy: LDO4 { 479 regulator-always-on; 480 regulator-boot-on; 481 regulator-max-microvolt = <900000>; 482 regulator-min-microvolt = <900000>; 483 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 484 }; 485 486 reg_nvcc_sd: LDO5 { 487 regulator-always-on; 488 regulator-max-microvolt = <3300000>; 489 regulator-min-microvolt = <1800000>; 490 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 491 }; 492 }; 493 }; 494 495 rtc_i2c: rtc@32 { 496 compatible = "epson,rx8130"; 497 reg = <0x32>; 498 }; 499 500 adc@49 { 501 compatible = "ti,ads1015"; 502 reg = <0x49>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 507 channel@0 { 508 reg = <0>; 509 ti,datarate = <4>; 510 ti,gain = <2>; 511 }; 512 513 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 514 channel@1 { 515 reg = <1>; 516 ti,datarate = <4>; 517 ti,gain = <2>; 518 }; 519 520 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 521 channel@2 { 522 reg = <2>; 523 ti,datarate = <4>; 524 ti,gain = <2>; 525 }; 526 527 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 528 channel@3 { 529 reg = <3>; 530 ti,datarate = <4>; 531 ti,gain = <2>; 532 }; 533 534 /* Verdin I2C_1 ADC_4 */ 535 channel@4 { 536 reg = <4>; 537 ti,datarate = <4>; 538 ti,gain = <2>; 539 }; 540 541 /* Verdin I2C_1 ADC_3 */ 542 channel@5 { 543 reg = <5>; 544 ti,datarate = <4>; 545 ti,gain = <2>; 546 }; 547 548 /* Verdin I2C_1 ADC_2 */ 549 channel@6 { 550 reg = <6>; 551 ti,datarate = <4>; 552 ti,gain = <2>; 553 }; 554 555 /* Verdin I2C_1 ADC_1 */ 556 channel@7 { 557 reg = <7>; 558 ti,datarate = <4>; 559 ti,gain = <2>; 560 }; 561 }; 562 563 eeprom@50 { 564 compatible = "st,24c02"; 565 pagesize = <16>; 566 reg = <0x50>; 567 }; 568}; 569 570/* Verdin I2C_2_DSI */ 571&i2c2 { 572 clock-frequency = <400000>; 573 pinctrl-names = "default", "gpio"; 574 pinctrl-0 = <&pinctrl_i2c2>; 575 pinctrl-1 = <&pinctrl_i2c2_gpio>; 576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 578 status = "disabled"; 579}; 580 581/* Verdin I2C_3_HDMI N/A */ 582 583/* Verdin I2C_4_CSI */ 584&i2c3 { 585 clock-frequency = <400000>; 586 pinctrl-names = "default", "gpio"; 587 pinctrl-0 = <&pinctrl_i2c3>; 588 pinctrl-1 = <&pinctrl_i2c3_gpio>; 589 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 590 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 591}; 592 593/* Verdin I2C_1 */ 594&i2c4 { 595 clock-frequency = <400000>; 596 pinctrl-names = "default", "gpio"; 597 pinctrl-0 = <&pinctrl_i2c4>; 598 pinctrl-1 = <&pinctrl_i2c4_gpio>; 599 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 600 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 601 602 gpio_expander_21: gpio-expander@21 { 603 compatible = "nxp,pcal6416"; 604 #gpio-cells = <2>; 605 gpio-controller; 606 reg = <0x21>; 607 vcc-supply = <®_3p3v>; 608 status = "disabled"; 609 }; 610 611 lvds_ti_sn65dsi84: bridge@2c { 612 compatible = "ti,sn65dsi84"; 613 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 614 /* Verdin GPIO_10_DSI (SODIMM 21) */ 615 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 618 reg = <0x2c>; 619 status = "disabled"; 620 }; 621 622 /* Current measurement into module VCC */ 623 hwmon: hwmon@40 { 624 compatible = "ti,ina219"; 625 reg = <0x40>; 626 shunt-resistor = <10000>; 627 status = "disabled"; 628 }; 629 630 hdmi_lontium_lt8912: hdmi@48 { 631 compatible = "lontium,lt8912b"; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 634 reg = <0x48>; 635 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 636 /* Verdin GPIO_10_DSI (SODIMM 21) */ 637 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 638 status = "disabled"; 639 }; 640 641 atmel_mxt_ts: touch@4a { 642 compatible = "atmel,maxtouch"; 643 /* 644 * Verdin GPIO_9_DSI 645 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 646 */ 647 interrupt-parent = <&gpio3>; 648 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 651 reg = <0x4a>; 652 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 653 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 654 status = "disabled"; 655 }; 656 657 /* Temperature sensor on carrier board */ 658 hwmon_temp: sensor@4f { 659 compatible = "ti,tmp75c"; 660 reg = <0x4f>; 661 status = "disabled"; 662 }; 663 664 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 665 eeprom_display_adapter: eeprom@50 { 666 compatible = "st,24c02"; 667 pagesize = <16>; 668 reg = <0x50>; 669 status = "disabled"; 670 }; 671 672 /* EEPROM on carrier board */ 673 eeprom_carrier_board: eeprom@57 { 674 compatible = "st,24c02"; 675 pagesize = <16>; 676 reg = <0x57>; 677 status = "disabled"; 678 }; 679}; 680 681/* Verdin PCIE_1 */ 682&pcie0 { 683 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 684 <&clk IMX8MM_CLK_PCIE1_CTRL>; 685 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 686 <&clk IMX8MM_SYS_PLL2_250M>; 687 assigned-clock-rates = <10000000>, <250000000>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pinctrl_pcie0>; 690 /* PCIE_1_RESET# (SODIMM 244) */ 691 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 692}; 693 694&pcie_phy { 695 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 696 clock-names = "ref"; 697 fsl,clkreq-unsupported; 698 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 699 fsl,tx-deemph-gen1 = <0x2d>; 700 fsl,tx-deemph-gen2 = <0xf>; 701}; 702 703/* Verdin PWM_3_DSI */ 704&pwm1 { 705 pinctrl-names = "default"; 706 pinctrl-0 = <&pinctrl_pwm_1>; 707 #pwm-cells = <3>; 708}; 709 710/* Verdin PWM_1 */ 711&pwm2 { 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pinctrl_pwm_2>; 714 #pwm-cells = <3>; 715}; 716 717/* Verdin PWM_2 */ 718&pwm3 { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_pwm_3>; 721 #pwm-cells = <3>; 722}; 723 724/* Verdin I2S_1 */ 725&sai2 { 726 #sound-dai-cells = <0>; 727 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 728 assigned-clock-rates = <24576000>; 729 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&pinctrl_sai2>; 732}; 733 734&snvs_pwrkey { 735 status = "okay"; 736}; 737 738/* Verdin UART_3, used as the Linux console */ 739&uart1 { 740 pinctrl-names = "default"; 741 pinctrl-0 = <&pinctrl_uart1>; 742}; 743 744/* Verdin UART_1 */ 745&uart2 { 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_uart2>; 748 uart-has-rtscts; 749}; 750 751/* Verdin UART_2 */ 752&uart3 { 753 pinctrl-names = "default"; 754 pinctrl-0 = <&pinctrl_uart3>; 755 uart-has-rtscts; 756}; 757 758/* 759 * Verdin UART_4 760 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 761 */ 762&uart4 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_uart4>; 765}; 766 767/* Verdin USB_1 */ 768&usbotg1 { 769 adp-disable; 770 dr_mode = "otg"; 771 hnp-disable; 772 samsung,picophy-dc-vol-level-adjust = <7>; 773 samsung,picophy-pre-emp-curr-control = <3>; 774 srp-disable; 775 vbus-supply = <®_usb_otg1_vbus>; 776}; 777 778/* Verdin USB_2 */ 779&usbotg2 { 780 dr_mode = "host"; 781 samsung,picophy-dc-vol-level-adjust = <7>; 782 samsung,picophy-pre-emp-curr-control = <3>; 783 vbus-supply = <®_usb_otg2_vbus>; 784}; 785 786&usbphynop1 { 787 vcc-supply = <®_vdd_3v3>; 788}; 789 790&usbphynop2 { 791 power-domains = <&pgc_otg2>; 792 vcc-supply = <®_vdd_3v3>; 793}; 794 795/* On-module eMMC */ 796&usdhc1 { 797 bus-width = <8>; 798 keep-power-in-suspend; 799 non-removable; 800 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 801 pinctrl-0 = <&pinctrl_usdhc1>; 802 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 803 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 804 status = "okay"; 805}; 806 807/* Verdin SD_1 */ 808&usdhc2 { 809 bus-width = <4>; 810 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 811 disable-wp; 812 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 813 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 814 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 815 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 816 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 817 vmmc-supply = <®_usdhc2_vmmc>; 818 vqmmc-supply = <®_usdhc2_vqmmc>; 819}; 820 821&wdog1 { 822 fsl,ext-reset-output; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&pinctrl_wdog>; 825 status = "okay"; 826}; 827 828&iomuxc { 829 pinctrl-names = "default"; 830 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 831 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 832 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 833 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; 834 835 pinctrl_can1_int: can1intgrp { 836 fsl,pins = 837 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 838 }; 839 840 pinctrl_can2_int: can2intgrp { 841 fsl,pins = 842 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 843 }; 844 845 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 846 fsl,pins = 847 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 848 }; 849 850 pinctrl_ecspi2: ecspi2grp { 851 fsl,pins = 852 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 853 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 854 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 855 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 856 }; 857 858 pinctrl_ecspi3: ecspi3grp { 859 fsl,pins = 860 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 861 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 862 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 863 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 864 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 865 }; 866 867 pinctrl_fec1: fec1grp { 868 fsl,pins = 869 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 870 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 871 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 872 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 873 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 874 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 875 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 876 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 877 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 878 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 879 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 880 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 881 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 882 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 883 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 884 }; 885 886 pinctrl_fec1_sleep: fec1-sleepgrp { 887 fsl,pins = 888 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 889 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 890 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 891 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 892 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 893 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 894 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 895 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 896 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 897 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 898 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 899 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 900 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 901 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 902 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 903 }; 904 905 pinctrl_flexspi0: flexspi0grp { 906 fsl,pins = 907 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 908 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 909 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 910 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 911 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 912 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 913 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 914 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 915 }; 916 917 pinctrl_gpio1: gpio1grp { 918 fsl,pins = 919 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 920 }; 921 922 pinctrl_gpio2: gpio2grp { 923 fsl,pins = 924 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 925 }; 926 927 pinctrl_gpio3: gpio3grp { 928 fsl,pins = 929 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 930 }; 931 932 pinctrl_gpio4: gpio4grp { 933 fsl,pins = 934 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 935 }; 936 937 pinctrl_gpio5: gpio5grp { 938 fsl,pins = 939 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 940 }; 941 942 pinctrl_gpio6: gpio6grp { 943 fsl,pins = 944 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 945 }; 946 947 pinctrl_gpio7: gpio7grp { 948 fsl,pins = 949 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 950 }; 951 952 pinctrl_gpio8: gpio8grp { 953 fsl,pins = 954 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 955 }; 956 957 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 958 pinctrl_gpio_9_dsi: gpio9dsigrp { 959 fsl,pins = 960 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */ 961 }; 962 963 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 964 pinctrl_gpio_10_dsi: gpio10dsigrp { 965 fsl,pins = 966 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 967 }; 968 969 pinctrl_gpio_hog1: gpiohog1grp { 970 fsl,pins = 971 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 972 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 973 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 974 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 975 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 976 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 977 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 978 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 979 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 980 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 981 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 982 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 983 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 984 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 985 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 986 }; 987 988 pinctrl_gpio_hog2: gpiohog2grp { 989 fsl,pins = 990 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 991 }; 992 993 pinctrl_gpio_hog3: gpiohog3grp { 994 fsl,pins = 995 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 996 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 997 }; 998 999 pinctrl_gpio_keys: gpiokeysgrp { 1000 fsl,pins = 1001 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 1002 }; 1003 1004 /* On-module I2C */ 1005 pinctrl_i2c1: i2c1grp { 1006 fsl,pins = 1007 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 1008 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 1009 }; 1010 1011 pinctrl_i2c1_gpio: i2c1gpiogrp { 1012 fsl,pins = 1013 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 1014 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 1015 }; 1016 1017 /* Verdin I2C_4_CSI */ 1018 pinctrl_i2c2: i2c2grp { 1019 fsl,pins = 1020 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 1021 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 1022 }; 1023 1024 pinctrl_i2c2_gpio: i2c2gpiogrp { 1025 fsl,pins = 1026 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1027 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1028 }; 1029 1030 /* Verdin I2C_2_DSI */ 1031 pinctrl_i2c3: i2c3grp { 1032 fsl,pins = 1033 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1034 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1035 }; 1036 1037 pinctrl_i2c3_gpio: i2c3gpiogrp { 1038 fsl,pins = 1039 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1040 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1041 }; 1042 1043 /* Verdin I2C_1 */ 1044 pinctrl_i2c4: i2c4grp { 1045 fsl,pins = 1046 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1047 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1048 }; 1049 1050 pinctrl_i2c4_gpio: i2c4gpiogrp { 1051 fsl,pins = 1052 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1053 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1054 }; 1055 1056 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1057 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1058 fsl,pins = 1059 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1060 }; 1061 1062 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1063 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1064 fsl,pins = 1065 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1066 }; 1067 1068 pinctrl_pcie0: pcie0grp { 1069 fsl,pins = 1070 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1071 /* PMIC_EN_PCIe_CLK, unused */ 1072 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1073 }; 1074 1075 pinctrl_pmic: pmicirqgrp { 1076 fsl,pins = 1077 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1078 }; 1079 1080 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1081 pinctrl_pwm_1: pwm1grp { 1082 fsl,pins = 1083 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1084 }; 1085 1086 pinctrl_pwm_2: pwm2grp { 1087 fsl,pins = 1088 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1089 }; 1090 1091 pinctrl_pwm_3: pwm3grp { 1092 fsl,pins = 1093 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1094 }; 1095 1096 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1097 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1098 fsl,pins = 1099 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1100 }; 1101 1102 pinctrl_reg_eth: regethgrp { 1103 fsl,pins = 1104 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1105 }; 1106 1107 pinctrl_reg_usb1_en: regusb1engrp { 1108 fsl,pins = 1109 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1110 }; 1111 1112 pinctrl_reg_usb2_en: regusb2engrp { 1113 fsl,pins = 1114 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1115 }; 1116 1117 pinctrl_sai2: sai2grp { 1118 fsl,pins = 1119 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1120 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1121 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1122 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1123 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1124 }; 1125 1126 pinctrl_sai5: sai5grp { 1127 fsl,pins = 1128 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1129 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1130 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1131 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1132 }; 1133 1134 /* control signal for optional ATTPM20P or SE050 */ 1135 pinctrl_tpm_spi_cs: tpmspicsgrp { 1136 fsl,pins = 1137 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1138 }; 1139 1140 pinctrl_tsp: tspgrp { 1141 fsl,pins = 1142 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1143 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1144 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1145 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1146 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1147 }; 1148 1149 pinctrl_uart1: uart1grp { 1150 fsl,pins = 1151 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1152 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1153 }; 1154 1155 pinctrl_uart2: uart2grp { 1156 fsl,pins = 1157 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1158 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1159 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1160 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1161 }; 1162 1163 pinctrl_uart3: uart3grp { 1164 fsl,pins = 1165 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1166 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1167 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1168 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1169 }; 1170 1171 pinctrl_uart4: uart4grp { 1172 fsl,pins = 1173 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1174 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1175 }; 1176 1177 pinctrl_usdhc1: usdhc1grp { 1178 fsl,pins = 1179 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1180 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1181 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1182 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1183 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1184 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1185 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1186 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1187 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1188 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1189 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1190 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1191 }; 1192 1193 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1194 fsl,pins = 1195 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1196 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1197 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1198 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1199 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1200 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1201 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1202 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1203 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1204 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1205 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1206 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1207 }; 1208 1209 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1210 fsl,pins = 1211 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1212 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1213 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1214 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1215 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1216 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1217 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1218 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1219 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1220 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1221 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1222 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1223 }; 1224 1225 pinctrl_usdhc2_cd: usdhc2cdgrp { 1226 fsl,pins = 1227 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1228 }; 1229 1230 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1231 fsl,pins = 1232 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1233 }; 1234 1235 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1236 fsl,pins = 1237 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1238 }; 1239 1240 pinctrl_usdhc2_vsel: usdhc2vselgrp { 1241 fsl,pins = 1242 <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */ 1243 }; 1244 1245 /* 1246 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1247 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1248 */ 1249 pinctrl_usdhc2: usdhc2grp { 1250 fsl,pins = 1251 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1252 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1253 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1254 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1255 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1256 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1257 }; 1258 1259 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1260 fsl,pins = 1261 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1262 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1263 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1264 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1265 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1266 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1267 }; 1268 1269 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1270 fsl,pins = 1271 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1272 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1273 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1274 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1275 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1276 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1277 }; 1278 1279 /* Avoid backfeeding with removed card power */ 1280 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1281 fsl,pins = 1282 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1283 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1284 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1285 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1286 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1287 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1288 }; 1289 1290 /* 1291 * On-module Wi-Fi/BT or type specific SDHC interface 1292 * (e.g. on X52 extension slot of Verdin Development Board) 1293 */ 1294 pinctrl_usdhc3: usdhc3grp { 1295 fsl,pins = 1296 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1297 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1298 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1299 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1300 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1301 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1302 }; 1303 1304 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1305 fsl,pins = 1306 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1307 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1308 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1309 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1310 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1311 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1312 }; 1313 1314 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1315 fsl,pins = 1316 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1317 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1318 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1319 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1320 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1321 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1322 }; 1323 1324 pinctrl_wdog: wdoggrp { 1325 fsl,pins = 1326 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1327 }; 1328 1329 pinctrl_wifi_ctrl: wifictrlgrp { 1330 fsl,pins = 1331 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1332 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1333 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1334 }; 1335 1336 pinctrl_wifi_i2s: bti2sgrp { 1337 fsl,pins = 1338 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1339 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1340 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1341 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1342 }; 1343 1344 pinctrl_wifi_pwr_en: wifipwrengrp { 1345 fsl,pins = 1346 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1347 }; 1348}; 1349