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1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
12	compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
13
14	memory@40000000 {
15		device_type = "memory";
16		reg = <0x0 0x40000000 0 0x80000000>;
17	};
18
19	/* identical to buck4_reg, but should never change */
20	reg_vcc3v3: regulator-vcc3v3 {
21		compatible = "regulator-fixed";
22		regulator-name = "VCC3V3";
23		regulator-min-microvolt = <3300000>;
24		regulator-max-microvolt = <3300000>;
25		regulator-always-on;
26	};
27
28	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
29		compatible = "regulator-gpio";
30		pinctrl-names = "default";
31		pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
32		regulator-name = "V_SD2";
33		regulator-min-microvolt = <1800000>;
34		regulator-max-microvolt = <3300000>;
35		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
36		states = <1800000 0x1>,
37			 <3300000 0x0>;
38		vin-supply = <&ldo5_reg>;
39		status = "disabled";
40	};
41};
42
43&A53_0 {
44	cpu-supply = <&buck2_reg>;
45};
46
47&flexspi {
48	pinctrl-names = "default";
49	pinctrl-0 = <&pinctrl_flexspi0>;
50	status = "okay";
51
52	flash0: flash@0 {
53		reg = <0>;
54		compatible = "jedec,spi-nor";
55		spi-max-frequency = <80000000>;
56		spi-tx-bus-width = <1>;
57		spi-rx-bus-width = <4>;
58
59		partitions {
60			compatible = "fixed-partitions";
61			#address-cells = <1>;
62			#size-cells = <1>;
63		};
64	};
65};
66
67&i2c1 {
68	clock-frequency = <384000>;
69	pinctrl-names = "default", "gpio";
70	pinctrl-0 = <&pinctrl_i2c1>;
71	pinctrl-1 = <&pinctrl_i2c1_gpio>;
72	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
73	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
74	status = "okay";
75
76	se97: temperature-sensor@1b {
77		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
78		reg = <0x1b>;
79	};
80
81	pmic: pmic@25 {
82		reg = <0x25>;
83		compatible = "nxp,pca9450c";
84
85		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
86		pinctrl-0 = <&pinctrl_pmic>;
87		pinctrl-names = "default";
88		interrupt-parent = <&gpio1>;
89		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
90
91		regulators {
92			/* V_0V85_SOC: 0.85 .. 0.95 */
93			buck1_reg: BUCK1 {
94				regulator-name = "BUCK1";
95				regulator-min-microvolt = <850000>;
96				regulator-max-microvolt = <950000>;
97				regulator-boot-on;
98				regulator-always-on;
99				regulator-ramp-delay = <3125>;
100			};
101
102			/* VDD_ARM */
103			buck2_reg: BUCK2 {
104				regulator-name = "BUCK2";
105				regulator-min-microvolt = <850000>;
106				regulator-max-microvolt = <1000000>;
107				regulator-boot-on;
108				regulator-always-on;
109				nxp,dvs-run-voltage = <950000>;
110				nxp,dvs-standby-voltage = <850000>;
111				regulator-ramp-delay = <3125>;
112			};
113
114			/* VCC3V3 -> VMMC, ... must not be changed */
115			buck4_reg: BUCK4 {
116				regulator-name = "BUCK4";
117				regulator-min-microvolt = <3300000>;
118				regulator-max-microvolt = <3300000>;
119				regulator-boot-on;
120				regulator-always-on;
121			};
122
123			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
124			buck5_reg: BUCK5 {
125				regulator-name = "BUCK5";
126				regulator-min-microvolt = <1800000>;
127				regulator-max-microvolt = <1800000>;
128				regulator-boot-on;
129				regulator-always-on;
130			};
131
132			/* V_1V1 -> RAM, ... must not be changed */
133			buck6_reg: BUCK6 {
134				regulator-name = "BUCK6";
135				regulator-min-microvolt = <1100000>;
136				regulator-max-microvolt = <1100000>;
137				regulator-boot-on;
138				regulator-always-on;
139			};
140
141			/* V_1V8_SNVS */
142			ldo1_reg: LDO1 {
143				regulator-name = "LDO1";
144				regulator-min-microvolt = <1800000>;
145				regulator-max-microvolt = <1800000>;
146				regulator-boot-on;
147				regulator-always-on;
148			};
149
150			/* V_1V8_ANA */
151			ldo3_reg: LDO3 {
152				regulator-name = "LDO3";
153				regulator-min-microvolt = <1800000>;
154				regulator-max-microvolt = <1800000>;
155				regulator-boot-on;
156				regulator-always-on;
157			};
158
159			/* unused */
160			ldo4_reg: LDO4 {
161				regulator-name = "LDO4";
162				regulator-min-microvolt = <800000>;
163				regulator-max-microvolt = <3300000>;
164			};
165
166			/* VCC SD IO - switched using SD2 VSELECT */
167			ldo5_reg: LDO5 {
168				regulator-name = "LDO5";
169				regulator-min-microvolt = <1800000>;
170				regulator-max-microvolt = <3300000>;
171			};
172		};
173	};
174
175	pcf85063: rtc@51 {
176		compatible = "nxp,pcf85063a";
177		reg = <0x51>;
178	};
179
180	at24c02: eeprom@53 {
181		compatible = "nxp,se97b", "atmel,24c02";
182		read-only;
183		reg = <0x53>;
184		pagesize = <16>;
185		vcc-supply = <&reg_vcc3v3>;
186	};
187
188	m24c64: eeprom@57 {
189		compatible = "atmel,24c64";
190		reg = <0x57>;
191		pagesize = <32>;
192		vcc-supply = <&reg_vcc3v3>;
193	};
194};
195
196&usdhc2 {
197	vqmmc-supply = <&reg_usdhc2_vqmmc>;
198};
199
200&usdhc3 {
201	pinctrl-names = "default", "state_100mhz", "state_200mhz";
202	pinctrl-0 = <&pinctrl_usdhc3>;
203	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
204	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
205	bus-width = <8>;
206	non-removable;
207	no-sd;
208	no-sdio;
209	vmmc-supply = <&reg_vcc3v3>;
210	vqmmc-supply = <&buck5_reg>;
211	status = "okay";
212};
213
214&wdog1 {
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_wdog>;
217	fsl,ext-reset-output;
218	status = "okay";
219};
220
221&iomuxc {
222	pinctrl_flexspi0: flexspi0grp {
223		fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK	0x142>,
224			   <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
225			   <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
226			   <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
227			   <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
228			   <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>;
229	};
230
231	pinctrl_i2c1: i2c1grp {
232		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e2>,
233			   <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e2>;
234	};
235
236	pinctrl_i2c1_gpio: i2c1-gpiogrp {
237		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001e2>,
238			   <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001e2>;
239	};
240
241	pinctrl_pmic: pmicirqgrp {
242		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x1c0>;
243	};
244
245	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
246		fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10>;
247	};
248
249	pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
250		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04		0xc0>;
251	};
252
253	pinctrl_usdhc3: usdhc3grp {
254		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
255			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
256			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
257			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
258			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
259			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
260			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
261			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
262			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
263			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
264			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
265			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
266	};
267
268	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
269		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
270			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
271			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
272			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
273			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
274			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
275			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
276			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
277			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
278			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
279			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
280			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
281	};
282
283	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
284		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
285			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
286			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
287			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
288			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
289			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
290			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
291			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
292			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
293			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
294			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
295			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
296	};
297
298	pinctrl_wdog: wdoggrp {
299		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x1c4>;
300	};
301};
302