1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 621 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 622 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 623 <&vdosys0 CLK_VDO0_SMI_GALS>, 624 <&vdosys0 CLK_VDO0_SMI_COMMON>, 625 <&vdosys0 CLK_VDO0_SMI_EMI>, 626 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 627 <&vdosys0 CLK_VDO0_SMI_LARB>, 628 <&vdosys0 CLK_VDO0_SMI_RSI>; 629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 630 "vdosys0-2", "vdosys0-3", 631 "vdosys0-4", "vdosys0-5"; 632 mediatek,infracfg = <&infracfg_ao>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #power-domain-cells = <1>; 636 637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 638 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 639 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 640 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 641 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 642 clock-names = "vppsys1", "vppsys1-0", 643 "vppsys1-1"; 644 mediatek,infracfg = <&infracfg_ao>; 645 #power-domain-cells = <0>; 646 }; 647 648 power-domain@MT8195_POWER_DOMAIN_WPESYS { 649 reg = <MT8195_POWER_DOMAIN_WPESYS>; 650 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 651 <&wpesys CLK_WPE_SMI_LARB8>, 652 <&wpesys CLK_WPE_SMI_LARB7_P>, 653 <&wpesys CLK_WPE_SMI_LARB8_P>; 654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 655 "wepsys-3"; 656 mediatek,infracfg = <&infracfg_ao>; 657 #power-domain-cells = <0>; 658 }; 659 660 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 661 reg = <MT8195_POWER_DOMAIN_VDEC0>; 662 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 663 clock-names = "vdec0-0"; 664 mediatek,infracfg = <&infracfg_ao>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 #power-domain-cells = <0>; 668 669 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 670 reg = <MT8195_POWER_DOMAIN_VDEC1>; 671 clocks = <&vdecsys CLK_VDEC_LARB1>; 672 clock-names = "vdec1-0"; 673 mediatek,infracfg = <&infracfg_ao>; 674 #power-domain-cells = <0>; 675 }; 676 677 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 678 reg = <MT8195_POWER_DOMAIN_VDEC2>; 679 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 680 clock-names = "vdec2-0"; 681 mediatek,infracfg = <&infracfg_ao>; 682 #power-domain-cells = <0>; 683 }; 684 }; 685 686 power-domain@MT8195_POWER_DOMAIN_VENC { 687 reg = <MT8195_POWER_DOMAIN_VENC>; 688 clocks = <&vencsys CLK_VENC_LARB>; 689 clock-names = "venc0-larb"; 690 mediatek,infracfg = <&infracfg_ao>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 #power-domain-cells = <0>; 694 695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 696 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 697 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; 698 clock-names = "venc1-larb"; 699 mediatek,infracfg = <&infracfg_ao>; 700 #power-domain-cells = <0>; 701 }; 702 }; 703 704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 705 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 706 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 707 <&vdosys1 CLK_VDO1_SMI_LARB2>, 708 <&vdosys1 CLK_VDO1_SMI_LARB3>, 709 <&vdosys1 CLK_VDO1_GALS>; 710 clock-names = "vdosys1", "vdosys1-0", 711 "vdosys1-1", "vdosys1-2"; 712 mediatek,infracfg = <&infracfg_ao>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 #power-domain-cells = <1>; 716 717 power-domain@MT8195_POWER_DOMAIN_DP_TX { 718 reg = <MT8195_POWER_DOMAIN_DP_TX>; 719 mediatek,infracfg = <&infracfg_ao>; 720 #power-domain-cells = <0>; 721 }; 722 723 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 724 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 725 mediatek,infracfg = <&infracfg_ao>; 726 #power-domain-cells = <0>; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 730 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 731 clocks = <&topckgen CLK_TOP_HDMI_APB>; 732 clock-names = "hdmi_tx"; 733 #power-domain-cells = <0>; 734 }; 735 }; 736 737 power-domain@MT8195_POWER_DOMAIN_IMG { 738 reg = <MT8195_POWER_DOMAIN_IMG>; 739 clocks = <&imgsys CLK_IMG_LARB9>, 740 <&imgsys CLK_IMG_GALS>; 741 clock-names = "img-0", "img-1"; 742 mediatek,infracfg = <&infracfg_ao>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 #power-domain-cells = <1>; 746 747 power-domain@MT8195_POWER_DOMAIN_DIP { 748 reg = <MT8195_POWER_DOMAIN_DIP>; 749 #power-domain-cells = <0>; 750 }; 751 752 power-domain@MT8195_POWER_DOMAIN_IPE { 753 reg = <MT8195_POWER_DOMAIN_IPE>; 754 clocks = <&topckgen CLK_TOP_IPE>, 755 <&imgsys CLK_IMG_IPE>, 756 <&ipesys CLK_IPE_SMI_LARB12>; 757 clock-names = "ipe", "ipe-0", "ipe-1"; 758 mediatek,infracfg = <&infracfg_ao>; 759 #power-domain-cells = <0>; 760 }; 761 }; 762 763 power-domain@MT8195_POWER_DOMAIN_CAM { 764 reg = <MT8195_POWER_DOMAIN_CAM>; 765 clocks = <&camsys CLK_CAM_LARB13>, 766 <&camsys CLK_CAM_LARB14>, 767 <&camsys CLK_CAM_CAM2MM0_GALS>, 768 <&camsys CLK_CAM_CAM2MM1_GALS>, 769 <&camsys CLK_CAM_CAM2SYS_GALS>; 770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 771 "cam-4"; 772 mediatek,infracfg = <&infracfg_ao>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 #power-domain-cells = <1>; 776 777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 778 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 779 #power-domain-cells = <0>; 780 }; 781 782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 783 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 784 #power-domain-cells = <0>; 785 }; 786 787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 788 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 789 #power-domain-cells = <0>; 790 }; 791 }; 792 }; 793 }; 794 795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 796 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 797 mediatek,infracfg = <&infracfg_ao>; 798 #power-domain-cells = <0>; 799 }; 800 801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 802 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 803 mediatek,infracfg = <&infracfg_ao>; 804 #power-domain-cells = <0>; 805 }; 806 807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 808 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 809 #power-domain-cells = <0>; 810 }; 811 812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 813 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 818 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 819 clocks = <&topckgen CLK_TOP_SENINF>, 820 <&topckgen CLK_TOP_SENINF2>; 821 clock-names = "csi_rx_top", "csi_rx_top1"; 822 #power-domain-cells = <0>; 823 }; 824 825 power-domain@MT8195_POWER_DOMAIN_ETHER { 826 reg = <MT8195_POWER_DOMAIN_ETHER>; 827 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 828 clock-names = "ether"; 829 #power-domain-cells = <0>; 830 }; 831 832 power-domain@MT8195_POWER_DOMAIN_ADSP { 833 reg = <MT8195_POWER_DOMAIN_ADSP>; 834 clocks = <&topckgen CLK_TOP_ADSP>, 835 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 836 clock-names = "adsp", "adsp1"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 mediatek,infracfg = <&infracfg_ao>; 840 #power-domain-cells = <1>; 841 842 power-domain@MT8195_POWER_DOMAIN_AUDIO { 843 reg = <MT8195_POWER_DOMAIN_AUDIO>; 844 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 845 <&topckgen CLK_TOP_AUD_INTBUS>, 846 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 847 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 848 clock-names = "audio", "audio1", "audio2", 849 "audio3"; 850 mediatek,infracfg = <&infracfg_ao>; 851 #power-domain-cells = <0>; 852 }; 853 }; 854 }; 855 }; 856 857 watchdog: watchdog@10007000 { 858 compatible = "mediatek,mt8195-wdt"; 859 mediatek,disable-extrst; 860 reg = <0 0x10007000 0 0x100>; 861 #reset-cells = <1>; 862 }; 863 864 apmixedsys: syscon@1000c000 { 865 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 866 reg = <0 0x1000c000 0 0x1000>; 867 #clock-cells = <1>; 868 }; 869 870 systimer: timer@10017000 { 871 compatible = "mediatek,mt8195-timer", 872 "mediatek,mt6765-timer"; 873 reg = <0 0x10017000 0 0x1000>; 874 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&clk13m>; 876 }; 877 878 pwrap: pwrap@10024000 { 879 compatible = "mediatek,mt8195-pwrap", "syscon"; 880 reg = <0 0x10024000 0 0x1000>; 881 reg-names = "pwrap"; 882 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 883 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 884 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 885 clock-names = "spi", "wrap"; 886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 888 }; 889 890 spmi: spmi@10027000 { 891 compatible = "mediatek,mt8195-spmi"; 892 reg = <0 0x10027000 0 0x000e00>, 893 <0 0x10029000 0 0x000100>; 894 reg-names = "pmif", "spmimst"; 895 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 896 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 897 <&topckgen CLK_TOP_SPMI_M_MST>; 898 clock-names = "pmif_sys_ck", 899 "pmif_tmr_ck", 900 "spmimst_clk_mux"; 901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 903 }; 904 905 iommu_infra: infra-iommu@10315000 { 906 compatible = "mediatek,mt8195-iommu-infra"; 907 reg = <0 0x10315000 0 0x5000>; 908 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 909 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 910 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 911 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 912 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 913 #iommu-cells = <1>; 914 }; 915 916 gce0: mailbox@10320000 { 917 compatible = "mediatek,mt8195-gce"; 918 reg = <0 0x10320000 0 0x4000>; 919 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 920 #mbox-cells = <2>; 921 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 922 }; 923 924 gce1: mailbox@10330000 { 925 compatible = "mediatek,mt8195-gce"; 926 reg = <0 0x10330000 0 0x4000>; 927 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 928 #mbox-cells = <2>; 929 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 930 }; 931 932 scp: scp@10500000 { 933 compatible = "mediatek,mt8195-scp"; 934 reg = <0 0x10500000 0 0x100000>, 935 <0 0x10720000 0 0xe0000>, 936 <0 0x10700000 0 0x8000>; 937 reg-names = "sram", "cfg", "l1tcm"; 938 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 939 status = "disabled"; 940 }; 941 942 scp_adsp: clock-controller@10720000 { 943 compatible = "mediatek,mt8195-scp_adsp"; 944 reg = <0 0x10720000 0 0x1000>; 945 #clock-cells = <1>; 946 }; 947 948 adsp: dsp@10803000 { 949 compatible = "mediatek,mt8195-dsp"; 950 reg = <0 0x10803000 0 0x1000>, 951 <0 0x10840000 0 0x40000>; 952 reg-names = "cfg", "sram"; 953 clocks = <&topckgen CLK_TOP_ADSP>, 954 <&clk26m>, 955 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 956 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 957 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 958 <&topckgen CLK_TOP_AUDIO_H>; 959 clock-names = "adsp_sel", 960 "clk26m_ck", 961 "audio_local_bus", 962 "mainpll_d7_d2", 963 "scp_adsp_audiodsp", 964 "audio_h"; 965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 966 mbox-names = "rx", "tx"; 967 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 968 status = "disabled"; 969 }; 970 971 adsp_mailbox0: mailbox@10816000 { 972 compatible = "mediatek,mt8195-adsp-mbox"; 973 #mbox-cells = <0>; 974 reg = <0 0x10816000 0 0x1000>; 975 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 976 }; 977 978 adsp_mailbox1: mailbox@10817000 { 979 compatible = "mediatek,mt8195-adsp-mbox"; 980 #mbox-cells = <0>; 981 reg = <0 0x10817000 0 0x1000>; 982 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 983 }; 984 985 afe: mt8195-afe-pcm@10890000 { 986 compatible = "mediatek,mt8195-audio"; 987 reg = <0 0x10890000 0 0x10000>; 988 mediatek,topckgen = <&topckgen>; 989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 990 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 991 resets = <&watchdog 14>; 992 reset-names = "audiosys"; 993 clocks = <&clk26m>, 994 <&apmixedsys CLK_APMIXED_APLL1>, 995 <&apmixedsys CLK_APMIXED_APLL2>, 996 <&topckgen CLK_TOP_APLL12_DIV0>, 997 <&topckgen CLK_TOP_APLL12_DIV1>, 998 <&topckgen CLK_TOP_APLL12_DIV2>, 999 <&topckgen CLK_TOP_APLL12_DIV3>, 1000 <&topckgen CLK_TOP_APLL12_DIV9>, 1001 <&topckgen CLK_TOP_A1SYS_HP>, 1002 <&topckgen CLK_TOP_AUD_INTBUS>, 1003 <&topckgen CLK_TOP_AUDIO_H>, 1004 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1005 <&topckgen CLK_TOP_DPTX_MCK>, 1006 <&topckgen CLK_TOP_I2SO1_MCK>, 1007 <&topckgen CLK_TOP_I2SO2_MCK>, 1008 <&topckgen CLK_TOP_I2SI1_MCK>, 1009 <&topckgen CLK_TOP_I2SI2_MCK>, 1010 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1011 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1012 clock-names = "clk26m", 1013 "apll1_ck", 1014 "apll2_ck", 1015 "apll12_div0", 1016 "apll12_div1", 1017 "apll12_div2", 1018 "apll12_div3", 1019 "apll12_div9", 1020 "a1sys_hp_sel", 1021 "aud_intbus_sel", 1022 "audio_h_sel", 1023 "audio_local_bus_sel", 1024 "dptx_m_sel", 1025 "i2so1_m_sel", 1026 "i2so2_m_sel", 1027 "i2si1_m_sel", 1028 "i2si2_m_sel", 1029 "infra_ao_audio_26m_b", 1030 "scp_adsp_audiodsp"; 1031 status = "disabled"; 1032 }; 1033 1034 uart0: serial@11001100 { 1035 compatible = "mediatek,mt8195-uart", 1036 "mediatek,mt6577-uart"; 1037 reg = <0 0x11001100 0 0x100>; 1038 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1039 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1040 clock-names = "baud", "bus"; 1041 status = "disabled"; 1042 }; 1043 1044 uart1: serial@11001200 { 1045 compatible = "mediatek,mt8195-uart", 1046 "mediatek,mt6577-uart"; 1047 reg = <0 0x11001200 0 0x100>; 1048 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1049 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1050 clock-names = "baud", "bus"; 1051 status = "disabled"; 1052 }; 1053 1054 uart2: serial@11001300 { 1055 compatible = "mediatek,mt8195-uart", 1056 "mediatek,mt6577-uart"; 1057 reg = <0 0x11001300 0 0x100>; 1058 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1059 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1060 clock-names = "baud", "bus"; 1061 status = "disabled"; 1062 }; 1063 1064 uart3: serial@11001400 { 1065 compatible = "mediatek,mt8195-uart", 1066 "mediatek,mt6577-uart"; 1067 reg = <0 0x11001400 0 0x100>; 1068 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1069 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1070 clock-names = "baud", "bus"; 1071 status = "disabled"; 1072 }; 1073 1074 uart4: serial@11001500 { 1075 compatible = "mediatek,mt8195-uart", 1076 "mediatek,mt6577-uart"; 1077 reg = <0 0x11001500 0 0x100>; 1078 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1079 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1080 clock-names = "baud", "bus"; 1081 status = "disabled"; 1082 }; 1083 1084 uart5: serial@11001600 { 1085 compatible = "mediatek,mt8195-uart", 1086 "mediatek,mt6577-uart"; 1087 reg = <0 0x11001600 0 0x100>; 1088 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1089 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1090 clock-names = "baud", "bus"; 1091 status = "disabled"; 1092 }; 1093 1094 auxadc: auxadc@11002000 { 1095 compatible = "mediatek,mt8195-auxadc", 1096 "mediatek,mt8173-auxadc"; 1097 reg = <0 0x11002000 0 0x1000>; 1098 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1099 clock-names = "main"; 1100 #io-channel-cells = <1>; 1101 status = "disabled"; 1102 }; 1103 1104 pericfg_ao: syscon@11003000 { 1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1106 reg = <0 0x11003000 0 0x1000>; 1107 #clock-cells = <1>; 1108 }; 1109 1110 spi0: spi@1100a000 { 1111 compatible = "mediatek,mt8195-spi", 1112 "mediatek,mt6765-spi"; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 reg = <0 0x1100a000 0 0x1000>; 1116 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1117 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1118 <&topckgen CLK_TOP_SPI>, 1119 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1120 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1121 status = "disabled"; 1122 }; 1123 1124 lvts_ap: thermal-sensor@1100b000 { 1125 compatible = "mediatek,mt8195-lvts-ap"; 1126 reg = <0 0x1100b000 0 0xc00>; 1127 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1128 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1129 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1132 #thermal-sensor-cells = <1>; 1133 }; 1134 1135 svs: svs@1100bc00 { 1136 compatible = "mediatek,mt8195-svs"; 1137 reg = <0 0x1100bc00 0 0x400>; 1138 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>; 1139 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1140 clock-names = "main"; 1141 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; 1142 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1143 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; 1144 reset-names = "svs_rst"; 1145 }; 1146 1147 disp_pwm0: pwm@1100e000 { 1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1149 reg = <0 0x1100e000 0 0x1000>; 1150 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1152 #pwm-cells = <2>; 1153 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1154 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1155 clock-names = "main", "mm"; 1156 status = "disabled"; 1157 }; 1158 1159 disp_pwm1: pwm@1100f000 { 1160 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1161 reg = <0 0x1100f000 0 0x1000>; 1162 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1163 #pwm-cells = <2>; 1164 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1165 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1166 clock-names = "main", "mm"; 1167 status = "disabled"; 1168 }; 1169 1170 spi1: spi@11010000 { 1171 compatible = "mediatek,mt8195-spi", 1172 "mediatek,mt6765-spi"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 reg = <0 0x11010000 0 0x1000>; 1176 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1177 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1178 <&topckgen CLK_TOP_SPI>, 1179 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1180 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1181 status = "disabled"; 1182 }; 1183 1184 spi2: spi@11012000 { 1185 compatible = "mediatek,mt8195-spi", 1186 "mediatek,mt6765-spi"; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 reg = <0 0x11012000 0 0x1000>; 1190 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1191 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1192 <&topckgen CLK_TOP_SPI>, 1193 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1194 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1195 status = "disabled"; 1196 }; 1197 1198 spi3: spi@11013000 { 1199 compatible = "mediatek,mt8195-spi", 1200 "mediatek,mt6765-spi"; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 reg = <0 0x11013000 0 0x1000>; 1204 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1206 <&topckgen CLK_TOP_SPI>, 1207 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1208 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1209 status = "disabled"; 1210 }; 1211 1212 spi4: spi@11018000 { 1213 compatible = "mediatek,mt8195-spi", 1214 "mediatek,mt6765-spi"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 reg = <0 0x11018000 0 0x1000>; 1218 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1220 <&topckgen CLK_TOP_SPI>, 1221 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1222 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1223 status = "disabled"; 1224 }; 1225 1226 spi5: spi@11019000 { 1227 compatible = "mediatek,mt8195-spi", 1228 "mediatek,mt6765-spi"; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 reg = <0 0x11019000 0 0x1000>; 1232 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1233 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1234 <&topckgen CLK_TOP_SPI>, 1235 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1236 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1237 status = "disabled"; 1238 }; 1239 1240 spis0: spi@1101d000 { 1241 compatible = "mediatek,mt8195-spi-slave"; 1242 reg = <0 0x1101d000 0 0x1000>; 1243 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1244 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1245 clock-names = "spi"; 1246 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1247 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1248 status = "disabled"; 1249 }; 1250 1251 spis1: spi@1101e000 { 1252 compatible = "mediatek,mt8195-spi-slave"; 1253 reg = <0 0x1101e000 0 0x1000>; 1254 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1255 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1256 clock-names = "spi"; 1257 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1258 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1259 status = "disabled"; 1260 }; 1261 1262 eth: ethernet@11021000 { 1263 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1264 reg = <0 0x11021000 0 0x4000>; 1265 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1266 interrupt-names = "macirq"; 1267 clock-names = "axi", 1268 "apb", 1269 "mac_main", 1270 "ptp_ref", 1271 "rmii_internal", 1272 "mac_cg"; 1273 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1274 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1275 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1278 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1279 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1280 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1281 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1282 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1283 <&topckgen CLK_TOP_ETHPLL_D8>, 1284 <&topckgen CLK_TOP_ETHPLL_D10>; 1285 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1286 mediatek,pericfg = <&infracfg_ao>; 1287 snps,axi-config = <&stmmac_axi_setup>; 1288 snps,mtl-rx-config = <&mtl_rx_setup>; 1289 snps,mtl-tx-config = <&mtl_tx_setup>; 1290 snps,txpbl = <16>; 1291 snps,rxpbl = <16>; 1292 snps,clk-csr = <0>; 1293 status = "disabled"; 1294 1295 mdio { 1296 compatible = "snps,dwmac-mdio"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 }; 1300 1301 stmmac_axi_setup: stmmac-axi-config { 1302 snps,wr_osr_lmt = <0x7>; 1303 snps,rd_osr_lmt = <0x7>; 1304 snps,blen = <0 0 0 0 16 8 4>; 1305 }; 1306 1307 mtl_rx_setup: rx-queues-config { 1308 snps,rx-queues-to-use = <4>; 1309 snps,rx-sched-sp; 1310 queue0 { 1311 snps,dcb-algorithm; 1312 snps,map-to-dma-channel = <0x0>; 1313 }; 1314 queue1 { 1315 snps,dcb-algorithm; 1316 snps,map-to-dma-channel = <0x0>; 1317 }; 1318 queue2 { 1319 snps,dcb-algorithm; 1320 snps,map-to-dma-channel = <0x0>; 1321 }; 1322 queue3 { 1323 snps,dcb-algorithm; 1324 snps,map-to-dma-channel = <0x0>; 1325 }; 1326 }; 1327 1328 mtl_tx_setup: tx-queues-config { 1329 snps,tx-queues-to-use = <4>; 1330 snps,tx-sched-wrr; 1331 queue0 { 1332 snps,weight = <0x10>; 1333 snps,dcb-algorithm; 1334 snps,priority = <0x0>; 1335 }; 1336 queue1 { 1337 snps,weight = <0x11>; 1338 snps,dcb-algorithm; 1339 snps,priority = <0x1>; 1340 }; 1341 queue2 { 1342 snps,weight = <0x12>; 1343 snps,dcb-algorithm; 1344 snps,priority = <0x2>; 1345 }; 1346 queue3 { 1347 snps,weight = <0x13>; 1348 snps,dcb-algorithm; 1349 snps,priority = <0x3>; 1350 }; 1351 }; 1352 }; 1353 1354 ssusb0: usb@11201000 { 1355 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1356 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1357 reg-names = "mac", "ippc"; 1358 ranges = <0 0 0 0x11200000 0 0x3f00>; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1362 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1363 <&topckgen CLK_TOP_SSUSB_REF>, 1364 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1365 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1366 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 1367 wakeup-source; 1368 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1369 status = "disabled"; 1370 1371 xhci0: usb@0 { 1372 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1373 reg = <0 0 0 0x1000>; 1374 reg-names = "mac"; 1375 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1376 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1377 <&topckgen CLK_TOP_SSUSB_XHCI>; 1378 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1379 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1380 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1381 <&topckgen CLK_TOP_SSUSB_REF>, 1382 <&apmixedsys CLK_APMIXED_USB1PLL>, 1383 <&clk26m>, 1384 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1385 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1386 status = "disabled"; 1387 }; 1388 }; 1389 1390 mmc0: mmc@11230000 { 1391 compatible = "mediatek,mt8195-mmc", 1392 "mediatek,mt8183-mmc"; 1393 reg = <0 0x11230000 0 0x10000>, 1394 <0 0x11f50000 0 0x1000>; 1395 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1397 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1398 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1399 clock-names = "source", "hclk", "source_cg"; 1400 status = "disabled"; 1401 }; 1402 1403 mmc1: mmc@11240000 { 1404 compatible = "mediatek,mt8195-mmc", 1405 "mediatek,mt8183-mmc"; 1406 reg = <0 0x11240000 0 0x1000>, 1407 <0 0x11c70000 0 0x1000>; 1408 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1409 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1410 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1411 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1412 clock-names = "source", "hclk", "source_cg"; 1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1415 status = "disabled"; 1416 }; 1417 1418 mmc2: mmc@11250000 { 1419 compatible = "mediatek,mt8195-mmc", 1420 "mediatek,mt8183-mmc"; 1421 reg = <0 0x11250000 0 0x1000>, 1422 <0 0x11e60000 0 0x1000>; 1423 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1424 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1425 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1426 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1427 clock-names = "source", "hclk", "source_cg"; 1428 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1429 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1430 status = "disabled"; 1431 }; 1432 1433 lvts_mcu: thermal-sensor@11278000 { 1434 compatible = "mediatek,mt8195-lvts-mcu"; 1435 reg = <0 0x11278000 0 0x1000>; 1436 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1437 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1438 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1439 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1440 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1441 #thermal-sensor-cells = <1>; 1442 }; 1443 1444 xhci1: usb@11290000 { 1445 compatible = "mediatek,mt8195-xhci", 1446 "mediatek,mtk-xhci"; 1447 reg = <0 0x11290000 0 0x1000>, 1448 <0 0x11293e00 0 0x0100>; 1449 reg-names = "mac", "ippc"; 1450 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1451 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1452 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1453 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1454 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1455 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1456 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1457 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1458 <&apmixedsys CLK_APMIXED_USB1PLL>, 1459 <&clk26m>, 1460 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1461 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1462 "xhci_ck"; 1463 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1464 wakeup-source; 1465 status = "disabled"; 1466 }; 1467 1468 ssusb2: usb@112a1000 { 1469 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1470 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1471 reg-names = "mac", "ippc"; 1472 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1473 #address-cells = <2>; 1474 #size-cells = <2>; 1475 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1476 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1477 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1478 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1479 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1480 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1481 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1482 phys = <&u2port2 PHY_TYPE_USB2>; 1483 wakeup-source; 1484 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1485 status = "disabled"; 1486 1487 xhci2: usb@0 { 1488 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1489 reg = <0 0 0 0x1000>; 1490 reg-names = "mac"; 1491 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1492 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1493 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1494 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1495 clock-names = "sys_ck"; 1496 status = "disabled"; 1497 }; 1498 }; 1499 1500 ssusb3: usb@112b1000 { 1501 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1502 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1503 reg-names = "mac", "ippc"; 1504 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1505 #address-cells = <2>; 1506 #size-cells = <2>; 1507 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1508 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1509 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1510 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1511 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1512 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1513 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1514 phys = <&u2port3 PHY_TYPE_USB2>; 1515 wakeup-source; 1516 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1517 status = "disabled"; 1518 1519 xhci3: usb@0 { 1520 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1521 reg = <0 0 0 0x1000>; 1522 reg-names = "mac"; 1523 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1524 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1525 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1526 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1527 clock-names = "sys_ck"; 1528 status = "disabled"; 1529 }; 1530 }; 1531 1532 pcie0: pcie@112f0000 { 1533 compatible = "mediatek,mt8195-pcie", 1534 "mediatek,mt8192-pcie"; 1535 device_type = "pci"; 1536 #address-cells = <3>; 1537 #size-cells = <2>; 1538 reg = <0 0x112f0000 0 0x4000>; 1539 reg-names = "pcie-mac"; 1540 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1541 bus-range = <0x00 0xff>; 1542 ranges = <0x81000000 0 0x20000000 1543 0x0 0x20000000 0 0x200000>, 1544 <0x82000000 0 0x20200000 1545 0x0 0x20200000 0 0x3e00000>; 1546 1547 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1548 iommu-map-mask = <0x0>; 1549 1550 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1551 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1552 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1553 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1554 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1555 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1556 clock-names = "pl_250m", "tl_26m", "tl_96m", 1557 "tl_32k", "peri_26m", "peri_mem"; 1558 assigned-clocks = <&topckgen CLK_TOP_TL>; 1559 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1560 1561 phys = <&pciephy>; 1562 phy-names = "pcie-phy"; 1563 1564 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1565 1566 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1567 reset-names = "mac"; 1568 1569 #interrupt-cells = <1>; 1570 interrupt-map-mask = <0 0 0 7>; 1571 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1572 <0 0 0 2 &pcie_intc0 1>, 1573 <0 0 0 3 &pcie_intc0 2>, 1574 <0 0 0 4 &pcie_intc0 3>; 1575 status = "disabled"; 1576 1577 pcie_intc0: interrupt-controller { 1578 interrupt-controller; 1579 #address-cells = <0>; 1580 #interrupt-cells = <1>; 1581 }; 1582 }; 1583 1584 pcie1: pcie@112f8000 { 1585 compatible = "mediatek,mt8195-pcie", 1586 "mediatek,mt8192-pcie"; 1587 device_type = "pci"; 1588 #address-cells = <3>; 1589 #size-cells = <2>; 1590 reg = <0 0x112f8000 0 0x4000>; 1591 reg-names = "pcie-mac"; 1592 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1593 bus-range = <0x00 0xff>; 1594 ranges = <0x81000000 0 0x24000000 1595 0x0 0x24000000 0 0x200000>, 1596 <0x82000000 0 0x24200000 1597 0x0 0x24200000 0 0x3e00000>; 1598 1599 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1600 iommu-map-mask = <0x0>; 1601 1602 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1603 <&clk26m>, 1604 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1605 <&clk26m>, 1606 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1607 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1608 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1609 clock-names = "pl_250m", "tl_26m", "tl_96m", 1610 "tl_32k", "peri_26m", "peri_mem"; 1611 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1612 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1613 1614 phys = <&u3port1 PHY_TYPE_PCIE>; 1615 phy-names = "pcie-phy"; 1616 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1617 1618 #interrupt-cells = <1>; 1619 interrupt-map-mask = <0 0 0 7>; 1620 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1621 <0 0 0 2 &pcie_intc1 1>, 1622 <0 0 0 3 &pcie_intc1 2>, 1623 <0 0 0 4 &pcie_intc1 3>; 1624 status = "disabled"; 1625 1626 pcie_intc1: interrupt-controller { 1627 interrupt-controller; 1628 #address-cells = <0>; 1629 #interrupt-cells = <1>; 1630 }; 1631 }; 1632 1633 nor_flash: spi@1132c000 { 1634 compatible = "mediatek,mt8195-nor", 1635 "mediatek,mt8173-nor"; 1636 reg = <0 0x1132c000 0 0x1000>; 1637 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1638 clocks = <&topckgen CLK_TOP_SPINOR>, 1639 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1640 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1641 clock-names = "spi", "sf", "axi"; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 efuse: efuse@11c10000 { 1648 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1649 reg = <0 0x11c10000 0 0x1000>; 1650 #address-cells = <1>; 1651 #size-cells = <1>; 1652 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1653 reg = <0x184 0x1>; 1654 bits = <0 5>; 1655 }; 1656 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1657 reg = <0x184 0x2>; 1658 bits = <5 5>; 1659 }; 1660 u3_intr_p0: usb3-intr@185 { 1661 reg = <0x185 0x1>; 1662 bits = <2 6>; 1663 }; 1664 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1665 reg = <0x186 0x1>; 1666 bits = <0 5>; 1667 }; 1668 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1669 reg = <0x186 0x2>; 1670 bits = <5 5>; 1671 }; 1672 comb_intr_p1: usb3-intr@187 { 1673 reg = <0x187 0x1>; 1674 bits = <2 6>; 1675 }; 1676 u2_intr_p0: usb2-intr-p0@188,1 { 1677 reg = <0x188 0x1>; 1678 bits = <0 5>; 1679 }; 1680 u2_intr_p1: usb2-intr-p1@188,2 { 1681 reg = <0x188 0x2>; 1682 bits = <5 5>; 1683 }; 1684 u2_intr_p2: usb2-intr-p2@189,1 { 1685 reg = <0x189 0x1>; 1686 bits = <2 5>; 1687 }; 1688 u2_intr_p3: usb2-intr-p3@189,2 { 1689 reg = <0x189 0x2>; 1690 bits = <7 5>; 1691 }; 1692 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1693 reg = <0x190 0x1>; 1694 bits = <0 4>; 1695 }; 1696 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1697 reg = <0x190 0x1>; 1698 bits = <4 4>; 1699 }; 1700 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1701 reg = <0x191 0x1>; 1702 bits = <0 4>; 1703 }; 1704 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1705 reg = <0x191 0x1>; 1706 bits = <4 4>; 1707 }; 1708 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1709 reg = <0x192 0x1>; 1710 bits = <0 4>; 1711 }; 1712 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1713 reg = <0x192 0x1>; 1714 bits = <4 4>; 1715 }; 1716 pciephy_glb_intr: pciephy-glb-intr@193 { 1717 reg = <0x193 0x1>; 1718 bits = <0 4>; 1719 }; 1720 dp_calibration: dp-data@1ac { 1721 reg = <0x1ac 0x10>; 1722 }; 1723 lvts_efuse_data1: lvts1-calib@1bc { 1724 reg = <0x1bc 0x14>; 1725 }; 1726 lvts_efuse_data2: lvts2-calib@1d0 { 1727 reg = <0x1d0 0x38>; 1728 }; 1729 svs_calib_data: svs-calib@580 { 1730 reg = <0x580 0x64>; 1731 }; 1732 socinfo-data1@7a0 { 1733 reg = <0x7a0 0x4>; 1734 }; 1735 }; 1736 1737 u3phy2: t-phy@11c40000 { 1738 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1739 #address-cells = <1>; 1740 #size-cells = <1>; 1741 ranges = <0 0 0x11c40000 0x700>; 1742 status = "disabled"; 1743 1744 u2port2: usb-phy@0 { 1745 reg = <0x0 0x700>; 1746 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1747 clock-names = "ref"; 1748 #phy-cells = <1>; 1749 }; 1750 }; 1751 1752 u3phy3: t-phy@11c50000 { 1753 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1754 #address-cells = <1>; 1755 #size-cells = <1>; 1756 ranges = <0 0 0x11c50000 0x700>; 1757 status = "disabled"; 1758 1759 u2port3: usb-phy@0 { 1760 reg = <0x0 0x700>; 1761 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1762 clock-names = "ref"; 1763 #phy-cells = <1>; 1764 }; 1765 }; 1766 1767 mipi_tx0: dsi-phy@11c80000 { 1768 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1769 reg = <0 0x11c80000 0 0x1000>; 1770 clocks = <&clk26m>; 1771 clock-output-names = "mipi_tx0_pll"; 1772 #clock-cells = <0>; 1773 #phy-cells = <0>; 1774 status = "disabled"; 1775 }; 1776 1777 mipi_tx1: dsi-phy@11c90000 { 1778 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1779 reg = <0 0x11c90000 0 0x1000>; 1780 clocks = <&clk26m>; 1781 clock-output-names = "mipi_tx1_pll"; 1782 #clock-cells = <0>; 1783 #phy-cells = <0>; 1784 status = "disabled"; 1785 }; 1786 1787 i2c5: i2c@11d00000 { 1788 compatible = "mediatek,mt8195-i2c", 1789 "mediatek,mt8192-i2c"; 1790 reg = <0 0x11d00000 0 0x1000>, 1791 <0 0x10220580 0 0x80>; 1792 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1793 clock-div = <1>; 1794 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1795 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1796 clock-names = "main", "dma"; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 status = "disabled"; 1800 }; 1801 1802 i2c6: i2c@11d01000 { 1803 compatible = "mediatek,mt8195-i2c", 1804 "mediatek,mt8192-i2c"; 1805 reg = <0 0x11d01000 0 0x1000>, 1806 <0 0x10220600 0 0x80>; 1807 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1808 clock-div = <1>; 1809 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1810 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1811 clock-names = "main", "dma"; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 status = "disabled"; 1815 }; 1816 1817 i2c7: i2c@11d02000 { 1818 compatible = "mediatek,mt8195-i2c", 1819 "mediatek,mt8192-i2c"; 1820 reg = <0 0x11d02000 0 0x1000>, 1821 <0 0x10220680 0 0x80>; 1822 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1823 clock-div = <1>; 1824 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1825 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1826 clock-names = "main", "dma"; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 status = "disabled"; 1830 }; 1831 1832 imp_iic_wrap_s: clock-controller@11d03000 { 1833 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1834 reg = <0 0x11d03000 0 0x1000>; 1835 #clock-cells = <1>; 1836 }; 1837 1838 i2c0: i2c@11e00000 { 1839 compatible = "mediatek,mt8195-i2c", 1840 "mediatek,mt8192-i2c"; 1841 reg = <0 0x11e00000 0 0x1000>, 1842 <0 0x10220080 0 0x80>; 1843 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1844 clock-div = <1>; 1845 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1846 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1847 clock-names = "main", "dma"; 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 status = "disabled"; 1851 }; 1852 1853 i2c1: i2c@11e01000 { 1854 compatible = "mediatek,mt8195-i2c", 1855 "mediatek,mt8192-i2c"; 1856 reg = <0 0x11e01000 0 0x1000>, 1857 <0 0x10220200 0 0x80>; 1858 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1859 clock-div = <1>; 1860 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1861 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1862 clock-names = "main", "dma"; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 status = "disabled"; 1866 }; 1867 1868 i2c2: i2c@11e02000 { 1869 compatible = "mediatek,mt8195-i2c", 1870 "mediatek,mt8192-i2c"; 1871 reg = <0 0x11e02000 0 0x1000>, 1872 <0 0x10220380 0 0x80>; 1873 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1874 clock-div = <1>; 1875 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1876 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1877 clock-names = "main", "dma"; 1878 #address-cells = <1>; 1879 #size-cells = <0>; 1880 status = "disabled"; 1881 }; 1882 1883 i2c3: i2c@11e03000 { 1884 compatible = "mediatek,mt8195-i2c", 1885 "mediatek,mt8192-i2c"; 1886 reg = <0 0x11e03000 0 0x1000>, 1887 <0 0x10220480 0 0x80>; 1888 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1889 clock-div = <1>; 1890 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1891 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1892 clock-names = "main", "dma"; 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 status = "disabled"; 1896 }; 1897 1898 i2c4: i2c@11e04000 { 1899 compatible = "mediatek,mt8195-i2c", 1900 "mediatek,mt8192-i2c"; 1901 reg = <0 0x11e04000 0 0x1000>, 1902 <0 0x10220500 0 0x80>; 1903 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1904 clock-div = <1>; 1905 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1906 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1907 clock-names = "main", "dma"; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 status = "disabled"; 1911 }; 1912 1913 imp_iic_wrap_w: clock-controller@11e05000 { 1914 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1915 reg = <0 0x11e05000 0 0x1000>; 1916 #clock-cells = <1>; 1917 }; 1918 1919 u3phy1: t-phy@11e30000 { 1920 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1921 #address-cells = <1>; 1922 #size-cells = <1>; 1923 ranges = <0 0 0x11e30000 0xe00>; 1924 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1925 status = "disabled"; 1926 1927 u2port1: usb-phy@0 { 1928 reg = <0x0 0x700>; 1929 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1930 <&clk26m>; 1931 clock-names = "ref", "da_ref"; 1932 #phy-cells = <1>; 1933 }; 1934 1935 u3port1: usb-phy@700 { 1936 reg = <0x700 0x700>; 1937 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1938 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1939 clock-names = "ref", "da_ref"; 1940 nvmem-cells = <&comb_intr_p1>, 1941 <&comb_rx_imp_p1>, 1942 <&comb_tx_imp_p1>; 1943 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1944 #phy-cells = <1>; 1945 }; 1946 }; 1947 1948 u3phy0: t-phy@11e40000 { 1949 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1950 #address-cells = <1>; 1951 #size-cells = <1>; 1952 ranges = <0 0 0x11e40000 0xe00>; 1953 status = "disabled"; 1954 1955 u2port0: usb-phy@0 { 1956 reg = <0x0 0x700>; 1957 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1958 <&clk26m>; 1959 clock-names = "ref", "da_ref"; 1960 #phy-cells = <1>; 1961 }; 1962 1963 u3port0: usb-phy@700 { 1964 reg = <0x700 0x700>; 1965 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1966 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1967 clock-names = "ref", "da_ref"; 1968 nvmem-cells = <&u3_intr_p0>, 1969 <&u3_rx_imp_p0>, 1970 <&u3_tx_imp_p0>; 1971 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1972 #phy-cells = <1>; 1973 }; 1974 }; 1975 1976 pciephy: phy@11e80000 { 1977 compatible = "mediatek,mt8195-pcie-phy"; 1978 reg = <0 0x11e80000 0 0x10000>; 1979 reg-names = "sif"; 1980 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1981 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1982 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1983 <&pciephy_rx_ln1>; 1984 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1985 "tx_ln0_nmos", "rx_ln0", 1986 "tx_ln1_pmos", "tx_ln1_nmos", 1987 "rx_ln1"; 1988 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1989 #phy-cells = <0>; 1990 status = "disabled"; 1991 }; 1992 1993 ufsphy: ufs-phy@11fa0000 { 1994 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1995 reg = <0 0x11fa0000 0 0xc000>; 1996 clocks = <&clk26m>, <&clk26m>; 1997 clock-names = "unipro", "mp"; 1998 #phy-cells = <0>; 1999 status = "disabled"; 2000 }; 2001 2002 gpu: gpu@13000000 { 2003 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 2004 "arm,mali-valhall-jm"; 2005 reg = <0 0x13000000 0 0x4000>; 2006 2007 clocks = <&mfgcfg CLK_MFG_BG3D>; 2008 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 2009 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 2010 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 2011 interrupt-names = "job", "mmu", "gpu"; 2012 operating-points-v2 = <&gpu_opp_table>; 2013 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 2014 <&spm MT8195_POWER_DOMAIN_MFG3>, 2015 <&spm MT8195_POWER_DOMAIN_MFG4>, 2016 <&spm MT8195_POWER_DOMAIN_MFG5>, 2017 <&spm MT8195_POWER_DOMAIN_MFG6>; 2018 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 2019 status = "disabled"; 2020 }; 2021 2022 mfgcfg: clock-controller@13fbf000 { 2023 compatible = "mediatek,mt8195-mfgcfg"; 2024 reg = <0 0x13fbf000 0 0x1000>; 2025 #clock-cells = <1>; 2026 }; 2027 2028 vppsys0: syscon@14000000 { 2029 compatible = "mediatek,mt8195-vppsys0", "syscon"; 2030 reg = <0 0x14000000 0 0x1000>; 2031 #clock-cells = <1>; 2032 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; 2033 }; 2034 2035 dma-controller@14001000 { 2036 compatible = "mediatek,mt8195-mdp3-rdma"; 2037 reg = <0 0x14001000 0 0x1000>; 2038 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2039 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2040 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2041 mediatek,scp = <&scp>; 2042 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2043 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; 2044 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2045 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, 2046 <&gce1 13 CMDQ_THR_PRIO_1>, 2047 <&gce1 14 CMDQ_THR_PRIO_1>, 2048 <&gce1 21 CMDQ_THR_PRIO_1>, 2049 <&gce1 22 CMDQ_THR_PRIO_1>; 2050 #dma-cells = <1>; 2051 }; 2052 2053 display@14002000 { 2054 compatible = "mediatek,mt8195-mdp3-fg"; 2055 reg = <0 0x14002000 0 0x1000>; 2056 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2057 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2058 }; 2059 2060 display@14003000 { 2061 compatible = "mediatek,mt8195-mdp3-stitch"; 2062 reg = <0 0x14003000 0 0x1000>; 2063 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; 2064 clocks = <&vppsys0 CLK_VPP0_STITCH>; 2065 }; 2066 2067 display@14004000 { 2068 compatible = "mediatek,mt8195-mdp3-hdr"; 2069 reg = <0 0x14004000 0 0x1000>; 2070 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2071 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2072 }; 2073 2074 display@14005000 { 2075 compatible = "mediatek,mt8195-mdp3-aal"; 2076 reg = <0 0x14005000 0 0x1000>; 2077 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2078 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2079 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2080 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2081 }; 2082 2083 display@14006000 { 2084 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2085 reg = <0 0x14006000 0 0x1000>; 2086 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2087 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2088 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2089 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2090 }; 2091 2092 display@14007000 { 2093 compatible = "mediatek,mt8195-mdp3-tdshp"; 2094 reg = <0 0x14007000 0 0x1000>; 2095 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2096 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2097 }; 2098 2099 display@14008000 { 2100 compatible = "mediatek,mt8195-mdp3-color"; 2101 reg = <0 0x14008000 0 0x1000>; 2102 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2103 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2104 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2105 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2106 }; 2107 2108 display@14009000 { 2109 compatible = "mediatek,mt8195-mdp3-ovl"; 2110 reg = <0 0x14009000 0 0x1000>; 2111 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2112 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2113 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2114 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2115 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; 2116 }; 2117 2118 display@1400a000 { 2119 compatible = "mediatek,mt8195-mdp3-padding"; 2120 reg = <0 0x1400a000 0 0x1000>; 2121 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2122 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2123 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2124 }; 2125 2126 display@1400b000 { 2127 compatible = "mediatek,mt8195-mdp3-tcc"; 2128 reg = <0 0x1400b000 0 0x1000>; 2129 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2130 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2131 }; 2132 2133 dma-controller@1400c000 { 2134 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2135 reg = <0 0x1400c000 0 0x1000>; 2136 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2137 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2138 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2139 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2140 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; 2141 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2142 #dma-cells = <1>; 2143 }; 2144 2145 mutex@1400f000 { 2146 compatible = "mediatek,mt8195-vpp-mutex"; 2147 reg = <0 0x1400f000 0 0x1000>; 2148 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2149 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2150 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2151 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2152 }; 2153 2154 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 2155 compatible = "mediatek,mt8195-smi-sub-common"; 2156 reg = <0 0x14010000 0 0x1000>; 2157 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2158 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2159 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2160 clock-names = "apb", "smi", "gals0"; 2161 mediatek,smi = <&smi_common_vpp>; 2162 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2163 }; 2164 2165 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 2166 compatible = "mediatek,mt8195-smi-sub-common"; 2167 reg = <0 0x14011000 0 0x1000>; 2168 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2169 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2170 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 2171 clock-names = "apb", "smi", "gals0"; 2172 mediatek,smi = <&smi_common_vpp>; 2173 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2174 }; 2175 2176 smi_common_vpp: smi@14012000 { 2177 compatible = "mediatek,mt8195-smi-common-vpp"; 2178 reg = <0 0x14012000 0 0x1000>; 2179 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2180 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2181 <&vppsys0 CLK_VPP0_SMI_RSI>, 2182 <&vppsys0 CLK_VPP0_SMI_RSI>; 2183 clock-names = "apb", "smi", "gals0", "gals1"; 2184 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2185 }; 2186 2187 larb4: larb@14013000 { 2188 compatible = "mediatek,mt8195-smi-larb"; 2189 reg = <0 0x14013000 0 0x1000>; 2190 mediatek,larb-id = <4>; 2191 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2192 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2193 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2194 clock-names = "apb", "smi"; 2195 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2196 }; 2197 2198 iommu_vpp: iommu@14018000 { 2199 compatible = "mediatek,mt8195-iommu-vpp"; 2200 reg = <0 0x14018000 0 0x1000>; 2201 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2202 &larb12 &larb14 &larb16 &larb18 2203 &larb20 &larb22 &larb23 &larb26 2204 &larb27>; 2205 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2206 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2207 clock-names = "bclk"; 2208 #iommu-cells = <1>; 2209 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2210 }; 2211 2212 wpesys: clock-controller@14e00000 { 2213 compatible = "mediatek,mt8195-wpesys"; 2214 reg = <0 0x14e00000 0 0x1000>; 2215 #clock-cells = <1>; 2216 }; 2217 2218 wpesys_vpp0: clock-controller@14e02000 { 2219 compatible = "mediatek,mt8195-wpesys_vpp0"; 2220 reg = <0 0x14e02000 0 0x1000>; 2221 #clock-cells = <1>; 2222 }; 2223 2224 wpesys_vpp1: clock-controller@14e03000 { 2225 compatible = "mediatek,mt8195-wpesys_vpp1"; 2226 reg = <0 0x14e03000 0 0x1000>; 2227 #clock-cells = <1>; 2228 }; 2229 2230 larb7: larb@14e04000 { 2231 compatible = "mediatek,mt8195-smi-larb"; 2232 reg = <0 0x14e04000 0 0x1000>; 2233 mediatek,larb-id = <7>; 2234 mediatek,smi = <&smi_common_vdo>; 2235 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2236 <&wpesys CLK_WPE_SMI_LARB7>; 2237 clock-names = "apb", "smi"; 2238 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2239 }; 2240 2241 larb8: larb@14e05000 { 2242 compatible = "mediatek,mt8195-smi-larb"; 2243 reg = <0 0x14e05000 0 0x1000>; 2244 mediatek,larb-id = <8>; 2245 mediatek,smi = <&smi_common_vpp>; 2246 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2247 <&wpesys CLK_WPE_SMI_LARB8>, 2248 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2249 clock-names = "apb", "smi", "gals"; 2250 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2251 }; 2252 2253 vppsys1: syscon@14f00000 { 2254 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2255 reg = <0 0x14f00000 0 0x1000>; 2256 #clock-cells = <1>; 2257 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; 2258 }; 2259 2260 mutex@14f01000 { 2261 compatible = "mediatek,mt8195-vpp-mutex"; 2262 reg = <0 0x14f01000 0 0x1000>; 2263 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2264 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2265 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2266 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2267 }; 2268 2269 larb5: larb@14f02000 { 2270 compatible = "mediatek,mt8195-smi-larb"; 2271 reg = <0 0x14f02000 0 0x1000>; 2272 mediatek,larb-id = <5>; 2273 mediatek,smi = <&smi_common_vdo>; 2274 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2275 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2276 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2277 clock-names = "apb", "smi", "gals"; 2278 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2279 }; 2280 2281 larb6: larb@14f03000 { 2282 compatible = "mediatek,mt8195-smi-larb"; 2283 reg = <0 0x14f03000 0 0x1000>; 2284 mediatek,larb-id = <6>; 2285 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2286 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2287 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2288 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2289 clock-names = "apb", "smi", "gals"; 2290 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2291 }; 2292 2293 display@14f06000 { 2294 compatible = "mediatek,mt8195-mdp3-split"; 2295 reg = <0 0x14f06000 0 0x1000>; 2296 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; 2297 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, 2298 <&vppsys1 CLK_VPP1_HDMI_META>, 2299 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 2300 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2301 }; 2302 2303 display@14f07000 { 2304 compatible = "mediatek,mt8195-mdp3-tcc"; 2305 reg = <0 0x14f07000 0 0x1000>; 2306 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; 2307 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; 2308 }; 2309 2310 dma-controller@14f08000 { 2311 compatible = "mediatek,mt8195-mdp3-rdma"; 2312 reg = <0 0x14f08000 0 0x1000>; 2313 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; 2314 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, 2315 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; 2316 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; 2317 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; 2318 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2319 #dma-cells = <1>; 2320 }; 2321 2322 dma-controller@14f09000 { 2323 compatible = "mediatek,mt8195-mdp3-rdma"; 2324 reg = <0 0x14f09000 0 0x1000>; 2325 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2326 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2327 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2328 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2329 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; 2330 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2331 #dma-cells = <1>; 2332 }; 2333 2334 dma-controller@14f0a000 { 2335 compatible = "mediatek,mt8195-mdp3-rdma"; 2336 reg = <0 0x14f0a000 0 0x1000>; 2337 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2338 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2339 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2340 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2341 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; 2342 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2343 #dma-cells = <1>; 2344 }; 2345 2346 display@14f0b000 { 2347 compatible = "mediatek,mt8195-mdp3-fg"; 2348 reg = <0 0x14f0b000 0 0x1000>; 2349 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; 2350 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; 2351 }; 2352 2353 display@14f0c000 { 2354 compatible = "mediatek,mt8195-mdp3-fg"; 2355 reg = <0 0x14f0c000 0 0x1000>; 2356 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2357 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2358 }; 2359 2360 display@14f0d000 { 2361 compatible = "mediatek,mt8195-mdp3-fg"; 2362 reg = <0 0x14f0d000 0 0x1000>; 2363 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2364 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2365 }; 2366 2367 display@14f0e000 { 2368 compatible = "mediatek,mt8195-mdp3-hdr"; 2369 reg = <0 0x14f0e000 0 0x1000>; 2370 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; 2371 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; 2372 }; 2373 2374 display@14f0f000 { 2375 compatible = "mediatek,mt8195-mdp3-hdr"; 2376 reg = <0 0x14f0f000 0 0x1000>; 2377 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2378 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2379 }; 2380 2381 display@14f10000 { 2382 compatible = "mediatek,mt8195-mdp3-hdr"; 2383 reg = <0 0x14f10000 0 0x1000>; 2384 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2385 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2386 }; 2387 2388 display@14f11000 { 2389 compatible = "mediatek,mt8195-mdp3-aal"; 2390 reg = <0 0x14f11000 0 0x1000>; 2391 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; 2392 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; 2393 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; 2394 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2395 }; 2396 2397 display@14f12000 { 2398 compatible = "mediatek,mt8195-mdp3-aal"; 2399 reg = <0 0x14f12000 0 0x1000>; 2400 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2401 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2402 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2403 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2404 }; 2405 2406 display@14f13000 { 2407 compatible = "mediatek,mt8195-mdp3-aal"; 2408 reg = <0 0x14f13000 0 0x1000>; 2409 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2410 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2411 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2412 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2413 }; 2414 2415 display@14f14000 { 2416 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2417 reg = <0 0x14f14000 0 0x1000>; 2418 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; 2419 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, 2420 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; 2421 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; 2422 }; 2423 2424 display@14f15000 { 2425 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2426 reg = <0 0x14f15000 0 0x1000>; 2427 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2428 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2429 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2430 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2431 }; 2432 2433 display@14f16000 { 2434 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2435 reg = <0 0x14f16000 0 0x1000>; 2436 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2437 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2438 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2439 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2440 }; 2441 2442 display@14f17000 { 2443 compatible = "mediatek,mt8195-mdp3-tdshp"; 2444 reg = <0 0x14f17000 0 0x1000>; 2445 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; 2446 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; 2447 }; 2448 2449 display@14f18000 { 2450 compatible = "mediatek,mt8195-mdp3-tdshp"; 2451 reg = <0 0x14f18000 0 0x1000>; 2452 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2453 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2454 }; 2455 2456 display@14f19000 { 2457 compatible = "mediatek,mt8195-mdp3-tdshp"; 2458 reg = <0 0x14f19000 0 0x1000>; 2459 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2460 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2461 }; 2462 2463 display@14f1a000 { 2464 compatible = "mediatek,mt8195-mdp3-merge"; 2465 reg = <0 0x14f1a000 0 0x1000>; 2466 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2467 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2468 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2469 }; 2470 2471 display@14f1b000 { 2472 compatible = "mediatek,mt8195-mdp3-merge"; 2473 reg = <0 0x14f1b000 0 0x1000>; 2474 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2475 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2476 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2477 }; 2478 2479 display@14f1c000 { 2480 compatible = "mediatek,mt8195-mdp3-color"; 2481 reg = <0 0x14f1c000 0 0x1000>; 2482 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; 2483 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; 2484 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; 2485 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2486 }; 2487 2488 display@14f1d000 { 2489 compatible = "mediatek,mt8195-mdp3-color"; 2490 reg = <0 0x14f1d000 0 0x1000>; 2491 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2492 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2493 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2494 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2495 }; 2496 2497 display@14f1e000 { 2498 compatible = "mediatek,mt8195-mdp3-color"; 2499 reg = <0 0x14f1e000 0 0x1000>; 2500 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2501 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2502 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2503 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2504 }; 2505 2506 display@14f1f000 { 2507 compatible = "mediatek,mt8195-mdp3-ovl"; 2508 reg = <0 0x14f1f000 0 0x1000>; 2509 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; 2510 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; 2511 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; 2512 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2513 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; 2514 }; 2515 2516 display@14f20000 { 2517 compatible = "mediatek,mt8195-mdp3-padding"; 2518 reg = <0 0x14f20000 0 0x1000>; 2519 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; 2520 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; 2521 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2522 }; 2523 2524 display@14f21000 { 2525 compatible = "mediatek,mt8195-mdp3-padding"; 2526 reg = <0 0x14f21000 0 0x1000>; 2527 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2528 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2529 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2530 }; 2531 2532 display@14f22000 { 2533 compatible = "mediatek,mt8195-mdp3-padding"; 2534 reg = <0 0x14f22000 0 0x1000>; 2535 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2536 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2537 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2538 }; 2539 2540 dma-controller@14f23000 { 2541 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2542 reg = <0 0x14f23000 0 0x1000>; 2543 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; 2544 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, 2545 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; 2546 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; 2547 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; 2548 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2549 #dma-cells = <1>; 2550 }; 2551 2552 dma-controller@14f24000 { 2553 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2554 reg = <0 0x14f24000 0 0x1000>; 2555 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2556 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2557 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2558 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2559 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; 2560 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2561 #dma-cells = <1>; 2562 }; 2563 2564 dma-controller@14f25000 { 2565 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2566 reg = <0 0x14f25000 0 0x1000>; 2567 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2568 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2569 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2570 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2571 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; 2572 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2573 #dma-cells = <1>; 2574 }; 2575 2576 imgsys: clock-controller@15000000 { 2577 compatible = "mediatek,mt8195-imgsys"; 2578 reg = <0 0x15000000 0 0x1000>; 2579 #clock-cells = <1>; 2580 }; 2581 2582 larb9: larb@15001000 { 2583 compatible = "mediatek,mt8195-smi-larb"; 2584 reg = <0 0x15001000 0 0x1000>; 2585 mediatek,larb-id = <9>; 2586 mediatek,smi = <&smi_sub_common_img1_3x1>; 2587 clocks = <&imgsys CLK_IMG_LARB9>, 2588 <&imgsys CLK_IMG_LARB9>, 2589 <&imgsys CLK_IMG_GALS>; 2590 clock-names = "apb", "smi", "gals"; 2591 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2592 }; 2593 2594 smi_sub_common_img0_3x1: smi@15002000 { 2595 compatible = "mediatek,mt8195-smi-sub-common"; 2596 reg = <0 0x15002000 0 0x1000>; 2597 clocks = <&imgsys CLK_IMG_IPE>, 2598 <&imgsys CLK_IMG_IPE>, 2599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2600 clock-names = "apb", "smi", "gals0"; 2601 mediatek,smi = <&smi_common_vpp>; 2602 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2603 }; 2604 2605 smi_sub_common_img1_3x1: smi@15003000 { 2606 compatible = "mediatek,mt8195-smi-sub-common"; 2607 reg = <0 0x15003000 0 0x1000>; 2608 clocks = <&imgsys CLK_IMG_LARB9>, 2609 <&imgsys CLK_IMG_LARB9>, 2610 <&imgsys CLK_IMG_GALS>; 2611 clock-names = "apb", "smi", "gals0"; 2612 mediatek,smi = <&smi_common_vdo>; 2613 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2614 }; 2615 2616 imgsys1_dip_top: clock-controller@15110000 { 2617 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2618 reg = <0 0x15110000 0 0x1000>; 2619 #clock-cells = <1>; 2620 }; 2621 2622 larb10: larb@15120000 { 2623 compatible = "mediatek,mt8195-smi-larb"; 2624 reg = <0 0x15120000 0 0x1000>; 2625 mediatek,larb-id = <10>; 2626 mediatek,smi = <&smi_sub_common_img1_3x1>; 2627 clocks = <&imgsys CLK_IMG_DIP0>, 2628 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2629 clock-names = "apb", "smi"; 2630 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2631 }; 2632 2633 imgsys1_dip_nr: clock-controller@15130000 { 2634 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2635 reg = <0 0x15130000 0 0x1000>; 2636 #clock-cells = <1>; 2637 }; 2638 2639 imgsys1_wpe: clock-controller@15220000 { 2640 compatible = "mediatek,mt8195-imgsys1_wpe"; 2641 reg = <0 0x15220000 0 0x1000>; 2642 #clock-cells = <1>; 2643 }; 2644 2645 larb11: larb@15230000 { 2646 compatible = "mediatek,mt8195-smi-larb"; 2647 reg = <0 0x15230000 0 0x1000>; 2648 mediatek,larb-id = <11>; 2649 mediatek,smi = <&smi_sub_common_img1_3x1>; 2650 clocks = <&imgsys CLK_IMG_WPE0>, 2651 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2652 clock-names = "apb", "smi"; 2653 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2654 }; 2655 2656 ipesys: clock-controller@15330000 { 2657 compatible = "mediatek,mt8195-ipesys"; 2658 reg = <0 0x15330000 0 0x1000>; 2659 #clock-cells = <1>; 2660 }; 2661 2662 larb12: larb@15340000 { 2663 compatible = "mediatek,mt8195-smi-larb"; 2664 reg = <0 0x15340000 0 0x1000>; 2665 mediatek,larb-id = <12>; 2666 mediatek,smi = <&smi_sub_common_img0_3x1>; 2667 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2668 <&ipesys CLK_IPE_SMI_LARB12>; 2669 clock-names = "apb", "smi"; 2670 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2671 }; 2672 2673 camsys: clock-controller@16000000 { 2674 compatible = "mediatek,mt8195-camsys"; 2675 reg = <0 0x16000000 0 0x1000>; 2676 #clock-cells = <1>; 2677 }; 2678 2679 larb13: larb@16001000 { 2680 compatible = "mediatek,mt8195-smi-larb"; 2681 reg = <0 0x16001000 0 0x1000>; 2682 mediatek,larb-id = <13>; 2683 mediatek,smi = <&smi_sub_common_cam_4x1>; 2684 clocks = <&camsys CLK_CAM_LARB13>, 2685 <&camsys CLK_CAM_LARB13>, 2686 <&camsys CLK_CAM_CAM2MM0_GALS>; 2687 clock-names = "apb", "smi", "gals"; 2688 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2689 }; 2690 2691 larb14: larb@16002000 { 2692 compatible = "mediatek,mt8195-smi-larb"; 2693 reg = <0 0x16002000 0 0x1000>; 2694 mediatek,larb-id = <14>; 2695 mediatek,smi = <&smi_sub_common_cam_7x1>; 2696 clocks = <&camsys CLK_CAM_LARB14>, 2697 <&camsys CLK_CAM_LARB14>; 2698 clock-names = "apb", "smi"; 2699 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2700 }; 2701 2702 smi_sub_common_cam_4x1: smi@16004000 { 2703 compatible = "mediatek,mt8195-smi-sub-common"; 2704 reg = <0 0x16004000 0 0x1000>; 2705 clocks = <&camsys CLK_CAM_LARB13>, 2706 <&camsys CLK_CAM_LARB13>, 2707 <&camsys CLK_CAM_CAM2MM0_GALS>; 2708 clock-names = "apb", "smi", "gals0"; 2709 mediatek,smi = <&smi_common_vdo>; 2710 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2711 }; 2712 2713 smi_sub_common_cam_7x1: smi@16005000 { 2714 compatible = "mediatek,mt8195-smi-sub-common"; 2715 reg = <0 0x16005000 0 0x1000>; 2716 clocks = <&camsys CLK_CAM_LARB14>, 2717 <&camsys CLK_CAM_CAM2MM1_GALS>, 2718 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2719 clock-names = "apb", "smi", "gals0"; 2720 mediatek,smi = <&smi_common_vpp>; 2721 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2722 }; 2723 2724 larb16: larb@16012000 { 2725 compatible = "mediatek,mt8195-smi-larb"; 2726 reg = <0 0x16012000 0 0x1000>; 2727 mediatek,larb-id = <16>; 2728 mediatek,smi = <&smi_sub_common_cam_7x1>; 2729 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2730 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2731 clock-names = "apb", "smi"; 2732 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2733 }; 2734 2735 larb17: larb@16013000 { 2736 compatible = "mediatek,mt8195-smi-larb"; 2737 reg = <0 0x16013000 0 0x1000>; 2738 mediatek,larb-id = <17>; 2739 mediatek,smi = <&smi_sub_common_cam_4x1>; 2740 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2741 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2742 clock-names = "apb", "smi"; 2743 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2744 }; 2745 2746 larb27: larb@16014000 { 2747 compatible = "mediatek,mt8195-smi-larb"; 2748 reg = <0 0x16014000 0 0x1000>; 2749 mediatek,larb-id = <27>; 2750 mediatek,smi = <&smi_sub_common_cam_7x1>; 2751 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2752 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2753 clock-names = "apb", "smi"; 2754 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2755 }; 2756 2757 larb28: larb@16015000 { 2758 compatible = "mediatek,mt8195-smi-larb"; 2759 reg = <0 0x16015000 0 0x1000>; 2760 mediatek,larb-id = <28>; 2761 mediatek,smi = <&smi_sub_common_cam_4x1>; 2762 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2763 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2764 clock-names = "apb", "smi"; 2765 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2766 }; 2767 2768 camsys_rawa: clock-controller@1604f000 { 2769 compatible = "mediatek,mt8195-camsys_rawa"; 2770 reg = <0 0x1604f000 0 0x1000>; 2771 #clock-cells = <1>; 2772 }; 2773 2774 camsys_yuva: clock-controller@1606f000 { 2775 compatible = "mediatek,mt8195-camsys_yuva"; 2776 reg = <0 0x1606f000 0 0x1000>; 2777 #clock-cells = <1>; 2778 }; 2779 2780 camsys_rawb: clock-controller@1608f000 { 2781 compatible = "mediatek,mt8195-camsys_rawb"; 2782 reg = <0 0x1608f000 0 0x1000>; 2783 #clock-cells = <1>; 2784 }; 2785 2786 camsys_yuvb: clock-controller@160af000 { 2787 compatible = "mediatek,mt8195-camsys_yuvb"; 2788 reg = <0 0x160af000 0 0x1000>; 2789 #clock-cells = <1>; 2790 }; 2791 2792 camsys_mraw: clock-controller@16140000 { 2793 compatible = "mediatek,mt8195-camsys_mraw"; 2794 reg = <0 0x16140000 0 0x1000>; 2795 #clock-cells = <1>; 2796 }; 2797 2798 larb25: larb@16141000 { 2799 compatible = "mediatek,mt8195-smi-larb"; 2800 reg = <0 0x16141000 0 0x1000>; 2801 mediatek,larb-id = <25>; 2802 mediatek,smi = <&smi_sub_common_cam_4x1>; 2803 clocks = <&camsys CLK_CAM_LARB13>, 2804 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2805 <&camsys CLK_CAM_CAM2MM0_GALS>; 2806 clock-names = "apb", "smi", "gals"; 2807 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2808 }; 2809 2810 larb26: larb@16142000 { 2811 compatible = "mediatek,mt8195-smi-larb"; 2812 reg = <0 0x16142000 0 0x1000>; 2813 mediatek,larb-id = <26>; 2814 mediatek,smi = <&smi_sub_common_cam_7x1>; 2815 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2816 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2817 clock-names = "apb", "smi"; 2818 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2819 2820 }; 2821 2822 ccusys: clock-controller@17200000 { 2823 compatible = "mediatek,mt8195-ccusys"; 2824 reg = <0 0x17200000 0 0x1000>; 2825 #clock-cells = <1>; 2826 }; 2827 2828 larb18: larb@17201000 { 2829 compatible = "mediatek,mt8195-smi-larb"; 2830 reg = <0 0x17201000 0 0x1000>; 2831 mediatek,larb-id = <18>; 2832 mediatek,smi = <&smi_sub_common_cam_7x1>; 2833 clocks = <&ccusys CLK_CCU_LARB18>, 2834 <&ccusys CLK_CCU_LARB18>; 2835 clock-names = "apb", "smi"; 2836 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2837 }; 2838 2839 video-codec@18000000 { 2840 compatible = "mediatek,mt8195-vcodec-dec"; 2841 mediatek,scp = <&scp>; 2842 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2843 #address-cells = <2>; 2844 #size-cells = <2>; 2845 reg = <0 0x18000000 0 0x1000>, 2846 <0 0x18004000 0 0x1000>; 2847 ranges = <0 0 0 0x18000000 0 0x26000>; 2848 2849 video-codec@2000 { 2850 compatible = "mediatek,mtk-vcodec-lat-soc"; 2851 reg = <0 0x2000 0 0x800>; 2852 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2853 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2854 clocks = <&topckgen CLK_TOP_VDEC>, 2855 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2856 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2857 <&topckgen CLK_TOP_UNIVPLL_D4>; 2858 clock-names = "sel", "vdec", "lat", "top"; 2859 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2860 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2861 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2862 }; 2863 2864 video-codec@10000 { 2865 compatible = "mediatek,mtk-vcodec-lat"; 2866 reg = <0 0x10000 0 0x800>; 2867 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2868 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2869 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2870 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2871 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2872 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2873 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2874 clocks = <&topckgen CLK_TOP_VDEC>, 2875 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2876 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2877 <&topckgen CLK_TOP_UNIVPLL_D4>; 2878 clock-names = "sel", "vdec", "lat", "top"; 2879 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2880 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2881 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2882 }; 2883 2884 video-codec@25000 { 2885 compatible = "mediatek,mtk-vcodec-core"; 2886 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2887 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2888 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2889 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2890 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2891 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2892 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2893 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2894 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2895 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2896 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2897 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2898 clocks = <&topckgen CLK_TOP_VDEC>, 2899 <&vdecsys CLK_VDEC_VDEC>, 2900 <&vdecsys CLK_VDEC_LAT>, 2901 <&topckgen CLK_TOP_UNIVPLL_D4>; 2902 clock-names = "sel", "vdec", "lat", "top"; 2903 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2904 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2905 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2906 }; 2907 }; 2908 2909 larb24: larb@1800d000 { 2910 compatible = "mediatek,mt8195-smi-larb"; 2911 reg = <0 0x1800d000 0 0x1000>; 2912 mediatek,larb-id = <24>; 2913 mediatek,smi = <&smi_common_vdo>; 2914 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2915 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2916 clock-names = "apb", "smi"; 2917 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2918 }; 2919 2920 larb23: larb@1800e000 { 2921 compatible = "mediatek,mt8195-smi-larb"; 2922 reg = <0 0x1800e000 0 0x1000>; 2923 mediatek,larb-id = <23>; 2924 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2925 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2926 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2927 clock-names = "apb", "smi"; 2928 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2929 }; 2930 2931 vdecsys_soc: clock-controller@1800f000 { 2932 compatible = "mediatek,mt8195-vdecsys_soc"; 2933 reg = <0 0x1800f000 0 0x1000>; 2934 #clock-cells = <1>; 2935 }; 2936 2937 larb21: larb@1802e000 { 2938 compatible = "mediatek,mt8195-smi-larb"; 2939 reg = <0 0x1802e000 0 0x1000>; 2940 mediatek,larb-id = <21>; 2941 mediatek,smi = <&smi_common_vdo>; 2942 clocks = <&vdecsys CLK_VDEC_LARB1>, 2943 <&vdecsys CLK_VDEC_LARB1>; 2944 clock-names = "apb", "smi"; 2945 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2946 }; 2947 2948 vdecsys: clock-controller@1802f000 { 2949 compatible = "mediatek,mt8195-vdecsys"; 2950 reg = <0 0x1802f000 0 0x1000>; 2951 #clock-cells = <1>; 2952 }; 2953 2954 larb22: larb@1803e000 { 2955 compatible = "mediatek,mt8195-smi-larb"; 2956 reg = <0 0x1803e000 0 0x1000>; 2957 mediatek,larb-id = <22>; 2958 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2959 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2960 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2961 clock-names = "apb", "smi"; 2962 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2963 }; 2964 2965 vdecsys_core1: clock-controller@1803f000 { 2966 compatible = "mediatek,mt8195-vdecsys_core1"; 2967 reg = <0 0x1803f000 0 0x1000>; 2968 #clock-cells = <1>; 2969 }; 2970 2971 apusys_pll: clock-controller@190f3000 { 2972 compatible = "mediatek,mt8195-apusys_pll"; 2973 reg = <0 0x190f3000 0 0x1000>; 2974 #clock-cells = <1>; 2975 }; 2976 2977 vencsys: clock-controller@1a000000 { 2978 compatible = "mediatek,mt8195-vencsys"; 2979 reg = <0 0x1a000000 0 0x1000>; 2980 #clock-cells = <1>; 2981 }; 2982 2983 larb19: larb@1a010000 { 2984 compatible = "mediatek,mt8195-smi-larb"; 2985 reg = <0 0x1a010000 0 0x1000>; 2986 mediatek,larb-id = <19>; 2987 mediatek,smi = <&smi_common_vdo>; 2988 clocks = <&vencsys CLK_VENC_VENC>, 2989 <&vencsys CLK_VENC_GALS>; 2990 clock-names = "apb", "smi"; 2991 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2992 }; 2993 2994 venc: video-codec@1a020000 { 2995 compatible = "mediatek,mt8195-vcodec-enc"; 2996 reg = <0 0x1a020000 0 0x10000>; 2997 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2998 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2999 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 3000 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 3001 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 3002 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 3003 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 3004 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 3005 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 3006 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 3007 mediatek,scp = <&scp>; 3008 clocks = <&vencsys CLK_VENC_VENC>; 3009 clock-names = "venc_sel"; 3010 assigned-clocks = <&topckgen CLK_TOP_VENC>; 3011 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 3012 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3013 #address-cells = <2>; 3014 #size-cells = <2>; 3015 }; 3016 3017 jpgdec-master { 3018 compatible = "mediatek,mt8195-jpgdec"; 3019 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3020 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3021 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3022 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3023 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3024 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3025 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3026 #address-cells = <2>; 3027 #size-cells = <2>; 3028 ranges; 3029 3030 jpgdec@1a040000 { 3031 compatible = "mediatek,mt8195-jpgdec-hw"; 3032 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 3033 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3034 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3035 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3036 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3037 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3038 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3039 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 3040 clocks = <&vencsys CLK_VENC_JPGDEC>; 3041 clock-names = "jpgdec"; 3042 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 3043 }; 3044 3045 jpgdec@1a050000 { 3046 compatible = "mediatek,mt8195-jpgdec-hw"; 3047 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 3048 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3049 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3050 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3051 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3052 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3053 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3054 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 3055 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 3056 clock-names = "jpgdec"; 3057 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3058 }; 3059 3060 jpgdec@1b040000 { 3061 compatible = "mediatek,mt8195-jpgdec-hw"; 3062 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 3063 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 3064 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 3065 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 3066 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 3067 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 3068 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 3069 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 3070 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 3071 clock-names = "jpgdec"; 3072 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3073 }; 3074 }; 3075 3076 vencsys_core1: clock-controller@1b000000 { 3077 compatible = "mediatek,mt8195-vencsys_core1"; 3078 reg = <0 0x1b000000 0 0x1000>; 3079 #clock-cells = <1>; 3080 }; 3081 3082 vdosys0: syscon@1c01a000 { 3083 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 3084 reg = <0 0x1c01a000 0 0x1000>; 3085 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3086 #clock-cells = <1>; 3087 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 3088 }; 3089 3090 3091 jpgenc-master { 3092 compatible = "mediatek,mt8195-jpgenc"; 3093 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3094 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3095 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3096 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3097 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3098 #address-cells = <2>; 3099 #size-cells = <2>; 3100 ranges; 3101 3102 jpgenc@1a030000 { 3103 compatible = "mediatek,mt8195-jpgenc-hw"; 3104 reg = <0 0x1a030000 0 0x10000>; 3105 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 3106 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 3107 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 3108 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 3109 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 3110 clocks = <&vencsys CLK_VENC_JPGENC>; 3111 clock-names = "jpgenc"; 3112 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3113 }; 3114 3115 jpgenc@1b030000 { 3116 compatible = "mediatek,mt8195-jpgenc-hw"; 3117 reg = <0 0x1b030000 0 0x10000>; 3118 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3119 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3120 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3121 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3122 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 3123 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 3124 clock-names = "jpgenc"; 3125 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3126 }; 3127 }; 3128 3129 larb20: larb@1b010000 { 3130 compatible = "mediatek,mt8195-smi-larb"; 3131 reg = <0 0x1b010000 0 0x1000>; 3132 mediatek,larb-id = <20>; 3133 mediatek,smi = <&smi_common_vpp>; 3134 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, 3135 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 3136 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3137 clock-names = "apb", "smi", "gals"; 3138 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3139 }; 3140 3141 ovl0: ovl@1c000000 { 3142 compatible = "mediatek,mt8195-disp-ovl"; 3143 reg = <0 0x1c000000 0 0x1000>; 3144 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 3145 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3146 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 3147 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 3148 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 3149 }; 3150 3151 rdma0: rdma@1c002000 { 3152 compatible = "mediatek,mt8195-disp-rdma"; 3153 reg = <0 0x1c002000 0 0x1000>; 3154 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 3155 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3156 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 3157 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 3158 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 3159 }; 3160 3161 color0: color@1c003000 { 3162 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 3163 reg = <0 0x1c003000 0 0x1000>; 3164 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 3165 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3166 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 3167 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 3168 }; 3169 3170 ccorr0: ccorr@1c004000 { 3171 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 3172 reg = <0 0x1c004000 0 0x1000>; 3173 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 3174 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3175 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 3176 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 3177 }; 3178 3179 aal0: aal@1c005000 { 3180 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 3181 reg = <0 0x1c005000 0 0x1000>; 3182 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3183 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3184 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3185 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3186 }; 3187 3188 gamma0: gamma@1c006000 { 3189 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 3190 reg = <0 0x1c006000 0 0x1000>; 3191 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3192 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3193 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3194 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3195 }; 3196 3197 dither0: dither@1c007000 { 3198 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 3199 reg = <0 0x1c007000 0 0x1000>; 3200 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3201 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3202 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3203 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3204 }; 3205 3206 dsi0: dsi@1c008000 { 3207 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3208 reg = <0 0x1c008000 0 0x1000>; 3209 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3210 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3211 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3212 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3213 <&mipi_tx0>; 3214 clock-names = "engine", "digital", "hs"; 3215 phys = <&mipi_tx0>; 3216 phy-names = "dphy"; 3217 status = "disabled"; 3218 }; 3219 3220 dsc0: dsc@1c009000 { 3221 compatible = "mediatek,mt8195-disp-dsc"; 3222 reg = <0 0x1c009000 0 0x1000>; 3223 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3224 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3225 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3226 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3227 }; 3228 3229 dsi1: dsi@1c012000 { 3230 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3231 reg = <0 0x1c012000 0 0x1000>; 3232 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3233 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3234 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3235 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3236 <&mipi_tx1>; 3237 clock-names = "engine", "digital", "hs"; 3238 phys = <&mipi_tx1>; 3239 phy-names = "dphy"; 3240 status = "disabled"; 3241 }; 3242 3243 merge0: merge@1c014000 { 3244 compatible = "mediatek,mt8195-disp-merge"; 3245 reg = <0 0x1c014000 0 0x1000>; 3246 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3247 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3248 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 3249 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3250 }; 3251 3252 dp_intf0: dp-intf@1c015000 { 3253 compatible = "mediatek,mt8195-dp-intf"; 3254 reg = <0 0x1c015000 0 0x1000>; 3255 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3256 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3257 <&vdosys0 CLK_VDO0_DP_INTF0>, 3258 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3259 clock-names = "pixel", "engine", "pll"; 3260 status = "disabled"; 3261 }; 3262 3263 mutex: mutex@1c016000 { 3264 compatible = "mediatek,mt8195-disp-mutex"; 3265 reg = <0 0x1c016000 0 0x1000>; 3266 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3267 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3268 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3269 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 3270 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3271 }; 3272 3273 larb0: larb@1c018000 { 3274 compatible = "mediatek,mt8195-smi-larb"; 3275 reg = <0 0x1c018000 0 0x1000>; 3276 mediatek,larb-id = <0>; 3277 mediatek,smi = <&smi_common_vdo>; 3278 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3279 <&vdosys0 CLK_VDO0_SMI_LARB>, 3280 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 3281 clock-names = "apb", "smi", "gals"; 3282 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3283 }; 3284 3285 larb1: larb@1c019000 { 3286 compatible = "mediatek,mt8195-smi-larb"; 3287 reg = <0 0x1c019000 0 0x1000>; 3288 mediatek,larb-id = <1>; 3289 mediatek,smi = <&smi_common_vpp>; 3290 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3291 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 3292 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 3293 clock-names = "apb", "smi", "gals"; 3294 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3295 }; 3296 3297 vdosys1: syscon@1c100000 { 3298 compatible = "mediatek,mt8195-vdosys1", "syscon"; 3299 reg = <0 0x1c100000 0 0x1000>; 3300 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3301 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 3302 #clock-cells = <1>; 3303 #reset-cells = <1>; 3304 }; 3305 3306 smi_common_vdo: smi@1c01b000 { 3307 compatible = "mediatek,mt8195-smi-common-vdo"; 3308 reg = <0 0x1c01b000 0 0x1000>; 3309 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3310 <&vdosys0 CLK_VDO0_SMI_EMI>, 3311 <&vdosys0 CLK_VDO0_SMI_RSI>, 3312 <&vdosys0 CLK_VDO0_SMI_GALS>; 3313 clock-names = "apb", "smi", "gals0", "gals1"; 3314 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3315 3316 }; 3317 3318 iommu_vdo: iommu@1c01f000 { 3319 compatible = "mediatek,mt8195-iommu-vdo"; 3320 reg = <0 0x1c01f000 0 0x1000>; 3321 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 3322 &larb10 &larb11 &larb13 &larb17 3323 &larb19 &larb21 &larb24 &larb25 3324 &larb28>; 3325 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 3326 #iommu-cells = <1>; 3327 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3328 clock-names = "bclk"; 3329 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3330 }; 3331 3332 mutex1: mutex@1c101000 { 3333 compatible = "mediatek,mt8195-disp-mutex"; 3334 reg = <0 0x1c101000 0 0x1000>; 3335 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3336 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3337 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3338 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 3339 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3340 }; 3341 3342 larb2: larb@1c102000 { 3343 compatible = "mediatek,mt8195-smi-larb"; 3344 reg = <0 0x1c102000 0 0x1000>; 3345 mediatek,larb-id = <2>; 3346 mediatek,smi = <&smi_common_vdo>; 3347 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3348 <&vdosys1 CLK_VDO1_SMI_LARB2>, 3349 <&vdosys1 CLK_VDO1_GALS>; 3350 clock-names = "apb", "smi", "gals"; 3351 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3352 }; 3353 3354 larb3: larb@1c103000 { 3355 compatible = "mediatek,mt8195-smi-larb"; 3356 reg = <0 0x1c103000 0 0x1000>; 3357 mediatek,larb-id = <3>; 3358 mediatek,smi = <&smi_common_vpp>; 3359 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3360 <&vdosys1 CLK_VDO1_GALS>, 3361 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3362 clock-names = "apb", "smi", "gals"; 3363 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3364 }; 3365 3366 vdo1_rdma0: dma-controller@1c104000 { 3367 compatible = "mediatek,mt8195-vdo1-rdma"; 3368 reg = <0 0x1c104000 0 0x1000>; 3369 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3370 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3371 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3372 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 3373 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3374 #dma-cells = <1>; 3375 }; 3376 3377 vdo1_rdma1: dma-controller@1c105000 { 3378 compatible = "mediatek,mt8195-vdo1-rdma"; 3379 reg = <0 0x1c105000 0 0x1000>; 3380 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3381 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3382 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3383 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 3384 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3385 #dma-cells = <1>; 3386 }; 3387 3388 vdo1_rdma2: dma-controller@1c106000 { 3389 compatible = "mediatek,mt8195-vdo1-rdma"; 3390 reg = <0 0x1c106000 0 0x1000>; 3391 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3392 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3393 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3394 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 3395 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3396 #dma-cells = <1>; 3397 }; 3398 3399 vdo1_rdma3: dma-controller@1c107000 { 3400 compatible = "mediatek,mt8195-vdo1-rdma"; 3401 reg = <0 0x1c107000 0 0x1000>; 3402 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3403 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3404 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3405 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 3406 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3407 #dma-cells = <1>; 3408 }; 3409 3410 vdo1_rdma4: dma-controller@1c108000 { 3411 compatible = "mediatek,mt8195-vdo1-rdma"; 3412 reg = <0 0x1c108000 0 0x1000>; 3413 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3414 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3415 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3416 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 3417 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3418 #dma-cells = <1>; 3419 }; 3420 3421 vdo1_rdma5: dma-controller@1c109000 { 3422 compatible = "mediatek,mt8195-vdo1-rdma"; 3423 reg = <0 0x1c109000 0 0x1000>; 3424 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3425 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3426 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3427 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 3428 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3429 #dma-cells = <1>; 3430 }; 3431 3432 vdo1_rdma6: dma-controller@1c10a000 { 3433 compatible = "mediatek,mt8195-vdo1-rdma"; 3434 reg = <0 0x1c10a000 0 0x1000>; 3435 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3436 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3437 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3438 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 3439 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3440 #dma-cells = <1>; 3441 }; 3442 3443 vdo1_rdma7: dma-controller@1c10b000 { 3444 compatible = "mediatek,mt8195-vdo1-rdma"; 3445 reg = <0 0x1c10b000 0 0x1000>; 3446 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3447 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3448 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3449 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 3450 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3451 #dma-cells = <1>; 3452 }; 3453 3454 merge1: vpp-merge@1c10c000 { 3455 compatible = "mediatek,mt8195-disp-merge"; 3456 reg = <0 0x1c10c000 0 0x1000>; 3457 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3458 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3459 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3460 clock-names = "merge","merge_async"; 3461 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3462 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3463 mediatek,merge-mute; 3464 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 3465 }; 3466 3467 merge2: vpp-merge@1c10d000 { 3468 compatible = "mediatek,mt8195-disp-merge"; 3469 reg = <0 0x1c10d000 0 0x1000>; 3470 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3471 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3472 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3473 clock-names = "merge","merge_async"; 3474 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3475 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3476 mediatek,merge-mute; 3477 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 3478 }; 3479 3480 merge3: vpp-merge@1c10e000 { 3481 compatible = "mediatek,mt8195-disp-merge"; 3482 reg = <0 0x1c10e000 0 0x1000>; 3483 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3484 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3485 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3486 clock-names = "merge","merge_async"; 3487 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3488 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3489 mediatek,merge-mute; 3490 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3491 }; 3492 3493 merge4: vpp-merge@1c10f000 { 3494 compatible = "mediatek,mt8195-disp-merge"; 3495 reg = <0 0x1c10f000 0 0x1000>; 3496 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3497 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3498 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3499 clock-names = "merge","merge_async"; 3500 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3501 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3502 mediatek,merge-mute; 3503 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3504 }; 3505 3506 merge5: vpp-merge@1c110000 { 3507 compatible = "mediatek,mt8195-disp-merge"; 3508 reg = <0 0x1c110000 0 0x1000>; 3509 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3510 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3511 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3512 clock-names = "merge","merge_async"; 3513 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3514 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3515 mediatek,merge-fifo-en; 3516 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3517 }; 3518 3519 dp_intf1: dp-intf@1c113000 { 3520 compatible = "mediatek,mt8195-dp-intf"; 3521 reg = <0 0x1c113000 0 0x1000>; 3522 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3523 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3524 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3525 <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3526 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3527 clock-names = "pixel", "engine", "pll"; 3528 status = "disabled"; 3529 }; 3530 3531 ethdr0: hdr-engine@1c114000 { 3532 compatible = "mediatek,mt8195-disp-ethdr"; 3533 reg = <0 0x1c114000 0 0x1000>, 3534 <0 0x1c115000 0 0x1000>, 3535 <0 0x1c117000 0 0x1000>, 3536 <0 0x1c119000 0 0x1000>, 3537 <0 0x1c11a000 0 0x1000>, 3538 <0 0x1c11b000 0 0x1000>, 3539 <0 0x1c11c000 0 0x1000>; 3540 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3541 "vdo_be", "adl_ds"; 3542 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3543 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3544 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3545 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3546 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3547 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3548 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3549 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3550 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3551 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3552 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3553 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3554 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3555 <&vdosys1 CLK_VDO1_26M_SLOW>, 3556 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3557 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3558 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3559 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3560 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3561 <&topckgen CLK_TOP_ETHDR>; 3562 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3563 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3564 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3565 "ethdr_top"; 3566 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3567 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3568 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3569 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3570 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3571 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3572 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3573 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3574 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3575 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3576 "gfx_fe1_async", "vdo_be_async"; 3577 }; 3578 3579 edp_tx: edp-tx@1c500000 { 3580 compatible = "mediatek,mt8195-edp-tx"; 3581 reg = <0 0x1c500000 0 0x8000>; 3582 nvmem-cells = <&dp_calibration>; 3583 nvmem-cell-names = "dp_calibration_data"; 3584 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3585 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3586 max-linkrate-mhz = <8100>; 3587 status = "disabled"; 3588 }; 3589 3590 dp_tx: dp-tx@1c600000 { 3591 compatible = "mediatek,mt8195-dp-tx"; 3592 reg = <0 0x1c600000 0 0x8000>; 3593 nvmem-cells = <&dp_calibration>; 3594 nvmem-cell-names = "dp_calibration_data"; 3595 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3596 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3597 max-linkrate-mhz = <8100>; 3598 status = "disabled"; 3599 }; 3600 }; 3601 3602 thermal_zones: thermal-zones { 3603 cpu0-thermal { 3604 polling-delay = <1000>; 3605 polling-delay-passive = <250>; 3606 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3607 3608 trips { 3609 cpu0_alert: trip-alert { 3610 temperature = <85000>; 3611 hysteresis = <2000>; 3612 type = "passive"; 3613 }; 3614 3615 cpu0_crit: trip-crit { 3616 temperature = <100000>; 3617 hysteresis = <2000>; 3618 type = "critical"; 3619 }; 3620 }; 3621 3622 cooling-maps { 3623 map0 { 3624 trip = <&cpu0_alert>; 3625 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3626 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3627 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3628 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3629 }; 3630 }; 3631 }; 3632 3633 cpu1-thermal { 3634 polling-delay = <1000>; 3635 polling-delay-passive = <250>; 3636 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3637 3638 trips { 3639 cpu1_alert: trip-alert { 3640 temperature = <85000>; 3641 hysteresis = <2000>; 3642 type = "passive"; 3643 }; 3644 3645 cpu1_crit: trip-crit { 3646 temperature = <100000>; 3647 hysteresis = <2000>; 3648 type = "critical"; 3649 }; 3650 }; 3651 3652 cooling-maps { 3653 map0 { 3654 trip = <&cpu1_alert>; 3655 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3656 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3657 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3658 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3659 }; 3660 }; 3661 }; 3662 3663 cpu2-thermal { 3664 polling-delay = <1000>; 3665 polling-delay-passive = <250>; 3666 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3667 3668 trips { 3669 cpu2_alert: trip-alert { 3670 temperature = <85000>; 3671 hysteresis = <2000>; 3672 type = "passive"; 3673 }; 3674 3675 cpu2_crit: trip-crit { 3676 temperature = <100000>; 3677 hysteresis = <2000>; 3678 type = "critical"; 3679 }; 3680 }; 3681 3682 cooling-maps { 3683 map0 { 3684 trip = <&cpu2_alert>; 3685 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3686 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3687 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3688 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3689 }; 3690 }; 3691 }; 3692 3693 cpu3-thermal { 3694 polling-delay = <1000>; 3695 polling-delay-passive = <250>; 3696 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3697 3698 trips { 3699 cpu3_alert: trip-alert { 3700 temperature = <85000>; 3701 hysteresis = <2000>; 3702 type = "passive"; 3703 }; 3704 3705 cpu3_crit: trip-crit { 3706 temperature = <100000>; 3707 hysteresis = <2000>; 3708 type = "critical"; 3709 }; 3710 }; 3711 3712 cooling-maps { 3713 map0 { 3714 trip = <&cpu3_alert>; 3715 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3719 }; 3720 }; 3721 }; 3722 3723 cpu4-thermal { 3724 polling-delay = <1000>; 3725 polling-delay-passive = <250>; 3726 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3727 3728 trips { 3729 cpu4_alert: trip-alert { 3730 temperature = <85000>; 3731 hysteresis = <2000>; 3732 type = "passive"; 3733 }; 3734 3735 cpu4_crit: trip-crit { 3736 temperature = <100000>; 3737 hysteresis = <2000>; 3738 type = "critical"; 3739 }; 3740 }; 3741 3742 cooling-maps { 3743 map0 { 3744 trip = <&cpu4_alert>; 3745 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3749 }; 3750 }; 3751 }; 3752 3753 cpu5-thermal { 3754 polling-delay = <1000>; 3755 polling-delay-passive = <250>; 3756 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3757 3758 trips { 3759 cpu5_alert: trip-alert { 3760 temperature = <85000>; 3761 hysteresis = <2000>; 3762 type = "passive"; 3763 }; 3764 3765 cpu5_crit: trip-crit { 3766 temperature = <100000>; 3767 hysteresis = <2000>; 3768 type = "critical"; 3769 }; 3770 }; 3771 3772 cooling-maps { 3773 map0 { 3774 trip = <&cpu5_alert>; 3775 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3779 }; 3780 }; 3781 }; 3782 3783 cpu6-thermal { 3784 polling-delay = <1000>; 3785 polling-delay-passive = <250>; 3786 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3787 3788 trips { 3789 cpu6_alert: trip-alert { 3790 temperature = <85000>; 3791 hysteresis = <2000>; 3792 type = "passive"; 3793 }; 3794 3795 cpu6_crit: trip-crit { 3796 temperature = <100000>; 3797 hysteresis = <2000>; 3798 type = "critical"; 3799 }; 3800 }; 3801 3802 cooling-maps { 3803 map0 { 3804 trip = <&cpu6_alert>; 3805 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3809 }; 3810 }; 3811 }; 3812 3813 cpu7-thermal { 3814 polling-delay = <1000>; 3815 polling-delay-passive = <250>; 3816 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3817 3818 trips { 3819 cpu7_alert: trip-alert { 3820 temperature = <85000>; 3821 hysteresis = <2000>; 3822 type = "passive"; 3823 }; 3824 3825 cpu7_crit: trip-crit { 3826 temperature = <100000>; 3827 hysteresis = <2000>; 3828 type = "critical"; 3829 }; 3830 }; 3831 3832 cooling-maps { 3833 map0 { 3834 trip = <&cpu7_alert>; 3835 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3839 }; 3840 }; 3841 }; 3842 3843 vpu0-thermal { 3844 polling-delay = <1000>; 3845 polling-delay-passive = <250>; 3846 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 3847 3848 trips { 3849 vpu0_alert: trip-alert { 3850 temperature = <85000>; 3851 hysteresis = <2000>; 3852 type = "passive"; 3853 }; 3854 3855 vpu0_crit: trip-crit { 3856 temperature = <100000>; 3857 hysteresis = <2000>; 3858 type = "critical"; 3859 }; 3860 }; 3861 }; 3862 3863 vpu1-thermal { 3864 polling-delay = <1000>; 3865 polling-delay-passive = <250>; 3866 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 3867 3868 trips { 3869 vpu1_alert: trip-alert { 3870 temperature = <85000>; 3871 hysteresis = <2000>; 3872 type = "passive"; 3873 }; 3874 3875 vpu1_crit: trip-crit { 3876 temperature = <100000>; 3877 hysteresis = <2000>; 3878 type = "critical"; 3879 }; 3880 }; 3881 }; 3882 3883 gpu-thermal { 3884 polling-delay = <1000>; 3885 polling-delay-passive = <250>; 3886 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 3887 3888 trips { 3889 gpu0_alert: trip-alert { 3890 temperature = <85000>; 3891 hysteresis = <2000>; 3892 type = "passive"; 3893 }; 3894 3895 gpu0_crit: trip-crit { 3896 temperature = <100000>; 3897 hysteresis = <2000>; 3898 type = "critical"; 3899 }; 3900 }; 3901 }; 3902 3903 gpu1-thermal { 3904 polling-delay = <1000>; 3905 polling-delay-passive = <250>; 3906 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 3907 3908 trips { 3909 gpu1_alert: trip-alert { 3910 temperature = <85000>; 3911 hysteresis = <2000>; 3912 type = "passive"; 3913 }; 3914 3915 gpu1_crit: trip-crit { 3916 temperature = <100000>; 3917 hysteresis = <2000>; 3918 type = "critical"; 3919 }; 3920 }; 3921 }; 3922 3923 vdec-thermal { 3924 polling-delay = <1000>; 3925 polling-delay-passive = <250>; 3926 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 3927 3928 trips { 3929 vdec_alert: trip-alert { 3930 temperature = <85000>; 3931 hysteresis = <2000>; 3932 type = "passive"; 3933 }; 3934 3935 vdec_crit: trip-crit { 3936 temperature = <100000>; 3937 hysteresis = <2000>; 3938 type = "critical"; 3939 }; 3940 }; 3941 }; 3942 3943 img-thermal { 3944 polling-delay = <1000>; 3945 polling-delay-passive = <250>; 3946 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 3947 3948 trips { 3949 img_alert: trip-alert { 3950 temperature = <85000>; 3951 hysteresis = <2000>; 3952 type = "passive"; 3953 }; 3954 3955 img_crit: trip-crit { 3956 temperature = <100000>; 3957 hysteresis = <2000>; 3958 type = "critical"; 3959 }; 3960 }; 3961 }; 3962 3963 infra-thermal { 3964 polling-delay = <1000>; 3965 polling-delay-passive = <250>; 3966 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 3967 3968 trips { 3969 infra_alert: trip-alert { 3970 temperature = <85000>; 3971 hysteresis = <2000>; 3972 type = "passive"; 3973 }; 3974 3975 infra_crit: trip-crit { 3976 temperature = <100000>; 3977 hysteresis = <2000>; 3978 type = "critical"; 3979 }; 3980 }; 3981 }; 3982 3983 cam0-thermal { 3984 polling-delay = <1000>; 3985 polling-delay-passive = <250>; 3986 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 3987 3988 trips { 3989 cam0_alert: trip-alert { 3990 temperature = <85000>; 3991 hysteresis = <2000>; 3992 type = "passive"; 3993 }; 3994 3995 cam0_crit: trip-crit { 3996 temperature = <100000>; 3997 hysteresis = <2000>; 3998 type = "critical"; 3999 }; 4000 }; 4001 }; 4002 4003 cam1-thermal { 4004 polling-delay = <1000>; 4005 polling-delay-passive = <250>; 4006 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 4007 4008 trips { 4009 cam1_alert: trip-alert { 4010 temperature = <85000>; 4011 hysteresis = <2000>; 4012 type = "passive"; 4013 }; 4014 4015 cam1_crit: trip-crit { 4016 temperature = <100000>; 4017 hysteresis = <2000>; 4018 type = "critical"; 4019 }; 4020 }; 4021 }; 4022 }; 4023}; 4024