1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 pinmux: pinmux@2430000 { 115 compatible = "nvidia,tegra194-pinmux"; 116 reg = <0x0 0x2430000 0x0 0x17000>; 117 status = "okay"; 118 119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 120 clkreq { 121 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 122 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 123 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 124 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 }; 128 }; 129 130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 131 pex_rst { 132 nvidia,pins = "pex_l5_rst_n_pgg1"; 133 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 }; 139 }; 140 }; 141 142 ethernet@2490000 { 143 compatible = "nvidia,tegra194-eqos", 144 "nvidia,tegra186-eqos", 145 "snps,dwc-qos-ethernet-4.10"; 146 reg = <0x0 0x02490000 0x0 0x10000>; 147 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149 <&bpmp TEGRA194_CLK_EQOS_AXI>, 150 <&bpmp TEGRA194_CLK_EQOS_RX>, 151 <&bpmp TEGRA194_CLK_EQOS_TX>, 152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154 resets = <&bpmp TEGRA194_RESET_EQOS>; 155 reset-names = "eqos"; 156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158 interconnect-names = "dma-mem", "write"; 159 iommus = <&smmu TEGRA194_SID_EQOS>; 160 status = "disabled"; 161 162 snps,write-requests = <1>; 163 snps,read-requests = <3>; 164 snps,burst-map = <0x7>; 165 snps,txpbl = <16>; 166 snps,rxpbl = <8>; 167 }; 168 169 gpcdma: dma-controller@2600000 { 170 compatible = "nvidia,tegra194-gpcdma", 171 "nvidia,tegra186-gpcdma"; 172 reg = <0x0 0x2600000 0x0 0x210000>; 173 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174 reset-names = "gpcdma"; 175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207 #dma-cells = <1>; 208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209 dma-coherent; 210 dma-channel-mask = <0xfffffffe>; 211 status = "okay"; 212 }; 213 214 aconnect@2900000 { 215 compatible = "nvidia,tegra194-aconnect", 216 "nvidia,tegra210-aconnect"; 217 clocks = <&bpmp TEGRA194_CLK_APE>, 218 <&bpmp TEGRA194_CLK_APB2APE>; 219 clock-names = "ape", "apb2ape"; 220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 221 status = "disabled"; 222 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 226 227 tegra_ahub: ahub@2900800 { 228 compatible = "nvidia,tegra194-ahub", 229 "nvidia,tegra186-ahub"; 230 reg = <0x0 0x02900800 0x0 0x800>; 231 clocks = <&bpmp TEGRA194_CLK_AHUB>; 232 clock-names = "ahub"; 233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>; 235 assigned-clock-rates = <81600000>; 236 status = "disabled"; 237 238 #address-cells = <2>; 239 #size-cells = <2>; 240 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 241 242 tegra_i2s1: i2s@2901000 { 243 compatible = "nvidia,tegra194-i2s", 244 "nvidia,tegra210-i2s"; 245 reg = <0x0 0x2901000 0x0 0x100>; 246 clocks = <&bpmp TEGRA194_CLK_I2S1>, 247 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 248 clock-names = "i2s", "sync_input"; 249 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 251 assigned-clock-rates = <1536000>; 252 sound-name-prefix = "I2S1"; 253 status = "disabled"; 254 }; 255 256 tegra_i2s2: i2s@2901100 { 257 compatible = "nvidia,tegra194-i2s", 258 "nvidia,tegra210-i2s"; 259 reg = <0x0 0x2901100 0x0 0x100>; 260 clocks = <&bpmp TEGRA194_CLK_I2S2>, 261 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 262 clock-names = "i2s", "sync_input"; 263 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 265 assigned-clock-rates = <1536000>; 266 sound-name-prefix = "I2S2"; 267 status = "disabled"; 268 }; 269 270 tegra_i2s3: i2s@2901200 { 271 compatible = "nvidia,tegra194-i2s", 272 "nvidia,tegra210-i2s"; 273 reg = <0x0 0x2901200 0x0 0x100>; 274 clocks = <&bpmp TEGRA194_CLK_I2S3>, 275 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 276 clock-names = "i2s", "sync_input"; 277 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 279 assigned-clock-rates = <1536000>; 280 sound-name-prefix = "I2S3"; 281 status = "disabled"; 282 }; 283 284 tegra_i2s4: i2s@2901300 { 285 compatible = "nvidia,tegra194-i2s", 286 "nvidia,tegra210-i2s"; 287 reg = <0x0 0x2901300 0x0 0x100>; 288 clocks = <&bpmp TEGRA194_CLK_I2S4>, 289 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 290 clock-names = "i2s", "sync_input"; 291 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 293 assigned-clock-rates = <1536000>; 294 sound-name-prefix = "I2S4"; 295 status = "disabled"; 296 }; 297 298 tegra_i2s5: i2s@2901400 { 299 compatible = "nvidia,tegra194-i2s", 300 "nvidia,tegra210-i2s"; 301 reg = <0x0 0x2901400 0x0 0x100>; 302 clocks = <&bpmp TEGRA194_CLK_I2S5>, 303 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 304 clock-names = "i2s", "sync_input"; 305 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 307 assigned-clock-rates = <1536000>; 308 sound-name-prefix = "I2S5"; 309 status = "disabled"; 310 }; 311 312 tegra_i2s6: i2s@2901500 { 313 compatible = "nvidia,tegra194-i2s", 314 "nvidia,tegra210-i2s"; 315 reg = <0x0 0x2901500 0x0 0x100>; 316 clocks = <&bpmp TEGRA194_CLK_I2S6>, 317 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 318 clock-names = "i2s", "sync_input"; 319 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 321 assigned-clock-rates = <1536000>; 322 sound-name-prefix = "I2S6"; 323 status = "disabled"; 324 }; 325 326 tegra_sfc1: sfc@2902000 { 327 compatible = "nvidia,tegra194-sfc", 328 "nvidia,tegra210-sfc"; 329 reg = <0x0 0x2902000 0x0 0x200>; 330 sound-name-prefix = "SFC1"; 331 status = "disabled"; 332 }; 333 334 tegra_sfc2: sfc@2902200 { 335 compatible = "nvidia,tegra194-sfc", 336 "nvidia,tegra210-sfc"; 337 reg = <0x0 0x2902200 0x0 0x200>; 338 sound-name-prefix = "SFC2"; 339 status = "disabled"; 340 }; 341 342 tegra_sfc3: sfc@2902400 { 343 compatible = "nvidia,tegra194-sfc", 344 "nvidia,tegra210-sfc"; 345 reg = <0x0 0x2902400 0x0 0x200>; 346 sound-name-prefix = "SFC3"; 347 status = "disabled"; 348 }; 349 350 tegra_sfc4: sfc@2902600 { 351 compatible = "nvidia,tegra194-sfc", 352 "nvidia,tegra210-sfc"; 353 reg = <0x0 0x2902600 0x0 0x200>; 354 sound-name-prefix = "SFC4"; 355 status = "disabled"; 356 }; 357 358 tegra_amx1: amx@2903000 { 359 compatible = "nvidia,tegra194-amx"; 360 reg = <0x0 0x2903000 0x0 0x100>; 361 sound-name-prefix = "AMX1"; 362 status = "disabled"; 363 }; 364 365 tegra_amx2: amx@2903100 { 366 compatible = "nvidia,tegra194-amx"; 367 reg = <0x0 0x2903100 0x0 0x100>; 368 sound-name-prefix = "AMX2"; 369 status = "disabled"; 370 }; 371 372 tegra_amx3: amx@2903200 { 373 compatible = "nvidia,tegra194-amx"; 374 reg = <0x0 0x2903200 0x0 0x100>; 375 sound-name-prefix = "AMX3"; 376 status = "disabled"; 377 }; 378 379 tegra_amx4: amx@2903300 { 380 compatible = "nvidia,tegra194-amx"; 381 reg = <0x0 0x2903300 0x0 0x100>; 382 sound-name-prefix = "AMX4"; 383 status = "disabled"; 384 }; 385 386 tegra_adx1: adx@2903800 { 387 compatible = "nvidia,tegra194-adx", 388 "nvidia,tegra210-adx"; 389 reg = <0x0 0x2903800 0x0 0x100>; 390 sound-name-prefix = "ADX1"; 391 status = "disabled"; 392 }; 393 394 tegra_adx2: adx@2903900 { 395 compatible = "nvidia,tegra194-adx", 396 "nvidia,tegra210-adx"; 397 reg = <0x0 0x2903900 0x0 0x100>; 398 sound-name-prefix = "ADX2"; 399 status = "disabled"; 400 }; 401 402 tegra_adx3: adx@2903a00 { 403 compatible = "nvidia,tegra194-adx", 404 "nvidia,tegra210-adx"; 405 reg = <0x0 0x2903a00 0x0 0x100>; 406 sound-name-prefix = "ADX3"; 407 status = "disabled"; 408 }; 409 410 tegra_adx4: adx@2903b00 { 411 compatible = "nvidia,tegra194-adx", 412 "nvidia,tegra210-adx"; 413 reg = <0x0 0x2903b00 0x0 0x100>; 414 sound-name-prefix = "ADX4"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic1: dmic@2904000 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x0 0x2904000 0x0 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC1"; 428 status = "disabled"; 429 }; 430 431 tegra_dmic2: dmic@2904100 { 432 compatible = "nvidia,tegra194-dmic", 433 "nvidia,tegra210-dmic"; 434 reg = <0x0 0x2904100 0x0 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 436 clock-names = "dmic"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <3072000>; 440 sound-name-prefix = "DMIC2"; 441 status = "disabled"; 442 }; 443 444 tegra_dmic3: dmic@2904200 { 445 compatible = "nvidia,tegra194-dmic", 446 "nvidia,tegra210-dmic"; 447 reg = <0x0 0x2904200 0x0 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 449 clock-names = "dmic"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <3072000>; 453 sound-name-prefix = "DMIC3"; 454 status = "disabled"; 455 }; 456 457 tegra_dmic4: dmic@2904300 { 458 compatible = "nvidia,tegra194-dmic", 459 "nvidia,tegra210-dmic"; 460 reg = <0x0 0x2904300 0x0 0x100>; 461 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 462 clock-names = "dmic"; 463 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 464 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 465 assigned-clock-rates = <3072000>; 466 sound-name-prefix = "DMIC4"; 467 status = "disabled"; 468 }; 469 470 tegra_dspk1: dspk@2905000 { 471 compatible = "nvidia,tegra194-dspk", 472 "nvidia,tegra186-dspk"; 473 reg = <0x0 0x2905000 0x0 0x100>; 474 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 475 clock-names = "dspk"; 476 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 477 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 478 assigned-clock-rates = <12288000>; 479 sound-name-prefix = "DSPK1"; 480 status = "disabled"; 481 }; 482 483 tegra_dspk2: dspk@2905100 { 484 compatible = "nvidia,tegra194-dspk", 485 "nvidia,tegra186-dspk"; 486 reg = <0x0 0x2905100 0x0 0x100>; 487 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 488 clock-names = "dspk"; 489 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 490 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 491 assigned-clock-rates = <12288000>; 492 sound-name-prefix = "DSPK2"; 493 status = "disabled"; 494 }; 495 496 tegra_ope1: processing-engine@2908000 { 497 compatible = "nvidia,tegra194-ope", 498 "nvidia,tegra210-ope"; 499 reg = <0x0 0x2908000 0x0 0x100>; 500 sound-name-prefix = "OPE1"; 501 status = "disabled"; 502 503 #address-cells = <2>; 504 #size-cells = <2>; 505 ranges; 506 507 equalizer@2908100 { 508 compatible = "nvidia,tegra194-peq", 509 "nvidia,tegra210-peq"; 510 reg = <0x0 0x2908100 0x0 0x100>; 511 }; 512 513 dynamic-range-compressor@2908200 { 514 compatible = "nvidia,tegra194-mbdrc", 515 "nvidia,tegra210-mbdrc"; 516 reg = <0x0 0x2908200 0x0 0x200>; 517 }; 518 }; 519 520 tegra_mvc1: mvc@290a000 { 521 compatible = "nvidia,tegra194-mvc", 522 "nvidia,tegra210-mvc"; 523 reg = <0x0 0x290a000 0x0 0x200>; 524 sound-name-prefix = "MVC1"; 525 status = "disabled"; 526 }; 527 528 tegra_mvc2: mvc@290a200 { 529 compatible = "nvidia,tegra194-mvc", 530 "nvidia,tegra210-mvc"; 531 reg = <0x0 0x290a200 0x0 0x200>; 532 sound-name-prefix = "MVC2"; 533 status = "disabled"; 534 }; 535 536 tegra_amixer: amixer@290bb00 { 537 compatible = "nvidia,tegra194-amixer", 538 "nvidia,tegra210-amixer"; 539 reg = <0x0 0x290bb00 0x0 0x800>; 540 sound-name-prefix = "MIXER1"; 541 status = "disabled"; 542 }; 543 544 tegra_admaif: admaif@290f000 { 545 compatible = "nvidia,tegra194-admaif", 546 "nvidia,tegra186-admaif"; 547 reg = <0x0 0x0290f000 0x0 0x1000>; 548 dmas = <&adma 1>, <&adma 1>, 549 <&adma 2>, <&adma 2>, 550 <&adma 3>, <&adma 3>, 551 <&adma 4>, <&adma 4>, 552 <&adma 5>, <&adma 5>, 553 <&adma 6>, <&adma 6>, 554 <&adma 7>, <&adma 7>, 555 <&adma 8>, <&adma 8>, 556 <&adma 9>, <&adma 9>, 557 <&adma 10>, <&adma 10>, 558 <&adma 11>, <&adma 11>, 559 <&adma 12>, <&adma 12>, 560 <&adma 13>, <&adma 13>, 561 <&adma 14>, <&adma 14>, 562 <&adma 15>, <&adma 15>, 563 <&adma 16>, <&adma 16>, 564 <&adma 17>, <&adma 17>, 565 <&adma 18>, <&adma 18>, 566 <&adma 19>, <&adma 19>, 567 <&adma 20>, <&adma 20>; 568 dma-names = "rx1", "tx1", 569 "rx2", "tx2", 570 "rx3", "tx3", 571 "rx4", "tx4", 572 "rx5", "tx5", 573 "rx6", "tx6", 574 "rx7", "tx7", 575 "rx8", "tx8", 576 "rx9", "tx9", 577 "rx10", "tx10", 578 "rx11", "tx11", 579 "rx12", "tx12", 580 "rx13", "tx13", 581 "rx14", "tx14", 582 "rx15", "tx15", 583 "rx16", "tx16", 584 "rx17", "tx17", 585 "rx18", "tx18", 586 "rx19", "tx19", 587 "rx20", "tx20"; 588 status = "disabled"; 589 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 590 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 591 interconnect-names = "dma-mem", "write"; 592 iommus = <&smmu TEGRA194_SID_APE>; 593 }; 594 595 tegra_asrc: asrc@2910000 { 596 compatible = "nvidia,tegra194-asrc", 597 "nvidia,tegra186-asrc"; 598 reg = <0x0 0x2910000 0x0 0x2000>; 599 sound-name-prefix = "ASRC1"; 600 status = "disabled"; 601 }; 602 }; 603 604 adma: dma-controller@2930000 { 605 compatible = "nvidia,tegra194-adma", 606 "nvidia,tegra186-adma"; 607 reg = <0x0 0x02930000 0x0 0x20000>; 608 interrupt-parent = <&agic>; 609 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 641 #dma-cells = <1>; 642 clocks = <&bpmp TEGRA194_CLK_AHUB>; 643 clock-names = "d_audio"; 644 status = "disabled"; 645 }; 646 647 agic: interrupt-controller@2a40000 { 648 compatible = "nvidia,tegra194-agic", 649 "nvidia,tegra210-agic"; 650 #interrupt-cells = <3>; 651 interrupt-controller; 652 reg = <0x0 0x02a41000 0x0 0x1000>, 653 <0x0 0x02a42000 0x0 0x2000>; 654 interrupts = <GIC_SPI 145 655 (GIC_CPU_MASK_SIMPLE(4) | 656 IRQ_TYPE_LEVEL_HIGH)>; 657 clocks = <&bpmp TEGRA194_CLK_APE>; 658 clock-names = "clk"; 659 status = "disabled"; 660 }; 661 }; 662 663 mc: memory-controller@2c00000 { 664 compatible = "nvidia,tegra194-mc"; 665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 666 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 667 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 668 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 669 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 670 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 671 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 672 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 673 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 674 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 675 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 676 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 677 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 678 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 679 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 680 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 681 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 682 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 683 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 684 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 685 "ch11", "ch12", "ch13", "ch14", "ch15"; 686 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 687 #interconnect-cells = <1>; 688 status = "disabled"; 689 690 #address-cells = <2>; 691 #size-cells = <2>; 692 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 693 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 694 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 695 696 /* 697 * Bit 39 of addresses passing through the memory 698 * controller selects the XBAR format used when memory 699 * is accessed. This is used to transparently access 700 * memory in the XBAR format used by the discrete GPU 701 * (bit 39 set) or Tegra (bit 39 clear). 702 * 703 * As a consequence, the operating system must ensure 704 * that bit 39 is never used implicitly, for example 705 * via an I/O virtual address mapping of an IOMMU. If 706 * devices require access to the XBAR switch, their 707 * drivers must set this bit explicitly. 708 * 709 * Limit the DMA range for memory clients to [38:0]. 710 */ 711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 712 713 emc: external-memory-controller@2c60000 { 714 compatible = "nvidia,tegra194-emc"; 715 reg = <0x0 0x02c60000 0x0 0x90000>, 716 <0x0 0x01780000 0x0 0x80000>; 717 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&bpmp TEGRA194_CLK_EMC>; 719 clock-names = "emc"; 720 721 #interconnect-cells = <0>; 722 723 nvidia,bpmp = <&bpmp>; 724 }; 725 }; 726 727 timer@3010000 { 728 compatible = "nvidia,tegra186-timer"; 729 reg = <0x0 0x03010000 0x0 0x000e0000>; 730 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 740 status = "okay"; 741 }; 742 743 uarta: serial@3100000 { 744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 745 reg = <0x0 0x03100000 0x0 0x40>; 746 reg-shift = <2>; 747 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&bpmp TEGRA194_CLK_UARTA>; 749 resets = <&bpmp TEGRA194_RESET_UARTA>; 750 status = "disabled"; 751 }; 752 753 uartb: serial@3110000 { 754 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 755 reg = <0x0 0x03110000 0x0 0x40>; 756 reg-shift = <2>; 757 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&bpmp TEGRA194_CLK_UARTB>; 759 resets = <&bpmp TEGRA194_RESET_UARTB>; 760 status = "disabled"; 761 }; 762 763 uartd: serial@3130000 { 764 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 765 reg = <0x0 0x03130000 0x0 0x40>; 766 reg-shift = <2>; 767 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&bpmp TEGRA194_CLK_UARTD>; 769 resets = <&bpmp TEGRA194_RESET_UARTD>; 770 status = "disabled"; 771 }; 772 773 uarte: serial@3140000 { 774 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 775 reg = <0x0 0x03140000 0x0 0x40>; 776 reg-shift = <2>; 777 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&bpmp TEGRA194_CLK_UARTE>; 779 resets = <&bpmp TEGRA194_RESET_UARTE>; 780 status = "disabled"; 781 }; 782 783 uartf: serial@3150000 { 784 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 785 reg = <0x0 0x03150000 0x0 0x40>; 786 reg-shift = <2>; 787 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&bpmp TEGRA194_CLK_UARTF>; 789 resets = <&bpmp TEGRA194_RESET_UARTF>; 790 status = "disabled"; 791 }; 792 793 gen1_i2c: i2c@3160000 { 794 compatible = "nvidia,tegra194-i2c"; 795 reg = <0x0 0x03160000 0x0 0x10000>; 796 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 clocks = <&bpmp TEGRA194_CLK_I2C1>; 800 clock-names = "div-clk"; 801 resets = <&bpmp TEGRA194_RESET_I2C1>; 802 reset-names = "i2c"; 803 dmas = <&gpcdma 21>, <&gpcdma 21>; 804 dma-names = "rx", "tx"; 805 status = "disabled"; 806 }; 807 808 uarth: serial@3170000 { 809 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 810 reg = <0x0 0x03170000 0x0 0x40>; 811 reg-shift = <2>; 812 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&bpmp TEGRA194_CLK_UARTH>; 814 resets = <&bpmp TEGRA194_RESET_UARTH>; 815 status = "disabled"; 816 }; 817 818 cam_i2c: i2c@3180000 { 819 compatible = "nvidia,tegra194-i2c"; 820 reg = <0x0 0x03180000 0x0 0x10000>; 821 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&bpmp TEGRA194_CLK_I2C3>; 825 clock-names = "div-clk"; 826 resets = <&bpmp TEGRA194_RESET_I2C3>; 827 reset-names = "i2c"; 828 dmas = <&gpcdma 23>, <&gpcdma 23>; 829 dma-names = "rx", "tx"; 830 status = "disabled"; 831 }; 832 833 /* shares pads with dpaux1 */ 834 dp_aux_ch1_i2c: i2c@3190000 { 835 compatible = "nvidia,tegra194-i2c"; 836 reg = <0x0 0x03190000 0x0 0x10000>; 837 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 clocks = <&bpmp TEGRA194_CLK_I2C4>; 841 clock-names = "div-clk"; 842 resets = <&bpmp TEGRA194_RESET_I2C4>; 843 reset-names = "i2c"; 844 pinctrl-0 = <&state_dpaux1_i2c>; 845 pinctrl-1 = <&state_dpaux1_off>; 846 pinctrl-names = "default", "idle"; 847 dmas = <&gpcdma 26>, <&gpcdma 26>; 848 dma-names = "rx", "tx"; 849 status = "disabled"; 850 }; 851 852 /* shares pads with dpaux0 */ 853 dp_aux_ch0_i2c: i2c@31b0000 { 854 compatible = "nvidia,tegra194-i2c"; 855 reg = <0x0 0x031b0000 0x0 0x10000>; 856 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 clocks = <&bpmp TEGRA194_CLK_I2C6>; 860 clock-names = "div-clk"; 861 resets = <&bpmp TEGRA194_RESET_I2C6>; 862 reset-names = "i2c"; 863 pinctrl-0 = <&state_dpaux0_i2c>; 864 pinctrl-1 = <&state_dpaux0_off>; 865 pinctrl-names = "default", "idle"; 866 dmas = <&gpcdma 30>, <&gpcdma 30>; 867 dma-names = "rx", "tx"; 868 status = "disabled"; 869 }; 870 871 /* shares pads with dpaux2 */ 872 dp_aux_ch2_i2c: i2c@31c0000 { 873 compatible = "nvidia,tegra194-i2c"; 874 reg = <0x0 0x031c0000 0x0 0x10000>; 875 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 clocks = <&bpmp TEGRA194_CLK_I2C7>; 879 clock-names = "div-clk"; 880 resets = <&bpmp TEGRA194_RESET_I2C7>; 881 reset-names = "i2c"; 882 pinctrl-0 = <&state_dpaux2_i2c>; 883 pinctrl-1 = <&state_dpaux2_off>; 884 pinctrl-names = "default", "idle"; 885 dmas = <&gpcdma 27>, <&gpcdma 27>; 886 dma-names = "rx", "tx"; 887 status = "disabled"; 888 }; 889 890 /* shares pads with dpaux3 */ 891 dp_aux_ch3_i2c: i2c@31e0000 { 892 compatible = "nvidia,tegra194-i2c"; 893 reg = <0x0 0x031e0000 0x0 0x10000>; 894 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 clocks = <&bpmp TEGRA194_CLK_I2C9>; 898 clock-names = "div-clk"; 899 resets = <&bpmp TEGRA194_RESET_I2C9>; 900 reset-names = "i2c"; 901 pinctrl-0 = <&state_dpaux3_i2c>; 902 pinctrl-1 = <&state_dpaux3_off>; 903 pinctrl-names = "default", "idle"; 904 dmas = <&gpcdma 31>, <&gpcdma 31>; 905 dma-names = "rx", "tx"; 906 status = "disabled"; 907 }; 908 909 spi@3270000 { 910 compatible = "nvidia,tegra194-qspi"; 911 reg = <0x0 0x3270000 0x0 0x1000>; 912 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 916 <&bpmp TEGRA194_CLK_QSPI0_PM>; 917 clock-names = "qspi", "qspi_out"; 918 resets = <&bpmp TEGRA194_RESET_QSPI0>; 919 status = "disabled"; 920 }; 921 922 pwm1: pwm@3280000 { 923 compatible = "nvidia,tegra194-pwm", 924 "nvidia,tegra186-pwm"; 925 reg = <0x0 0x3280000 0x0 0x10000>; 926 clocks = <&bpmp TEGRA194_CLK_PWM1>; 927 resets = <&bpmp TEGRA194_RESET_PWM1>; 928 reset-names = "pwm"; 929 status = "disabled"; 930 #pwm-cells = <2>; 931 }; 932 933 pwm2: pwm@3290000 { 934 compatible = "nvidia,tegra194-pwm", 935 "nvidia,tegra186-pwm"; 936 reg = <0x0 0x3290000 0x0 0x10000>; 937 clocks = <&bpmp TEGRA194_CLK_PWM2>; 938 resets = <&bpmp TEGRA194_RESET_PWM2>; 939 reset-names = "pwm"; 940 status = "disabled"; 941 #pwm-cells = <2>; 942 }; 943 944 pwm3: pwm@32a0000 { 945 compatible = "nvidia,tegra194-pwm", 946 "nvidia,tegra186-pwm"; 947 reg = <0x0 0x32a0000 0x0 0x10000>; 948 clocks = <&bpmp TEGRA194_CLK_PWM3>; 949 resets = <&bpmp TEGRA194_RESET_PWM3>; 950 reset-names = "pwm"; 951 status = "disabled"; 952 #pwm-cells = <2>; 953 }; 954 955 pwm5: pwm@32c0000 { 956 compatible = "nvidia,tegra194-pwm", 957 "nvidia,tegra186-pwm"; 958 reg = <0x0 0x32c0000 0x0 0x10000>; 959 clocks = <&bpmp TEGRA194_CLK_PWM5>; 960 resets = <&bpmp TEGRA194_RESET_PWM5>; 961 reset-names = "pwm"; 962 status = "disabled"; 963 #pwm-cells = <2>; 964 }; 965 966 pwm6: pwm@32d0000 { 967 compatible = "nvidia,tegra194-pwm", 968 "nvidia,tegra186-pwm"; 969 reg = <0x0 0x32d0000 0x0 0x10000>; 970 clocks = <&bpmp TEGRA194_CLK_PWM6>; 971 resets = <&bpmp TEGRA194_RESET_PWM6>; 972 reset-names = "pwm"; 973 status = "disabled"; 974 #pwm-cells = <2>; 975 }; 976 977 pwm7: pwm@32e0000 { 978 compatible = "nvidia,tegra194-pwm", 979 "nvidia,tegra186-pwm"; 980 reg = <0x0 0x32e0000 0x0 0x10000>; 981 clocks = <&bpmp TEGRA194_CLK_PWM7>; 982 resets = <&bpmp TEGRA194_RESET_PWM7>; 983 reset-names = "pwm"; 984 status = "disabled"; 985 #pwm-cells = <2>; 986 }; 987 988 pwm8: pwm@32f0000 { 989 compatible = "nvidia,tegra194-pwm", 990 "nvidia,tegra186-pwm"; 991 reg = <0x0 0x32f0000 0x0 0x10000>; 992 clocks = <&bpmp TEGRA194_CLK_PWM8>; 993 resets = <&bpmp TEGRA194_RESET_PWM8>; 994 reset-names = "pwm"; 995 status = "disabled"; 996 #pwm-cells = <2>; 997 }; 998 999 spi@3300000 { 1000 compatible = "nvidia,tegra194-qspi"; 1001 reg = <0x0 0x3300000 0x0 0x1000>; 1002 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1006 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1007 clock-names = "qspi", "qspi_out"; 1008 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1009 status = "disabled"; 1010 }; 1011 1012 sdmmc1: mmc@3400000 { 1013 compatible = "nvidia,tegra194-sdhci"; 1014 reg = <0x0 0x03400000 0x0 0x10000>; 1015 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1017 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1018 clock-names = "sdhci", "tmclk"; 1019 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1020 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1021 assigned-clock-parents = 1022 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1023 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1024 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1025 reset-names = "sdhci"; 1026 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1027 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1028 interconnect-names = "dma-mem", "write"; 1029 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1030 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1031 pinctrl-0 = <&sdmmc1_3v3>; 1032 pinctrl-1 = <&sdmmc1_1v8>; 1033 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1034 <0x07>; 1035 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1036 <0x07>; 1037 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1038 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1039 <0x07>; 1040 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1041 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1042 nvidia,default-tap = <0x9>; 1043 nvidia,default-trim = <0x5>; 1044 sd-uhs-sdr25; 1045 sd-uhs-sdr50; 1046 sd-uhs-ddr50; 1047 sd-uhs-sdr104; 1048 status = "disabled"; 1049 }; 1050 1051 sdmmc3: mmc@3440000 { 1052 compatible = "nvidia,tegra194-sdhci"; 1053 reg = <0x0 0x03440000 0x0 0x10000>; 1054 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1056 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1057 clock-names = "sdhci", "tmclk"; 1058 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1059 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1060 assigned-clock-parents = 1061 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1062 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1063 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1064 reset-names = "sdhci"; 1065 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1066 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1067 interconnect-names = "dma-mem", "write"; 1068 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1069 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1070 pinctrl-0 = <&sdmmc3_3v3>; 1071 pinctrl-1 = <&sdmmc3_1v8>; 1072 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1073 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1074 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1075 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1076 <0x07>; 1077 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1078 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1079 <0x07>; 1080 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1081 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1082 nvidia,default-tap = <0x9>; 1083 nvidia,default-trim = <0x5>; 1084 sd-uhs-sdr25; 1085 sd-uhs-sdr50; 1086 sd-uhs-ddr50; 1087 sd-uhs-sdr104; 1088 status = "disabled"; 1089 }; 1090 1091 sdmmc4: mmc@3460000 { 1092 compatible = "nvidia,tegra194-sdhci"; 1093 reg = <0x0 0x03460000 0x0 0x10000>; 1094 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1096 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1097 clock-names = "sdhci", "tmclk"; 1098 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1099 <&bpmp TEGRA194_CLK_PLLC4>; 1100 assigned-clock-parents = 1101 <&bpmp TEGRA194_CLK_PLLC4>; 1102 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1103 reset-names = "sdhci"; 1104 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1105 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1106 interconnect-names = "dma-mem", "write"; 1107 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1108 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1109 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1110 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1111 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1112 <0x0a>; 1113 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1114 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1115 <0x0a>; 1116 nvidia,default-tap = <0x8>; 1117 nvidia,default-trim = <0x14>; 1118 nvidia,dqs-trim = <40>; 1119 cap-mmc-highspeed; 1120 mmc-ddr-1_8v; 1121 mmc-hs200-1_8v; 1122 mmc-hs400-1_8v; 1123 mmc-hs400-enhanced-strobe; 1124 supports-cqe; 1125 status = "disabled"; 1126 }; 1127 1128 hda@3510000 { 1129 compatible = "nvidia,tegra194-hda"; 1130 reg = <0x0 0x3510000 0x0 0x10000>; 1131 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&bpmp TEGRA194_CLK_HDA>, 1133 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1134 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1135 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1136 resets = <&bpmp TEGRA194_RESET_HDA>, 1137 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1138 reset-names = "hda", "hda2hdmi"; 1139 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1140 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1141 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1142 interconnect-names = "dma-mem", "write"; 1143 iommus = <&smmu TEGRA194_SID_HDA>; 1144 status = "disabled"; 1145 }; 1146 1147 xusb_padctl: padctl@3520000 { 1148 compatible = "nvidia,tegra194-xusb-padctl"; 1149 reg = <0x0 0x03520000 0x0 0x1000>, 1150 <0x0 0x03540000 0x0 0x1000>; 1151 reg-names = "padctl", "ao"; 1152 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1153 1154 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1155 reset-names = "padctl"; 1156 1157 status = "disabled"; 1158 1159 pads { 1160 usb2 { 1161 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1162 clock-names = "trk"; 1163 1164 lanes { 1165 usb2-0 { 1166 nvidia,function = "xusb"; 1167 status = "disabled"; 1168 #phy-cells = <0>; 1169 }; 1170 1171 usb2-1 { 1172 nvidia,function = "xusb"; 1173 status = "disabled"; 1174 #phy-cells = <0>; 1175 }; 1176 1177 usb2-2 { 1178 nvidia,function = "xusb"; 1179 status = "disabled"; 1180 #phy-cells = <0>; 1181 }; 1182 1183 usb2-3 { 1184 nvidia,function = "xusb"; 1185 status = "disabled"; 1186 #phy-cells = <0>; 1187 }; 1188 }; 1189 }; 1190 1191 usb3 { 1192 lanes { 1193 usb3-0 { 1194 nvidia,function = "xusb"; 1195 status = "disabled"; 1196 #phy-cells = <0>; 1197 }; 1198 1199 usb3-1 { 1200 nvidia,function = "xusb"; 1201 status = "disabled"; 1202 #phy-cells = <0>; 1203 }; 1204 1205 usb3-2 { 1206 nvidia,function = "xusb"; 1207 status = "disabled"; 1208 #phy-cells = <0>; 1209 }; 1210 1211 usb3-3 { 1212 nvidia,function = "xusb"; 1213 status = "disabled"; 1214 #phy-cells = <0>; 1215 }; 1216 }; 1217 }; 1218 }; 1219 1220 ports { 1221 usb2-0 { 1222 status = "disabled"; 1223 }; 1224 1225 usb2-1 { 1226 status = "disabled"; 1227 }; 1228 1229 usb2-2 { 1230 status = "disabled"; 1231 }; 1232 1233 usb2-3 { 1234 status = "disabled"; 1235 }; 1236 1237 usb3-0 { 1238 status = "disabled"; 1239 }; 1240 1241 usb3-1 { 1242 status = "disabled"; 1243 }; 1244 1245 usb3-2 { 1246 status = "disabled"; 1247 }; 1248 1249 usb3-3 { 1250 status = "disabled"; 1251 }; 1252 }; 1253 }; 1254 1255 usb@3550000 { 1256 compatible = "nvidia,tegra194-xudc"; 1257 reg = <0x0 0x03550000 0x0 0x8000>, 1258 <0x0 0x03558000 0x0 0x1000>; 1259 reg-names = "base", "fpci"; 1260 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1262 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1263 <&bpmp TEGRA194_CLK_XUSB_SS>, 1264 <&bpmp TEGRA194_CLK_XUSB_FS>; 1265 clock-names = "dev", "ss", "ss_src", "fs_src"; 1266 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1267 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1268 interconnect-names = "dma-mem", "write"; 1269 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1270 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1271 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1272 power-domain-names = "dev", "ss"; 1273 nvidia,xusb-padctl = <&xusb_padctl>; 1274 dma-coherent; 1275 status = "disabled"; 1276 }; 1277 1278 usb@3610000 { 1279 compatible = "nvidia,tegra194-xusb"; 1280 reg = <0x0 0x03610000 0x0 0x40000>, 1281 <0x0 0x03600000 0x0 0x10000>; 1282 reg-names = "hcd", "fpci"; 1283 1284 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1286 1287 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1288 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1289 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1290 <&bpmp TEGRA194_CLK_XUSB_SS>, 1291 <&bpmp TEGRA194_CLK_CLK_M>, 1292 <&bpmp TEGRA194_CLK_XUSB_FS>, 1293 <&bpmp TEGRA194_CLK_UTMIPLL>, 1294 <&bpmp TEGRA194_CLK_CLK_M>, 1295 <&bpmp TEGRA194_CLK_PLLE>; 1296 clock-names = "xusb_host", "xusb_falcon_src", 1297 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1298 "xusb_fs_src", "pll_u_480m", "clk_m", 1299 "pll_e"; 1300 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1301 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1302 interconnect-names = "dma-mem", "write"; 1303 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1304 1305 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1306 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1307 power-domain-names = "xusb_host", "xusb_ss"; 1308 1309 nvidia,xusb-padctl = <&xusb_padctl>; 1310 status = "disabled"; 1311 }; 1312 1313 fuse@3820000 { 1314 compatible = "nvidia,tegra194-efuse"; 1315 reg = <0x0 0x03820000 0x0 0x10000>; 1316 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1317 clock-names = "fuse"; 1318 }; 1319 1320 gic: interrupt-controller@3881000 { 1321 compatible = "arm,gic-400"; 1322 #interrupt-cells = <3>; 1323 interrupt-controller; 1324 reg = <0x0 0x03881000 0x0 0x1000>, 1325 <0x0 0x03882000 0x0 0x2000>, 1326 <0x0 0x03884000 0x0 0x2000>, 1327 <0x0 0x03886000 0x0 0x2000>; 1328 interrupts = <GIC_PPI 9 1329 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1330 interrupt-parent = <&gic>; 1331 }; 1332 1333 cec@3960000 { 1334 compatible = "nvidia,tegra194-cec"; 1335 reg = <0x0 0x03960000 0x0 0x10000>; 1336 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&bpmp TEGRA194_CLK_CEC>; 1338 clock-names = "cec"; 1339 status = "disabled"; 1340 }; 1341 1342 hte_lic: hardware-timestamp@3aa0000 { 1343 compatible = "nvidia,tegra194-gte-lic"; 1344 reg = <0x0 0x3aa0000 0x0 0x10000>; 1345 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1346 nvidia,int-threshold = <1>; 1347 nvidia,slices = <11>; 1348 #timestamp-cells = <1>; 1349 status = "okay"; 1350 }; 1351 1352 hsp_top0: hsp@3c00000 { 1353 compatible = "nvidia,tegra194-hsp"; 1354 reg = <0x0 0x03c00000 0x0 0xa0000>; 1355 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1364 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1365 "shared3", "shared4", "shared5", "shared6", 1366 "shared7"; 1367 #mbox-cells = <2>; 1368 }; 1369 1370 p2u_hsio_0: phy@3e10000 { 1371 compatible = "nvidia,tegra194-p2u"; 1372 reg = <0x0 0x03e10000 0x0 0x10000>; 1373 reg-names = "ctl"; 1374 1375 #phy-cells = <0>; 1376 }; 1377 1378 p2u_hsio_1: phy@3e20000 { 1379 compatible = "nvidia,tegra194-p2u"; 1380 reg = <0x0 0x03e20000 0x0 0x10000>; 1381 reg-names = "ctl"; 1382 1383 #phy-cells = <0>; 1384 }; 1385 1386 p2u_hsio_2: phy@3e30000 { 1387 compatible = "nvidia,tegra194-p2u"; 1388 reg = <0x0 0x03e30000 0x0 0x10000>; 1389 reg-names = "ctl"; 1390 1391 #phy-cells = <0>; 1392 }; 1393 1394 p2u_hsio_3: phy@3e40000 { 1395 compatible = "nvidia,tegra194-p2u"; 1396 reg = <0x0 0x03e40000 0x0 0x10000>; 1397 reg-names = "ctl"; 1398 1399 #phy-cells = <0>; 1400 }; 1401 1402 p2u_hsio_4: phy@3e50000 { 1403 compatible = "nvidia,tegra194-p2u"; 1404 reg = <0x0 0x03e50000 0x0 0x10000>; 1405 reg-names = "ctl"; 1406 1407 #phy-cells = <0>; 1408 }; 1409 1410 p2u_hsio_5: phy@3e60000 { 1411 compatible = "nvidia,tegra194-p2u"; 1412 reg = <0x0 0x03e60000 0x0 0x10000>; 1413 reg-names = "ctl"; 1414 1415 #phy-cells = <0>; 1416 }; 1417 1418 p2u_hsio_6: phy@3e70000 { 1419 compatible = "nvidia,tegra194-p2u"; 1420 reg = <0x0 0x03e70000 0x0 0x10000>; 1421 reg-names = "ctl"; 1422 1423 #phy-cells = <0>; 1424 }; 1425 1426 p2u_hsio_7: phy@3e80000 { 1427 compatible = "nvidia,tegra194-p2u"; 1428 reg = <0x0 0x03e80000 0x0 0x10000>; 1429 reg-names = "ctl"; 1430 1431 #phy-cells = <0>; 1432 }; 1433 1434 p2u_hsio_8: phy@3e90000 { 1435 compatible = "nvidia,tegra194-p2u"; 1436 reg = <0x0 0x03e90000 0x0 0x10000>; 1437 reg-names = "ctl"; 1438 1439 #phy-cells = <0>; 1440 }; 1441 1442 p2u_hsio_9: phy@3ea0000 { 1443 compatible = "nvidia,tegra194-p2u"; 1444 reg = <0x0 0x03ea0000 0x0 0x10000>; 1445 reg-names = "ctl"; 1446 1447 #phy-cells = <0>; 1448 }; 1449 1450 p2u_nvhs_0: phy@3eb0000 { 1451 compatible = "nvidia,tegra194-p2u"; 1452 reg = <0x0 0x03eb0000 0x0 0x10000>; 1453 reg-names = "ctl"; 1454 1455 #phy-cells = <0>; 1456 }; 1457 1458 p2u_nvhs_1: phy@3ec0000 { 1459 compatible = "nvidia,tegra194-p2u"; 1460 reg = <0x0 0x03ec0000 0x0 0x10000>; 1461 reg-names = "ctl"; 1462 1463 #phy-cells = <0>; 1464 }; 1465 1466 p2u_nvhs_2: phy@3ed0000 { 1467 compatible = "nvidia,tegra194-p2u"; 1468 reg = <0x0 0x03ed0000 0x0 0x10000>; 1469 reg-names = "ctl"; 1470 1471 #phy-cells = <0>; 1472 }; 1473 1474 p2u_nvhs_3: phy@3ee0000 { 1475 compatible = "nvidia,tegra194-p2u"; 1476 reg = <0x0 0x03ee0000 0x0 0x10000>; 1477 reg-names = "ctl"; 1478 1479 #phy-cells = <0>; 1480 }; 1481 1482 p2u_nvhs_4: phy@3ef0000 { 1483 compatible = "nvidia,tegra194-p2u"; 1484 reg = <0x0 0x03ef0000 0x0 0x10000>; 1485 reg-names = "ctl"; 1486 1487 #phy-cells = <0>; 1488 }; 1489 1490 p2u_nvhs_5: phy@3f00000 { 1491 compatible = "nvidia,tegra194-p2u"; 1492 reg = <0x0 0x03f00000 0x0 0x10000>; 1493 reg-names = "ctl"; 1494 1495 #phy-cells = <0>; 1496 }; 1497 1498 p2u_nvhs_6: phy@3f10000 { 1499 compatible = "nvidia,tegra194-p2u"; 1500 reg = <0x0 0x03f10000 0x0 0x10000>; 1501 reg-names = "ctl"; 1502 1503 #phy-cells = <0>; 1504 }; 1505 1506 p2u_nvhs_7: phy@3f20000 { 1507 compatible = "nvidia,tegra194-p2u"; 1508 reg = <0x0 0x03f20000 0x0 0x10000>; 1509 reg-names = "ctl"; 1510 1511 #phy-cells = <0>; 1512 }; 1513 1514 p2u_hsio_10: phy@3f30000 { 1515 compatible = "nvidia,tegra194-p2u"; 1516 reg = <0x0 0x03f30000 0x0 0x10000>; 1517 reg-names = "ctl"; 1518 1519 #phy-cells = <0>; 1520 }; 1521 1522 p2u_hsio_11: phy@3f40000 { 1523 compatible = "nvidia,tegra194-p2u"; 1524 reg = <0x0 0x03f40000 0x0 0x10000>; 1525 reg-names = "ctl"; 1526 1527 #phy-cells = <0>; 1528 }; 1529 1530 sce-noc@b600000 { 1531 compatible = "nvidia,tegra194-sce-noc"; 1532 reg = <0x0 0xb600000 0x0 0x1000>; 1533 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1535 nvidia,axi2apb = <&axi2apb>; 1536 nvidia,apbmisc = <&apbmisc>; 1537 status = "okay"; 1538 }; 1539 1540 rce-noc@be00000 { 1541 compatible = "nvidia,tegra194-rce-noc"; 1542 reg = <0x0 0xbe00000 0x0 0x1000>; 1543 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1545 nvidia,axi2apb = <&axi2apb>; 1546 nvidia,apbmisc = <&apbmisc>; 1547 status = "okay"; 1548 }; 1549 1550 hsp_aon: hsp@c150000 { 1551 compatible = "nvidia,tegra194-hsp"; 1552 reg = <0x0 0x0c150000 0x0 0x90000>; 1553 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1557 /* 1558 * Shared interrupt 0 is routed only to AON/SPE, so 1559 * we only have 4 shared interrupts for the CCPLEX. 1560 */ 1561 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1562 #mbox-cells = <2>; 1563 }; 1564 1565 hte_aon: hardware-timestamp@c1e0000 { 1566 compatible = "nvidia,tegra194-gte-aon"; 1567 reg = <0x0 0xc1e0000 0x0 0x10000>; 1568 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1569 nvidia,int-threshold = <1>; 1570 nvidia,slices = <3>; 1571 #timestamp-cells = <1>; 1572 status = "okay"; 1573 }; 1574 1575 gen2_i2c: i2c@c240000 { 1576 compatible = "nvidia,tegra194-i2c"; 1577 reg = <0x0 0x0c240000 0x0 0x10000>; 1578 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1582 clock-names = "div-clk"; 1583 resets = <&bpmp TEGRA194_RESET_I2C2>; 1584 reset-names = "i2c"; 1585 dmas = <&gpcdma 22>, <&gpcdma 22>; 1586 dma-names = "rx", "tx"; 1587 status = "disabled"; 1588 }; 1589 1590 gen8_i2c: i2c@c250000 { 1591 compatible = "nvidia,tegra194-i2c"; 1592 reg = <0x0 0x0c250000 0x0 0x10000>; 1593 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1597 clock-names = "div-clk"; 1598 resets = <&bpmp TEGRA194_RESET_I2C8>; 1599 reset-names = "i2c"; 1600 dmas = <&gpcdma 0>, <&gpcdma 0>; 1601 dma-names = "rx", "tx"; 1602 status = "disabled"; 1603 }; 1604 1605 uartc: serial@c280000 { 1606 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1607 reg = <0x0 0x0c280000 0x0 0x40>; 1608 reg-shift = <2>; 1609 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1610 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1611 resets = <&bpmp TEGRA194_RESET_UARTC>; 1612 status = "disabled"; 1613 }; 1614 1615 uartg: serial@c290000 { 1616 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1617 reg = <0x0 0x0c290000 0x0 0x40>; 1618 reg-shift = <2>; 1619 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1620 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1621 resets = <&bpmp TEGRA194_RESET_UARTG>; 1622 status = "disabled"; 1623 }; 1624 1625 rtc: rtc@c2a0000 { 1626 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1627 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1628 interrupt-parent = <&pmc>; 1629 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1630 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1631 clock-names = "rtc"; 1632 status = "disabled"; 1633 }; 1634 1635 gpio_aon: gpio@c2f0000 { 1636 compatible = "nvidia,tegra194-gpio-aon"; 1637 reg-names = "security", "gpio"; 1638 reg = <0x0 0xc2f0000 0x0 0x1000>, 1639 <0x0 0xc2f1000 0x0 0x1000>; 1640 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1644 gpio-controller; 1645 #gpio-cells = <2>; 1646 interrupt-controller; 1647 #interrupt-cells = <2>; 1648 gpio-ranges = <&pinmux_aon 0 0 30>; 1649 }; 1650 1651 pinmux_aon: pinmux@c300000 { 1652 compatible = "nvidia,tegra194-pinmux-aon"; 1653 reg = <0x0 0xc300000 0x0 0x4000>; 1654 1655 status = "okay"; 1656 }; 1657 1658 pwm4: pwm@c340000 { 1659 compatible = "nvidia,tegra194-pwm", 1660 "nvidia,tegra186-pwm"; 1661 reg = <0x0 0xc340000 0x0 0x10000>; 1662 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1663 resets = <&bpmp TEGRA194_RESET_PWM4>; 1664 reset-names = "pwm"; 1665 status = "disabled"; 1666 #pwm-cells = <2>; 1667 }; 1668 1669 pmc: pmc@c360000 { 1670 compatible = "nvidia,tegra194-pmc"; 1671 reg = <0x0 0x0c360000 0x0 0x10000>, 1672 <0x0 0x0c370000 0x0 0x10000>, 1673 <0x0 0x0c380000 0x0 0x10000>, 1674 <0x0 0x0c390000 0x0 0x10000>, 1675 <0x0 0x0c3a0000 0x0 0x10000>; 1676 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1677 1678 #interrupt-cells = <2>; 1679 interrupt-controller; 1680 1681 sdmmc1_1v8: sdmmc1-1v8 { 1682 pins = "sdmmc1-hv"; 1683 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1684 }; 1685 1686 sdmmc1_3v3: sdmmc1-3v3 { 1687 pins = "sdmmc1-hv"; 1688 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1689 }; 1690 1691 sdmmc3_1v8: sdmmc3-1v8 { 1692 pins = "sdmmc3-hv"; 1693 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1694 }; 1695 1696 sdmmc3_3v3: sdmmc3-3v3 { 1697 pins = "sdmmc3-hv"; 1698 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1699 }; 1700 }; 1701 1702 aon-noc@c600000 { 1703 compatible = "nvidia,tegra194-aon-noc"; 1704 reg = <0x0 0xc600000 0x0 0x1000>; 1705 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1707 nvidia,apbmisc = <&apbmisc>; 1708 status = "okay"; 1709 }; 1710 1711 bpmp-noc@d600000 { 1712 compatible = "nvidia,tegra194-bpmp-noc"; 1713 reg = <0x0 0xd600000 0x0 0x1000>; 1714 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1716 nvidia,axi2apb = <&axi2apb>; 1717 nvidia,apbmisc = <&apbmisc>; 1718 status = "okay"; 1719 }; 1720 1721 iommu@10000000 { 1722 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1723 reg = <0x0 0x10000000 0x0 0x800000>; 1724 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1789 stream-match-mask = <0x7f80>; 1790 #global-interrupts = <1>; 1791 #iommu-cells = <1>; 1792 1793 nvidia,memory-controller = <&mc>; 1794 status = "disabled"; 1795 }; 1796 1797 smmu: iommu@12000000 { 1798 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1799 reg = <0x0 0x12000000 0x0 0x800000>, 1800 <0x0 0x11000000 0x0 0x800000>; 1801 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1867 stream-match-mask = <0x7f80>; 1868 #global-interrupts = <2>; 1869 #iommu-cells = <1>; 1870 1871 nvidia,memory-controller = <&mc>; 1872 status = "okay"; 1873 }; 1874 1875 host1x@13e00000 { 1876 compatible = "nvidia,tegra194-host1x"; 1877 reg = <0x0 0x13e00000 0x0 0x10000>, 1878 <0x0 0x13e10000 0x0 0x10000>; 1879 reg-names = "hypervisor", "vm"; 1880 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1882 interrupt-names = "syncpt", "host1x"; 1883 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1884 clock-names = "host1x"; 1885 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1886 reset-names = "host1x"; 1887 1888 #address-cells = <2>; 1889 #size-cells = <2>; 1890 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1891 1892 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1893 interconnect-names = "dma-mem"; 1894 iommus = <&smmu TEGRA194_SID_HOST1X>; 1895 dma-coherent; 1896 1897 /* Context isolation domains */ 1898 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1899 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1900 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1901 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1902 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1903 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1904 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1905 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1906 1907 nvdec@15140000 { 1908 compatible = "nvidia,tegra194-nvdec"; 1909 reg = <0x0 0x15140000 0x0 0x00040000>; 1910 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1911 clock-names = "nvdec"; 1912 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1913 reset-names = "nvdec"; 1914 1915 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1916 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1917 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1918 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1919 interconnect-names = "dma-mem", "read-1", "write"; 1920 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1921 dma-coherent; 1922 1923 nvidia,host1x-class = <0xf5>; 1924 }; 1925 1926 display-hub@15200000 { 1927 compatible = "nvidia,tegra194-display"; 1928 reg = <0x0 0x15200000 0x0 0x00040000>; 1929 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1930 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1931 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1932 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1933 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1934 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1935 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1936 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1937 "wgrp3", "wgrp4", "wgrp5"; 1938 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1939 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1940 clock-names = "disp", "hub"; 1941 status = "disabled"; 1942 1943 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1944 1945 #address-cells = <2>; 1946 #size-cells = <2>; 1947 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1948 1949 display@15200000 { 1950 compatible = "nvidia,tegra194-dc"; 1951 reg = <0x0 0x15200000 0x0 0x10000>; 1952 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1953 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1954 clock-names = "dc"; 1955 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1956 reset-names = "dc"; 1957 1958 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1959 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1960 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1961 interconnect-names = "dma-mem", "read-1"; 1962 1963 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1964 nvidia,head = <0>; 1965 }; 1966 1967 display@15210000 { 1968 compatible = "nvidia,tegra194-dc"; 1969 reg = <0x0 0x15210000 0x0 0x10000>; 1970 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1971 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1972 clock-names = "dc"; 1973 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1974 reset-names = "dc"; 1975 1976 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1977 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1978 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1979 interconnect-names = "dma-mem", "read-1"; 1980 1981 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1982 nvidia,head = <1>; 1983 }; 1984 1985 display@15220000 { 1986 compatible = "nvidia,tegra194-dc"; 1987 reg = <0x0 0x15220000 0x0 0x10000>; 1988 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1989 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1990 clock-names = "dc"; 1991 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1992 reset-names = "dc"; 1993 1994 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1995 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1996 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1997 interconnect-names = "dma-mem", "read-1"; 1998 1999 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2000 nvidia,head = <2>; 2001 }; 2002 2003 display@15230000 { 2004 compatible = "nvidia,tegra194-dc"; 2005 reg = <0x0 0x15230000 0x0 0x10000>; 2006 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2007 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2008 clock-names = "dc"; 2009 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2010 reset-names = "dc"; 2011 2012 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2013 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2014 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2015 interconnect-names = "dma-mem", "read-1"; 2016 2017 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2018 nvidia,head = <3>; 2019 }; 2020 }; 2021 2022 vic@15340000 { 2023 compatible = "nvidia,tegra194-vic"; 2024 reg = <0x0 0x15340000 0x0 0x00040000>; 2025 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2026 clocks = <&bpmp TEGRA194_CLK_VIC>; 2027 clock-names = "vic"; 2028 resets = <&bpmp TEGRA194_RESET_VIC>; 2029 reset-names = "vic"; 2030 2031 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2032 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2033 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2034 interconnect-names = "dma-mem", "write"; 2035 iommus = <&smmu TEGRA194_SID_VIC>; 2036 dma-coherent; 2037 }; 2038 2039 nvjpg@15380000 { 2040 compatible = "nvidia,tegra194-nvjpg"; 2041 reg = <0x0 0x15380000 0x0 0x40000>; 2042 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2043 clock-names = "nvjpg"; 2044 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2045 reset-names = "nvjpg"; 2046 2047 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2048 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2049 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2050 interconnect-names = "dma-mem", "write"; 2051 iommus = <&smmu TEGRA194_SID_NVJPG>; 2052 dma-coherent; 2053 }; 2054 2055 nvdec@15480000 { 2056 compatible = "nvidia,tegra194-nvdec"; 2057 reg = <0x0 0x15480000 0x0 0x00040000>; 2058 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2059 clock-names = "nvdec"; 2060 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2061 reset-names = "nvdec"; 2062 2063 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2064 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2065 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2066 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2067 interconnect-names = "dma-mem", "read-1", "write"; 2068 iommus = <&smmu TEGRA194_SID_NVDEC>; 2069 dma-coherent; 2070 2071 nvidia,host1x-class = <0xf0>; 2072 }; 2073 2074 nvenc@154c0000 { 2075 compatible = "nvidia,tegra194-nvenc"; 2076 reg = <0x0 0x154c0000 0x0 0x40000>; 2077 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2078 clock-names = "nvenc"; 2079 resets = <&bpmp TEGRA194_RESET_NVENC>; 2080 reset-names = "nvenc"; 2081 2082 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2083 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2084 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2085 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2086 interconnect-names = "dma-mem", "read-1", "write"; 2087 iommus = <&smmu TEGRA194_SID_NVENC>; 2088 dma-coherent; 2089 2090 nvidia,host1x-class = <0x21>; 2091 }; 2092 2093 dpaux0: dpaux@155c0000 { 2094 compatible = "nvidia,tegra194-dpaux"; 2095 reg = <0x0 0x155c0000 0x0 0x10000>; 2096 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2097 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2098 <&bpmp TEGRA194_CLK_PLLDP>; 2099 clock-names = "dpaux", "parent"; 2100 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2101 reset-names = "dpaux"; 2102 status = "disabled"; 2103 2104 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2105 2106 state_dpaux0_aux: pinmux-aux { 2107 groups = "dpaux-io"; 2108 function = "aux"; 2109 }; 2110 2111 state_dpaux0_i2c: pinmux-i2c { 2112 groups = "dpaux-io"; 2113 function = "i2c"; 2114 }; 2115 2116 state_dpaux0_off: pinmux-off { 2117 groups = "dpaux-io"; 2118 function = "off"; 2119 }; 2120 2121 i2c-bus { 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 }; 2125 }; 2126 2127 dpaux1: dpaux@155d0000 { 2128 compatible = "nvidia,tegra194-dpaux"; 2129 reg = <0x0 0x155d0000 0x0 0x10000>; 2130 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2131 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2132 <&bpmp TEGRA194_CLK_PLLDP>; 2133 clock-names = "dpaux", "parent"; 2134 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2135 reset-names = "dpaux"; 2136 status = "disabled"; 2137 2138 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2139 2140 state_dpaux1_aux: pinmux-aux { 2141 groups = "dpaux-io"; 2142 function = "aux"; 2143 }; 2144 2145 state_dpaux1_i2c: pinmux-i2c { 2146 groups = "dpaux-io"; 2147 function = "i2c"; 2148 }; 2149 2150 state_dpaux1_off: pinmux-off { 2151 groups = "dpaux-io"; 2152 function = "off"; 2153 }; 2154 2155 i2c-bus { 2156 #address-cells = <1>; 2157 #size-cells = <0>; 2158 }; 2159 }; 2160 2161 dpaux2: dpaux@155e0000 { 2162 compatible = "nvidia,tegra194-dpaux"; 2163 reg = <0x0 0x155e0000 0x0 0x10000>; 2164 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2165 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2166 <&bpmp TEGRA194_CLK_PLLDP>; 2167 clock-names = "dpaux", "parent"; 2168 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2169 reset-names = "dpaux"; 2170 status = "disabled"; 2171 2172 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2173 2174 state_dpaux2_aux: pinmux-aux { 2175 groups = "dpaux-io"; 2176 function = "aux"; 2177 }; 2178 2179 state_dpaux2_i2c: pinmux-i2c { 2180 groups = "dpaux-io"; 2181 function = "i2c"; 2182 }; 2183 2184 state_dpaux2_off: pinmux-off { 2185 groups = "dpaux-io"; 2186 function = "off"; 2187 }; 2188 2189 i2c-bus { 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 }; 2193 }; 2194 2195 dpaux3: dpaux@155f0000 { 2196 compatible = "nvidia,tegra194-dpaux"; 2197 reg = <0x0 0x155f0000 0x0 0x10000>; 2198 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2199 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2200 <&bpmp TEGRA194_CLK_PLLDP>; 2201 clock-names = "dpaux", "parent"; 2202 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2203 reset-names = "dpaux"; 2204 status = "disabled"; 2205 2206 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2207 2208 state_dpaux3_aux: pinmux-aux { 2209 groups = "dpaux-io"; 2210 function = "aux"; 2211 }; 2212 2213 state_dpaux3_i2c: pinmux-i2c { 2214 groups = "dpaux-io"; 2215 function = "i2c"; 2216 }; 2217 2218 state_dpaux3_off: pinmux-off { 2219 groups = "dpaux-io"; 2220 function = "off"; 2221 }; 2222 2223 i2c-bus { 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 }; 2227 }; 2228 2229 nvenc@15a80000 { 2230 compatible = "nvidia,tegra194-nvenc"; 2231 reg = <0x0 0x15a80000 0x0 0x00040000>; 2232 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2233 clock-names = "nvenc"; 2234 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2235 reset-names = "nvenc"; 2236 2237 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2238 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2239 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2240 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2241 interconnect-names = "dma-mem", "read-1", "write"; 2242 iommus = <&smmu TEGRA194_SID_NVENC1>; 2243 dma-coherent; 2244 2245 nvidia,host1x-class = <0x22>; 2246 }; 2247 2248 sor0: sor@15b00000 { 2249 compatible = "nvidia,tegra194-sor"; 2250 reg = <0x0 0x15b00000 0x0 0x40000>; 2251 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2252 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2253 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2254 <&bpmp TEGRA194_CLK_PLLD>, 2255 <&bpmp TEGRA194_CLK_PLLDP>, 2256 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2257 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2258 clock-names = "sor", "out", "parent", "dp", "safe", 2259 "pad"; 2260 resets = <&bpmp TEGRA194_RESET_SOR0>; 2261 reset-names = "sor"; 2262 pinctrl-0 = <&state_dpaux0_aux>; 2263 pinctrl-1 = <&state_dpaux0_i2c>; 2264 pinctrl-2 = <&state_dpaux0_off>; 2265 pinctrl-names = "aux", "i2c", "off"; 2266 status = "disabled"; 2267 2268 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2269 nvidia,interface = <0>; 2270 }; 2271 2272 sor1: sor@15b40000 { 2273 compatible = "nvidia,tegra194-sor"; 2274 reg = <0x0 0x15b40000 0x0 0x40000>; 2275 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2276 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2277 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2278 <&bpmp TEGRA194_CLK_PLLD2>, 2279 <&bpmp TEGRA194_CLK_PLLDP>, 2280 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2281 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2282 clock-names = "sor", "out", "parent", "dp", "safe", 2283 "pad"; 2284 resets = <&bpmp TEGRA194_RESET_SOR1>; 2285 reset-names = "sor"; 2286 pinctrl-0 = <&state_dpaux1_aux>; 2287 pinctrl-1 = <&state_dpaux1_i2c>; 2288 pinctrl-2 = <&state_dpaux1_off>; 2289 pinctrl-names = "aux", "i2c", "off"; 2290 status = "disabled"; 2291 2292 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2293 nvidia,interface = <1>; 2294 }; 2295 2296 sor2: sor@15b80000 { 2297 compatible = "nvidia,tegra194-sor"; 2298 reg = <0x0 0x15b80000 0x0 0x40000>; 2299 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2300 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2301 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2302 <&bpmp TEGRA194_CLK_PLLD3>, 2303 <&bpmp TEGRA194_CLK_PLLDP>, 2304 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2305 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2306 clock-names = "sor", "out", "parent", "dp", "safe", 2307 "pad"; 2308 resets = <&bpmp TEGRA194_RESET_SOR2>; 2309 reset-names = "sor"; 2310 pinctrl-0 = <&state_dpaux2_aux>; 2311 pinctrl-1 = <&state_dpaux2_i2c>; 2312 pinctrl-2 = <&state_dpaux2_off>; 2313 pinctrl-names = "aux", "i2c", "off"; 2314 status = "disabled"; 2315 2316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2317 nvidia,interface = <2>; 2318 }; 2319 2320 sor3: sor@15bc0000 { 2321 compatible = "nvidia,tegra194-sor"; 2322 reg = <0x0 0x15bc0000 0x0 0x40000>; 2323 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2324 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2325 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2326 <&bpmp TEGRA194_CLK_PLLD4>, 2327 <&bpmp TEGRA194_CLK_PLLDP>, 2328 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2329 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2330 clock-names = "sor", "out", "parent", "dp", "safe", 2331 "pad"; 2332 resets = <&bpmp TEGRA194_RESET_SOR3>; 2333 reset-names = "sor"; 2334 pinctrl-0 = <&state_dpaux3_aux>; 2335 pinctrl-1 = <&state_dpaux3_i2c>; 2336 pinctrl-2 = <&state_dpaux3_off>; 2337 pinctrl-names = "aux", "i2c", "off"; 2338 status = "disabled"; 2339 2340 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2341 nvidia,interface = <3>; 2342 }; 2343 }; 2344 2345 pcie@14100000 { 2346 compatible = "nvidia,tegra194-pcie"; 2347 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2348 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2349 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2350 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2351 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2352 reg-names = "appl", "config", "atu_dma", "dbi"; 2353 2354 status = "disabled"; 2355 2356 #address-cells = <3>; 2357 #size-cells = <2>; 2358 device_type = "pci"; 2359 num-lanes = <1>; 2360 linux,pci-domain = <1>; 2361 2362 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2363 clock-names = "core"; 2364 2365 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2366 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2367 reset-names = "apb", "core"; 2368 2369 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2370 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2371 interrupt-names = "intr", "msi"; 2372 2373 #interrupt-cells = <1>; 2374 interrupt-map-mask = <0 0 0 0>; 2375 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2376 2377 nvidia,bpmp = <&bpmp 1>; 2378 2379 nvidia,aspm-cmrt-us = <60>; 2380 nvidia,aspm-pwr-on-t-us = <20>; 2381 nvidia,aspm-l0s-entrance-latency-us = <3>; 2382 2383 bus-range = <0x0 0xff>; 2384 2385 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2386 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2387 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2388 2389 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2390 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2391 interconnect-names = "dma-mem", "write"; 2392 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2393 iommu-map-mask = <0x0>; 2394 dma-coherent; 2395 }; 2396 2397 pcie@14120000 { 2398 compatible = "nvidia,tegra194-pcie"; 2399 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2400 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2401 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2402 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2403 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2404 reg-names = "appl", "config", "atu_dma", "dbi"; 2405 2406 status = "disabled"; 2407 2408 #address-cells = <3>; 2409 #size-cells = <2>; 2410 device_type = "pci"; 2411 num-lanes = <1>; 2412 linux,pci-domain = <2>; 2413 2414 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2415 clock-names = "core"; 2416 2417 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2418 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2419 reset-names = "apb", "core"; 2420 2421 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2422 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2423 interrupt-names = "intr", "msi"; 2424 2425 #interrupt-cells = <1>; 2426 interrupt-map-mask = <0 0 0 0>; 2427 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2428 2429 nvidia,bpmp = <&bpmp 2>; 2430 2431 nvidia,aspm-cmrt-us = <60>; 2432 nvidia,aspm-pwr-on-t-us = <20>; 2433 nvidia,aspm-l0s-entrance-latency-us = <3>; 2434 2435 bus-range = <0x0 0xff>; 2436 2437 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2438 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2439 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2440 2441 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2442 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2443 interconnect-names = "dma-mem", "write"; 2444 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2445 iommu-map-mask = <0x0>; 2446 dma-coherent; 2447 }; 2448 2449 pcie@14140000 { 2450 compatible = "nvidia,tegra194-pcie"; 2451 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2452 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2453 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2454 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2455 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2456 reg-names = "appl", "config", "atu_dma", "dbi"; 2457 2458 status = "disabled"; 2459 2460 #address-cells = <3>; 2461 #size-cells = <2>; 2462 device_type = "pci"; 2463 num-lanes = <1>; 2464 linux,pci-domain = <3>; 2465 2466 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2467 clock-names = "core"; 2468 2469 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2470 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2471 reset-names = "apb", "core"; 2472 2473 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2474 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2475 interrupt-names = "intr", "msi"; 2476 2477 #interrupt-cells = <1>; 2478 interrupt-map-mask = <0 0 0 0>; 2479 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2480 2481 nvidia,bpmp = <&bpmp 3>; 2482 2483 nvidia,aspm-cmrt-us = <60>; 2484 nvidia,aspm-pwr-on-t-us = <20>; 2485 nvidia,aspm-l0s-entrance-latency-us = <3>; 2486 2487 bus-range = <0x0 0xff>; 2488 2489 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2490 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2491 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2492 2493 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2494 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2495 interconnect-names = "dma-mem", "write"; 2496 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2497 iommu-map-mask = <0x0>; 2498 dma-coherent; 2499 }; 2500 2501 pcie@14160000 { 2502 compatible = "nvidia,tegra194-pcie"; 2503 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2504 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2505 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2506 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2507 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2508 reg-names = "appl", "config", "atu_dma", "dbi"; 2509 2510 status = "disabled"; 2511 2512 #address-cells = <3>; 2513 #size-cells = <2>; 2514 device_type = "pci"; 2515 num-lanes = <4>; 2516 linux,pci-domain = <4>; 2517 2518 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2519 clock-names = "core"; 2520 2521 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2522 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2523 reset-names = "apb", "core"; 2524 2525 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2526 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2527 interrupt-names = "intr", "msi"; 2528 2529 #interrupt-cells = <1>; 2530 interrupt-map-mask = <0 0 0 0>; 2531 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2532 2533 nvidia,bpmp = <&bpmp 4>; 2534 2535 nvidia,aspm-cmrt-us = <60>; 2536 nvidia,aspm-pwr-on-t-us = <20>; 2537 nvidia,aspm-l0s-entrance-latency-us = <3>; 2538 2539 bus-range = <0x0 0xff>; 2540 2541 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2542 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2543 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2544 2545 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2546 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2547 interconnect-names = "dma-mem", "write"; 2548 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2549 iommu-map-mask = <0x0>; 2550 dma-coherent; 2551 }; 2552 2553 pcie-ep@14160000 { 2554 compatible = "nvidia,tegra194-pcie-ep"; 2555 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2556 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2557 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2558 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2559 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2560 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2561 2562 status = "disabled"; 2563 2564 num-lanes = <4>; 2565 num-ib-windows = <2>; 2566 num-ob-windows = <8>; 2567 2568 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2569 clock-names = "core"; 2570 2571 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2572 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2573 reset-names = "apb", "core"; 2574 2575 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2576 interrupt-names = "intr"; 2577 2578 nvidia,bpmp = <&bpmp 4>; 2579 2580 nvidia,aspm-cmrt-us = <60>; 2581 nvidia,aspm-pwr-on-t-us = <20>; 2582 nvidia,aspm-l0s-entrance-latency-us = <3>; 2583 2584 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2585 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2586 interconnect-names = "dma-mem", "write"; 2587 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2588 iommu-map-mask = <0x0>; 2589 dma-coherent; 2590 }; 2591 2592 pcie@14180000 { 2593 compatible = "nvidia,tegra194-pcie"; 2594 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2595 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2596 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2597 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2598 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2599 reg-names = "appl", "config", "atu_dma", "dbi"; 2600 2601 status = "disabled"; 2602 2603 #address-cells = <3>; 2604 #size-cells = <2>; 2605 device_type = "pci"; 2606 num-lanes = <8>; 2607 linux,pci-domain = <0>; 2608 2609 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2610 clock-names = "core"; 2611 2612 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2613 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2614 reset-names = "apb", "core"; 2615 2616 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2617 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2618 interrupt-names = "intr", "msi"; 2619 2620 #interrupt-cells = <1>; 2621 interrupt-map-mask = <0 0 0 0>; 2622 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2623 2624 nvidia,bpmp = <&bpmp 0>; 2625 2626 nvidia,aspm-cmrt-us = <60>; 2627 nvidia,aspm-pwr-on-t-us = <20>; 2628 nvidia,aspm-l0s-entrance-latency-us = <3>; 2629 2630 bus-range = <0x0 0xff>; 2631 2632 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2633 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2634 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2635 2636 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2637 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2638 interconnect-names = "dma-mem", "write"; 2639 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2640 iommu-map-mask = <0x0>; 2641 dma-coherent; 2642 }; 2643 2644 pcie-ep@14180000 { 2645 compatible = "nvidia,tegra194-pcie-ep"; 2646 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2647 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2648 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2649 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2650 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2651 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2652 2653 status = "disabled"; 2654 2655 num-lanes = <8>; 2656 num-ib-windows = <2>; 2657 num-ob-windows = <8>; 2658 2659 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2660 clock-names = "core"; 2661 2662 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2663 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2664 reset-names = "apb", "core"; 2665 2666 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2667 interrupt-names = "intr"; 2668 2669 nvidia,bpmp = <&bpmp 0>; 2670 2671 nvidia,aspm-cmrt-us = <60>; 2672 nvidia,aspm-pwr-on-t-us = <20>; 2673 nvidia,aspm-l0s-entrance-latency-us = <3>; 2674 2675 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2676 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2677 interconnect-names = "dma-mem", "write"; 2678 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2679 iommu-map-mask = <0x0>; 2680 dma-coherent; 2681 }; 2682 2683 pcie@141a0000 { 2684 compatible = "nvidia,tegra194-pcie"; 2685 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2686 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2687 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2688 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2689 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2690 reg-names = "appl", "config", "atu_dma", "dbi"; 2691 2692 status = "disabled"; 2693 2694 #address-cells = <3>; 2695 #size-cells = <2>; 2696 device_type = "pci"; 2697 num-lanes = <8>; 2698 linux,pci-domain = <5>; 2699 2700 pinctrl-names = "default"; 2701 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2702 2703 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2704 clock-names = "core"; 2705 2706 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2707 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2708 reset-names = "apb", "core"; 2709 2710 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2711 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2712 interrupt-names = "intr", "msi"; 2713 2714 nvidia,bpmp = <&bpmp 5>; 2715 2716 #interrupt-cells = <1>; 2717 interrupt-map-mask = <0 0 0 0>; 2718 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2719 2720 nvidia,aspm-cmrt-us = <60>; 2721 nvidia,aspm-pwr-on-t-us = <20>; 2722 nvidia,aspm-l0s-entrance-latency-us = <3>; 2723 2724 bus-range = <0x0 0xff>; 2725 2726 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2727 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2728 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2729 2730 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2731 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2732 interconnect-names = "dma-mem", "write"; 2733 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2734 iommu-map-mask = <0x0>; 2735 dma-coherent; 2736 }; 2737 2738 pcie-ep@141a0000 { 2739 compatible = "nvidia,tegra194-pcie-ep"; 2740 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2741 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2742 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2743 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2744 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2745 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2746 2747 status = "disabled"; 2748 2749 num-lanes = <8>; 2750 num-ib-windows = <2>; 2751 num-ob-windows = <8>; 2752 2753 pinctrl-names = "default"; 2754 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2755 2756 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2757 clock-names = "core"; 2758 2759 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2760 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2761 reset-names = "apb", "core"; 2762 2763 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2764 interrupt-names = "intr"; 2765 2766 nvidia,bpmp = <&bpmp 5>; 2767 2768 nvidia,aspm-cmrt-us = <60>; 2769 nvidia,aspm-pwr-on-t-us = <20>; 2770 nvidia,aspm-l0s-entrance-latency-us = <3>; 2771 2772 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2773 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2774 interconnect-names = "dma-mem", "write"; 2775 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2776 iommu-map-mask = <0x0>; 2777 dma-coherent; 2778 }; 2779 2780 gpu@17000000 { 2781 compatible = "nvidia,gv11b"; 2782 reg = <0x0 0x17000000 0x0 0x1000000>, 2783 <0x0 0x18000000 0x0 0x1000000>; 2784 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2786 interrupt-names = "stall", "nonstall"; 2787 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2788 <&bpmp TEGRA194_CLK_GPU_PWR>, 2789 <&bpmp TEGRA194_CLK_FUSE>; 2790 clock-names = "gpu", "pwr", "fuse"; 2791 resets = <&bpmp TEGRA194_RESET_GPU>; 2792 reset-names = "gpu"; 2793 dma-coherent; 2794 2795 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2796 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2797 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2798 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2799 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2800 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2801 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2802 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2803 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2804 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2805 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2806 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2807 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2808 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2809 "read-1", "read-1-hp", "write-1", 2810 "read-2", "read-2-hp", "write-2", 2811 "read-3", "read-3-hp", "write-3"; 2812 }; 2813 }; 2814 2815 sram@40000000 { 2816 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2817 reg = <0x0 0x40000000 0x0 0x50000>; 2818 2819 #address-cells = <1>; 2820 #size-cells = <1>; 2821 ranges = <0x0 0x0 0x40000000 0x50000>; 2822 2823 no-memory-wc; 2824 2825 cpu_bpmp_tx: sram@4e000 { 2826 reg = <0x4e000 0x1000>; 2827 label = "cpu-bpmp-tx"; 2828 pool; 2829 }; 2830 2831 cpu_bpmp_rx: sram@4f000 { 2832 reg = <0x4f000 0x1000>; 2833 label = "cpu-bpmp-rx"; 2834 pool; 2835 }; 2836 }; 2837 2838 bpmp: bpmp { 2839 compatible = "nvidia,tegra186-bpmp"; 2840 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2841 TEGRA_HSP_DB_MASTER_BPMP>; 2842 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2843 #clock-cells = <1>; 2844 #reset-cells = <1>; 2845 #power-domain-cells = <1>; 2846 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2847 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2848 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2849 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2850 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2851 iommus = <&smmu TEGRA194_SID_BPMP>; 2852 2853 bpmp_i2c: i2c { 2854 compatible = "nvidia,tegra186-bpmp-i2c"; 2855 nvidia,bpmp-bus-id = <5>; 2856 #address-cells = <1>; 2857 #size-cells = <0>; 2858 }; 2859 2860 bpmp_thermal: thermal { 2861 compatible = "nvidia,tegra186-bpmp-thermal"; 2862 #thermal-sensor-cells = <1>; 2863 }; 2864 }; 2865 2866 cpus { 2867 compatible = "nvidia,tegra194-ccplex"; 2868 nvidia,bpmp = <&bpmp>; 2869 #address-cells = <1>; 2870 #size-cells = <0>; 2871 2872 cpu0_0: cpu@0 { 2873 compatible = "nvidia,tegra194-carmel"; 2874 device_type = "cpu"; 2875 reg = <0x000>; 2876 enable-method = "psci"; 2877 i-cache-size = <131072>; 2878 i-cache-line-size = <64>; 2879 i-cache-sets = <512>; 2880 d-cache-size = <65536>; 2881 d-cache-line-size = <64>; 2882 d-cache-sets = <256>; 2883 next-level-cache = <&l2c_0>; 2884 }; 2885 2886 cpu0_1: cpu@1 { 2887 compatible = "nvidia,tegra194-carmel"; 2888 device_type = "cpu"; 2889 reg = <0x001>; 2890 enable-method = "psci"; 2891 i-cache-size = <131072>; 2892 i-cache-line-size = <64>; 2893 i-cache-sets = <512>; 2894 d-cache-size = <65536>; 2895 d-cache-line-size = <64>; 2896 d-cache-sets = <256>; 2897 next-level-cache = <&l2c_0>; 2898 }; 2899 2900 cpu1_0: cpu@100 { 2901 compatible = "nvidia,tegra194-carmel"; 2902 device_type = "cpu"; 2903 reg = <0x100>; 2904 enable-method = "psci"; 2905 i-cache-size = <131072>; 2906 i-cache-line-size = <64>; 2907 i-cache-sets = <512>; 2908 d-cache-size = <65536>; 2909 d-cache-line-size = <64>; 2910 d-cache-sets = <256>; 2911 next-level-cache = <&l2c_1>; 2912 }; 2913 2914 cpu1_1: cpu@101 { 2915 compatible = "nvidia,tegra194-carmel"; 2916 device_type = "cpu"; 2917 reg = <0x101>; 2918 enable-method = "psci"; 2919 i-cache-size = <131072>; 2920 i-cache-line-size = <64>; 2921 i-cache-sets = <512>; 2922 d-cache-size = <65536>; 2923 d-cache-line-size = <64>; 2924 d-cache-sets = <256>; 2925 next-level-cache = <&l2c_1>; 2926 }; 2927 2928 cpu2_0: cpu@200 { 2929 compatible = "nvidia,tegra194-carmel"; 2930 device_type = "cpu"; 2931 reg = <0x200>; 2932 enable-method = "psci"; 2933 i-cache-size = <131072>; 2934 i-cache-line-size = <64>; 2935 i-cache-sets = <512>; 2936 d-cache-size = <65536>; 2937 d-cache-line-size = <64>; 2938 d-cache-sets = <256>; 2939 next-level-cache = <&l2c_2>; 2940 }; 2941 2942 cpu2_1: cpu@201 { 2943 compatible = "nvidia,tegra194-carmel"; 2944 device_type = "cpu"; 2945 reg = <0x201>; 2946 enable-method = "psci"; 2947 i-cache-size = <131072>; 2948 i-cache-line-size = <64>; 2949 i-cache-sets = <512>; 2950 d-cache-size = <65536>; 2951 d-cache-line-size = <64>; 2952 d-cache-sets = <256>; 2953 next-level-cache = <&l2c_2>; 2954 }; 2955 2956 cpu3_0: cpu@300 { 2957 compatible = "nvidia,tegra194-carmel"; 2958 device_type = "cpu"; 2959 reg = <0x300>; 2960 enable-method = "psci"; 2961 i-cache-size = <131072>; 2962 i-cache-line-size = <64>; 2963 i-cache-sets = <512>; 2964 d-cache-size = <65536>; 2965 d-cache-line-size = <64>; 2966 d-cache-sets = <256>; 2967 next-level-cache = <&l2c_3>; 2968 }; 2969 2970 cpu3_1: cpu@301 { 2971 compatible = "nvidia,tegra194-carmel"; 2972 device_type = "cpu"; 2973 reg = <0x301>; 2974 enable-method = "psci"; 2975 i-cache-size = <131072>; 2976 i-cache-line-size = <64>; 2977 i-cache-sets = <512>; 2978 d-cache-size = <65536>; 2979 d-cache-line-size = <64>; 2980 d-cache-sets = <256>; 2981 next-level-cache = <&l2c_3>; 2982 }; 2983 2984 cpu-map { 2985 cluster0 { 2986 core0 { 2987 cpu = <&cpu0_0>; 2988 }; 2989 2990 core1 { 2991 cpu = <&cpu0_1>; 2992 }; 2993 }; 2994 2995 cluster1 { 2996 core0 { 2997 cpu = <&cpu1_0>; 2998 }; 2999 3000 core1 { 3001 cpu = <&cpu1_1>; 3002 }; 3003 }; 3004 3005 cluster2 { 3006 core0 { 3007 cpu = <&cpu2_0>; 3008 }; 3009 3010 core1 { 3011 cpu = <&cpu2_1>; 3012 }; 3013 }; 3014 3015 cluster3 { 3016 core0 { 3017 cpu = <&cpu3_0>; 3018 }; 3019 3020 core1 { 3021 cpu = <&cpu3_1>; 3022 }; 3023 }; 3024 }; 3025 3026 l2c_0: l2-cache0 { 3027 compatible = "cache"; 3028 cache-unified; 3029 cache-size = <2097152>; 3030 cache-line-size = <64>; 3031 cache-sets = <2048>; 3032 cache-level = <2>; 3033 next-level-cache = <&l3c>; 3034 }; 3035 3036 l2c_1: l2-cache1 { 3037 compatible = "cache"; 3038 cache-unified; 3039 cache-size = <2097152>; 3040 cache-line-size = <64>; 3041 cache-sets = <2048>; 3042 cache-level = <2>; 3043 next-level-cache = <&l3c>; 3044 }; 3045 3046 l2c_2: l2-cache2 { 3047 compatible = "cache"; 3048 cache-unified; 3049 cache-size = <2097152>; 3050 cache-line-size = <64>; 3051 cache-sets = <2048>; 3052 cache-level = <2>; 3053 next-level-cache = <&l3c>; 3054 }; 3055 3056 l2c_3: l2-cache3 { 3057 compatible = "cache"; 3058 cache-unified; 3059 cache-size = <2097152>; 3060 cache-line-size = <64>; 3061 cache-sets = <2048>; 3062 cache-level = <2>; 3063 next-level-cache = <&l3c>; 3064 }; 3065 3066 l3c: l3-cache { 3067 compatible = "cache"; 3068 cache-unified; 3069 cache-size = <4194304>; 3070 cache-line-size = <64>; 3071 cache-level = <3>; 3072 cache-sets = <4096>; 3073 }; 3074 }; 3075 3076 pmu { 3077 compatible = "nvidia,carmel-pmu"; 3078 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3086 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3087 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3088 }; 3089 3090 psci { 3091 compatible = "arm,psci-1.0"; 3092 status = "okay"; 3093 method = "smc"; 3094 }; 3095 3096 tcu: serial { 3097 compatible = "nvidia,tegra194-tcu"; 3098 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3099 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3100 mbox-names = "rx", "tx"; 3101 }; 3102 3103 sound { 3104 status = "disabled"; 3105 3106 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3107 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3108 clock-names = "pll_a", "plla_out0"; 3109 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3110 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3111 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3112 assigned-clock-parents = <0>, 3113 <&bpmp TEGRA194_CLK_PLLA>, 3114 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3115 /* 3116 * PLLA supports dynamic ramp. Below initial rate is chosen 3117 * for this to work and oscillate between base rates required 3118 * for 8x and 11.025x sample rate streams. 3119 */ 3120 assigned-clock-rates = <258000000>; 3121 }; 3122 3123 thermal-zones { 3124 cpu-thermal { 3125 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3126 status = "disabled"; 3127 }; 3128 3129 gpu-thermal { 3130 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3131 status = "disabled"; 3132 }; 3133 3134 aux-thermal { 3135 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3136 status = "disabled"; 3137 }; 3138 3139 pllx-thermal { 3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3141 status = "disabled"; 3142 }; 3143 3144 ao-thermal { 3145 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3146 status = "disabled"; 3147 }; 3148 3149 tj-thermal { 3150 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3151 status = "disabled"; 3152 }; 3153 }; 3154 3155 timer { 3156 compatible = "arm,armv8-timer"; 3157 interrupts = <GIC_PPI 13 3158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3159 <GIC_PPI 14 3160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3161 <GIC_PPI 11 3162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3163 <GIC_PPI 10 3164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3165 interrupt-parent = <&gic>; 3166 always-on; 3167 }; 3168}; 3169