1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,icc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/power/qcom,rpmhpd.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 clocks { 25 xo_board_clk: xo-board-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 qcom,freq-domain = <&cpufreq_hw 0>; 46 next-level-cache = <&L2_0>; 47 capacity-dmips-mhz = <1024>; 48 dynamic-power-coefficient = <100>; 49 L2_0: l2-cache { 50 compatible = "cache"; 51 cache-level = <2>; 52 cache-unified; 53 next-level-cache = <&L3_0>; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 cache-level = <3>; 57 cache-unified; 58 }; 59 }; 60 }; 61 62 CPU1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 qcom,freq-domain = <&cpufreq_hw 0>; 68 next-level-cache = <&L2_1>; 69 capacity-dmips-mhz = <1024>; 70 dynamic-power-coefficient = <100>; 71 L2_1: l2-cache { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 next-level-cache = <&L3_0>; 76 }; 77 }; 78 79 CPU2: cpu@200 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo"; 82 reg = <0x0 0x200>; 83 enable-method = "psci"; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 next-level-cache = <&L2_2>; 86 capacity-dmips-mhz = <1024>; 87 dynamic-power-coefficient = <100>; 88 L2_2: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU3: cpu@300 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo"; 99 reg = <0x0 0x300>; 100 enable-method = "psci"; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 next-level-cache = <&L2_3>; 103 capacity-dmips-mhz = <1024>; 104 dynamic-power-coefficient = <100>; 105 L2_3: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 next-level-cache = <&L3_0>; 110 }; 111 }; 112 113 CPU4: cpu@10000 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo"; 116 reg = <0x0 0x10000>; 117 enable-method = "psci"; 118 qcom,freq-domain = <&cpufreq_hw 1>; 119 next-level-cache = <&L2_4>; 120 capacity-dmips-mhz = <1024>; 121 dynamic-power-coefficient = <100>; 122 L2_4: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_1>; 127 L3_1: l3-cache { 128 compatible = "cache"; 129 cache-level = <3>; 130 cache-unified; 131 }; 132 133 }; 134 }; 135 136 CPU5: cpu@10100 { 137 device_type = "cpu"; 138 compatible = "qcom,kryo"; 139 reg = <0x0 0x10100>; 140 enable-method = "psci"; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 next-level-cache = <&L2_5>; 143 capacity-dmips-mhz = <1024>; 144 dynamic-power-coefficient = <100>; 145 L2_5: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_1>; 150 }; 151 }; 152 153 CPU6: cpu@10200 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo"; 156 reg = <0x0 0x10200>; 157 enable-method = "psci"; 158 qcom,freq-domain = <&cpufreq_hw 1>; 159 next-level-cache = <&L2_6>; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <100>; 162 L2_6: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_1>; 167 }; 168 }; 169 170 CPU7: cpu@10300 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo"; 173 reg = <0x0 0x10300>; 174 enable-method = "psci"; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 next-level-cache = <&L2_7>; 177 capacity-dmips-mhz = <1024>; 178 dynamic-power-coefficient = <100>; 179 L2_7: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 next-level-cache = <&L3_1>; 184 }; 185 }; 186 187 cpu-map { 188 cluster0 { 189 core0 { 190 cpu = <&CPU0>; 191 }; 192 193 core1 { 194 cpu = <&CPU1>; 195 }; 196 197 core2 { 198 cpu = <&CPU2>; 199 }; 200 201 core3 { 202 cpu = <&CPU3>; 203 }; 204 }; 205 206 cluster1 { 207 core0 { 208 cpu = <&CPU4>; 209 }; 210 211 core1 { 212 cpu = <&CPU5>; 213 }; 214 215 core2 { 216 cpu = <&CPU6>; 217 }; 218 219 core3 { 220 cpu = <&CPU7>; 221 }; 222 }; 223 }; 224 225 idle-states { 226 entry-method = "psci"; 227 228 GOLD_CPU_SLEEP_0: cpu-sleep-0 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "gold-power-collapse"; 231 arm,psci-suspend-param = <0x40000003>; 232 entry-latency-us = <549>; 233 exit-latency-us = <901>; 234 min-residency-us = <1774>; 235 local-timer-stop; 236 }; 237 238 GOLD_RAIL_CPU_SLEEP_0: cpu-sleep-1 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "gold-rail-power-collapse"; 241 arm,psci-suspend-param = <0x40000004>; 242 entry-latency-us = <702>; 243 exit-latency-us = <1061>; 244 min-residency-us = <4488>; 245 local-timer-stop; 246 }; 247 }; 248 249 domain-idle-states { 250 CLUSTER_SLEEP_GOLD: cluster-sleep-0 { 251 compatible = "domain-idle-state"; 252 arm,psci-suspend-param = <0x41000044>; 253 entry-latency-us = <2752>; 254 exit-latency-us = <3048>; 255 min-residency-us = <6118>; 256 }; 257 258 CLUSTER_SLEEP_APSS_RSC_PC: cluster-sleep-1 { 259 compatible = "domain-idle-state"; 260 arm,psci-suspend-param = <0x42000144>; 261 entry-latency-us = <3263>; 262 exit-latency-us = <6562>; 263 min-residency-us = <9987>; 264 }; 265 }; 266 }; 267 268 dummy-sink { 269 compatible = "arm,coresight-dummy-sink"; 270 271 in-ports { 272 port { 273 eud_in: endpoint { 274 remote-endpoint = 275 <&swao_rep_out1>; 276 }; 277 }; 278 }; 279 }; 280 281 firmware { 282 scm { 283 compatible = "qcom,scm-sa8775p", "qcom,scm"; 284 memory-region = <&tz_ffi_mem>; 285 }; 286 }; 287 288 aggre1_noc: interconnect-aggre1-noc { 289 compatible = "qcom,sa8775p-aggre1-noc"; 290 #interconnect-cells = <2>; 291 qcom,bcm-voters = <&apps_bcm_voter>; 292 }; 293 294 aggre2_noc: interconnect-aggre2-noc { 295 compatible = "qcom,sa8775p-aggre2-noc"; 296 #interconnect-cells = <2>; 297 qcom,bcm-voters = <&apps_bcm_voter>; 298 }; 299 300 clk_virt: interconnect-clk-virt { 301 compatible = "qcom,sa8775p-clk-virt"; 302 #interconnect-cells = <2>; 303 qcom,bcm-voters = <&apps_bcm_voter>; 304 }; 305 306 config_noc: interconnect-config-noc { 307 compatible = "qcom,sa8775p-config-noc"; 308 #interconnect-cells = <2>; 309 qcom,bcm-voters = <&apps_bcm_voter>; 310 }; 311 312 dc_noc: interconnect-dc-noc { 313 compatible = "qcom,sa8775p-dc-noc"; 314 #interconnect-cells = <2>; 315 qcom,bcm-voters = <&apps_bcm_voter>; 316 }; 317 318 gem_noc: interconnect-gem-noc { 319 compatible = "qcom,sa8775p-gem-noc"; 320 #interconnect-cells = <2>; 321 qcom,bcm-voters = <&apps_bcm_voter>; 322 }; 323 324 gpdsp_anoc: interconnect-gpdsp-anoc { 325 compatible = "qcom,sa8775p-gpdsp-anoc"; 326 #interconnect-cells = <2>; 327 qcom,bcm-voters = <&apps_bcm_voter>; 328 }; 329 330 lpass_ag_noc: interconnect-lpass-ag-noc { 331 compatible = "qcom,sa8775p-lpass-ag-noc"; 332 #interconnect-cells = <2>; 333 qcom,bcm-voters = <&apps_bcm_voter>; 334 }; 335 336 mc_virt: interconnect-mc-virt { 337 compatible = "qcom,sa8775p-mc-virt"; 338 #interconnect-cells = <2>; 339 qcom,bcm-voters = <&apps_bcm_voter>; 340 }; 341 342 mmss_noc: interconnect-mmss-noc { 343 compatible = "qcom,sa8775p-mmss-noc"; 344 #interconnect-cells = <2>; 345 qcom,bcm-voters = <&apps_bcm_voter>; 346 }; 347 348 nspa_noc: interconnect-nspa-noc { 349 compatible = "qcom,sa8775p-nspa-noc"; 350 #interconnect-cells = <2>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 nspb_noc: interconnect-nspb-noc { 355 compatible = "qcom,sa8775p-nspb-noc"; 356 #interconnect-cells = <2>; 357 qcom,bcm-voters = <&apps_bcm_voter>; 358 }; 359 360 pcie_anoc: interconnect-pcie-anoc { 361 compatible = "qcom,sa8775p-pcie-anoc"; 362 #interconnect-cells = <2>; 363 qcom,bcm-voters = <&apps_bcm_voter>; 364 }; 365 366 system_noc: interconnect-system-noc { 367 compatible = "qcom,sa8775p-system-noc"; 368 #interconnect-cells = <2>; 369 qcom,bcm-voters = <&apps_bcm_voter>; 370 }; 371 372 /* Will be updated by the bootloader. */ 373 memory@80000000 { 374 device_type = "memory"; 375 reg = <0x0 0x80000000 0x0 0x0>; 376 }; 377 378 qup_opp_table_100mhz: opp-table-qup100mhz { 379 compatible = "operating-points-v2"; 380 381 opp-100000000 { 382 opp-hz = /bits/ 64 <100000000>; 383 required-opps = <&rpmhpd_opp_svs_l1>; 384 }; 385 }; 386 387 pmu { 388 compatible = "arm,armv8-pmuv3"; 389 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 390 }; 391 392 psci { 393 compatible = "arm,psci-1.0"; 394 method = "smc"; 395 396 CPU_PD0: power-domain-cpu0 { 397 #power-domain-cells = <0>; 398 power-domains = <&CLUSTER_0_PD>; 399 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 400 <&GOLD_RAIL_CPU_SLEEP_0>; 401 }; 402 403 CPU_PD1: power-domain-cpu1 { 404 #power-domain-cells = <0>; 405 power-domains = <&CLUSTER_0_PD>; 406 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 407 <&GOLD_RAIL_CPU_SLEEP_0>; 408 }; 409 410 CPU_PD2: power-domain-cpu2 { 411 #power-domain-cells = <0>; 412 power-domains = <&CLUSTER_0_PD>; 413 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 414 <&GOLD_RAIL_CPU_SLEEP_0>; 415 }; 416 417 CPU_PD3: power-domain-cpu3 { 418 #power-domain-cells = <0>; 419 power-domains = <&CLUSTER_0_PD>; 420 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 421 <&GOLD_RAIL_CPU_SLEEP_0>; 422 }; 423 424 CPU_PD4: power-domain-cpu4 { 425 #power-domain-cells = <0>; 426 power-domains = <&CLUSTER_1_PD>; 427 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 428 <&GOLD_RAIL_CPU_SLEEP_0>; 429 }; 430 431 CPU_PD5: power-domain-cpu5 { 432 #power-domain-cells = <0>; 433 power-domains = <&CLUSTER_1_PD>; 434 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 435 <&GOLD_RAIL_CPU_SLEEP_0>; 436 }; 437 438 CPU_PD6: power-domain-cpu6 { 439 #power-domain-cells = <0>; 440 power-domains = <&CLUSTER_1_PD>; 441 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 442 <&GOLD_RAIL_CPU_SLEEP_0>; 443 }; 444 445 CPU_PD7: power-domain-cpu7 { 446 #power-domain-cells = <0>; 447 power-domains = <&CLUSTER_1_PD>; 448 domain-idle-states = <&GOLD_CPU_SLEEP_0>, 449 <&GOLD_RAIL_CPU_SLEEP_0>; 450 }; 451 452 CLUSTER_0_PD: power-domain-cluster0 { 453 #power-domain-cells = <0>; 454 power-domains = <&CLUSTER_2_PD>; 455 domain-idle-states = <&CLUSTER_SLEEP_GOLD>; 456 }; 457 458 CLUSTER_1_PD: power-domain-cluster1 { 459 #power-domain-cells = <0>; 460 power-domains = <&CLUSTER_2_PD>; 461 domain-idle-states = <&CLUSTER_SLEEP_GOLD>; 462 }; 463 464 CLUSTER_2_PD: power-domain-cluster2 { 465 #power-domain-cells = <0>; 466 domain-idle-states = <&CLUSTER_SLEEP_APSS_RSC_PC>; 467 }; 468 }; 469 470 reserved-memory { 471 #address-cells = <2>; 472 #size-cells = <2>; 473 ranges; 474 475 sail_ss_mem: sail-ss@80000000 { 476 reg = <0x0 0x80000000 0x0 0x10000000>; 477 no-map; 478 }; 479 480 hyp_mem: hyp@90000000 { 481 reg = <0x0 0x90000000 0x0 0x600000>; 482 no-map; 483 }; 484 485 xbl_boot_mem: xbl-boot@90600000 { 486 reg = <0x0 0x90600000 0x0 0x200000>; 487 no-map; 488 }; 489 490 aop_image_mem: aop-image@90800000 { 491 reg = <0x0 0x90800000 0x0 0x60000>; 492 no-map; 493 }; 494 495 aop_cmd_db_mem: aop-cmd-db@90860000 { 496 compatible = "qcom,cmd-db"; 497 reg = <0x0 0x90860000 0x0 0x20000>; 498 no-map; 499 }; 500 501 uefi_log: uefi-log@908b0000 { 502 reg = <0x0 0x908b0000 0x0 0x10000>; 503 no-map; 504 }; 505 506 ddr_training_checksum: ddr-training-checksum@908c0000 { 507 reg = <0x0 0x908c0000 0x0 0x1000>; 508 no-map; 509 }; 510 511 reserved_mem: reserved@908f0000 { 512 reg = <0x0 0x908f0000 0x0 0xe000>; 513 no-map; 514 }; 515 516 secdata_apss_mem: secdata-apss@908fe000 { 517 reg = <0x0 0x908fe000 0x0 0x2000>; 518 no-map; 519 }; 520 521 smem_mem: smem@90900000 { 522 compatible = "qcom,smem"; 523 reg = <0x0 0x90900000 0x0 0x200000>; 524 no-map; 525 hwlocks = <&tcsr_mutex 3>; 526 }; 527 528 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 529 reg = <0x0 0x90c00000 0x0 0x100000>; 530 no-map; 531 }; 532 533 sail_mailbox_mem: sail-ss@90d00000 { 534 reg = <0x0 0x90d00000 0x0 0x100000>; 535 no-map; 536 }; 537 538 sail_ota_mem: sail-ss@90e00000 { 539 reg = <0x0 0x90e00000 0x0 0x300000>; 540 no-map; 541 }; 542 543 aoss_backup_mem: aoss-backup@91b00000 { 544 reg = <0x0 0x91b00000 0x0 0x40000>; 545 no-map; 546 }; 547 548 cpucp_backup_mem: cpucp-backup@91b40000 { 549 reg = <0x0 0x91b40000 0x0 0x40000>; 550 no-map; 551 }; 552 553 tz_config_backup_mem: tz-config-backup@91b80000 { 554 reg = <0x0 0x91b80000 0x0 0x10000>; 555 no-map; 556 }; 557 558 ddr_training_data_mem: ddr-training-data@91b90000 { 559 reg = <0x0 0x91b90000 0x0 0x10000>; 560 no-map; 561 }; 562 563 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 564 reg = <0x0 0x91ba0000 0x0 0x1000>; 565 no-map; 566 }; 567 568 tz_ffi_mem: tz-ffi@91c00000 { 569 compatible = "shared-dma-pool"; 570 reg = <0x0 0x91c00000 0x0 0x1400000>; 571 no-map; 572 }; 573 574 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 575 reg = <0x0 0x93b00000 0x0 0xf00000>; 576 no-map; 577 }; 578 579 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 580 reg = <0x0 0x94a00000 0x0 0x800000>; 581 no-map; 582 }; 583 584 pil_camera_mem: pil-camera@95200000 { 585 reg = <0x0 0x95200000 0x0 0x500000>; 586 no-map; 587 }; 588 589 pil_adsp_mem: pil-adsp@95c00000 { 590 reg = <0x0 0x95c00000 0x0 0x1e00000>; 591 no-map; 592 }; 593 594 pil_gdsp0_mem: pil-gdsp0@97b00000 { 595 reg = <0x0 0x97b00000 0x0 0x1e00000>; 596 no-map; 597 }; 598 599 pil_gdsp1_mem: pil-gdsp1@99900000 { 600 reg = <0x0 0x99900000 0x0 0x1e00000>; 601 no-map; 602 }; 603 604 pil_cdsp0_mem: pil-cdsp0@9b800000 { 605 reg = <0x0 0x9b800000 0x0 0x1e00000>; 606 no-map; 607 }; 608 609 pil_gpu_mem: pil-gpu@9d600000 { 610 reg = <0x0 0x9d600000 0x0 0x2000>; 611 no-map; 612 }; 613 614 pil_cdsp1_mem: pil-cdsp1@9d700000 { 615 reg = <0x0 0x9d700000 0x0 0x1e00000>; 616 no-map; 617 }; 618 619 pil_cvp_mem: pil-cvp@9f500000 { 620 reg = <0x0 0x9f500000 0x0 0x700000>; 621 no-map; 622 }; 623 624 pil_video_mem: pil-video@9fc00000 { 625 reg = <0x0 0x9fc00000 0x0 0x700000>; 626 no-map; 627 }; 628 629 audio_mdf_mem: audio-mdf-region@ae000000 { 630 reg = <0x0 0xae000000 0x0 0x1000000>; 631 no-map; 632 }; 633 634 firmware_mem: firmware-region@b0000000 { 635 reg = <0x0 0xb0000000 0x0 0x800000>; 636 no-map; 637 }; 638 639 hyptz_reserved_mem: hyptz-reserved@beb00000 { 640 reg = <0x0 0xbeb00000 0x0 0x11500000>; 641 no-map; 642 }; 643 644 scmi_mem: scmi-region@d0000000 { 645 reg = <0x0 0xd0000000 0x0 0x40000>; 646 no-map; 647 }; 648 649 firmware_logs_mem: firmware-logs@d0040000 { 650 reg = <0x0 0xd0040000 0x0 0x10000>; 651 no-map; 652 }; 653 654 firmware_audio_mem: firmware-audio@d0050000 { 655 reg = <0x0 0xd0050000 0x0 0x4000>; 656 no-map; 657 }; 658 659 firmware_reserved_mem: firmware-reserved@d0054000 { 660 reg = <0x0 0xd0054000 0x0 0x9c000>; 661 no-map; 662 }; 663 664 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 665 reg = <0x0 0xd00f0000 0x0 0x10000>; 666 no-map; 667 }; 668 669 tags_mem: tags@d0100000 { 670 reg = <0x0 0xd0100000 0x0 0x1200000>; 671 no-map; 672 }; 673 674 qtee_mem: qtee@d1300000 { 675 reg = <0x0 0xd1300000 0x0 0x500000>; 676 no-map; 677 }; 678 679 deepsleep_backup_mem: deepsleep-backup@d1800000 { 680 reg = <0x0 0xd1800000 0x0 0x100000>; 681 no-map; 682 }; 683 684 trusted_apps_mem: trusted-apps@d1900000 { 685 reg = <0x0 0xd1900000 0x0 0x3800000>; 686 no-map; 687 }; 688 689 tz_stat_mem: tz-stat@db100000 { 690 reg = <0x0 0xdb100000 0x0 0x100000>; 691 no-map; 692 }; 693 694 cpucp_fw_mem: cpucp-fw@db200000 { 695 reg = <0x0 0xdb200000 0x0 0x100000>; 696 no-map; 697 }; 698 }; 699 700 smp2p-adsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <443>, <429>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <2>; 710 711 smp2p_adsp_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 smp2p_adsp_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 }; 721 }; 722 723 smp2p-cdsp0 { 724 compatible = "qcom,smp2p"; 725 qcom,smem = <94>, <432>; 726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 727 IPCC_MPROC_SIGNAL_SMP2P 728 IRQ_TYPE_EDGE_RISING>; 729 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 730 731 qcom,local-pid = <0>; 732 qcom,remote-pid = <5>; 733 734 smp2p_cdsp0_out: master-kernel { 735 qcom,entry-name = "master-kernel"; 736 #qcom,smem-state-cells = <1>; 737 }; 738 739 smp2p_cdsp0_in: slave-kernel { 740 qcom,entry-name = "slave-kernel"; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 }; 744 }; 745 746 smp2p-cdsp1 { 747 compatible = "qcom,smp2p"; 748 qcom,smem = <617>, <616>; 749 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 750 IPCC_MPROC_SIGNAL_SMP2P 751 IRQ_TYPE_EDGE_RISING>; 752 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 753 754 qcom,local-pid = <0>; 755 qcom,remote-pid = <12>; 756 757 smp2p_cdsp1_out: master-kernel { 758 qcom,entry-name = "master-kernel"; 759 #qcom,smem-state-cells = <1>; 760 }; 761 762 smp2p_cdsp1_in: slave-kernel { 763 qcom,entry-name = "slave-kernel"; 764 interrupt-controller; 765 #interrupt-cells = <2>; 766 }; 767 }; 768 769 smp2p-gpdsp0 { 770 compatible = "qcom,smp2p"; 771 qcom,smem = <617>, <616>; 772 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 773 IPCC_MPROC_SIGNAL_SMP2P 774 IRQ_TYPE_EDGE_RISING>; 775 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 776 777 qcom,local-pid = <0>; 778 qcom,remote-pid = <17>; 779 780 smp2p_gpdsp0_out: master-kernel { 781 qcom,entry-name = "master-kernel"; 782 #qcom,smem-state-cells = <1>; 783 }; 784 785 smp2p_gpdsp0_in: slave-kernel { 786 qcom,entry-name = "slave-kernel"; 787 interrupt-controller; 788 #interrupt-cells = <2>; 789 }; 790 }; 791 792 smp2p-gpdsp1 { 793 compatible = "qcom,smp2p"; 794 qcom,smem = <617>, <616>; 795 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 796 IPCC_MPROC_SIGNAL_SMP2P 797 IRQ_TYPE_EDGE_RISING>; 798 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 799 800 qcom,local-pid = <0>; 801 qcom,remote-pid = <18>; 802 803 smp2p_gpdsp1_out: master-kernel { 804 qcom,entry-name = "master-kernel"; 805 #qcom,smem-state-cells = <1>; 806 }; 807 808 smp2p_gpdsp1_in: slave-kernel { 809 qcom,entry-name = "slave-kernel"; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 }; 813 }; 814 815 soc: soc@0 { 816 compatible = "simple-bus"; 817 #address-cells = <2>; 818 #size-cells = <2>; 819 ranges = <0 0 0 0 0x10 0>; 820 821 gcc: clock-controller@100000 { 822 compatible = "qcom,sa8775p-gcc"; 823 reg = <0x0 0x00100000 0x0 0xc7018>; 824 #clock-cells = <1>; 825 #reset-cells = <1>; 826 #power-domain-cells = <1>; 827 clocks = <&rpmhcc RPMH_CXO_CLK>, 828 <&sleep_clk>, 829 <0>, 830 <0>, 831 <0>, 832 <&usb_0_qmpphy>, 833 <&usb_1_qmpphy>, 834 <0>, 835 <0>, 836 <0>, 837 <&pcie0_phy>, 838 <&pcie1_phy>, 839 <0>, 840 <0>, 841 <0>; 842 power-domains = <&rpmhpd SA8775P_CX>; 843 }; 844 845 ipcc: mailbox@408000 { 846 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 847 reg = <0x0 0x00408000 0x0 0x1000>; 848 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-controller; 850 #interrupt-cells = <3>; 851 #mbox-cells = <2>; 852 }; 853 854 qupv3_id_2: geniqup@8c0000 { 855 compatible = "qcom,geni-se-qup"; 856 reg = <0x0 0x008c0000 0x0 0x6000>; 857 ranges; 858 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 859 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 860 clock-names = "m-ahb", "s-ahb"; 861 iommus = <&apps_smmu 0x5a3 0x0>; 862 #address-cells = <2>; 863 #size-cells = <2>; 864 status = "disabled"; 865 866 i2c14: i2c@880000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0x0 0x880000 0x0 0x4000>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 873 clock-names = "se"; 874 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 875 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 876 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 877 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 878 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 879 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 880 interconnect-names = "qup-core", 881 "qup-config", 882 "qup-memory"; 883 power-domains = <&rpmhpd SA8775P_CX>; 884 status = "disabled"; 885 }; 886 887 spi14: spi@880000 { 888 compatible = "qcom,geni-spi"; 889 reg = <0x0 0x880000 0x0 0x4000>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 894 clock-names = "se"; 895 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 896 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 897 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 898 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 899 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 900 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 901 interconnect-names = "qup-core", 902 "qup-config", 903 "qup-memory"; 904 power-domains = <&rpmhpd SA8775P_CX>; 905 status = "disabled"; 906 }; 907 908 i2c15: i2c@884000 { 909 compatible = "qcom,geni-i2c"; 910 reg = <0x0 0x884000 0x0 0x4000>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 915 clock-names = "se"; 916 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 917 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 919 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 920 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 922 interconnect-names = "qup-core", 923 "qup-config", 924 "qup-memory"; 925 power-domains = <&rpmhpd SA8775P_CX>; 926 status = "disabled"; 927 }; 928 929 spi15: spi@884000 { 930 compatible = "qcom,geni-spi"; 931 reg = <0x0 0x884000 0x0 0x4000>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 936 clock-names = "se"; 937 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 938 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 939 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 940 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 941 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 942 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 943 interconnect-names = "qup-core", 944 "qup-config", 945 "qup-memory"; 946 power-domains = <&rpmhpd SA8775P_CX>; 947 status = "disabled"; 948 }; 949 950 i2c16: i2c@888000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0x0 0x888000 0x0 0x4000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 957 clock-names = "se"; 958 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 959 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 960 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 961 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 962 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 963 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 964 interconnect-names = "qup-core", 965 "qup-config", 966 "qup-memory"; 967 power-domains = <&rpmhpd SA8775P_CX>; 968 status = "disabled"; 969 }; 970 971 spi16: spi@888000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0x0 0x00888000 0x0 0x4000>; 974 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 976 clock-names = "se"; 977 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 978 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 980 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 981 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 983 interconnect-names = "qup-core", 984 "qup-config", 985 "qup-memory"; 986 power-domains = <&rpmhpd SA8775P_CX>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 i2c17: i2c@88c000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0x0 0x88c000 0x0 0x4000>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 999 clock-names = "se"; 1000 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1001 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1003 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1004 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1006 interconnect-names = "qup-core", 1007 "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd SA8775P_CX>; 1010 status = "disabled"; 1011 }; 1012 1013 spi17: spi@88c000 { 1014 compatible = "qcom,geni-spi"; 1015 reg = <0x0 0x88c000 0x0 0x4000>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1020 clock-names = "se"; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1022 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1024 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1025 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1027 interconnect-names = "qup-core", 1028 "qup-config", 1029 "qup-memory"; 1030 power-domains = <&rpmhpd SA8775P_CX>; 1031 status = "disabled"; 1032 }; 1033 1034 uart17: serial@88c000 { 1035 compatible = "qcom,geni-uart"; 1036 reg = <0x0 0x0088c000 0x0 0x4000>; 1037 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1039 clock-names = "se"; 1040 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1041 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1042 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1043 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1044 interconnect-names = "qup-core", "qup-config"; 1045 power-domains = <&rpmhpd SA8775P_CX>; 1046 status = "disabled"; 1047 }; 1048 1049 i2c18: i2c@890000 { 1050 compatible = "qcom,geni-i2c"; 1051 reg = <0x0 0x00890000 0x0 0x4000>; 1052 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1054 clock-names = "se"; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1056 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1058 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1059 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1061 interconnect-names = "qup-core", 1062 "qup-config", 1063 "qup-memory"; 1064 power-domains = <&rpmhpd SA8775P_CX>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 spi18: spi@890000 { 1071 compatible = "qcom,geni-spi"; 1072 reg = <0x0 0x890000 0x0 0x4000>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1077 clock-names = "se"; 1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1079 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1080 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1081 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1082 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1084 interconnect-names = "qup-core", 1085 "qup-config", 1086 "qup-memory"; 1087 power-domains = <&rpmhpd SA8775P_CX>; 1088 status = "disabled"; 1089 }; 1090 1091 i2c19: i2c@894000 { 1092 compatible = "qcom,geni-i2c"; 1093 reg = <0x0 0x894000 0x0 0x4000>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1098 clock-names = "se"; 1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1100 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1101 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1102 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1103 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1104 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1105 interconnect-names = "qup-core", 1106 "qup-config", 1107 "qup-memory"; 1108 power-domains = <&rpmhpd SA8775P_CX>; 1109 status = "disabled"; 1110 }; 1111 1112 spi19: spi@894000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0x0 0x894000 0x0 0x4000>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1119 clock-names = "se"; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", 1127 "qup-config", 1128 "qup-memory"; 1129 power-domains = <&rpmhpd SA8775P_CX>; 1130 status = "disabled"; 1131 }; 1132 1133 i2c20: i2c@898000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0x0 0x898000 0x0 0x4000>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1140 clock-names = "se"; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1142 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1143 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1144 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1145 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1146 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1147 interconnect-names = "qup-core", 1148 "qup-config", 1149 "qup-memory"; 1150 power-domains = <&rpmhpd SA8775P_CX>; 1151 status = "disabled"; 1152 }; 1153 1154 spi20: spi@898000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0x0 0x898000 0x0 0x4000>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1161 clock-names = "se"; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1163 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1164 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1165 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1166 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1168 interconnect-names = "qup-core", 1169 "qup-config", 1170 "qup-memory"; 1171 power-domains = <&rpmhpd SA8775P_CX>; 1172 status = "disabled"; 1173 }; 1174 }; 1175 1176 qupv3_id_0: geniqup@9c0000 { 1177 compatible = "qcom,geni-se-qup"; 1178 reg = <0x0 0x9c0000 0x0 0x6000>; 1179 #address-cells = <2>; 1180 #size-cells = <2>; 1181 ranges; 1182 clock-names = "m-ahb", "s-ahb"; 1183 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1184 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1185 iommus = <&apps_smmu 0x403 0x0>; 1186 status = "disabled"; 1187 1188 i2c0: i2c@980000 { 1189 compatible = "qcom,geni-i2c"; 1190 reg = <0x0 0x980000 0x0 0x4000>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1195 clock-names = "se"; 1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1197 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1198 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1199 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1200 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1201 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1202 interconnect-names = "qup-core", 1203 "qup-config", 1204 "qup-memory"; 1205 power-domains = <&rpmhpd SA8775P_CX>; 1206 status = "disabled"; 1207 }; 1208 1209 spi0: spi@980000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0x0 0x980000 0x0 0x4000>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1216 clock-names = "se"; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1218 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1220 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1221 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1223 interconnect-names = "qup-core", 1224 "qup-config", 1225 "qup-memory"; 1226 power-domains = <&rpmhpd SA8775P_CX>; 1227 status = "disabled"; 1228 }; 1229 1230 i2c1: i2c@984000 { 1231 compatible = "qcom,geni-i2c"; 1232 reg = <0x0 0x984000 0x0 0x4000>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1237 clock-names = "se"; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1239 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1241 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1242 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", 1245 "qup-config", 1246 "qup-memory"; 1247 power-domains = <&rpmhpd SA8775P_CX>; 1248 status = "disabled"; 1249 }; 1250 1251 spi1: spi@984000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0x0 0x984000 0x0 0x4000>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1258 clock-names = "se"; 1259 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1260 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1261 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1262 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1263 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1265 interconnect-names = "qup-core", 1266 "qup-config", 1267 "qup-memory"; 1268 power-domains = <&rpmhpd SA8775P_CX>; 1269 status = "disabled"; 1270 }; 1271 1272 i2c2: i2c@988000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0x0 0x988000 0x0 0x4000>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1279 clock-names = "se"; 1280 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1281 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1282 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1283 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1284 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1285 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1286 interconnect-names = "qup-core", 1287 "qup-config", 1288 "qup-memory"; 1289 power-domains = <&rpmhpd SA8775P_CX>; 1290 status = "disabled"; 1291 }; 1292 1293 spi2: spi@988000 { 1294 compatible = "qcom,geni-spi"; 1295 reg = <0x0 0x988000 0x0 0x4000>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1300 clock-names = "se"; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1302 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1303 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1304 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1305 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1306 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1307 interconnect-names = "qup-core", 1308 "qup-config", 1309 "qup-memory"; 1310 power-domains = <&rpmhpd SA8775P_CX>; 1311 status = "disabled"; 1312 }; 1313 1314 i2c3: i2c@98c000 { 1315 compatible = "qcom,geni-i2c"; 1316 reg = <0x0 0x98c000 0x0 0x4000>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1321 clock-names = "se"; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1323 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1324 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1325 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1326 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1328 interconnect-names = "qup-core", 1329 "qup-config", 1330 "qup-memory"; 1331 power-domains = <&rpmhpd SA8775P_CX>; 1332 status = "disabled"; 1333 }; 1334 1335 spi3: spi@98c000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0x0 0x98c000 0x0 0x4000>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1342 clock-names = "se"; 1343 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1344 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1346 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1347 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1349 interconnect-names = "qup-core", 1350 "qup-config", 1351 "qup-memory"; 1352 power-domains = <&rpmhpd SA8775P_CX>; 1353 status = "disabled"; 1354 }; 1355 1356 i2c4: i2c@990000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0x0 0x990000 0x0 0x4000>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1363 clock-names = "se"; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1365 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1366 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1367 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1368 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1369 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1370 interconnect-names = "qup-core", 1371 "qup-config", 1372 "qup-memory"; 1373 power-domains = <&rpmhpd SA8775P_CX>; 1374 status = "disabled"; 1375 }; 1376 1377 spi4: spi@990000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0x0 0x990000 0x0 0x4000>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1384 clock-names = "se"; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1388 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1389 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1391 interconnect-names = "qup-core", 1392 "qup-config", 1393 "qup-memory"; 1394 power-domains = <&rpmhpd SA8775P_CX>; 1395 status = "disabled"; 1396 }; 1397 1398 i2c5: i2c@994000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0x0 0x994000 0x0 0x4000>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1405 clock-names = "se"; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1407 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1408 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1409 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1410 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1412 interconnect-names = "qup-core", 1413 "qup-config", 1414 "qup-memory"; 1415 power-domains = <&rpmhpd SA8775P_CX>; 1416 status = "disabled"; 1417 }; 1418 1419 spi5: spi@994000 { 1420 compatible = "qcom,geni-spi"; 1421 reg = <0x0 0x994000 0x0 0x4000>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1426 clock-names = "se"; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1428 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1430 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1431 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config", 1435 "qup-memory"; 1436 power-domains = <&rpmhpd SA8775P_CX>; 1437 status = "disabled"; 1438 }; 1439 1440 uart5: serial@994000 { 1441 compatible = "qcom,geni-uart"; 1442 reg = <0x0 0x994000 0x0 0x4000>; 1443 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1445 clock-names = "se"; 1446 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1447 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1449 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1450 interconnect-names = "qup-core", "qup-config"; 1451 power-domains = <&rpmhpd SA8775P_CX>; 1452 status = "disabled"; 1453 }; 1454 }; 1455 1456 qupv3_id_1: geniqup@ac0000 { 1457 compatible = "qcom,geni-se-qup"; 1458 reg = <0x0 0x00ac0000 0x0 0x6000>; 1459 #address-cells = <2>; 1460 #size-cells = <2>; 1461 ranges; 1462 clock-names = "m-ahb", "s-ahb"; 1463 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1464 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1465 iommus = <&apps_smmu 0x443 0x0>; 1466 status = "disabled"; 1467 1468 i2c7: i2c@a80000 { 1469 compatible = "qcom,geni-i2c"; 1470 reg = <0x0 0xa80000 0x0 0x4000>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1474 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1475 clock-names = "se"; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1477 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1479 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1480 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1482 interconnect-names = "qup-core", 1483 "qup-config", 1484 "qup-memory"; 1485 power-domains = <&rpmhpd SA8775P_CX>; 1486 status = "disabled"; 1487 }; 1488 1489 spi7: spi@a80000 { 1490 compatible = "qcom,geni-spi"; 1491 reg = <0x0 0xa80000 0x0 0x4000>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1495 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1496 clock-names = "se"; 1497 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1498 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1499 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1500 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1501 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1502 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1503 interconnect-names = "qup-core", 1504 "qup-config", 1505 "qup-memory"; 1506 power-domains = <&rpmhpd SA8775P_CX>; 1507 status = "disabled"; 1508 }; 1509 1510 i2c8: i2c@a84000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0x0 0xa84000 0x0 0x4000>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1517 clock-names = "se"; 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1522 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1524 interconnect-names = "qup-core", 1525 "qup-config", 1526 "qup-memory"; 1527 power-domains = <&rpmhpd SA8775P_CX>; 1528 status = "disabled"; 1529 }; 1530 1531 spi8: spi@a84000 { 1532 compatible = "qcom,geni-spi"; 1533 reg = <0x0 0xa84000 0x0 0x4000>; 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1537 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1538 clock-names = "se"; 1539 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1540 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1541 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1542 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1543 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1544 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1545 interconnect-names = "qup-core", 1546 "qup-config", 1547 "qup-memory"; 1548 power-domains = <&rpmhpd SA8775P_CX>; 1549 status = "disabled"; 1550 }; 1551 1552 i2c9: i2c@a88000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0x0 0xa88000 0x0 0x4000>; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1558 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1559 clock-names = "se"; 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1561 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1562 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1563 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1564 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1565 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1566 interconnect-names = "qup-core", 1567 "qup-config", 1568 "qup-memory"; 1569 power-domains = <&rpmhpd SA8775P_CX>; 1570 status = "disabled"; 1571 }; 1572 1573 spi9: spi@a88000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0x0 0xa88000 0x0 0x4000>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1580 clock-names = "se"; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1587 interconnect-names = "qup-core", 1588 "qup-config", 1589 "qup-memory"; 1590 power-domains = <&rpmhpd SA8775P_CX>; 1591 status = "disabled"; 1592 }; 1593 1594 uart9: serial@a88000 { 1595 compatible = "qcom,geni-uart"; 1596 reg = <0x0 0xa88000 0x0 0x4000>; 1597 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1599 clock-names = "se"; 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1601 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1602 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1603 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 power-domains = <&rpmhpd SA8775P_CX>; 1606 status = "disabled"; 1607 }; 1608 1609 i2c10: i2c@a8c000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0x0 0xa8c000 0x0 0x4000>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1616 clock-names = "se"; 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1621 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1623 interconnect-names = "qup-core", 1624 "qup-config", 1625 "qup-memory"; 1626 power-domains = <&rpmhpd SA8775P_CX>; 1627 status = "disabled"; 1628 }; 1629 1630 spi10: spi@a8c000 { 1631 compatible = "qcom,geni-spi"; 1632 reg = <0x0 0xa8c000 0x0 0x4000>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1637 clock-names = "se"; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1639 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1640 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1641 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1642 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1643 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1644 interconnect-names = "qup-core", 1645 "qup-config", 1646 "qup-memory"; 1647 power-domains = <&rpmhpd SA8775P_CX>; 1648 status = "disabled"; 1649 }; 1650 1651 uart10: serial@a8c000 { 1652 compatible = "qcom,geni-uart"; 1653 reg = <0x0 0x00a8c000 0x0 0x4000>; 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 1659 &clk_virt SLAVE_QUP_CORE_1 0>, 1660 <&gem_noc MASTER_APPSS_PROC 0 1661 &config_noc SLAVE_QUP_1 0>; 1662 power-domains = <&rpmhpd SA8775P_CX>; 1663 operating-points-v2 = <&qup_opp_table_100mhz>; 1664 status = "disabled"; 1665 }; 1666 1667 i2c11: i2c@a90000 { 1668 compatible = "qcom,geni-i2c"; 1669 reg = <0x0 0xa90000 0x0 0x4000>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1674 clock-names = "se"; 1675 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1676 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1677 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1678 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1679 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1680 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1681 interconnect-names = "qup-core", 1682 "qup-config", 1683 "qup-memory"; 1684 power-domains = <&rpmhpd SA8775P_CX>; 1685 status = "disabled"; 1686 }; 1687 1688 spi11: spi@a90000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0x0 0xa90000 0x0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1695 clock-names = "se"; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1697 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1698 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1699 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1700 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1701 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1702 interconnect-names = "qup-core", 1703 "qup-config", 1704 "qup-memory"; 1705 power-domains = <&rpmhpd SA8775P_CX>; 1706 status = "disabled"; 1707 }; 1708 1709 i2c12: i2c@a94000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0x0 0xa94000 0x0 0x4000>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1716 clock-names = "se"; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1718 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1719 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1720 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1721 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1722 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1723 interconnect-names = "qup-core", 1724 "qup-config", 1725 "qup-memory"; 1726 power-domains = <&rpmhpd SA8775P_CX>; 1727 status = "disabled"; 1728 }; 1729 1730 spi12: spi@a94000 { 1731 compatible = "qcom,geni-spi"; 1732 reg = <0x0 0xa94000 0x0 0x4000>; 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1737 clock-names = "se"; 1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1739 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1740 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1741 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1742 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1743 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1744 interconnect-names = "qup-core", 1745 "qup-config", 1746 "qup-memory"; 1747 power-domains = <&rpmhpd SA8775P_CX>; 1748 status = "disabled"; 1749 }; 1750 1751 uart12: serial@a94000 { 1752 compatible = "qcom,geni-uart"; 1753 reg = <0x0 0x00a94000 0x0 0x4000>; 1754 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1756 clock-names = "se"; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1758 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1759 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1760 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1761 interconnect-names = "qup-core", "qup-config"; 1762 power-domains = <&rpmhpd SA8775P_CX>; 1763 status = "disabled"; 1764 }; 1765 1766 i2c13: i2c@a98000 { 1767 compatible = "qcom,geni-i2c"; 1768 reg = <0x0 0xa98000 0x0 0x4000>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1773 clock-names = "se"; 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1775 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1777 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1778 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1780 interconnect-names = "qup-core", 1781 "qup-config", 1782 "qup-memory"; 1783 power-domains = <&rpmhpd SA8775P_CX>; 1784 status = "disabled"; 1785 }; 1786 }; 1787 1788 qupv3_id_3: geniqup@bc0000 { 1789 compatible = "qcom,geni-se-qup"; 1790 reg = <0x0 0xbc0000 0x0 0x6000>; 1791 #address-cells = <2>; 1792 #size-cells = <2>; 1793 ranges; 1794 clock-names = "m-ahb", "s-ahb"; 1795 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 1796 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 1797 iommus = <&apps_smmu 0x43 0x0>; 1798 status = "disabled"; 1799 1800 i2c21: i2c@b80000 { 1801 compatible = "qcom,geni-i2c"; 1802 reg = <0x0 0xb80000 0x0 0x4000>; 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1806 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1807 clock-names = "se"; 1808 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1809 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1811 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1812 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1813 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1814 interconnect-names = "qup-core", 1815 "qup-config", 1816 "qup-memory"; 1817 power-domains = <&rpmhpd SA8775P_CX>; 1818 status = "disabled"; 1819 }; 1820 1821 spi21: spi@b80000 { 1822 compatible = "qcom,geni-spi"; 1823 reg = <0x0 0xb80000 0x0 0x4000>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1827 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1828 clock-names = "se"; 1829 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1830 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1831 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1832 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1833 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1834 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1835 interconnect-names = "qup-core", 1836 "qup-config", 1837 "qup-memory"; 1838 power-domains = <&rpmhpd SA8775P_CX>; 1839 status = "disabled"; 1840 }; 1841 }; 1842 1843 rng: rng@10d2000 { 1844 compatible = "qcom,sa8775p-trng", "qcom,trng"; 1845 reg = <0 0x010d2000 0 0x1000>; 1846 }; 1847 1848 ufs_mem_hc: ufs@1d84000 { 1849 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1850 reg = <0x0 0x01d84000 0x0 0x3000>; 1851 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1852 phys = <&ufs_mem_phy>; 1853 phy-names = "ufsphy"; 1854 lanes-per-direction = <2>; 1855 #reset-cells = <1>; 1856 resets = <&gcc GCC_UFS_PHY_BCR>; 1857 reset-names = "rst"; 1858 power-domains = <&gcc UFS_PHY_GDSC>; 1859 required-opps = <&rpmhpd_opp_nom>; 1860 iommus = <&apps_smmu 0x100 0x0>; 1861 dma-coherent; 1862 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1863 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1864 <&gcc GCC_UFS_PHY_AHB_CLK>, 1865 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1866 <&rpmhcc RPMH_CXO_CLK>, 1867 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1868 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1869 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1870 clock-names = "core_clk", 1871 "bus_aggr_clk", 1872 "iface_clk", 1873 "core_clk_unipro", 1874 "ref_clk", 1875 "tx_lane0_sync_clk", 1876 "rx_lane0_sync_clk", 1877 "rx_lane1_sync_clk"; 1878 freq-table-hz = <75000000 300000000>, 1879 <0 0>, 1880 <0 0>, 1881 <75000000 300000000>, 1882 <0 0>, 1883 <0 0>, 1884 <0 0>, 1885 <0 0>; 1886 qcom,ice = <&ice>; 1887 status = "disabled"; 1888 }; 1889 1890 ufs_mem_phy: phy@1d87000 { 1891 compatible = "qcom,sa8775p-qmp-ufs-phy"; 1892 reg = <0x0 0x01d87000 0x0 0xe10>; 1893 /* 1894 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 1895 * enables the CXO clock to eDP *and* UFS PHY. 1896 */ 1897 clocks = <&rpmhcc RPMH_CXO_CLK>, 1898 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1899 <&gcc GCC_EDP_REF_CLKREF_EN>; 1900 clock-names = "ref", "ref_aux", "qref"; 1901 power-domains = <&gcc UFS_PHY_GDSC>; 1902 resets = <&ufs_mem_hc 0>; 1903 reset-names = "ufsphy"; 1904 #phy-cells = <0>; 1905 status = "disabled"; 1906 }; 1907 1908 ice: crypto@1d88000 { 1909 compatible = "qcom,sa8775p-inline-crypto-engine", 1910 "qcom,inline-crypto-engine"; 1911 reg = <0x0 0x01d88000 0x0 0x8000>; 1912 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1913 }; 1914 1915 stm: stm@4002000 { 1916 compatible = "arm,coresight-stm", "arm,primecell"; 1917 reg = <0x0 0x4002000 0x0 0x1000>, 1918 <0x0 0x16280000 0x0 0x180000>; 1919 reg-names = "stm-base", "stm-stimulus-base"; 1920 1921 clocks = <&aoss_qmp>; 1922 clock-names = "apb_pclk"; 1923 1924 out-ports { 1925 port { 1926 stm_out: endpoint { 1927 remote-endpoint = 1928 <&funnel0_in7>; 1929 }; 1930 }; 1931 }; 1932 }; 1933 1934 tpdm@4003000 { 1935 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1936 reg = <0x0 0x4003000 0x0 0x1000>; 1937 1938 clocks = <&aoss_qmp>; 1939 clock-names = "apb_pclk"; 1940 1941 qcom,cmb-element-bits = <32>; 1942 qcom,cmb-msrs-num = <32>; 1943 status = "disabled"; 1944 1945 out-ports { 1946 port { 1947 qdss_tpdm0_out: endpoint { 1948 remote-endpoint = 1949 <&qdss_tpda_in0>; 1950 }; 1951 }; 1952 }; 1953 }; 1954 1955 tpda@4004000 { 1956 compatible = "qcom,coresight-tpda", "arm,primecell"; 1957 reg = <0x0 0x4004000 0x0 0x1000>; 1958 1959 clocks = <&aoss_qmp>; 1960 clock-names = "apb_pclk"; 1961 1962 out-ports { 1963 port { 1964 qdss_tpda_out: endpoint { 1965 remote-endpoint = 1966 <&funnel0_in6>; 1967 }; 1968 }; 1969 }; 1970 1971 in-ports { 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 port@0 { 1976 reg = <0>; 1977 qdss_tpda_in0: endpoint { 1978 remote-endpoint = 1979 <&qdss_tpdm0_out>; 1980 }; 1981 }; 1982 1983 port@1 { 1984 reg = <1>; 1985 qdss_tpda_in1: endpoint { 1986 remote-endpoint = 1987 <&qdss_tpdm1_out>; 1988 }; 1989 }; 1990 }; 1991 }; 1992 1993 tpdm@400f000 { 1994 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1995 reg = <0x0 0x400f000 0x0 0x1000>; 1996 1997 clocks = <&aoss_qmp>; 1998 clock-names = "apb_pclk"; 1999 2000 qcom,cmb-element-bits = <32>; 2001 qcom,cmb-msrs-num = <32>; 2002 2003 out-ports { 2004 port { 2005 qdss_tpdm1_out: endpoint { 2006 remote-endpoint = 2007 <&qdss_tpda_in1>; 2008 }; 2009 }; 2010 }; 2011 }; 2012 2013 funnel@4041000 { 2014 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2015 reg = <0x0 0x4041000 0x0 0x1000>; 2016 2017 clocks = <&aoss_qmp>; 2018 clock-names = "apb_pclk"; 2019 2020 out-ports { 2021 port { 2022 funnel0_out: endpoint { 2023 remote-endpoint = 2024 <&qdss_funnel_in0>; 2025 }; 2026 }; 2027 }; 2028 2029 in-ports { 2030 #address-cells = <1>; 2031 #size-cells = <0>; 2032 2033 port@6 { 2034 reg = <6>; 2035 funnel0_in6: endpoint { 2036 remote-endpoint = 2037 <&qdss_tpda_out>; 2038 }; 2039 }; 2040 2041 port@7 { 2042 reg = <7>; 2043 funnel0_in7: endpoint { 2044 remote-endpoint = 2045 <&stm_out>; 2046 }; 2047 }; 2048 }; 2049 }; 2050 2051 funnel@4042000 { 2052 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2053 reg = <0x0 0x4042000 0x0 0x1000>; 2054 2055 clocks = <&aoss_qmp>; 2056 clock-names = "apb_pclk"; 2057 2058 out-ports { 2059 port { 2060 funnel1_out: endpoint { 2061 remote-endpoint = 2062 <&qdss_funnel_in1>; 2063 }; 2064 }; 2065 }; 2066 2067 in-ports { 2068 #address-cells = <1>; 2069 #size-cells = <0>; 2070 2071 port@4 { 2072 reg = <4>; 2073 funnel1_in4: endpoint { 2074 remote-endpoint = 2075 <&apss_funnel1_out>; 2076 }; 2077 }; 2078 }; 2079 }; 2080 2081 funnel@4045000 { 2082 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2083 reg = <0x0 0x4045000 0x0 0x1000>; 2084 2085 clocks = <&aoss_qmp>; 2086 clock-names = "apb_pclk"; 2087 2088 out-ports { 2089 port { 2090 qdss_funnel_out: endpoint { 2091 remote-endpoint = 2092 <&aoss_funnel_in7>; 2093 }; 2094 }; 2095 }; 2096 2097 in-ports { 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 port@0 { 2102 reg = <0>; 2103 qdss_funnel_in0: endpoint { 2104 remote-endpoint = 2105 <&funnel0_out>; 2106 }; 2107 }; 2108 2109 port@1 { 2110 reg = <1>; 2111 qdss_funnel_in1: endpoint { 2112 remote-endpoint = 2113 <&funnel1_out>; 2114 }; 2115 }; 2116 }; 2117 }; 2118 2119 funnel@4b04000 { 2120 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2121 reg = <0x0 0x4b04000 0x0 0x1000>; 2122 2123 clocks = <&aoss_qmp>; 2124 clock-names = "apb_pclk"; 2125 2126 out-ports { 2127 port { 2128 aoss_funnel_out: endpoint { 2129 remote-endpoint = 2130 <&etf0_in>; 2131 }; 2132 }; 2133 }; 2134 2135 in-ports { 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 2139 port@6 { 2140 reg = <6>; 2141 aoss_funnel_in6: endpoint { 2142 remote-endpoint = 2143 <&aoss_tpda_out>; 2144 }; 2145 }; 2146 2147 port@7 { 2148 reg = <7>; 2149 aoss_funnel_in7: endpoint { 2150 remote-endpoint = 2151 <&qdss_funnel_out>; 2152 }; 2153 }; 2154 }; 2155 }; 2156 2157 tmc_etf: tmc@4b05000 { 2158 compatible = "arm,coresight-tmc", "arm,primecell"; 2159 reg = <0x0 0x4b05000 0x0 0x1000>; 2160 2161 clocks = <&aoss_qmp>; 2162 clock-names = "apb_pclk"; 2163 2164 out-ports { 2165 port { 2166 etf0_out: endpoint { 2167 remote-endpoint = 2168 <&swao_rep_in>; 2169 }; 2170 }; 2171 }; 2172 2173 in-ports { 2174 port { 2175 etf0_in: endpoint { 2176 remote-endpoint = 2177 <&aoss_funnel_out>; 2178 }; 2179 }; 2180 }; 2181 }; 2182 2183 replicator@4b06000 { 2184 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2185 reg = <0x0 0x4b06000 0x0 0x1000>; 2186 2187 clocks = <&aoss_qmp>; 2188 clock-names = "apb_pclk"; 2189 2190 out-ports { 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 2194 port@1 { 2195 reg = <1>; 2196 swao_rep_out1: endpoint { 2197 remote-endpoint = 2198 <&eud_in>; 2199 }; 2200 }; 2201 }; 2202 2203 in-ports { 2204 port { 2205 swao_rep_in: endpoint { 2206 remote-endpoint = 2207 <&etf0_out>; 2208 }; 2209 }; 2210 }; 2211 }; 2212 2213 tpda@4b08000 { 2214 compatible = "qcom,coresight-tpda", "arm,primecell"; 2215 reg = <0x0 0x4b08000 0x0 0x1000>; 2216 2217 clocks = <&aoss_qmp>; 2218 clock-names = "apb_pclk"; 2219 2220 out-ports { 2221 port { 2222 aoss_tpda_out: endpoint { 2223 remote-endpoint = 2224 <&aoss_funnel_in6>; 2225 }; 2226 }; 2227 }; 2228 2229 in-ports { 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 2233 port@0 { 2234 reg = <0>; 2235 aoss_tpda_in0: endpoint { 2236 remote-endpoint = 2237 <&aoss_tpdm0_out>; 2238 }; 2239 }; 2240 2241 port@1 { 2242 reg = <1>; 2243 aoss_tpda_in1: endpoint { 2244 remote-endpoint = 2245 <&aoss_tpdm1_out>; 2246 }; 2247 }; 2248 2249 port@2 { 2250 reg = <2>; 2251 aoss_tpda_in2: endpoint { 2252 remote-endpoint = 2253 <&aoss_tpdm2_out>; 2254 }; 2255 }; 2256 2257 port@3 { 2258 reg = <3>; 2259 aoss_tpda_in3: endpoint { 2260 remote-endpoint = 2261 <&aoss_tpdm3_out>; 2262 }; 2263 }; 2264 2265 port@4 { 2266 reg = <4>; 2267 aoss_tpda_in4: endpoint { 2268 remote-endpoint = 2269 <&aoss_tpdm4_out>; 2270 }; 2271 }; 2272 }; 2273 }; 2274 2275 tpdm@4b09000 { 2276 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2277 reg = <0x0 0x4b09000 0x0 0x1000>; 2278 2279 clocks = <&aoss_qmp>; 2280 clock-names = "apb_pclk"; 2281 2282 qcom,cmb-element-bits = <64>; 2283 qcom,cmb-msrs-num = <32>; 2284 2285 out-ports { 2286 port { 2287 aoss_tpdm0_out: endpoint { 2288 remote-endpoint = 2289 <&aoss_tpda_in0>; 2290 }; 2291 }; 2292 }; 2293 }; 2294 2295 tpdm@4b0a000 { 2296 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2297 reg = <0x0 0x4b0a000 0x0 0x1000>; 2298 2299 clocks = <&aoss_qmp>; 2300 clock-names = "apb_pclk"; 2301 2302 qcom,cmb-element-bits = <64>; 2303 qcom,cmb-msrs-num = <32>; 2304 2305 out-ports { 2306 port { 2307 aoss_tpdm1_out: endpoint { 2308 remote-endpoint = 2309 <&aoss_tpda_in1>; 2310 }; 2311 }; 2312 }; 2313 }; 2314 2315 tpdm@4b0b000 { 2316 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2317 reg = <0x0 0x4b0b000 0x0 0x1000>; 2318 2319 clocks = <&aoss_qmp>; 2320 clock-names = "apb_pclk"; 2321 2322 qcom,cmb-element-bits = <64>; 2323 qcom,cmb-msrs-num = <32>; 2324 2325 out-ports { 2326 port { 2327 aoss_tpdm2_out: endpoint { 2328 remote-endpoint = 2329 <&aoss_tpda_in2>; 2330 }; 2331 }; 2332 }; 2333 }; 2334 2335 tpdm@4b0c000 { 2336 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2337 reg = <0x0 0x4b0c000 0x0 0x1000>; 2338 2339 clocks = <&aoss_qmp>; 2340 clock-names = "apb_pclk"; 2341 2342 qcom,cmb-element-bits = <64>; 2343 qcom,cmb-msrs-num = <32>; 2344 2345 out-ports { 2346 port { 2347 aoss_tpdm3_out: endpoint { 2348 remote-endpoint = 2349 <&aoss_tpda_in3>; 2350 }; 2351 }; 2352 }; 2353 }; 2354 2355 tpdm@4b0d000 { 2356 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2357 reg = <0x0 0x4b0d000 0x0 0x1000>; 2358 2359 clocks = <&aoss_qmp>; 2360 clock-names = "apb_pclk"; 2361 2362 qcom,dsb-element-bits = <32>; 2363 qcom,dsb-msrs-num = <32>; 2364 2365 out-ports { 2366 port { 2367 aoss_tpdm4_out: endpoint { 2368 remote-endpoint = 2369 <&aoss_tpda_in4>; 2370 }; 2371 }; 2372 }; 2373 }; 2374 2375 aoss_cti: cti@4b13000 { 2376 compatible = "arm,coresight-cti", "arm,primecell"; 2377 reg = <0x0 0x4b13000 0x0 0x1000>; 2378 2379 clocks = <&aoss_qmp>; 2380 clock-names = "apb_pclk"; 2381 }; 2382 2383 etm@6040000 { 2384 compatible = "arm,primecell"; 2385 reg = <0x0 0x6040000 0x0 0x1000>; 2386 cpu = <&CPU0>; 2387 2388 clocks = <&aoss_qmp>; 2389 clock-names = "apb_pclk"; 2390 arm,coresight-loses-context-with-cpu; 2391 qcom,skip-power-up; 2392 2393 out-ports { 2394 port { 2395 etm0_out: endpoint { 2396 remote-endpoint = 2397 <&apss_funnel0_in0>; 2398 }; 2399 }; 2400 }; 2401 }; 2402 2403 etm@6140000 { 2404 compatible = "arm,primecell"; 2405 reg = <0x0 0x6140000 0x0 0x1000>; 2406 cpu = <&CPU1>; 2407 2408 clocks = <&aoss_qmp>; 2409 clock-names = "apb_pclk"; 2410 arm,coresight-loses-context-with-cpu; 2411 qcom,skip-power-up; 2412 2413 out-ports { 2414 port { 2415 etm1_out: endpoint { 2416 remote-endpoint = 2417 <&apss_funnel0_in1>; 2418 }; 2419 }; 2420 }; 2421 }; 2422 2423 etm@6240000 { 2424 compatible = "arm,primecell"; 2425 reg = <0x0 0x6240000 0x0 0x1000>; 2426 cpu = <&CPU2>; 2427 2428 clocks = <&aoss_qmp>; 2429 clock-names = "apb_pclk"; 2430 arm,coresight-loses-context-with-cpu; 2431 qcom,skip-power-up; 2432 2433 out-ports { 2434 port { 2435 etm2_out: endpoint { 2436 remote-endpoint = 2437 <&apss_funnel0_in2>; 2438 }; 2439 }; 2440 }; 2441 }; 2442 2443 etm@6340000 { 2444 compatible = "arm,primecell"; 2445 reg = <0x0 0x6340000 0x0 0x1000>; 2446 cpu = <&CPU3>; 2447 2448 clocks = <&aoss_qmp>; 2449 clock-names = "apb_pclk"; 2450 arm,coresight-loses-context-with-cpu; 2451 qcom,skip-power-up; 2452 2453 out-ports { 2454 port { 2455 etm3_out: endpoint { 2456 remote-endpoint = 2457 <&apss_funnel0_in3>; 2458 }; 2459 }; 2460 }; 2461 }; 2462 2463 etm@6440000 { 2464 compatible = "arm,primecell"; 2465 reg = <0x0 0x6440000 0x0 0x1000>; 2466 cpu = <&CPU4>; 2467 2468 clocks = <&aoss_qmp>; 2469 clock-names = "apb_pclk"; 2470 arm,coresight-loses-context-with-cpu; 2471 qcom,skip-power-up; 2472 2473 out-ports { 2474 port { 2475 etm4_out: endpoint { 2476 remote-endpoint = 2477 <&apss_funnel0_in4>; 2478 }; 2479 }; 2480 }; 2481 }; 2482 2483 etm@6540000 { 2484 compatible = "arm,primecell"; 2485 reg = <0x0 0x6540000 0x0 0x1000>; 2486 cpu = <&CPU5>; 2487 2488 clocks = <&aoss_qmp>; 2489 clock-names = "apb_pclk"; 2490 arm,coresight-loses-context-with-cpu; 2491 qcom,skip-power-up; 2492 2493 out-ports { 2494 port { 2495 etm5_out: endpoint { 2496 remote-endpoint = 2497 <&apss_funnel0_in5>; 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 etm@6640000 { 2504 compatible = "arm,primecell"; 2505 reg = <0x0 0x6640000 0x0 0x1000>; 2506 cpu = <&CPU6>; 2507 2508 clocks = <&aoss_qmp>; 2509 clock-names = "apb_pclk"; 2510 arm,coresight-loses-context-with-cpu; 2511 qcom,skip-power-up; 2512 2513 out-ports { 2514 port { 2515 etm6_out: endpoint { 2516 remote-endpoint = 2517 <&apss_funnel0_in6>; 2518 }; 2519 }; 2520 }; 2521 }; 2522 2523 etm@6740000 { 2524 compatible = "arm,primecell"; 2525 reg = <0x0 0x6740000 0x0 0x1000>; 2526 cpu = <&CPU7>; 2527 2528 clocks = <&aoss_qmp>; 2529 clock-names = "apb_pclk"; 2530 arm,coresight-loses-context-with-cpu; 2531 qcom,skip-power-up; 2532 2533 out-ports { 2534 port { 2535 etm7_out: endpoint { 2536 remote-endpoint = 2537 <&apss_funnel0_in7>; 2538 }; 2539 }; 2540 }; 2541 }; 2542 2543 funnel@6800000 { 2544 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2545 reg = <0x0 0x6800000 0x0 0x1000>; 2546 2547 clocks = <&aoss_qmp>; 2548 clock-names = "apb_pclk"; 2549 2550 out-ports { 2551 port { 2552 apss_funnel0_out: endpoint { 2553 remote-endpoint = 2554 <&apss_funnel1_in0>; 2555 }; 2556 }; 2557 }; 2558 2559 in-ports { 2560 #address-cells = <1>; 2561 #size-cells = <0>; 2562 2563 port@0 { 2564 reg = <0>; 2565 apss_funnel0_in0: endpoint { 2566 remote-endpoint = 2567 <&etm0_out>; 2568 }; 2569 }; 2570 2571 port@1 { 2572 reg = <1>; 2573 apss_funnel0_in1: endpoint { 2574 remote-endpoint = 2575 <&etm1_out>; 2576 }; 2577 }; 2578 2579 port@2 { 2580 reg = <2>; 2581 apss_funnel0_in2: endpoint { 2582 remote-endpoint = 2583 <&etm2_out>; 2584 }; 2585 }; 2586 2587 port@3 { 2588 reg = <3>; 2589 apss_funnel0_in3: endpoint { 2590 remote-endpoint = 2591 <&etm3_out>; 2592 }; 2593 }; 2594 2595 port@4 { 2596 reg = <4>; 2597 apss_funnel0_in4: endpoint { 2598 remote-endpoint = 2599 <&etm4_out>; 2600 }; 2601 }; 2602 2603 port@5 { 2604 reg = <5>; 2605 apss_funnel0_in5: endpoint { 2606 remote-endpoint = 2607 <&etm5_out>; 2608 }; 2609 }; 2610 2611 port@6 { 2612 reg = <6>; 2613 apss_funnel0_in6: endpoint { 2614 remote-endpoint = 2615 <&etm6_out>; 2616 }; 2617 }; 2618 2619 port@7 { 2620 reg = <7>; 2621 apss_funnel0_in7: endpoint { 2622 remote-endpoint = 2623 <&etm7_out>; 2624 }; 2625 }; 2626 }; 2627 }; 2628 2629 funnel@6810000 { 2630 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2631 reg = <0x0 0x6810000 0x0 0x1000>; 2632 2633 clocks = <&aoss_qmp>; 2634 clock-names = "apb_pclk"; 2635 2636 out-ports { 2637 port { 2638 apss_funnel1_out: endpoint { 2639 remote-endpoint = 2640 <&funnel1_in4>; 2641 }; 2642 }; 2643 }; 2644 2645 in-ports { 2646 #address-cells = <1>; 2647 #size-cells = <0>; 2648 2649 port@0 { 2650 reg = <0>; 2651 apss_funnel1_in0: endpoint { 2652 remote-endpoint = 2653 <&apss_funnel0_out>; 2654 }; 2655 }; 2656 2657 port@3 { 2658 reg = <3>; 2659 apss_funnel1_in3: endpoint { 2660 remote-endpoint = 2661 <&apss_tpda_out>; 2662 }; 2663 }; 2664 }; 2665 }; 2666 2667 tpdm@6860000 { 2668 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2669 reg = <0x0 0x6860000 0x0 0x1000>; 2670 2671 clocks = <&aoss_qmp>; 2672 clock-names = "apb_pclk"; 2673 2674 qcom,cmb-element-bits = <64>; 2675 qcom,cmb-msrs-num = <32>; 2676 2677 out-ports { 2678 port { 2679 apss_tpdm3_out: endpoint { 2680 remote-endpoint = 2681 <&apss_tpda_in3>; 2682 }; 2683 }; 2684 }; 2685 }; 2686 2687 tpdm@6861000 { 2688 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2689 reg = <0x0 0x6861000 0x0 0x1000>; 2690 2691 clocks = <&aoss_qmp>; 2692 clock-names = "apb_pclk"; 2693 2694 qcom,dsb-element-bits = <32>; 2695 qcom,dsb-msrs-num = <32>; 2696 2697 out-ports { 2698 port { 2699 apss_tpdm4_out: endpoint { 2700 remote-endpoint = 2701 <&apss_tpda_in4>; 2702 }; 2703 }; 2704 }; 2705 }; 2706 2707 tpda@6863000 { 2708 compatible = "qcom,coresight-tpda", "arm,primecell"; 2709 reg = <0x0 0x6863000 0x0 0x1000>; 2710 2711 clocks = <&aoss_qmp>; 2712 clock-names = "apb_pclk"; 2713 2714 out-ports { 2715 port { 2716 apss_tpda_out: endpoint { 2717 remote-endpoint = 2718 <&apss_funnel1_in3>; 2719 }; 2720 }; 2721 }; 2722 2723 in-ports { 2724 #address-cells = <1>; 2725 #size-cells = <0>; 2726 2727 port@0 { 2728 reg = <0>; 2729 apss_tpda_in0: endpoint { 2730 remote-endpoint = 2731 <&apss_tpdm0_out>; 2732 }; 2733 }; 2734 2735 port@1 { 2736 reg = <1>; 2737 apss_tpda_in1: endpoint { 2738 remote-endpoint = 2739 <&apss_tpdm1_out>; 2740 }; 2741 }; 2742 2743 port@2 { 2744 reg = <2>; 2745 apss_tpda_in2: endpoint { 2746 remote-endpoint = 2747 <&apss_tpdm2_out>; 2748 }; 2749 }; 2750 2751 port@3 { 2752 reg = <3>; 2753 apss_tpda_in3: endpoint { 2754 remote-endpoint = 2755 <&apss_tpdm3_out>; 2756 }; 2757 }; 2758 2759 port@4 { 2760 reg = <4>; 2761 apss_tpda_in4: endpoint { 2762 remote-endpoint = 2763 <&apss_tpdm4_out>; 2764 }; 2765 }; 2766 }; 2767 }; 2768 2769 tpdm@68a0000 { 2770 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2771 reg = <0x0 0x68a0000 0x0 0x1000>; 2772 2773 clocks = <&aoss_qmp>; 2774 clock-names = "apb_pclk"; 2775 2776 qcom,cmb-element-bits = <32>; 2777 qcom,cmb-msrs-num = <32>; 2778 2779 out-ports { 2780 port { 2781 apss_tpdm0_out: endpoint { 2782 remote-endpoint = 2783 <&apss_tpda_in0>; 2784 }; 2785 }; 2786 }; 2787 }; 2788 2789 tpdm@68b0000 { 2790 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2791 reg = <0x0 0x68b0000 0x0 0x1000>; 2792 2793 clocks = <&aoss_qmp>; 2794 clock-names = "apb_pclk"; 2795 2796 qcom,cmb-element-bits = <32>; 2797 qcom,cmb-msrs-num = <32>; 2798 2799 out-ports { 2800 port { 2801 apss_tpdm1_out: endpoint { 2802 remote-endpoint = 2803 <&apss_tpda_in1>; 2804 }; 2805 }; 2806 }; 2807 }; 2808 2809 tpdm@68c0000 { 2810 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2811 reg = <0x0 0x68c0000 0x0 0x1000>; 2812 2813 clocks = <&aoss_qmp>; 2814 clock-names = "apb_pclk"; 2815 2816 qcom,dsb-element-bits = <32>; 2817 qcom,dsb-msrs-num = <32>; 2818 2819 out-ports { 2820 port { 2821 apss_tpdm2_out: endpoint { 2822 remote-endpoint = 2823 <&apss_tpda_in2>; 2824 }; 2825 }; 2826 }; 2827 }; 2828 2829 usb_0_hsphy: phy@88e4000 { 2830 compatible = "qcom,sa8775p-usb-hs-phy", 2831 "qcom,usb-snps-hs-5nm-phy"; 2832 reg = <0 0x088e4000 0 0x120>; 2833 clocks = <&rpmhcc RPMH_CXO_CLK>; 2834 clock-names = "ref"; 2835 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 2836 2837 #phy-cells = <0>; 2838 2839 status = "disabled"; 2840 }; 2841 2842 usb_0_qmpphy: phy@88e8000 { 2843 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 2844 reg = <0 0x088e8000 0 0x2000>; 2845 2846 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2847 <&gcc GCC_USB_CLKREF_EN>, 2848 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2849 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2850 clock-names = "aux", "ref", "com_aux", "pipe"; 2851 2852 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2853 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2854 reset-names = "phy", "phy_phy"; 2855 2856 power-domains = <&gcc USB30_PRIM_GDSC>; 2857 2858 #clock-cells = <0>; 2859 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2860 2861 #phy-cells = <0>; 2862 2863 status = "disabled"; 2864 }; 2865 2866 usb_0: usb@a6f8800 { 2867 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 2868 reg = <0 0x0a6f8800 0 0x400>; 2869 #address-cells = <2>; 2870 #size-cells = <2>; 2871 ranges; 2872 2873 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2874 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2875 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2876 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2877 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2878 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 2879 2880 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2881 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2882 assigned-clock-rates = <19200000>, <200000000>; 2883 2884 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 2885 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2886 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2887 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2888 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 2889 interrupt-names = "pwr_event", 2890 "hs_phy_irq", 2891 "dp_hs_phy_irq", 2892 "dm_hs_phy_irq", 2893 "ss_phy_irq"; 2894 2895 power-domains = <&gcc USB30_PRIM_GDSC>; 2896 required-opps = <&rpmhpd_opp_nom>; 2897 2898 resets = <&gcc GCC_USB30_PRIM_BCR>; 2899 2900 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2901 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2902 interconnect-names = "usb-ddr", "apps-usb"; 2903 2904 wakeup-source; 2905 2906 status = "disabled"; 2907 2908 usb_0_dwc3: usb@a600000 { 2909 compatible = "snps,dwc3"; 2910 reg = <0 0x0a600000 0 0xe000>; 2911 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 2912 iommus = <&apps_smmu 0x080 0x0>; 2913 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 2914 phy-names = "usb2-phy", "usb3-phy"; 2915 }; 2916 }; 2917 2918 usb_1_hsphy: phy@88e6000 { 2919 compatible = "qcom,sa8775p-usb-hs-phy", 2920 "qcom,usb-snps-hs-5nm-phy"; 2921 reg = <0 0x088e6000 0 0x120>; 2922 clocks = <&gcc GCC_USB_CLKREF_EN>; 2923 clock-names = "ref"; 2924 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 2925 2926 #phy-cells = <0>; 2927 2928 status = "disabled"; 2929 }; 2930 2931 usb_1_qmpphy: phy@88ea000 { 2932 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 2933 reg = <0 0x088ea000 0 0x2000>; 2934 2935 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2936 <&gcc GCC_USB_CLKREF_EN>, 2937 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2938 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2939 clock-names = "aux", "ref", "com_aux", "pipe"; 2940 2941 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2942 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2943 reset-names = "phy", "phy_phy"; 2944 2945 power-domains = <&gcc USB30_SEC_GDSC>; 2946 2947 #clock-cells = <0>; 2948 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2949 2950 #phy-cells = <0>; 2951 2952 status = "disabled"; 2953 }; 2954 2955 usb_1: usb@a8f8800 { 2956 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 2957 reg = <0 0x0a8f8800 0 0x400>; 2958 #address-cells = <2>; 2959 #size-cells = <2>; 2960 ranges; 2961 2962 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2963 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2964 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2965 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2966 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 2967 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 2968 2969 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2970 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2971 assigned-clock-rates = <19200000>, <200000000>; 2972 2973 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 2974 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2975 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2976 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 2977 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 2978 interrupt-names = "pwr_event", 2979 "hs_phy_irq", 2980 "dp_hs_phy_irq", 2981 "dm_hs_phy_irq", 2982 "ss_phy_irq"; 2983 2984 power-domains = <&gcc USB30_SEC_GDSC>; 2985 required-opps = <&rpmhpd_opp_nom>; 2986 2987 resets = <&gcc GCC_USB30_SEC_BCR>; 2988 2989 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2990 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2991 interconnect-names = "usb-ddr", "apps-usb"; 2992 2993 wakeup-source; 2994 2995 status = "disabled"; 2996 2997 usb_1_dwc3: usb@a800000 { 2998 compatible = "snps,dwc3"; 2999 reg = <0 0x0a800000 0 0xe000>; 3000 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 3001 iommus = <&apps_smmu 0x0a0 0x0>; 3002 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 3003 phy-names = "usb2-phy", "usb3-phy"; 3004 }; 3005 }; 3006 3007 usb_2_hsphy: phy@88e7000 { 3008 compatible = "qcom,sa8775p-usb-hs-phy", 3009 "qcom,usb-snps-hs-5nm-phy"; 3010 reg = <0 0x088e7000 0 0x120>; 3011 clocks = <&gcc GCC_USB_CLKREF_EN>; 3012 clock-names = "ref"; 3013 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 3014 3015 #phy-cells = <0>; 3016 3017 status = "disabled"; 3018 }; 3019 3020 usb_2: usb@a4f8800 { 3021 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3022 reg = <0 0x0a4f8800 0 0x400>; 3023 #address-cells = <2>; 3024 #size-cells = <2>; 3025 ranges; 3026 3027 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 3028 <&gcc GCC_USB20_MASTER_CLK>, 3029 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 3030 <&gcc GCC_USB20_SLEEP_CLK>, 3031 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 3032 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3033 3034 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3035 <&gcc GCC_USB20_MASTER_CLK>; 3036 assigned-clock-rates = <19200000>, <200000000>; 3037 3038 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 3039 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 3040 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3041 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3042 interrupt-names = "pwr_event", 3043 "hs_phy_irq", 3044 "dp_hs_phy_irq", 3045 "dm_hs_phy_irq"; 3046 3047 power-domains = <&gcc USB20_PRIM_GDSC>; 3048 required-opps = <&rpmhpd_opp_nom>; 3049 3050 resets = <&gcc GCC_USB20_PRIM_BCR>; 3051 3052 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 3054 interconnect-names = "usb-ddr", "apps-usb"; 3055 3056 wakeup-source; 3057 3058 status = "disabled"; 3059 3060 usb_2_dwc3: usb@a400000 { 3061 compatible = "snps,dwc3"; 3062 reg = <0 0x0a400000 0 0xe000>; 3063 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 3064 iommus = <&apps_smmu 0x020 0x0>; 3065 phys = <&usb_2_hsphy>; 3066 phy-names = "usb2-phy"; 3067 }; 3068 }; 3069 3070 tcsr_mutex: hwlock@1f40000 { 3071 compatible = "qcom,tcsr-mutex"; 3072 reg = <0x0 0x01f40000 0x0 0x20000>; 3073 #hwlock-cells = <1>; 3074 }; 3075 3076 gpucc: clock-controller@3d90000 { 3077 compatible = "qcom,sa8775p-gpucc"; 3078 reg = <0x0 0x03d90000 0x0 0xa000>; 3079 clocks = <&rpmhcc RPMH_CXO_CLK>, 3080 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3081 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3082 clock-names = "bi_tcxo", 3083 "gcc_gpu_gpll0_clk_src", 3084 "gcc_gpu_gpll0_div_clk_src"; 3085 #clock-cells = <1>; 3086 #reset-cells = <1>; 3087 #power-domain-cells = <1>; 3088 }; 3089 3090 adreno_smmu: iommu@3da0000 { 3091 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 3092 "qcom,smmu-500", "arm,mmu-500"; 3093 reg = <0x0 0x03da0000 0x0 0x20000>; 3094 #iommu-cells = <2>; 3095 #global-interrupts = <2>; 3096 dma-coherent; 3097 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3098 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3099 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3100 <&gpucc GPU_CC_AHB_CLK>, 3101 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3102 <&gpucc GPU_CC_CX_GMU_CLK>, 3103 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3104 <&gpucc GPU_CC_HUB_AON_CLK>; 3105 clock-names = "gcc_gpu_memnoc_gfx_clk", 3106 "gcc_gpu_snoc_dvm_gfx_clk", 3107 "gpu_cc_ahb_clk", 3108 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3109 "gpu_cc_cx_gmu_clk", 3110 "gpu_cc_hub_cx_int_clk", 3111 "gpu_cc_hub_aon_clk"; 3112 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3124 }; 3125 3126 serdes0: phy@8901000 { 3127 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3128 reg = <0x0 0x08901000 0x0 0xe10>; 3129 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3130 clock-names = "sgmi_ref"; 3131 #phy-cells = <0>; 3132 status = "disabled"; 3133 }; 3134 3135 serdes1: phy@8902000 { 3136 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3137 reg = <0x0 0x08902000 0x0 0xe10>; 3138 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3139 clock-names = "sgmi_ref"; 3140 #phy-cells = <0>; 3141 status = "disabled"; 3142 }; 3143 3144 pmu@9091000 { 3145 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3146 reg = <0x0 0x9091000 0x0 0x1000>; 3147 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 3148 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3150 3151 operating-points-v2 = <&llcc_bwmon_opp_table>; 3152 3153 llcc_bwmon_opp_table: opp-table { 3154 compatible = "operating-points-v2"; 3155 3156 opp-0 { 3157 opp-peak-kBps = <762000>; 3158 }; 3159 3160 opp-1 { 3161 opp-peak-kBps = <1720000>; 3162 }; 3163 3164 opp-2 { 3165 opp-peak-kBps = <2086000>; 3166 }; 3167 3168 opp-3 { 3169 opp-peak-kBps = <2601000>; 3170 }; 3171 3172 opp-4 { 3173 opp-peak-kBps = <2929000>; 3174 }; 3175 3176 opp-5 { 3177 opp-peak-kBps = <5931000>; 3178 }; 3179 3180 opp-6 { 3181 opp-peak-kBps = <6515000>; 3182 }; 3183 3184 opp-7 { 3185 opp-peak-kBps = <7984000>; 3186 }; 3187 3188 opp-8 { 3189 opp-peak-kBps = <10437000>; 3190 }; 3191 3192 opp-9 { 3193 opp-peak-kBps = <12195000>; 3194 }; 3195 }; 3196 }; 3197 3198 pmu@90b5400 { 3199 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3200 reg = <0x0 0x90b5400 0x0 0x600>; 3201 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3202 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3203 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3204 3205 operating-points-v2 = <&cpu_bwmon_opp_table>; 3206 3207 cpu_bwmon_opp_table: opp-table { 3208 compatible = "operating-points-v2"; 3209 3210 opp-0 { 3211 opp-peak-kBps = <9155000>; 3212 }; 3213 3214 opp-1 { 3215 opp-peak-kBps = <12298000>; 3216 }; 3217 3218 opp-2 { 3219 opp-peak-kBps = <14236000>; 3220 }; 3221 3222 opp-3 { 3223 opp-peak-kBps = <16265000>; 3224 }; 3225 }; 3226 3227 }; 3228 3229 pmu@90b6400 { 3230 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3231 reg = <0x0 0x90b6400 0x0 0x600>; 3232 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3233 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3234 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3235 3236 operating-points-v2 = <&cpu_bwmon_opp_table>; 3237 }; 3238 3239 llcc: system-cache-controller@9200000 { 3240 compatible = "qcom,sa8775p-llcc"; 3241 reg = <0x0 0x09200000 0x0 0x80000>, 3242 <0x0 0x09300000 0x0 0x80000>, 3243 <0x0 0x09400000 0x0 0x80000>, 3244 <0x0 0x09500000 0x0 0x80000>, 3245 <0x0 0x09600000 0x0 0x80000>, 3246 <0x0 0x09700000 0x0 0x80000>, 3247 <0x0 0x09a00000 0x0 0x80000>; 3248 reg-names = "llcc0_base", 3249 "llcc1_base", 3250 "llcc2_base", 3251 "llcc3_base", 3252 "llcc4_base", 3253 "llcc5_base", 3254 "llcc_broadcast_base"; 3255 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 3256 }; 3257 3258 pdc: interrupt-controller@b220000 { 3259 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 3260 reg = <0x0 0x0b220000 0x0 0x30000>, 3261 <0x0 0x17c000f0 0x0 0x64>; 3262 qcom,pdc-ranges = <0 480 40>, 3263 <40 140 14>, 3264 <54 263 1>, 3265 <55 306 4>, 3266 <59 312 3>, 3267 <62 374 2>, 3268 <64 434 2>, 3269 <66 438 2>, 3270 <70 520 1>, 3271 <73 523 1>, 3272 <118 568 6>, 3273 <124 609 3>, 3274 <159 638 1>, 3275 <160 720 3>, 3276 <169 728 30>, 3277 <199 416 2>, 3278 <201 449 1>, 3279 <202 89 1>, 3280 <203 451 1>, 3281 <204 462 1>, 3282 <205 264 1>, 3283 <206 579 1>, 3284 <207 653 1>, 3285 <208 656 1>, 3286 <209 659 1>, 3287 <210 122 1>, 3288 <211 699 1>, 3289 <212 705 1>, 3290 <213 450 1>, 3291 <214 643 2>, 3292 <216 646 5>, 3293 <221 390 5>, 3294 <226 700 2>, 3295 <228 440 1>, 3296 <229 663 1>, 3297 <230 524 2>, 3298 <232 612 3>, 3299 <235 723 5>; 3300 #interrupt-cells = <2>; 3301 interrupt-parent = <&intc>; 3302 interrupt-controller; 3303 }; 3304 3305 tsens2: thermal-sensor@c251000 { 3306 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3307 reg = <0x0 0x0c251000 0x0 0x1ff>, 3308 <0x0 0x0c224000 0x0 0x8>; 3309 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 3311 #qcom,sensors = <13>; 3312 interrupt-names = "uplow", "critical"; 3313 #thermal-sensor-cells = <1>; 3314 }; 3315 3316 tsens3: thermal-sensor@c252000 { 3317 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3318 reg = <0x0 0x0c252000 0x0 0x1ff>, 3319 <0x0 0x0c225000 0x0 0x8>; 3320 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 3322 #qcom,sensors = <13>; 3323 interrupt-names = "uplow", "critical"; 3324 #thermal-sensor-cells = <1>; 3325 }; 3326 3327 tsens0: thermal-sensor@c263000 { 3328 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3329 reg = <0x0 0x0c263000 0x0 0x1ff>, 3330 <0x0 0x0c222000 0x0 0x8>; 3331 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3333 #qcom,sensors = <12>; 3334 interrupt-names = "uplow", "critical"; 3335 #thermal-sensor-cells = <1>; 3336 }; 3337 3338 tsens1: thermal-sensor@c265000 { 3339 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3340 reg = <0x0 0x0c265000 0x0 0x1ff>, 3341 <0x0 0x0c223000 0x0 0x8>; 3342 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3344 #qcom,sensors = <12>; 3345 interrupt-names = "uplow", "critical"; 3346 #thermal-sensor-cells = <1>; 3347 }; 3348 3349 aoss_qmp: power-management@c300000 { 3350 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 3351 reg = <0x0 0x0c300000 0x0 0x400>; 3352 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3353 IPCC_MPROC_SIGNAL_GLINK_QMP 3354 IRQ_TYPE_EDGE_RISING>; 3355 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3356 #clock-cells = <0>; 3357 }; 3358 3359 sram@c3f0000 { 3360 compatible = "qcom,rpmh-stats"; 3361 reg = <0x0 0x0c3f0000 0x0 0x400>; 3362 }; 3363 3364 spmi_bus: spmi@c440000 { 3365 compatible = "qcom,spmi-pmic-arb"; 3366 reg = <0x0 0x0c440000 0x0 0x1100>, 3367 <0x0 0x0c600000 0x0 0x2000000>, 3368 <0x0 0x0e600000 0x0 0x100000>, 3369 <0x0 0x0e700000 0x0 0xa0000>, 3370 <0x0 0x0c40a000 0x0 0x26000>; 3371 reg-names = "core", 3372 "chnls", 3373 "obsrvr", 3374 "intr", 3375 "cnfg"; 3376 qcom,channel = <0>; 3377 qcom,ee = <0>; 3378 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3379 interrupt-names = "periph_irq"; 3380 interrupt-controller; 3381 #interrupt-cells = <4>; 3382 #address-cells = <2>; 3383 #size-cells = <0>; 3384 }; 3385 3386 tlmm: pinctrl@f000000 { 3387 compatible = "qcom,sa8775p-tlmm"; 3388 reg = <0x0 0x0f000000 0x0 0x1000000>; 3389 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3390 gpio-controller; 3391 #gpio-cells = <2>; 3392 interrupt-controller; 3393 #interrupt-cells = <2>; 3394 gpio-ranges = <&tlmm 0 0 149>; 3395 wakeup-parent = <&pdc>; 3396 }; 3397 3398 sram: sram@146d8000 { 3399 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 3400 reg = <0x0 0x146d8000 0x0 0x1000>; 3401 ranges = <0x0 0x0 0x146d8000 0x1000>; 3402 3403 #address-cells = <1>; 3404 #size-cells = <1>; 3405 3406 pil-reloc@94c { 3407 compatible = "qcom,pil-reloc-info"; 3408 reg = <0x94c 0xc8>; 3409 }; 3410 }; 3411 3412 apps_smmu: iommu@15000000 { 3413 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3414 reg = <0x0 0x15000000 0x0 0x100000>; 3415 #iommu-cells = <2>; 3416 #global-interrupts = <2>; 3417 dma-coherent; 3418 3419 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 3549 }; 3550 3551 pcie_smmu: iommu@15200000 { 3552 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3553 reg = <0x0 0x15200000 0x0 0x80000>; 3554 #iommu-cells = <2>; 3555 #global-interrupts = <2>; 3556 dma-coherent; 3557 3558 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3624 }; 3625 3626 intc: interrupt-controller@17a00000 { 3627 compatible = "arm,gic-v3"; 3628 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3629 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3630 interrupt-controller; 3631 #interrupt-cells = <3>; 3632 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3633 #redistributor-regions = <1>; 3634 redistributor-stride = <0x0 0x20000>; 3635 }; 3636 3637 watchdog@17c10000 { 3638 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 3639 reg = <0x0 0x17c10000 0x0 0x1000>; 3640 clocks = <&sleep_clk>; 3641 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3642 }; 3643 3644 memtimer: timer@17c20000 { 3645 compatible = "arm,armv7-timer-mem"; 3646 reg = <0x0 0x17c20000 0x0 0x1000>; 3647 ranges = <0x0 0x0 0x0 0x20000000>; 3648 #address-cells = <1>; 3649 #size-cells = <1>; 3650 3651 frame@17c21000 { 3652 reg = <0x17c21000 0x1000>, 3653 <0x17c22000 0x1000>; 3654 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3656 frame-number = <0>; 3657 }; 3658 3659 frame@17c23000 { 3660 reg = <0x17c23000 0x1000>; 3661 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3662 frame-number = <1>; 3663 status = "disabled"; 3664 }; 3665 3666 frame@17c25000 { 3667 reg = <0x17c25000 0x1000>; 3668 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3669 frame-number = <2>; 3670 status = "disabled"; 3671 }; 3672 3673 frame@17c27000 { 3674 reg = <0x17c27000 0x1000>; 3675 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3676 frame-number = <3>; 3677 status = "disabled"; 3678 }; 3679 3680 frame@17c29000 { 3681 reg = <0x17c29000 0x1000>; 3682 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3683 frame-number = <4>; 3684 status = "disabled"; 3685 }; 3686 3687 frame@17c2b000 { 3688 reg = <0x17c2b000 0x1000>; 3689 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3690 frame-number = <5>; 3691 status = "disabled"; 3692 }; 3693 3694 frame@17c2d000 { 3695 reg = <0x17c2d000 0x1000>; 3696 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3697 frame-number = <6>; 3698 status = "disabled"; 3699 }; 3700 }; 3701 3702 apps_rsc: rsc@18200000 { 3703 compatible = "qcom,rpmh-rsc"; 3704 reg = <0x0 0x18200000 0x0 0x10000>, 3705 <0x0 0x18210000 0x0 0x10000>, 3706 <0x0 0x18220000 0x0 0x10000>; 3707 reg-names = "drv-0", "drv-1", "drv-2"; 3708 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3711 qcom,tcs-offset = <0xd00>; 3712 qcom,drv-id = <2>; 3713 qcom,tcs-config = <ACTIVE_TCS 2>, 3714 <SLEEP_TCS 3>, 3715 <WAKE_TCS 3>, 3716 <CONTROL_TCS 0>; 3717 label = "apps_rsc"; 3718 3719 apps_bcm_voter: bcm-voter { 3720 compatible = "qcom,bcm-voter"; 3721 }; 3722 3723 rpmhcc: clock-controller { 3724 compatible = "qcom,sa8775p-rpmh-clk"; 3725 #clock-cells = <1>; 3726 clock-names = "xo"; 3727 clocks = <&xo_board_clk>; 3728 }; 3729 3730 rpmhpd: power-controller { 3731 compatible = "qcom,sa8775p-rpmhpd"; 3732 #power-domain-cells = <1>; 3733 operating-points-v2 = <&rpmhpd_opp_table>; 3734 3735 rpmhpd_opp_table: opp-table { 3736 compatible = "operating-points-v2"; 3737 3738 rpmhpd_opp_ret: opp-0 { 3739 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3740 }; 3741 3742 rpmhpd_opp_min_svs: opp-1 { 3743 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3744 }; 3745 3746 rpmhpd_opp_low_svs: opp2 { 3747 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3748 }; 3749 3750 rpmhpd_opp_svs: opp3 { 3751 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3752 }; 3753 3754 rpmhpd_opp_svs_l1: opp-4 { 3755 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3756 }; 3757 3758 rpmhpd_opp_nom: opp-5 { 3759 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3760 }; 3761 3762 rpmhpd_opp_nom_l1: opp-6 { 3763 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3764 }; 3765 3766 rpmhpd_opp_nom_l2: opp-7 { 3767 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3768 }; 3769 3770 rpmhpd_opp_turbo: opp-8 { 3771 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3772 }; 3773 3774 rpmhpd_opp_turbo_l1: opp-9 { 3775 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3776 }; 3777 }; 3778 }; 3779 }; 3780 3781 cpufreq_hw: cpufreq@18591000 { 3782 compatible = "qcom,sa8775p-cpufreq-epss", 3783 "qcom,cpufreq-epss"; 3784 reg = <0x0 0x18591000 0x0 0x1000>, 3785 <0x0 0x18593000 0x0 0x1000>; 3786 reg-names = "freq-domain0", "freq-domain1"; 3787 3788 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3789 clock-names = "xo", "alternate"; 3790 3791 #freq-domain-cells = <1>; 3792 }; 3793 3794 remoteproc_gpdsp0: remoteproc@20c00000 { 3795 compatible = "qcom,sa8775p-gpdsp0-pas"; 3796 reg = <0x0 0x20c00000 0x0 0x10000>; 3797 3798 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 3799 <&smp2p_gpdsp0_in 0 0>, 3800 <&smp2p_gpdsp0_in 1 0>, 3801 <&smp2p_gpdsp0_in 2 0>, 3802 <&smp2p_gpdsp0_in 3 0>; 3803 interrupt-names = "wdog", "fatal", "ready", 3804 "handover", "stop-ack"; 3805 3806 clocks = <&rpmhcc RPMH_CXO_CLK>; 3807 clock-names = "xo"; 3808 3809 power-domains = <&rpmhpd RPMHPD_CX>, 3810 <&rpmhpd RPMHPD_MXC>; 3811 power-domain-names = "cx", "mxc"; 3812 3813 interconnects = <&gpdsp_anoc MASTER_DSP0 0 3814 &config_noc SLAVE_CLK_CTL 0>; 3815 3816 memory-region = <&pil_gdsp0_mem>; 3817 3818 qcom,qmp = <&aoss_qmp>; 3819 3820 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 3821 qcom,smem-state-names = "stop"; 3822 3823 status = "disabled"; 3824 3825 glink-edge { 3826 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 3827 IPCC_MPROC_SIGNAL_GLINK_QMP 3828 IRQ_TYPE_EDGE_RISING>; 3829 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 3830 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3831 3832 label = "gpdsp0"; 3833 qcom,remote-pid = <17>; 3834 }; 3835 }; 3836 3837 remoteproc_gpdsp1: remoteproc@21c00000 { 3838 compatible = "qcom,sa8775p-gpdsp1-pas"; 3839 reg = <0x0 0x21c00000 0x0 0x10000>; 3840 3841 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 3842 <&smp2p_gpdsp1_in 0 0>, 3843 <&smp2p_gpdsp1_in 1 0>, 3844 <&smp2p_gpdsp1_in 2 0>, 3845 <&smp2p_gpdsp1_in 3 0>; 3846 interrupt-names = "wdog", "fatal", "ready", 3847 "handover", "stop-ack"; 3848 3849 clocks = <&rpmhcc RPMH_CXO_CLK>; 3850 clock-names = "xo"; 3851 3852 power-domains = <&rpmhpd RPMHPD_CX>, 3853 <&rpmhpd RPMHPD_MXC>; 3854 power-domain-names = "cx", "mxc"; 3855 3856 interconnects = <&gpdsp_anoc MASTER_DSP1 0 3857 &config_noc SLAVE_CLK_CTL 0>; 3858 3859 memory-region = <&pil_gdsp1_mem>; 3860 3861 qcom,qmp = <&aoss_qmp>; 3862 3863 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 3864 qcom,smem-state-names = "stop"; 3865 3866 status = "disabled"; 3867 3868 glink-edge { 3869 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 3870 IPCC_MPROC_SIGNAL_GLINK_QMP 3871 IRQ_TYPE_EDGE_RISING>; 3872 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 3873 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3874 3875 label = "gpdsp1"; 3876 qcom,remote-pid = <18>; 3877 }; 3878 }; 3879 3880 ethernet1: ethernet@23000000 { 3881 compatible = "qcom,sa8775p-ethqos"; 3882 reg = <0x0 0x23000000 0x0 0x10000>, 3883 <0x0 0x23016000 0x0 0x100>; 3884 reg-names = "stmmaceth", "rgmii"; 3885 3886 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 3888 interrupt-names = "macirq", "sfty"; 3889 3890 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 3891 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 3892 <&gcc GCC_EMAC1_PTP_CLK>, 3893 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 3894 clock-names = "stmmaceth", 3895 "pclk", 3896 "ptp_ref", 3897 "phyaux"; 3898 3899 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 3900 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3901 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3902 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; 3903 interconnect-names = "mac-mem", "cpu-mac"; 3904 3905 power-domains = <&gcc EMAC1_GDSC>; 3906 3907 phys = <&serdes1>; 3908 phy-names = "serdes"; 3909 3910 iommus = <&apps_smmu 0x140 0xf>; 3911 dma-coherent; 3912 3913 snps,tso; 3914 snps,pbl = <32>; 3915 rx-fifo-depth = <16384>; 3916 tx-fifo-depth = <16384>; 3917 3918 status = "disabled"; 3919 }; 3920 3921 ethernet0: ethernet@23040000 { 3922 compatible = "qcom,sa8775p-ethqos"; 3923 reg = <0x0 0x23040000 0x0 0x10000>, 3924 <0x0 0x23056000 0x0 0x100>; 3925 reg-names = "stmmaceth", "rgmii"; 3926 3927 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 3929 interrupt-names = "macirq", "sfty"; 3930 3931 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 3932 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 3933 <&gcc GCC_EMAC0_PTP_CLK>, 3934 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 3935 clock-names = "stmmaceth", 3936 "pclk", 3937 "ptp_ref", 3938 "phyaux"; 3939 3940 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 3941 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3942 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3943 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; 3944 interconnect-names = "mac-mem", "cpu-mac"; 3945 3946 power-domains = <&gcc EMAC0_GDSC>; 3947 3948 phys = <&serdes0>; 3949 phy-names = "serdes"; 3950 3951 iommus = <&apps_smmu 0x120 0xf>; 3952 dma-coherent; 3953 3954 snps,tso; 3955 snps,pbl = <32>; 3956 rx-fifo-depth = <16384>; 3957 tx-fifo-depth = <16384>; 3958 3959 status = "disabled"; 3960 }; 3961 3962 remoteproc_cdsp0: remoteproc@26300000 { 3963 compatible = "qcom,sa8775p-cdsp0-pas"; 3964 reg = <0x0 0x26300000 0x0 0x10000>; 3965 3966 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3967 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 3968 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 3969 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 3970 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 3971 interrupt-names = "wdog", "fatal", "ready", 3972 "handover", "stop-ack"; 3973 3974 clocks = <&rpmhcc RPMH_CXO_CLK>; 3975 clock-names = "xo"; 3976 3977 power-domains = <&rpmhpd RPMHPD_CX>, 3978 <&rpmhpd RPMHPD_MXC>, 3979 <&rpmhpd RPMHPD_NSP0>; 3980 power-domain-names = "cx", "mxc", "nsp"; 3981 3982 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 3983 &mc_virt SLAVE_EBI1 0>; 3984 3985 memory-region = <&pil_cdsp0_mem>; 3986 3987 qcom,qmp = <&aoss_qmp>; 3988 3989 qcom,smem-states = <&smp2p_cdsp0_out 0>; 3990 qcom,smem-state-names = "stop"; 3991 3992 status = "disabled"; 3993 3994 glink-edge { 3995 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3996 IPCC_MPROC_SIGNAL_GLINK_QMP 3997 IRQ_TYPE_EDGE_RISING>; 3998 mboxes = <&ipcc IPCC_CLIENT_CDSP 3999 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4000 4001 label = "cdsp"; 4002 qcom,remote-pid = <5>; 4003 4004 fastrpc { 4005 compatible = "qcom,fastrpc"; 4006 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4007 label = "cdsp"; 4008 #address-cells = <1>; 4009 #size-cells = <0>; 4010 4011 compute-cb@1 { 4012 compatible = "qcom,fastrpc-compute-cb"; 4013 reg = <1>; 4014 iommus = <&apps_smmu 0x2141 0x04a0>, 4015 <&apps_smmu 0x2181 0x0400>; 4016 dma-coherent; 4017 }; 4018 4019 compute-cb@2 { 4020 compatible = "qcom,fastrpc-compute-cb"; 4021 reg = <2>; 4022 iommus = <&apps_smmu 0x2142 0x04a0>, 4023 <&apps_smmu 0x2182 0x0400>; 4024 dma-coherent; 4025 }; 4026 4027 compute-cb@3 { 4028 compatible = "qcom,fastrpc-compute-cb"; 4029 reg = <3>; 4030 iommus = <&apps_smmu 0x2143 0x04a0>, 4031 <&apps_smmu 0x2183 0x0400>; 4032 dma-coherent; 4033 }; 4034 4035 compute-cb@4 { 4036 compatible = "qcom,fastrpc-compute-cb"; 4037 reg = <4>; 4038 iommus = <&apps_smmu 0x2144 0x04a0>, 4039 <&apps_smmu 0x2184 0x0400>; 4040 dma-coherent; 4041 }; 4042 4043 compute-cb@5 { 4044 compatible = "qcom,fastrpc-compute-cb"; 4045 reg = <5>; 4046 iommus = <&apps_smmu 0x2145 0x04a0>, 4047 <&apps_smmu 0x2185 0x0400>; 4048 dma-coherent; 4049 }; 4050 4051 compute-cb@6 { 4052 compatible = "qcom,fastrpc-compute-cb"; 4053 reg = <6>; 4054 iommus = <&apps_smmu 0x2146 0x04a0>, 4055 <&apps_smmu 0x2186 0x0400>; 4056 dma-coherent; 4057 }; 4058 4059 compute-cb@7 { 4060 compatible = "qcom,fastrpc-compute-cb"; 4061 reg = <7>; 4062 iommus = <&apps_smmu 0x2147 0x04a0>, 4063 <&apps_smmu 0x2187 0x0400>; 4064 dma-coherent; 4065 }; 4066 4067 compute-cb@8 { 4068 compatible = "qcom,fastrpc-compute-cb"; 4069 reg = <8>; 4070 iommus = <&apps_smmu 0x2148 0x04a0>, 4071 <&apps_smmu 0x2188 0x0400>; 4072 dma-coherent; 4073 }; 4074 4075 compute-cb@9 { 4076 compatible = "qcom,fastrpc-compute-cb"; 4077 reg = <9>; 4078 iommus = <&apps_smmu 0x2149 0x04a0>, 4079 <&apps_smmu 0x2189 0x0400>; 4080 dma-coherent; 4081 }; 4082 4083 compute-cb@11 { 4084 compatible = "qcom,fastrpc-compute-cb"; 4085 reg = <11>; 4086 iommus = <&apps_smmu 0x214b 0x04a0>, 4087 <&apps_smmu 0x218b 0x0400>; 4088 dma-coherent; 4089 }; 4090 }; 4091 }; 4092 }; 4093 4094 remoteproc_cdsp1: remoteproc@2a300000 { 4095 compatible = "qcom,sa8775p-cdsp1-pas"; 4096 reg = <0x0 0x2A300000 0x0 0x10000>; 4097 4098 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 4099 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4100 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4101 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4102 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4103 interrupt-names = "wdog", "fatal", "ready", 4104 "handover", "stop-ack"; 4105 4106 clocks = <&rpmhcc RPMH_CXO_CLK>; 4107 clock-names = "xo"; 4108 4109 power-domains = <&rpmhpd RPMHPD_CX>, 4110 <&rpmhpd RPMHPD_MXC>, 4111 <&rpmhpd RPMHPD_NSP1>; 4112 power-domain-names = "cx", "mxc", "nsp"; 4113 4114 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 4115 &mc_virt SLAVE_EBI1 0>; 4116 4117 memory-region = <&pil_cdsp1_mem>; 4118 4119 qcom,qmp = <&aoss_qmp>; 4120 4121 qcom,smem-states = <&smp2p_cdsp1_out 0>; 4122 qcom,smem-state-names = "stop"; 4123 4124 status = "disabled"; 4125 4126 glink-edge { 4127 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4128 IPCC_MPROC_SIGNAL_GLINK_QMP 4129 IRQ_TYPE_EDGE_RISING>; 4130 mboxes = <&ipcc IPCC_CLIENT_NSP1 4131 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4132 4133 label = "cdsp"; 4134 qcom,remote-pid = <12>; 4135 4136 fastrpc { 4137 compatible = "qcom,fastrpc"; 4138 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4139 label = "cdsp1"; 4140 #address-cells = <1>; 4141 #size-cells = <0>; 4142 4143 compute-cb@1 { 4144 compatible = "qcom,fastrpc-compute-cb"; 4145 reg = <1>; 4146 iommus = <&apps_smmu 0x2941 0x04a0>, 4147 <&apps_smmu 0x2981 0x0400>; 4148 dma-coherent; 4149 }; 4150 4151 compute-cb@2 { 4152 compatible = "qcom,fastrpc-compute-cb"; 4153 reg = <2>; 4154 iommus = <&apps_smmu 0x2942 0x04a0>, 4155 <&apps_smmu 0x2982 0x0400>; 4156 dma-coherent; 4157 }; 4158 4159 compute-cb@3 { 4160 compatible = "qcom,fastrpc-compute-cb"; 4161 reg = <3>; 4162 iommus = <&apps_smmu 0x2943 0x04a0>, 4163 <&apps_smmu 0x2983 0x0400>; 4164 dma-coherent; 4165 }; 4166 4167 compute-cb@4 { 4168 compatible = "qcom,fastrpc-compute-cb"; 4169 reg = <4>; 4170 iommus = <&apps_smmu 0x2944 0x04a0>, 4171 <&apps_smmu 0x2984 0x0400>; 4172 dma-coherent; 4173 }; 4174 4175 compute-cb@5 { 4176 compatible = "qcom,fastrpc-compute-cb"; 4177 reg = <5>; 4178 iommus = <&apps_smmu 0x2945 0x04a0>, 4179 <&apps_smmu 0x2985 0x0400>; 4180 dma-coherent; 4181 }; 4182 4183 compute-cb@6 { 4184 compatible = "qcom,fastrpc-compute-cb"; 4185 reg = <6>; 4186 iommus = <&apps_smmu 0x2946 0x04a0>, 4187 <&apps_smmu 0x2986 0x0400>; 4188 dma-coherent; 4189 }; 4190 4191 compute-cb@7 { 4192 compatible = "qcom,fastrpc-compute-cb"; 4193 reg = <7>; 4194 iommus = <&apps_smmu 0x2947 0x04a0>, 4195 <&apps_smmu 0x2987 0x0400>; 4196 dma-coherent; 4197 }; 4198 4199 compute-cb@8 { 4200 compatible = "qcom,fastrpc-compute-cb"; 4201 reg = <8>; 4202 iommus = <&apps_smmu 0x2948 0x04a0>, 4203 <&apps_smmu 0x2988 0x0400>; 4204 dma-coherent; 4205 }; 4206 4207 compute-cb@9 { 4208 compatible = "qcom,fastrpc-compute-cb"; 4209 reg = <9>; 4210 iommus = <&apps_smmu 0x2949 0x04a0>, 4211 <&apps_smmu 0x2989 0x0400>; 4212 dma-coherent; 4213 }; 4214 4215 compute-cb@10 { 4216 compatible = "qcom,fastrpc-compute-cb"; 4217 reg = <10>; 4218 iommus = <&apps_smmu 0x294a 0x04a0>, 4219 <&apps_smmu 0x298a 0x0400>; 4220 dma-coherent; 4221 }; 4222 4223 compute-cb@11 { 4224 compatible = "qcom,fastrpc-compute-cb"; 4225 reg = <11>; 4226 iommus = <&apps_smmu 0x294b 0x04a0>, 4227 <&apps_smmu 0x298b 0x0400>; 4228 dma-coherent; 4229 }; 4230 4231 compute-cb@12 { 4232 compatible = "qcom,fastrpc-compute-cb"; 4233 reg = <12>; 4234 iommus = <&apps_smmu 0x294c 0x04a0>, 4235 <&apps_smmu 0x298c 0x0400>; 4236 dma-coherent; 4237 }; 4238 4239 compute-cb@13 { 4240 compatible = "qcom,fastrpc-compute-cb"; 4241 reg = <13>; 4242 iommus = <&apps_smmu 0x294d 0x04a0>, 4243 <&apps_smmu 0x298d 0x0400>; 4244 dma-coherent; 4245 }; 4246 }; 4247 }; 4248 }; 4249 4250 remoteproc_adsp: remoteproc@30000000 { 4251 compatible = "qcom,sa8775p-adsp-pas"; 4252 reg = <0x0 0x30000000 0x0 0x100>; 4253 4254 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4255 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4256 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4257 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4258 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4259 interrupt-names = "wdog", "fatal", "ready", "handover", 4260 "stop-ack"; 4261 4262 clocks = <&rpmhcc RPMH_CXO_CLK>; 4263 clock-names = "xo"; 4264 4265 power-domains = <&rpmhpd RPMHPD_LCX>, 4266 <&rpmhpd RPMHPD_LMX>; 4267 power-domain-names = "lcx", "lmx"; 4268 4269 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4270 4271 memory-region = <&pil_adsp_mem>; 4272 4273 qcom,qmp = <&aoss_qmp>; 4274 4275 qcom,smem-states = <&smp2p_adsp_out 0>; 4276 qcom,smem-state-names = "stop"; 4277 4278 status = "disabled"; 4279 4280 remoteproc_adsp_glink: glink-edge { 4281 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4282 IPCC_MPROC_SIGNAL_GLINK_QMP 4283 IRQ_TYPE_EDGE_RISING>; 4284 mboxes = <&ipcc IPCC_CLIENT_LPASS 4285 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4286 4287 label = "lpass"; 4288 qcom,remote-pid = <2>; 4289 4290 fastrpc { 4291 compatible = "qcom,fastrpc"; 4292 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4293 label = "adsp"; 4294 memory-region = <&adsp_rpc_remote_heap_mem>; 4295 qcom,vmids = <QCOM_SCM_VMID_LPASS 4296 QCOM_SCM_VMID_ADSP_HEAP>; 4297 #address-cells = <1>; 4298 #size-cells = <0>; 4299 4300 compute-cb@3 { 4301 compatible = "qcom,fastrpc-compute-cb"; 4302 reg = <3>; 4303 iommus = <&apps_smmu 0x3003 0x0>; 4304 dma-coherent; 4305 }; 4306 4307 compute-cb@4 { 4308 compatible = "qcom,fastrpc-compute-cb"; 4309 reg = <4>; 4310 iommus = <&apps_smmu 0x3004 0x0>; 4311 dma-coherent; 4312 }; 4313 4314 compute-cb@5 { 4315 compatible = "qcom,fastrpc-compute-cb"; 4316 reg = <5>; 4317 iommus = <&apps_smmu 0x3005 0x0>; 4318 qcom,nsessions = <5>; 4319 dma-coherent; 4320 }; 4321 }; 4322 }; 4323 }; 4324 }; 4325 4326 thermal-zones { 4327 aoss-0-thermal { 4328 thermal-sensors = <&tsens0 0>; 4329 4330 trips { 4331 trip-point0 { 4332 temperature = <105000>; 4333 hysteresis = <5000>; 4334 type = "passive"; 4335 }; 4336 4337 trip-point1 { 4338 temperature = <115000>; 4339 hysteresis = <5000>; 4340 type = "passive"; 4341 }; 4342 }; 4343 }; 4344 4345 cpu-0-0-0-thermal { 4346 polling-delay-passive = <10>; 4347 4348 thermal-sensors = <&tsens0 1>; 4349 4350 trips { 4351 trip-point0 { 4352 temperature = <105000>; 4353 hysteresis = <5000>; 4354 type = "passive"; 4355 }; 4356 4357 trip-point1 { 4358 temperature = <115000>; 4359 hysteresis = <5000>; 4360 type = "passive"; 4361 }; 4362 }; 4363 }; 4364 4365 cpu-0-1-0-thermal { 4366 polling-delay-passive = <10>; 4367 4368 thermal-sensors = <&tsens0 2>; 4369 4370 trips { 4371 trip-point0 { 4372 temperature = <105000>; 4373 hysteresis = <5000>; 4374 type = "passive"; 4375 }; 4376 4377 trip-point1 { 4378 temperature = <115000>; 4379 hysteresis = <5000>; 4380 type = "passive"; 4381 }; 4382 }; 4383 }; 4384 4385 cpu-0-2-0-thermal { 4386 polling-delay-passive = <10>; 4387 4388 thermal-sensors = <&tsens0 3>; 4389 4390 trips { 4391 trip-point0 { 4392 temperature = <105000>; 4393 hysteresis = <5000>; 4394 type = "passive"; 4395 }; 4396 4397 trip-point1 { 4398 temperature = <115000>; 4399 hysteresis = <5000>; 4400 type = "passive"; 4401 }; 4402 }; 4403 }; 4404 4405 cpu-0-3-0-thermal { 4406 polling-delay-passive = <10>; 4407 4408 thermal-sensors = <&tsens0 4>; 4409 4410 trips { 4411 trip-point0 { 4412 temperature = <105000>; 4413 hysteresis = <5000>; 4414 type = "passive"; 4415 }; 4416 4417 trip-point1 { 4418 temperature = <115000>; 4419 hysteresis = <5000>; 4420 type = "passive"; 4421 }; 4422 }; 4423 }; 4424 4425 gpuss-0-thermal { 4426 polling-delay-passive = <10>; 4427 4428 thermal-sensors = <&tsens0 5>; 4429 4430 trips { 4431 trip-point0 { 4432 temperature = <105000>; 4433 hysteresis = <5000>; 4434 type = "passive"; 4435 }; 4436 4437 trip-point1 { 4438 temperature = <115000>; 4439 hysteresis = <5000>; 4440 type = "passive"; 4441 }; 4442 }; 4443 }; 4444 4445 gpuss-1-thermal { 4446 polling-delay-passive = <10>; 4447 4448 thermal-sensors = <&tsens0 6>; 4449 4450 trips { 4451 trip-point0 { 4452 temperature = <105000>; 4453 hysteresis = <5000>; 4454 type = "passive"; 4455 }; 4456 4457 trip-point1 { 4458 temperature = <115000>; 4459 hysteresis = <5000>; 4460 type = "passive"; 4461 }; 4462 }; 4463 }; 4464 4465 gpuss-2-thermal { 4466 polling-delay-passive = <10>; 4467 4468 thermal-sensors = <&tsens0 7>; 4469 4470 trips { 4471 trip-point0 { 4472 temperature = <105000>; 4473 hysteresis = <5000>; 4474 type = "passive"; 4475 }; 4476 4477 trip-point1 { 4478 temperature = <115000>; 4479 hysteresis = <5000>; 4480 type = "passive"; 4481 }; 4482 }; 4483 }; 4484 4485 audio-thermal { 4486 thermal-sensors = <&tsens0 8>; 4487 4488 trips { 4489 trip-point0 { 4490 temperature = <105000>; 4491 hysteresis = <5000>; 4492 type = "passive"; 4493 }; 4494 4495 trip-point1 { 4496 temperature = <115000>; 4497 hysteresis = <5000>; 4498 type = "passive"; 4499 }; 4500 }; 4501 }; 4502 4503 camss-0-thermal { 4504 thermal-sensors = <&tsens0 9>; 4505 4506 trips { 4507 trip-point0 { 4508 temperature = <105000>; 4509 hysteresis = <5000>; 4510 type = "passive"; 4511 }; 4512 4513 trip-point1 { 4514 temperature = <115000>; 4515 hysteresis = <5000>; 4516 type = "passive"; 4517 }; 4518 }; 4519 }; 4520 4521 pcie-0-thermal { 4522 thermal-sensors = <&tsens0 10>; 4523 4524 trips { 4525 trip-point0 { 4526 temperature = <105000>; 4527 hysteresis = <5000>; 4528 type = "passive"; 4529 }; 4530 4531 trip-point1 { 4532 temperature = <115000>; 4533 hysteresis = <5000>; 4534 type = "passive"; 4535 }; 4536 }; 4537 }; 4538 4539 cpuss-0-0-thermal { 4540 thermal-sensors = <&tsens0 11>; 4541 4542 trips { 4543 trip-point0 { 4544 temperature = <105000>; 4545 hysteresis = <5000>; 4546 type = "passive"; 4547 }; 4548 4549 trip-point1 { 4550 temperature = <115000>; 4551 hysteresis = <5000>; 4552 type = "passive"; 4553 }; 4554 }; 4555 }; 4556 4557 aoss-1-thermal { 4558 thermal-sensors = <&tsens1 0>; 4559 4560 trips { 4561 trip-point0 { 4562 temperature = <105000>; 4563 hysteresis = <5000>; 4564 type = "passive"; 4565 }; 4566 4567 trip-point1 { 4568 temperature = <115000>; 4569 hysteresis = <5000>; 4570 type = "passive"; 4571 }; 4572 }; 4573 }; 4574 4575 cpu-0-0-1-thermal { 4576 polling-delay-passive = <10>; 4577 4578 thermal-sensors = <&tsens1 1>; 4579 4580 trips { 4581 trip-point0 { 4582 temperature = <105000>; 4583 hysteresis = <5000>; 4584 type = "passive"; 4585 }; 4586 4587 trip-point1 { 4588 temperature = <115000>; 4589 hysteresis = <5000>; 4590 type = "passive"; 4591 }; 4592 }; 4593 }; 4594 4595 cpu-0-1-1-thermal { 4596 polling-delay-passive = <10>; 4597 4598 thermal-sensors = <&tsens1 2>; 4599 4600 trips { 4601 trip-point0 { 4602 temperature = <105000>; 4603 hysteresis = <5000>; 4604 type = "passive"; 4605 }; 4606 4607 trip-point1 { 4608 temperature = <115000>; 4609 hysteresis = <5000>; 4610 type = "passive"; 4611 }; 4612 }; 4613 }; 4614 4615 cpu-0-2-1-thermal { 4616 polling-delay-passive = <10>; 4617 4618 thermal-sensors = <&tsens1 3>; 4619 4620 trips { 4621 trip-point0 { 4622 temperature = <105000>; 4623 hysteresis = <5000>; 4624 type = "passive"; 4625 }; 4626 4627 trip-point1 { 4628 temperature = <115000>; 4629 hysteresis = <5000>; 4630 type = "passive"; 4631 }; 4632 }; 4633 }; 4634 4635 cpu-0-3-1-thermal { 4636 polling-delay-passive = <10>; 4637 4638 thermal-sensors = <&tsens1 4>; 4639 4640 trips { 4641 trip-point0 { 4642 temperature = <105000>; 4643 hysteresis = <5000>; 4644 type = "passive"; 4645 }; 4646 4647 trip-point1 { 4648 temperature = <115000>; 4649 hysteresis = <5000>; 4650 type = "passive"; 4651 }; 4652 }; 4653 }; 4654 4655 gpuss-3-thermal { 4656 polling-delay-passive = <10>; 4657 4658 thermal-sensors = <&tsens1 5>; 4659 4660 trips { 4661 trip-point0 { 4662 temperature = <105000>; 4663 hysteresis = <5000>; 4664 type = "passive"; 4665 }; 4666 4667 trip-point1 { 4668 temperature = <115000>; 4669 hysteresis = <5000>; 4670 type = "passive"; 4671 }; 4672 }; 4673 }; 4674 4675 gpuss-4-thermal { 4676 polling-delay-passive = <10>; 4677 4678 thermal-sensors = <&tsens1 6>; 4679 4680 trips { 4681 trip-point0 { 4682 temperature = <105000>; 4683 hysteresis = <5000>; 4684 type = "passive"; 4685 }; 4686 4687 trip-point1 { 4688 temperature = <115000>; 4689 hysteresis = <5000>; 4690 type = "passive"; 4691 }; 4692 }; 4693 }; 4694 4695 gpuss-5-thermal { 4696 polling-delay-passive = <10>; 4697 4698 thermal-sensors = <&tsens1 7>; 4699 4700 trips { 4701 trip-point0 { 4702 temperature = <105000>; 4703 hysteresis = <5000>; 4704 type = "passive"; 4705 }; 4706 4707 trip-point1 { 4708 temperature = <115000>; 4709 hysteresis = <5000>; 4710 type = "passive"; 4711 }; 4712 }; 4713 }; 4714 4715 video-thermal { 4716 thermal-sensors = <&tsens1 8>; 4717 4718 trips { 4719 trip-point0 { 4720 temperature = <105000>; 4721 hysteresis = <5000>; 4722 type = "passive"; 4723 }; 4724 4725 trip-point1 { 4726 temperature = <115000>; 4727 hysteresis = <5000>; 4728 type = "passive"; 4729 }; 4730 }; 4731 }; 4732 4733 camss-1-thermal { 4734 thermal-sensors = <&tsens1 9>; 4735 4736 trips { 4737 trip-point0 { 4738 temperature = <105000>; 4739 hysteresis = <5000>; 4740 type = "passive"; 4741 }; 4742 4743 trip-point1 { 4744 temperature = <115000>; 4745 hysteresis = <5000>; 4746 type = "passive"; 4747 }; 4748 }; 4749 }; 4750 4751 pcie-1-thermal { 4752 thermal-sensors = <&tsens1 10>; 4753 4754 trips { 4755 trip-point0 { 4756 temperature = <105000>; 4757 hysteresis = <5000>; 4758 type = "passive"; 4759 }; 4760 4761 trip-point1 { 4762 temperature = <115000>; 4763 hysteresis = <5000>; 4764 type = "passive"; 4765 }; 4766 }; 4767 }; 4768 4769 cpuss-0-1-thermal { 4770 thermal-sensors = <&tsens1 11>; 4771 4772 trips { 4773 trip-point0 { 4774 temperature = <105000>; 4775 hysteresis = <5000>; 4776 type = "passive"; 4777 }; 4778 4779 trip-point1 { 4780 temperature = <115000>; 4781 hysteresis = <5000>; 4782 type = "passive"; 4783 }; 4784 }; 4785 }; 4786 4787 aoss-2-thermal { 4788 thermal-sensors = <&tsens2 0>; 4789 4790 trips { 4791 trip-point0 { 4792 temperature = <105000>; 4793 hysteresis = <5000>; 4794 type = "passive"; 4795 }; 4796 4797 trip-point1 { 4798 temperature = <115000>; 4799 hysteresis = <5000>; 4800 type = "passive"; 4801 }; 4802 }; 4803 }; 4804 4805 cpu-1-0-0-thermal { 4806 polling-delay-passive = <10>; 4807 4808 thermal-sensors = <&tsens2 1>; 4809 4810 trips { 4811 trip-point0 { 4812 temperature = <105000>; 4813 hysteresis = <5000>; 4814 type = "passive"; 4815 }; 4816 4817 trip-point1 { 4818 temperature = <115000>; 4819 hysteresis = <5000>; 4820 type = "passive"; 4821 }; 4822 }; 4823 }; 4824 4825 cpu-1-1-0-thermal { 4826 polling-delay-passive = <10>; 4827 4828 thermal-sensors = <&tsens2 2>; 4829 4830 trips { 4831 trip-point0 { 4832 temperature = <105000>; 4833 hysteresis = <5000>; 4834 type = "passive"; 4835 }; 4836 4837 trip-point1 { 4838 temperature = <115000>; 4839 hysteresis = <5000>; 4840 type = "passive"; 4841 }; 4842 }; 4843 }; 4844 4845 cpu-1-2-0-thermal { 4846 polling-delay-passive = <10>; 4847 4848 thermal-sensors = <&tsens2 3>; 4849 4850 trips { 4851 trip-point0 { 4852 temperature = <105000>; 4853 hysteresis = <5000>; 4854 type = "passive"; 4855 }; 4856 4857 trip-point1 { 4858 temperature = <115000>; 4859 hysteresis = <5000>; 4860 type = "passive"; 4861 }; 4862 }; 4863 }; 4864 4865 cpu-1-3-0-thermal { 4866 polling-delay-passive = <10>; 4867 4868 thermal-sensors = <&tsens2 4>; 4869 4870 trips { 4871 trip-point0 { 4872 temperature = <105000>; 4873 hysteresis = <5000>; 4874 type = "passive"; 4875 }; 4876 4877 trip-point1 { 4878 temperature = <115000>; 4879 hysteresis = <5000>; 4880 type = "passive"; 4881 }; 4882 }; 4883 }; 4884 4885 nsp-0-0-0-thermal { 4886 polling-delay-passive = <10>; 4887 4888 thermal-sensors = <&tsens2 5>; 4889 4890 trips { 4891 trip-point0 { 4892 temperature = <105000>; 4893 hysteresis = <5000>; 4894 type = "passive"; 4895 }; 4896 4897 trip-point1 { 4898 temperature = <115000>; 4899 hysteresis = <5000>; 4900 type = "passive"; 4901 }; 4902 }; 4903 }; 4904 4905 nsp-0-1-0-thermal { 4906 polling-delay-passive = <10>; 4907 4908 thermal-sensors = <&tsens2 6>; 4909 4910 trips { 4911 trip-point0 { 4912 temperature = <105000>; 4913 hysteresis = <5000>; 4914 type = "passive"; 4915 }; 4916 4917 trip-point1 { 4918 temperature = <115000>; 4919 hysteresis = <5000>; 4920 type = "passive"; 4921 }; 4922 }; 4923 }; 4924 4925 nsp-0-2-0-thermal { 4926 polling-delay-passive = <10>; 4927 4928 thermal-sensors = <&tsens2 7>; 4929 4930 trips { 4931 trip-point0 { 4932 temperature = <105000>; 4933 hysteresis = <5000>; 4934 type = "passive"; 4935 }; 4936 4937 trip-point1 { 4938 temperature = <115000>; 4939 hysteresis = <5000>; 4940 type = "passive"; 4941 }; 4942 }; 4943 }; 4944 4945 nsp-1-0-0-thermal { 4946 polling-delay-passive = <10>; 4947 4948 thermal-sensors = <&tsens2 8>; 4949 4950 trips { 4951 trip-point0 { 4952 temperature = <105000>; 4953 hysteresis = <5000>; 4954 type = "passive"; 4955 }; 4956 4957 trip-point1 { 4958 temperature = <115000>; 4959 hysteresis = <5000>; 4960 type = "passive"; 4961 }; 4962 }; 4963 }; 4964 4965 nsp-1-1-0-thermal { 4966 polling-delay-passive = <10>; 4967 4968 thermal-sensors = <&tsens2 9>; 4969 4970 trips { 4971 trip-point0 { 4972 temperature = <105000>; 4973 hysteresis = <5000>; 4974 type = "passive"; 4975 }; 4976 4977 trip-point1 { 4978 temperature = <115000>; 4979 hysteresis = <5000>; 4980 type = "passive"; 4981 }; 4982 }; 4983 }; 4984 4985 nsp-1-2-0-thermal { 4986 polling-delay-passive = <10>; 4987 4988 thermal-sensors = <&tsens2 10>; 4989 4990 trips { 4991 trip-point0 { 4992 temperature = <105000>; 4993 hysteresis = <5000>; 4994 type = "passive"; 4995 }; 4996 4997 trip-point1 { 4998 temperature = <115000>; 4999 hysteresis = <5000>; 5000 type = "passive"; 5001 }; 5002 }; 5003 }; 5004 5005 ddrss-0-thermal { 5006 thermal-sensors = <&tsens2 11>; 5007 5008 trips { 5009 trip-point0 { 5010 temperature = <105000>; 5011 hysteresis = <5000>; 5012 type = "passive"; 5013 }; 5014 5015 trip-point1 { 5016 temperature = <115000>; 5017 hysteresis = <5000>; 5018 type = "passive"; 5019 }; 5020 }; 5021 }; 5022 5023 cpuss-1-0-thermal { 5024 thermal-sensors = <&tsens2 12>; 5025 5026 trips { 5027 trip-point0 { 5028 temperature = <105000>; 5029 hysteresis = <5000>; 5030 type = "passive"; 5031 }; 5032 5033 trip-point1 { 5034 temperature = <115000>; 5035 hysteresis = <5000>; 5036 type = "passive"; 5037 }; 5038 }; 5039 }; 5040 5041 aoss-3-thermal { 5042 thermal-sensors = <&tsens3 0>; 5043 5044 trips { 5045 trip-point0 { 5046 temperature = <105000>; 5047 hysteresis = <5000>; 5048 type = "passive"; 5049 }; 5050 5051 trip-point1 { 5052 temperature = <115000>; 5053 hysteresis = <5000>; 5054 type = "passive"; 5055 }; 5056 }; 5057 }; 5058 5059 cpu-1-0-1-thermal { 5060 polling-delay-passive = <10>; 5061 5062 thermal-sensors = <&tsens3 1>; 5063 5064 trips { 5065 trip-point0 { 5066 temperature = <105000>; 5067 hysteresis = <5000>; 5068 type = "passive"; 5069 }; 5070 5071 trip-point1 { 5072 temperature = <115000>; 5073 hysteresis = <5000>; 5074 type = "passive"; 5075 }; 5076 }; 5077 }; 5078 5079 cpu-1-1-1-thermal { 5080 polling-delay-passive = <10>; 5081 5082 thermal-sensors = <&tsens3 2>; 5083 5084 trips { 5085 trip-point0 { 5086 temperature = <105000>; 5087 hysteresis = <5000>; 5088 type = "passive"; 5089 }; 5090 5091 trip-point1 { 5092 temperature = <115000>; 5093 hysteresis = <5000>; 5094 type = "passive"; 5095 }; 5096 }; 5097 }; 5098 5099 cpu-1-2-1-thermal { 5100 polling-delay-passive = <10>; 5101 5102 thermal-sensors = <&tsens3 3>; 5103 5104 trips { 5105 trip-point0 { 5106 temperature = <105000>; 5107 hysteresis = <5000>; 5108 type = "passive"; 5109 }; 5110 5111 trip-point1 { 5112 temperature = <115000>; 5113 hysteresis = <5000>; 5114 type = "passive"; 5115 }; 5116 }; 5117 }; 5118 5119 cpu-1-3-1-thermal { 5120 polling-delay-passive = <10>; 5121 5122 thermal-sensors = <&tsens3 4>; 5123 5124 trips { 5125 trip-point0 { 5126 temperature = <105000>; 5127 hysteresis = <5000>; 5128 type = "passive"; 5129 }; 5130 5131 trip-point1 { 5132 temperature = <115000>; 5133 hysteresis = <5000>; 5134 type = "passive"; 5135 }; 5136 }; 5137 }; 5138 5139 nsp-0-0-1-thermal { 5140 polling-delay-passive = <10>; 5141 5142 thermal-sensors = <&tsens3 5>; 5143 5144 trips { 5145 trip-point0 { 5146 temperature = <105000>; 5147 hysteresis = <5000>; 5148 type = "passive"; 5149 }; 5150 5151 trip-point1 { 5152 temperature = <115000>; 5153 hysteresis = <5000>; 5154 type = "passive"; 5155 }; 5156 }; 5157 }; 5158 5159 nsp-0-1-1-thermal { 5160 polling-delay-passive = <10>; 5161 5162 thermal-sensors = <&tsens3 6>; 5163 5164 trips { 5165 trip-point0 { 5166 temperature = <105000>; 5167 hysteresis = <5000>; 5168 type = "passive"; 5169 }; 5170 5171 trip-point1 { 5172 temperature = <115000>; 5173 hysteresis = <5000>; 5174 type = "passive"; 5175 }; 5176 }; 5177 }; 5178 5179 nsp-0-2-1-thermal { 5180 polling-delay-passive = <10>; 5181 5182 thermal-sensors = <&tsens3 7>; 5183 5184 trips { 5185 trip-point0 { 5186 temperature = <105000>; 5187 hysteresis = <5000>; 5188 type = "passive"; 5189 }; 5190 5191 trip-point1 { 5192 temperature = <115000>; 5193 hysteresis = <5000>; 5194 type = "passive"; 5195 }; 5196 }; 5197 }; 5198 5199 nsp-1-0-1-thermal { 5200 polling-delay-passive = <10>; 5201 5202 thermal-sensors = <&tsens3 8>; 5203 5204 trips { 5205 trip-point0 { 5206 temperature = <105000>; 5207 hysteresis = <5000>; 5208 type = "passive"; 5209 }; 5210 5211 trip-point1 { 5212 temperature = <115000>; 5213 hysteresis = <5000>; 5214 type = "passive"; 5215 }; 5216 }; 5217 }; 5218 5219 nsp-1-1-1-thermal { 5220 polling-delay-passive = <10>; 5221 5222 thermal-sensors = <&tsens3 9>; 5223 5224 trips { 5225 trip-point0 { 5226 temperature = <105000>; 5227 hysteresis = <5000>; 5228 type = "passive"; 5229 }; 5230 5231 trip-point1 { 5232 temperature = <115000>; 5233 hysteresis = <5000>; 5234 type = "passive"; 5235 }; 5236 }; 5237 }; 5238 5239 nsp-1-2-1-thermal { 5240 polling-delay-passive = <10>; 5241 5242 thermal-sensors = <&tsens3 10>; 5243 5244 trips { 5245 trip-point0 { 5246 temperature = <105000>; 5247 hysteresis = <5000>; 5248 type = "passive"; 5249 }; 5250 5251 trip-point1 { 5252 temperature = <115000>; 5253 hysteresis = <5000>; 5254 type = "passive"; 5255 }; 5256 }; 5257 }; 5258 5259 ddrss-1-thermal { 5260 thermal-sensors = <&tsens3 11>; 5261 5262 trips { 5263 trip-point0 { 5264 temperature = <105000>; 5265 hysteresis = <5000>; 5266 type = "passive"; 5267 }; 5268 5269 trip-point1 { 5270 temperature = <115000>; 5271 hysteresis = <5000>; 5272 type = "passive"; 5273 }; 5274 }; 5275 }; 5276 5277 cpuss-1-1-thermal { 5278 thermal-sensors = <&tsens3 12>; 5279 5280 trips { 5281 trip-point0 { 5282 temperature = <105000>; 5283 hysteresis = <5000>; 5284 type = "passive"; 5285 }; 5286 5287 trip-point1 { 5288 temperature = <115000>; 5289 hysteresis = <5000>; 5290 type = "passive"; 5291 }; 5292 }; 5293 }; 5294 }; 5295 5296 arch_timer: timer { 5297 compatible = "arm,armv8-timer"; 5298 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5299 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5300 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5301 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5302 }; 5303 5304 pcie0: pcie@1c00000 { 5305 compatible = "qcom,pcie-sa8775p"; 5306 reg = <0x0 0x01c00000 0x0 0x3000>, 5307 <0x0 0x40000000 0x0 0xf20>, 5308 <0x0 0x40000f20 0x0 0xa8>, 5309 <0x0 0x40001000 0x0 0x4000>, 5310 <0x0 0x40100000 0x0 0x100000>, 5311 <0x0 0x01c03000 0x0 0x1000>; 5312 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 5313 device_type = "pci"; 5314 5315 #address-cells = <3>; 5316 #size-cells = <2>; 5317 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 5318 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 5319 bus-range = <0x00 0xff>; 5320 5321 dma-coherent; 5322 5323 linux,pci-domain = <0>; 5324 num-lanes = <2>; 5325 5326 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 5334 interrupt-names = "msi0", "msi1", "msi2", "msi3", 5335 "msi4", "msi5", "msi6", "msi7"; 5336 #interrupt-cells = <1>; 5337 interrupt-map-mask = <0 0 0 0x7>; 5338 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 5339 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 5340 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 5341 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 5342 5343 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 5344 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 5345 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 5346 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 5347 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 5348 5349 clock-names = "aux", 5350 "cfg", 5351 "bus_master", 5352 "bus_slave", 5353 "slave_q2a"; 5354 5355 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 5356 assigned-clock-rates = <19200000>; 5357 5358 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 5359 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 5360 interconnect-names = "pcie-mem", "cpu-pcie"; 5361 5362 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 5363 <0x100 &pcie_smmu 0x0001 0x1>; 5364 5365 resets = <&gcc GCC_PCIE_0_BCR>; 5366 reset-names = "pci"; 5367 power-domains = <&gcc PCIE_0_GDSC>; 5368 5369 phys = <&pcie0_phy>; 5370 phy-names = "pciephy"; 5371 5372 status = "disabled"; 5373 5374 pcie@0 { 5375 device_type = "pci"; 5376 reg = <0x0 0x0 0x0 0x0 0x0>; 5377 bus-range = <0x01 0xff>; 5378 5379 #address-cells = <3>; 5380 #size-cells = <2>; 5381 ranges; 5382 }; 5383 }; 5384 5385 pcie0_ep: pcie-ep@1c00000 { 5386 compatible = "qcom,sa8775p-pcie-ep"; 5387 reg = <0x0 0x01c00000 0x0 0x3000>, 5388 <0x0 0x40000000 0x0 0xf20>, 5389 <0x0 0x40000f20 0x0 0xa8>, 5390 <0x0 0x40001000 0x0 0x4000>, 5391 <0x0 0x40200000 0x0 0x1fe00000>, 5392 <0x0 0x01c03000 0x0 0x1000>, 5393 <0x0 0x40005000 0x0 0x2000>; 5394 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 5395 "mmio", "dma"; 5396 5397 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 5398 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 5399 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 5400 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 5401 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 5402 5403 clock-names = "aux", 5404 "cfg", 5405 "bus_master", 5406 "bus_slave", 5407 "slave_q2a"; 5408 5409 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 5410 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 5411 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 5412 5413 interrupt-names = "global", "doorbell", "dma"; 5414 5415 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 5416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 5417 interconnect-names = "pcie-mem", "cpu-pcie"; 5418 5419 dma-coherent; 5420 iommus = <&pcie_smmu 0x0000 0x7f>; 5421 resets = <&gcc GCC_PCIE_0_BCR>; 5422 reset-names = "core"; 5423 power-domains = <&gcc PCIE_0_GDSC>; 5424 phys = <&pcie0_phy>; 5425 phy-names = "pciephy"; 5426 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 5427 num-lanes = <2>; 5428 5429 status = "disabled"; 5430 }; 5431 5432 pcie0_phy: phy@1c04000 { 5433 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 5434 reg = <0x0 0x1c04000 0x0 0x2000>; 5435 5436 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 5437 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 5438 <&gcc GCC_PCIE_CLKREF_EN>, 5439 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 5440 <&gcc GCC_PCIE_0_PIPE_CLK>, 5441 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 5442 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 5443 5444 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 5445 "pipediv2", "phy_aux"; 5446 5447 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 5448 assigned-clock-rates = <100000000>; 5449 5450 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 5451 reset-names = "phy"; 5452 5453 #clock-cells = <0>; 5454 clock-output-names = "pcie_0_pipe_clk"; 5455 5456 #phy-cells = <0>; 5457 5458 status = "disabled"; 5459 }; 5460 5461 pcie1: pcie@1c10000 { 5462 compatible = "qcom,pcie-sa8775p"; 5463 reg = <0x0 0x01c10000 0x0 0x3000>, 5464 <0x0 0x60000000 0x0 0xf20>, 5465 <0x0 0x60000f20 0x0 0xa8>, 5466 <0x0 0x60001000 0x0 0x4000>, 5467 <0x0 0x60100000 0x0 0x100000>, 5468 <0x0 0x01c13000 0x0 0x1000>; 5469 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 5470 device_type = "pci"; 5471 5472 #address-cells = <3>; 5473 #size-cells = <2>; 5474 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 5475 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 5476 bus-range = <0x00 0xff>; 5477 5478 dma-coherent; 5479 5480 linux,pci-domain = <1>; 5481 num-lanes = <4>; 5482 5483 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 5484 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 5485 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 5486 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 5487 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 5488 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 5489 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 5490 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 5491 interrupt-names = "msi0", "msi1", "msi2", "msi3", 5492 "msi4", "msi5", "msi6", "msi7"; 5493 #interrupt-cells = <1>; 5494 interrupt-map-mask = <0 0 0 0x7>; 5495 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 5496 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 5497 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 5498 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 5499 5500 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 5501 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 5502 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 5503 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 5504 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 5505 5506 clock-names = "aux", 5507 "cfg", 5508 "bus_master", 5509 "bus_slave", 5510 "slave_q2a"; 5511 5512 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 5513 assigned-clock-rates = <19200000>; 5514 5515 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 5516 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 5517 interconnect-names = "pcie-mem", "cpu-pcie"; 5518 5519 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 5520 <0x100 &pcie_smmu 0x0081 0x1>; 5521 5522 resets = <&gcc GCC_PCIE_1_BCR>; 5523 reset-names = "pci"; 5524 power-domains = <&gcc PCIE_1_GDSC>; 5525 5526 phys = <&pcie1_phy>; 5527 phy-names = "pciephy"; 5528 5529 status = "disabled"; 5530 5531 pcie@0 { 5532 device_type = "pci"; 5533 reg = <0x0 0x0 0x0 0x0 0x0>; 5534 bus-range = <0x01 0xff>; 5535 5536 #address-cells = <3>; 5537 #size-cells = <2>; 5538 ranges; 5539 }; 5540 }; 5541 5542 pcie1_ep: pcie-ep@1c10000 { 5543 compatible = "qcom,sa8775p-pcie-ep"; 5544 reg = <0x0 0x01c10000 0x0 0x3000>, 5545 <0x0 0x60000000 0x0 0xf20>, 5546 <0x0 0x60000f20 0x0 0xa8>, 5547 <0x0 0x60001000 0x0 0x4000>, 5548 <0x0 0x60200000 0x0 0x1fe00000>, 5549 <0x0 0x01c13000 0x0 0x1000>, 5550 <0x0 0x60005000 0x0 0x2000>; 5551 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 5552 "mmio", "dma"; 5553 5554 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 5555 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 5556 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 5557 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 5558 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 5559 5560 clock-names = "aux", 5561 "cfg", 5562 "bus_master", 5563 "bus_slave", 5564 "slave_q2a"; 5565 5566 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 5567 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 5568 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 5569 5570 interrupt-names = "global", "doorbell", "dma"; 5571 5572 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 5573 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 5574 interconnect-names = "pcie-mem", "cpu-pcie"; 5575 5576 dma-coherent; 5577 iommus = <&pcie_smmu 0x80 0x7f>; 5578 resets = <&gcc GCC_PCIE_1_BCR>; 5579 reset-names = "core"; 5580 power-domains = <&gcc PCIE_1_GDSC>; 5581 phys = <&pcie1_phy>; 5582 phy-names = "pciephy"; 5583 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 5584 num-lanes = <4>; 5585 5586 status = "disabled"; 5587 }; 5588 5589 pcie1_phy: phy@1c14000 { 5590 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 5591 reg = <0x0 0x1c14000 0x0 0x4000>; 5592 5593 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 5594 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 5595 <&gcc GCC_PCIE_CLKREF_EN>, 5596 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 5597 <&gcc GCC_PCIE_1_PIPE_CLK>, 5598 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 5599 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 5600 5601 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 5602 "pipediv2", "phy_aux"; 5603 5604 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 5605 assigned-clock-rates = <100000000>; 5606 5607 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 5608 reset-names = "phy"; 5609 5610 #clock-cells = <0>; 5611 clock-output-names = "pcie_1_pipe_clk"; 5612 5613 #phy-cells = <0>; 5614 5615 status = "disabled"; 5616 }; 5617}; 5618