1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-camcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 #clock-cells = <0>; 48 compatible = "fixed-factor-clock"; 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 #clock-cells = <0>; 56 compatible = "fixed-factor-clock"; 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 }; 62 63 cpus { 64 #address-cells = <2>; 65 #size-cells = <0>; 66 67 CPU0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a510"; 70 reg = <0 0>; 71 clocks = <&cpufreq_hw 0>; 72 enable-method = "psci"; 73 next-level-cache = <&L2_0>; 74 power-domains = <&CPU_PD0>; 75 power-domain-names = "psci"; 76 qcom,freq-domain = <&cpufreq_hw 0>; 77 capacity-dmips-mhz = <1024>; 78 dynamic-power-coefficient = <100>; 79 #cooling-cells = <2>; 80 L2_0: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 L3_0: l3-cache { 86 compatible = "cache"; 87 cache-level = <3>; 88 cache-unified; 89 }; 90 }; 91 }; 92 93 CPU1: cpu@100 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a510"; 96 reg = <0 0x100>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_100>; 100 power-domains = <&CPU_PD1>; 101 power-domain-names = "psci"; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 capacity-dmips-mhz = <1024>; 104 dynamic-power-coefficient = <100>; 105 #cooling-cells = <2>; 106 L2_100: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&L3_0>; 111 }; 112 }; 113 114 CPU2: cpu@200 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a510"; 117 reg = <0 0x200>; 118 clocks = <&cpufreq_hw 0>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_200>; 121 power-domains = <&CPU_PD2>; 122 power-domain-names = "psci"; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 capacity-dmips-mhz = <1024>; 125 dynamic-power-coefficient = <100>; 126 #cooling-cells = <2>; 127 L2_200: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU3: cpu@300 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a715"; 138 reg = <0 0x300>; 139 clocks = <&cpufreq_hw 1>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_300>; 142 power-domains = <&CPU_PD3>; 143 power-domain-names = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 capacity-dmips-mhz = <1792>; 146 dynamic-power-coefficient = <270>; 147 #cooling-cells = <2>; 148 L2_300: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&L3_0>; 153 }; 154 }; 155 156 CPU4: cpu@400 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a715"; 159 reg = <0 0x400>; 160 clocks = <&cpufreq_hw 1>; 161 enable-method = "psci"; 162 next-level-cache = <&L2_400>; 163 power-domains = <&CPU_PD4>; 164 power-domain-names = "psci"; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 capacity-dmips-mhz = <1792>; 167 dynamic-power-coefficient = <270>; 168 #cooling-cells = <2>; 169 L2_400: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "arm,cortex-a710"; 180 reg = <0 0x500>; 181 clocks = <&cpufreq_hw 1>; 182 enable-method = "psci"; 183 next-level-cache = <&L2_500>; 184 power-domains = <&CPU_PD5>; 185 power-domain-names = "psci"; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 capacity-dmips-mhz = <1792>; 188 dynamic-power-coefficient = <270>; 189 #cooling-cells = <2>; 190 L2_500: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU6: cpu@600 { 199 device_type = "cpu"; 200 compatible = "arm,cortex-a710"; 201 reg = <0 0x600>; 202 clocks = <&cpufreq_hw 1>; 203 enable-method = "psci"; 204 next-level-cache = <&L2_600>; 205 power-domains = <&CPU_PD6>; 206 power-domain-names = "psci"; 207 qcom,freq-domain = <&cpufreq_hw 1>; 208 capacity-dmips-mhz = <1792>; 209 dynamic-power-coefficient = <270>; 210 #cooling-cells = <2>; 211 L2_600: l2-cache { 212 compatible = "cache"; 213 cache-level = <2>; 214 cache-unified; 215 next-level-cache = <&L3_0>; 216 }; 217 }; 218 219 CPU7: cpu@700 { 220 device_type = "cpu"; 221 compatible = "arm,cortex-x3"; 222 reg = <0 0x700>; 223 clocks = <&cpufreq_hw 2>; 224 enable-method = "psci"; 225 next-level-cache = <&L2_700>; 226 power-domains = <&CPU_PD7>; 227 power-domain-names = "psci"; 228 qcom,freq-domain = <&cpufreq_hw 2>; 229 capacity-dmips-mhz = <1894>; 230 dynamic-power-coefficient = <588>; 231 #cooling-cells = <2>; 232 L2_700: l2-cache { 233 compatible = "cache"; 234 cache-level = <2>; 235 cache-unified; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 cpu-map { 241 cluster0 { 242 core0 { 243 cpu = <&CPU0>; 244 }; 245 246 core1 { 247 cpu = <&CPU1>; 248 }; 249 250 core2 { 251 cpu = <&CPU2>; 252 }; 253 254 core3 { 255 cpu = <&CPU3>; 256 }; 257 258 core4 { 259 cpu = <&CPU4>; 260 }; 261 262 core5 { 263 cpu = <&CPU5>; 264 }; 265 266 core6 { 267 cpu = <&CPU6>; 268 }; 269 270 core7 { 271 cpu = <&CPU7>; 272 }; 273 }; 274 }; 275 276 idle-states { 277 entry-method = "psci"; 278 279 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "silver-rail-power-collapse"; 282 arm,psci-suspend-param = <0x40000004>; 283 entry-latency-us = <550>; 284 exit-latency-us = <750>; 285 min-residency-us = <6700>; 286 local-timer-stop; 287 }; 288 289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 290 compatible = "arm,idle-state"; 291 idle-state-name = "gold-rail-power-collapse"; 292 arm,psci-suspend-param = <0x40000004>; 293 entry-latency-us = <600>; 294 exit-latency-us = <1300>; 295 min-residency-us = <8136>; 296 local-timer-stop; 297 }; 298 299 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { 300 compatible = "arm,idle-state"; 301 idle-state-name = "goldplus-rail-power-collapse"; 302 arm,psci-suspend-param = <0x40000004>; 303 entry-latency-us = <500>; 304 exit-latency-us = <1350>; 305 min-residency-us = <7480>; 306 local-timer-stop; 307 }; 308 }; 309 310 domain-idle-states { 311 CLUSTER_SLEEP_0: cluster-sleep-0 { 312 compatible = "domain-idle-state"; 313 arm,psci-suspend-param = <0x41000044>; 314 entry-latency-us = <750>; 315 exit-latency-us = <2350>; 316 min-residency-us = <9144>; 317 }; 318 319 CLUSTER_SLEEP_1: cluster-sleep-1 { 320 compatible = "domain-idle-state"; 321 arm,psci-suspend-param = <0x4100c344>; 322 entry-latency-us = <2800>; 323 exit-latency-us = <4400>; 324 min-residency-us = <10150>; 325 }; 326 }; 327 }; 328 329 firmware { 330 scm: scm { 331 compatible = "qcom,scm-sm8550", "qcom,scm"; 332 qcom,dload-mode = <&tcsr 0x19000>; 333 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 334 }; 335 }; 336 337 clk_virt: interconnect-0 { 338 compatible = "qcom,sm8550-clk-virt"; 339 #interconnect-cells = <2>; 340 qcom,bcm-voters = <&apps_bcm_voter>; 341 }; 342 343 mc_virt: interconnect-1 { 344 compatible = "qcom,sm8550-mc-virt"; 345 #interconnect-cells = <2>; 346 qcom,bcm-voters = <&apps_bcm_voter>; 347 }; 348 349 memory@a0000000 { 350 device_type = "memory"; 351 /* We expect the bootloader to fill in the size */ 352 reg = <0 0xa0000000 0 0>; 353 }; 354 355 pmu-a510 { 356 compatible = "arm,cortex-a510-pmu"; 357 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 358 }; 359 360 pmu-a710 { 361 compatible = "arm,cortex-a710-pmu"; 362 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 363 }; 364 365 pmu-a715 { 366 compatible = "arm,cortex-a715-pmu"; 367 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 368 }; 369 370 pmu-x3 { 371 compatible = "arm,cortex-x3-pmu"; 372 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 373 }; 374 375 psci { 376 compatible = "arm,psci-1.0"; 377 method = "smc"; 378 379 CPU_PD0: power-domain-cpu0 { 380 #power-domain-cells = <0>; 381 power-domains = <&CLUSTER_PD>; 382 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 383 }; 384 385 CPU_PD1: power-domain-cpu1 { 386 #power-domain-cells = <0>; 387 power-domains = <&CLUSTER_PD>; 388 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 389 }; 390 391 CPU_PD2: power-domain-cpu2 { 392 #power-domain-cells = <0>; 393 power-domains = <&CLUSTER_PD>; 394 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 395 }; 396 397 CPU_PD3: power-domain-cpu3 { 398 #power-domain-cells = <0>; 399 power-domains = <&CLUSTER_PD>; 400 domain-idle-states = <&BIG_CPU_SLEEP_0>; 401 }; 402 403 CPU_PD4: power-domain-cpu4 { 404 #power-domain-cells = <0>; 405 power-domains = <&CLUSTER_PD>; 406 domain-idle-states = <&BIG_CPU_SLEEP_0>; 407 }; 408 409 CPU_PD5: power-domain-cpu5 { 410 #power-domain-cells = <0>; 411 power-domains = <&CLUSTER_PD>; 412 domain-idle-states = <&BIG_CPU_SLEEP_0>; 413 }; 414 415 CPU_PD6: power-domain-cpu6 { 416 #power-domain-cells = <0>; 417 power-domains = <&CLUSTER_PD>; 418 domain-idle-states = <&BIG_CPU_SLEEP_0>; 419 }; 420 421 CPU_PD7: power-domain-cpu7 { 422 #power-domain-cells = <0>; 423 power-domains = <&CLUSTER_PD>; 424 domain-idle-states = <&PRIME_CPU_SLEEP_0>; 425 }; 426 427 CLUSTER_PD: power-domain-cluster { 428 #power-domain-cells = <0>; 429 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 430 }; 431 }; 432 433 reserved_memory: reserved-memory { 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 438 hyp_mem: hyp-region@80000000 { 439 reg = <0 0x80000000 0 0xa00000>; 440 no-map; 441 }; 442 443 cpusys_vm_mem: cpusys-vm-region@80a00000 { 444 reg = <0 0x80a00000 0 0x400000>; 445 no-map; 446 }; 447 448 hyp_tags_mem: hyp-tags-region@80e00000 { 449 reg = <0 0x80e00000 0 0x3d0000>; 450 no-map; 451 }; 452 453 xbl_sc_mem: xbl-sc-region@d8100000 { 454 reg = <0 0xd8100000 0 0x40000>; 455 no-map; 456 }; 457 458 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 459 reg = <0 0x811d0000 0 0x30000>; 460 no-map; 461 }; 462 463 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 464 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 465 reg = <0 0x81a00000 0 0x260000>; 466 no-map; 467 }; 468 469 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 470 compatible = "qcom,cmd-db"; 471 reg = <0 0x81c60000 0 0x20000>; 472 no-map; 473 }; 474 475 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 476 aop_config_merged_mem: aop-config-merged-region@81c80000 { 477 reg = <0 0x81c80000 0 0x74000>; 478 no-map; 479 }; 480 481 /* secdata region can be reused by apps */ 482 smem: smem@81d00000 { 483 compatible = "qcom,smem"; 484 reg = <0 0x81d00000 0 0x200000>; 485 hwlocks = <&tcsr_mutex 3>; 486 no-map; 487 }; 488 489 adsp_mhi_mem: adsp-mhi-region@81f00000 { 490 reg = <0 0x81f00000 0 0x20000>; 491 no-map; 492 }; 493 494 global_sync_mem: global-sync-region@82600000 { 495 reg = <0 0x82600000 0 0x100000>; 496 no-map; 497 }; 498 499 tz_stat_mem: tz-stat-region@82700000 { 500 reg = <0 0x82700000 0 0x100000>; 501 no-map; 502 }; 503 504 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 505 reg = <0 0x82800000 0 0x4600000>; 506 no-map; 507 }; 508 509 mpss_mem: mpss-region@8a800000 { 510 reg = <0 0x8a800000 0 0x10800000>; 511 no-map; 512 }; 513 514 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 515 reg = <0 0x9b000000 0 0x80000>; 516 no-map; 517 }; 518 519 ipa_fw_mem: ipa-fw-region@9b080000 { 520 reg = <0 0x9b080000 0 0x10000>; 521 no-map; 522 }; 523 524 ipa_gsi_mem: ipa-gsi-region@9b090000 { 525 reg = <0 0x9b090000 0 0xa000>; 526 no-map; 527 }; 528 529 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 530 reg = <0 0x9b09a000 0 0x2000>; 531 no-map; 532 }; 533 534 spss_region_mem: spss-region@9b100000 { 535 reg = <0 0x9b100000 0 0x180000>; 536 no-map; 537 }; 538 539 /* First part of the "SPU secure shared memory" region */ 540 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 541 reg = <0 0x9b280000 0 0x60000>; 542 no-map; 543 }; 544 545 /* Second part of the "SPU secure shared memory" region */ 546 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 547 reg = <0 0x9b2e0000 0 0x20000>; 548 no-map; 549 }; 550 551 camera_mem: camera-region@9b300000 { 552 reg = <0 0x9b300000 0 0x800000>; 553 no-map; 554 }; 555 556 video_mem: video-region@9bb00000 { 557 reg = <0 0x9bb00000 0 0x700000>; 558 no-map; 559 }; 560 561 cvp_mem: cvp-region@9c200000 { 562 reg = <0 0x9c200000 0 0x700000>; 563 no-map; 564 }; 565 566 cdsp_mem: cdsp-region@9c900000 { 567 reg = <0 0x9c900000 0 0x2000000>; 568 no-map; 569 }; 570 571 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 572 reg = <0 0x9e900000 0 0x80000>; 573 no-map; 574 }; 575 576 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 577 reg = <0 0x9e980000 0 0x80000>; 578 no-map; 579 }; 580 581 adspslpi_mem: adspslpi-region@9ea00000 { 582 reg = <0 0x9ea00000 0 0x4080000>; 583 no-map; 584 }; 585 586 /* uefi region can be reused by apps */ 587 588 /* Linux kernel image is loaded at 0xa8000000 */ 589 590 rmtfs_mem: rmtfs-region@d4a80000 { 591 compatible = "qcom,rmtfs-mem"; 592 reg = <0x0 0xd4a80000 0x0 0x280000>; 593 no-map; 594 595 qcom,client-id = <1>; 596 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 597 }; 598 599 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 600 reg = <0 0xd4d00000 0 0x3300000>; 601 no-map; 602 }; 603 604 tz_reserved_mem: tz-reserved-region@d8000000 { 605 reg = <0 0xd8000000 0 0x100000>; 606 no-map; 607 }; 608 609 cpucp_fw_mem: cpucp-fw-region@d8140000 { 610 reg = <0 0xd8140000 0 0x1c0000>; 611 no-map; 612 }; 613 614 qtee_mem: qtee-region@d8300000 { 615 reg = <0 0xd8300000 0 0x500000>; 616 no-map; 617 }; 618 619 ta_mem: ta-region@d8800000 { 620 reg = <0 0xd8800000 0 0x8a00000>; 621 no-map; 622 }; 623 624 tz_tags_mem: tz-tags-region@e1200000 { 625 reg = <0 0xe1200000 0 0x2740000>; 626 no-map; 627 }; 628 629 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 630 reg = <0 0xe6440000 0 0x279000>; 631 no-map; 632 }; 633 634 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 635 reg = <0 0xf3600000 0 0x4aee000>; 636 no-map; 637 }; 638 639 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 640 reg = <0 0xf80ee000 0 0x1000>; 641 no-map; 642 }; 643 644 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 645 reg = <0 0xf80ef000 0 0x9000>; 646 no-map; 647 }; 648 649 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 650 reg = <0 0xf80f8000 0 0x4000>; 651 no-map; 652 }; 653 654 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 655 reg = <0 0xf80fc000 0 0x4000>; 656 no-map; 657 }; 658 659 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 660 reg = <0 0xf8100000 0 0x100000>; 661 no-map; 662 }; 663 664 oem_vm_mem: oem-vm-region@f8400000 { 665 reg = <0 0xf8400000 0 0x4800000>; 666 no-map; 667 }; 668 669 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 670 reg = <0 0xfcc00000 0 0x4000>; 671 no-map; 672 }; 673 674 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 675 reg = <0 0xfcc04000 0 0x100000>; 676 no-map; 677 }; 678 679 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 680 reg = <0 0xfce00000 0 0x2900000>; 681 no-map; 682 }; 683 684 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 685 reg = <0 0xff700000 0 0x100000>; 686 no-map; 687 }; 688 }; 689 690 smp2p-adsp { 691 compatible = "qcom,smp2p"; 692 qcom,smem = <443>, <429>; 693 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 694 IPCC_MPROC_SIGNAL_SMP2P 695 IRQ_TYPE_EDGE_RISING>; 696 mboxes = <&ipcc IPCC_CLIENT_LPASS 697 IPCC_MPROC_SIGNAL_SMP2P>; 698 699 qcom,local-pid = <0>; 700 qcom,remote-pid = <2>; 701 702 smp2p_adsp_out: master-kernel { 703 qcom,entry-name = "master-kernel"; 704 #qcom,smem-state-cells = <1>; 705 }; 706 707 smp2p_adsp_in: slave-kernel { 708 qcom,entry-name = "slave-kernel"; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 }; 713 714 smp2p-cdsp { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <94>, <432>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_CDSP 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <5>; 725 726 smp2p_cdsp_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_cdsp_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 smp2p-modem { 739 compatible = "qcom,smp2p"; 740 qcom,smem = <435>, <428>; 741 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 742 IPCC_MPROC_SIGNAL_SMP2P 743 IRQ_TYPE_EDGE_RISING>; 744 mboxes = <&ipcc IPCC_CLIENT_MPSS 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,local-pid = <0>; 748 qcom,remote-pid = <1>; 749 750 smp2p_modem_out: master-kernel { 751 qcom,entry-name = "master-kernel"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 smp2p_modem_in: slave-kernel { 756 qcom,entry-name = "slave-kernel"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 761 ipa_smp2p_out: ipa-ap-to-modem { 762 qcom,entry-name = "ipa"; 763 #qcom,smem-state-cells = <1>; 764 }; 765 766 ipa_smp2p_in: ipa-modem-to-ap { 767 qcom,entry-name = "ipa"; 768 interrupt-controller; 769 #interrupt-cells = <2>; 770 }; 771 }; 772 773 soc: soc@0 { 774 compatible = "simple-bus"; 775 ranges = <0 0 0 0 0x10 0>; 776 dma-ranges = <0 0 0 0 0x10 0>; 777 778 #address-cells = <2>; 779 #size-cells = <2>; 780 781 gcc: clock-controller@100000 { 782 compatible = "qcom,sm8550-gcc"; 783 reg = <0 0x00100000 0 0x1f4200>; 784 #clock-cells = <1>; 785 #reset-cells = <1>; 786 #power-domain-cells = <1>; 787 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 788 <&pcie0_phy>, 789 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 790 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 791 <&ufs_mem_phy 0>, 792 <&ufs_mem_phy 1>, 793 <&ufs_mem_phy 2>, 794 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 795 }; 796 797 ipcc: mailbox@408000 { 798 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 799 reg = <0 0x00408000 0 0x1000>; 800 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-controller; 802 #interrupt-cells = <3>; 803 #mbox-cells = <2>; 804 }; 805 806 gpi_dma2: dma-controller@800000 { 807 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 808 #dma-cells = <3>; 809 reg = <0 0x00800000 0 0x60000>; 810 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 822 dma-channels = <12>; 823 dma-channel-mask = <0x3e>; 824 iommus = <&apps_smmu 0x436 0>; 825 dma-coherent; 826 status = "disabled"; 827 }; 828 829 qupv3_id_1: geniqup@8c0000 { 830 compatible = "qcom,geni-se-qup"; 831 reg = <0 0x008c0000 0 0x2000>; 832 ranges; 833 clock-names = "m-ahb", "s-ahb"; 834 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 835 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 836 iommus = <&apps_smmu 0x423 0>; 837 dma-coherent; 838 #address-cells = <2>; 839 #size-cells = <2>; 840 status = "disabled"; 841 842 i2c8: i2c@880000 { 843 compatible = "qcom,geni-i2c"; 844 reg = <0 0x00880000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_i2c8_data_clk>; 849 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 853 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 854 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 855 interconnect-names = "qup-core", "qup-config", "qup-memory"; 856 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 857 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 858 dma-names = "tx", "rx"; 859 status = "disabled"; 860 }; 861 862 spi8: spi@880000 { 863 compatible = "qcom,geni-spi"; 864 reg = <0 0x00880000 0 0x4000>; 865 clock-names = "se"; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 867 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 872 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 873 interconnect-names = "qup-core", "qup-config", "qup-memory"; 874 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 875 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 876 dma-names = "tx", "rx"; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 status = "disabled"; 880 }; 881 882 i2c9: i2c@884000 { 883 compatible = "qcom,geni-i2c"; 884 reg = <0 0x00884000 0 0x4000>; 885 clock-names = "se"; 886 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&qup_i2c9_data_clk>; 889 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 893 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 894 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 895 interconnect-names = "qup-core", "qup-config", "qup-memory"; 896 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 897 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 898 dma-names = "tx", "rx"; 899 status = "disabled"; 900 }; 901 902 spi9: spi@884000 { 903 compatible = "qcom,geni-spi"; 904 reg = <0 0x00884000 0 0x4000>; 905 clock-names = "se"; 906 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 907 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 910 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 912 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 913 interconnect-names = "qup-core", "qup-config", "qup-memory"; 914 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 i2c10: i2c@888000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0 0x00888000 0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c10_data_clk>; 929 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", "qup-memory"; 936 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 937 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 938 dma-names = "tx", "rx"; 939 status = "disabled"; 940 }; 941 942 spi10: spi@888000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x00888000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 947 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 952 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 954 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 955 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 956 dma-names = "tx", "rx"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 962 i2c11: i2c@88c000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0 0x0088c000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&qup_i2c11_data_clk>; 969 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 974 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 975 interconnect-names = "qup-core", "qup-config", "qup-memory"; 976 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 977 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 978 dma-names = "tx", "rx"; 979 status = "disabled"; 980 }; 981 982 spi11: spi@88c000 { 983 compatible = "qcom,geni-spi"; 984 reg = <0 0x0088c000 0 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 987 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 990 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 991 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 992 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 993 interconnect-names = "qup-core", "qup-config", "qup-memory"; 994 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 995 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 996 dma-names = "tx", "rx"; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 i2c12: i2c@890000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x00890000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c12_data_clk>; 1009 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1013 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1014 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1015 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1016 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1017 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1018 dma-names = "tx", "rx"; 1019 status = "disabled"; 1020 }; 1021 1022 spi12: spi@890000 { 1023 compatible = "qcom,geni-spi"; 1024 reg = <0 0x00890000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1027 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1030 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1031 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1032 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1033 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1034 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1035 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1036 dma-names = "tx", "rx"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 i2c13: i2c@894000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00894000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c13_data_clk>; 1049 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1054 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1055 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1056 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1057 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1058 dma-names = "tx", "rx"; 1059 status = "disabled"; 1060 }; 1061 1062 spi13: spi@894000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x00894000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1067 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1071 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1072 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1073 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1074 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1075 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1076 dma-names = "tx", "rx"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 uart14: serial@898000 { 1083 compatible = "qcom,geni-uart"; 1084 reg = <0 0x898000 0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1089 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1090 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1092 interconnect-names = "qup-core", "qup-config"; 1093 status = "disabled"; 1094 }; 1095 1096 i2c15: i2c@89c000 { 1097 compatible = "qcom,geni-i2c"; 1098 reg = <0 0x0089c000 0 0x4000>; 1099 clock-names = "se"; 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_i2c15_data_clk>; 1103 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1107 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1108 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1109 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1110 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1111 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1112 dma-names = "tx", "rx"; 1113 status = "disabled"; 1114 }; 1115 1116 spi15: spi@89c000 { 1117 compatible = "qcom,geni-spi"; 1118 reg = <0 0x0089c000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1121 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1124 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1125 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1126 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1127 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1128 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1129 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1130 dma-names = "tx", "rx"; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 i2c_master_hub_0: geniqup@9c0000 { 1138 compatible = "qcom,geni-se-i2c-master-hub"; 1139 reg = <0x0 0x009c0000 0x0 0x2000>; 1140 clock-names = "s-ahb"; 1141 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1142 #address-cells = <2>; 1143 #size-cells = <2>; 1144 ranges; 1145 status = "disabled"; 1146 1147 i2c_hub_0: i2c@980000 { 1148 compatible = "qcom,geni-i2c-master-hub"; 1149 reg = <0x0 0x00980000 0x0 0x4000>; 1150 clock-names = "se", "core"; 1151 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1152 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&hub_i2c0_data_clk>; 1155 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 status = "disabled"; 1162 }; 1163 1164 i2c_hub_1: i2c@984000 { 1165 compatible = "qcom,geni-i2c-master-hub"; 1166 reg = <0x0 0x00984000 0x0 0x4000>; 1167 clock-names = "se", "core"; 1168 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1169 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&hub_i2c1_data_clk>; 1172 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1176 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1177 interconnect-names = "qup-core", "qup-config"; 1178 status = "disabled"; 1179 }; 1180 1181 i2c_hub_2: i2c@988000 { 1182 compatible = "qcom,geni-i2c-master-hub"; 1183 reg = <0x0 0x00988000 0x0 0x4000>; 1184 clock-names = "se", "core"; 1185 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1186 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1187 pinctrl-names = "default"; 1188 pinctrl-0 = <&hub_i2c2_data_clk>; 1189 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1193 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1194 interconnect-names = "qup-core", "qup-config"; 1195 status = "disabled"; 1196 }; 1197 1198 i2c_hub_3: i2c@98c000 { 1199 compatible = "qcom,geni-i2c-master-hub"; 1200 reg = <0x0 0x0098c000 0x0 0x4000>; 1201 clock-names = "se", "core"; 1202 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1203 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&hub_i2c3_data_clk>; 1206 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c_hub_4: i2c@990000 { 1216 compatible = "qcom,geni-i2c-master-hub"; 1217 reg = <0x0 0x00990000 0x0 0x4000>; 1218 clock-names = "se", "core"; 1219 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1220 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&hub_i2c4_data_clk>; 1223 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1228 interconnect-names = "qup-core", "qup-config"; 1229 status = "disabled"; 1230 }; 1231 1232 i2c_hub_5: i2c@994000 { 1233 compatible = "qcom,geni-i2c-master-hub"; 1234 reg = <0 0x00994000 0 0x4000>; 1235 clock-names = "se", "core"; 1236 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1237 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&hub_i2c5_data_clk>; 1240 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1245 interconnect-names = "qup-core", "qup-config"; 1246 status = "disabled"; 1247 }; 1248 1249 i2c_hub_6: i2c@998000 { 1250 compatible = "qcom,geni-i2c-master-hub"; 1251 reg = <0 0x00998000 0 0x4000>; 1252 clock-names = "se", "core"; 1253 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1254 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&hub_i2c6_data_clk>; 1257 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c_hub_7: i2c@99c000 { 1267 compatible = "qcom,geni-i2c-master-hub"; 1268 reg = <0 0x0099c000 0 0x4000>; 1269 clock-names = "se", "core"; 1270 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&hub_i2c7_data_clk>; 1274 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1279 interconnect-names = "qup-core", "qup-config"; 1280 status = "disabled"; 1281 }; 1282 1283 i2c_hub_8: i2c@9a0000 { 1284 compatible = "qcom,geni-i2c-master-hub"; 1285 reg = <0 0x009a0000 0 0x4000>; 1286 clock-names = "se", "core"; 1287 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1288 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1289 pinctrl-names = "default"; 1290 pinctrl-0 = <&hub_i2c8_data_clk>; 1291 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1295 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1296 interconnect-names = "qup-core", "qup-config"; 1297 status = "disabled"; 1298 }; 1299 1300 i2c_hub_9: i2c@9a4000 { 1301 compatible = "qcom,geni-i2c-master-hub"; 1302 reg = <0 0x009a4000 0 0x4000>; 1303 clock-names = "se", "core"; 1304 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1305 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&hub_i2c9_data_clk>; 1308 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1312 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1313 interconnect-names = "qup-core", "qup-config"; 1314 status = "disabled"; 1315 }; 1316 }; 1317 1318 gpi_dma1: dma-controller@a00000 { 1319 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1320 #dma-cells = <3>; 1321 reg = <0 0x00a00000 0 0x60000>; 1322 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1334 dma-channels = <12>; 1335 dma-channel-mask = <0x1e>; 1336 iommus = <&apps_smmu 0xb6 0>; 1337 dma-coherent; 1338 status = "disabled"; 1339 }; 1340 1341 qupv3_id_0: geniqup@ac0000 { 1342 compatible = "qcom,geni-se-qup"; 1343 reg = <0 0x00ac0000 0 0x2000>; 1344 ranges; 1345 clock-names = "m-ahb", "s-ahb"; 1346 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1347 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1348 iommus = <&apps_smmu 0xa3 0>; 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1350 interconnect-names = "qup-core"; 1351 dma-coherent; 1352 #address-cells = <2>; 1353 #size-cells = <2>; 1354 status = "disabled"; 1355 1356 i2c0: i2c@a80000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0 0x00a80000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_i2c0_data_clk>; 1363 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1367 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1368 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1369 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1370 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1371 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 status = "disabled"; 1374 }; 1375 1376 spi0: spi@a80000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x00a80000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1381 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1384 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1386 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1387 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1388 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1389 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1390 dma-names = "tx", "rx"; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 status = "disabled"; 1394 }; 1395 1396 i2c1: i2c@a84000 { 1397 compatible = "qcom,geni-i2c"; 1398 reg = <0 0x00a84000 0 0x4000>; 1399 clock-names = "se"; 1400 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_i2c1_data_clk>; 1403 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1408 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1409 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1410 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1411 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1412 dma-names = "tx", "rx"; 1413 status = "disabled"; 1414 }; 1415 1416 spi1: spi@a84000 { 1417 compatible = "qcom,geni-spi"; 1418 reg = <0 0x00a84000 0 0x4000>; 1419 clock-names = "se"; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1421 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1425 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1426 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1427 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1428 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1429 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1430 dma-names = "tx", "rx"; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 i2c2: i2c@a88000 { 1437 compatible = "qcom,geni-i2c"; 1438 reg = <0 0x00a88000 0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&qup_i2c2_data_clk>; 1443 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1447 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1448 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1449 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1450 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1451 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1452 dma-names = "tx", "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 spi2: spi@a88000 { 1457 compatible = "qcom,geni-spi"; 1458 reg = <0 0x00a88000 0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1461 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1465 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1466 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1467 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1468 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1469 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1470 dma-names = "tx", "rx"; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 i2c3: i2c@a8c000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0 0x00a8c000 0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&qup_i2c3_data_clk>; 1483 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1488 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1489 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1490 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1491 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 spi3: spi@a8c000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00a8c000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1501 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1509 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1510 dma-names = "tx", "rx"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 i2c4: i2c@a90000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00a90000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c4_data_clk>; 1523 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1527 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1528 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1529 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1530 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1531 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1532 dma-names = "tx", "rx"; 1533 status = "disabled"; 1534 }; 1535 1536 spi4: spi@a90000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x00a90000 0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1541 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1546 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1547 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1548 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1549 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1550 dma-names = "tx", "rx"; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 status = "disabled"; 1554 }; 1555 1556 i2c5: i2c@a94000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0 0x00a94000 0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_i2c5_data_clk>; 1563 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1566 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1567 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1568 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1569 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1570 dma-names = "tx", "rx"; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 spi5: spi@a94000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0 0x00a94000 0 0x4000>; 1579 clock-names = "se"; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1581 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1585 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1586 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1587 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1588 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1589 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 status = "disabled"; 1594 }; 1595 1596 i2c6: i2c@a98000 { 1597 compatible = "qcom,geni-i2c"; 1598 reg = <0 0x00a98000 0 0x4000>; 1599 clock-names = "se"; 1600 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1601 pinctrl-names = "default"; 1602 pinctrl-0 = <&qup_i2c6_data_clk>; 1603 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1606 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1607 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1608 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1609 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1610 dma-names = "tx", "rx"; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 spi6: spi@a98000 { 1617 compatible = "qcom,geni-spi"; 1618 reg = <0 0x00a98000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1621 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1624 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1625 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1626 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1627 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1628 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1629 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1630 dma-names = "tx", "rx"; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 status = "disabled"; 1634 }; 1635 1636 uart7: serial@a9c000 { 1637 compatible = "qcom,geni-debug-uart"; 1638 reg = <0 0x00a9c000 0 0x4000>; 1639 clock-names = "se"; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&qup_uart7_default>; 1643 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1644 interconnect-names = "qup-core", "qup-config"; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1646 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1647 status = "disabled"; 1648 }; 1649 }; 1650 1651 cnoc_main: interconnect@1500000 { 1652 compatible = "qcom,sm8550-cnoc-main"; 1653 reg = <0 0x01500000 0 0x13080>; 1654 #interconnect-cells = <2>; 1655 qcom,bcm-voters = <&apps_bcm_voter>; 1656 }; 1657 1658 config_noc: interconnect@1600000 { 1659 compatible = "qcom,sm8550-config-noc"; 1660 reg = <0 0x01600000 0 0x6200>; 1661 #interconnect-cells = <2>; 1662 qcom,bcm-voters = <&apps_bcm_voter>; 1663 }; 1664 1665 system_noc: interconnect@1680000 { 1666 compatible = "qcom,sm8550-system-noc"; 1667 reg = <0 0x01680000 0 0x1d080>; 1668 #interconnect-cells = <2>; 1669 qcom,bcm-voters = <&apps_bcm_voter>; 1670 }; 1671 1672 pcie_noc: interconnect@16c0000 { 1673 compatible = "qcom,sm8550-pcie-anoc"; 1674 reg = <0 0x016c0000 0 0x12200>; 1675 #interconnect-cells = <2>; 1676 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1677 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1678 qcom,bcm-voters = <&apps_bcm_voter>; 1679 }; 1680 1681 aggre1_noc: interconnect@16e0000 { 1682 compatible = "qcom,sm8550-aggre1-noc"; 1683 reg = <0 0x016e0000 0 0x14400>; 1684 #interconnect-cells = <2>; 1685 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1686 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1687 qcom,bcm-voters = <&apps_bcm_voter>; 1688 }; 1689 1690 aggre2_noc: interconnect@1700000 { 1691 compatible = "qcom,sm8550-aggre2-noc"; 1692 reg = <0 0x01700000 0 0x1e400>; 1693 #interconnect-cells = <2>; 1694 clocks = <&rpmhcc RPMH_IPA_CLK>; 1695 qcom,bcm-voters = <&apps_bcm_voter>; 1696 }; 1697 1698 mmss_noc: interconnect@1780000 { 1699 compatible = "qcom,sm8550-mmss-noc"; 1700 reg = <0 0x01780000 0 0x5b800>; 1701 #interconnect-cells = <2>; 1702 qcom,bcm-voters = <&apps_bcm_voter>; 1703 }; 1704 1705 rng: rng@10c3000 { 1706 compatible = "qcom,sm8550-trng", "qcom,trng"; 1707 reg = <0 0x010c3000 0 0x1000>; 1708 }; 1709 1710 pcie0: pcie@1c00000 { 1711 device_type = "pci"; 1712 compatible = "qcom,pcie-sm8550"; 1713 reg = <0 0x01c00000 0 0x3000>, 1714 <0 0x60000000 0 0xf1d>, 1715 <0 0x60000f20 0 0xa8>, 1716 <0 0x60001000 0 0x1000>, 1717 <0 0x60100000 0 0x100000>; 1718 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1719 #address-cells = <3>; 1720 #size-cells = <2>; 1721 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1722 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1723 bus-range = <0x00 0xff>; 1724 1725 dma-coherent; 1726 1727 linux,pci-domain = <0>; 1728 num-lanes = <2>; 1729 1730 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "msi0", 1739 "msi1", 1740 "msi2", 1741 "msi3", 1742 "msi4", 1743 "msi5", 1744 "msi6", 1745 "msi7"; 1746 #interrupt-cells = <1>; 1747 interrupt-map-mask = <0 0 0 0x7>; 1748 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1749 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1750 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1751 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1752 1753 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1754 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1755 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1756 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1757 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1758 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1759 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1760 clock-names = "aux", 1761 "cfg", 1762 "bus_master", 1763 "bus_slave", 1764 "slave_q2a", 1765 "ddrss_sf_tbu", 1766 "noc_aggr"; 1767 1768 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1770 interconnect-names = "pcie-mem", "cpu-pcie"; 1771 1772 msi-map = <0x0 &gic_its 0x1400 0x1>, 1773 <0x100 &gic_its 0x1401 0x1>; 1774 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1775 <0x100 &apps_smmu 0x1401 0x1>; 1776 1777 resets = <&gcc GCC_PCIE_0_BCR>; 1778 reset-names = "pci"; 1779 1780 power-domains = <&gcc PCIE_0_GDSC>; 1781 1782 phys = <&pcie0_phy>; 1783 phy-names = "pciephy"; 1784 1785 status = "disabled"; 1786 1787 pcieport0: pcie@0 { 1788 device_type = "pci"; 1789 reg = <0x0 0x0 0x0 0x0 0x0>; 1790 bus-range = <0x01 0xff>; 1791 1792 #address-cells = <3>; 1793 #size-cells = <2>; 1794 ranges; 1795 }; 1796 }; 1797 1798 pcie0_phy: phy@1c06000 { 1799 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1800 reg = <0 0x01c06000 0 0x2000>; 1801 1802 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1803 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1804 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1805 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1806 <&gcc GCC_PCIE_0_PIPE_CLK>; 1807 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1808 "pipe"; 1809 1810 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1811 reset-names = "phy"; 1812 1813 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1814 assigned-clock-rates = <100000000>; 1815 1816 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1817 1818 #clock-cells = <0>; 1819 clock-output-names = "pcie0_pipe_clk"; 1820 1821 #phy-cells = <0>; 1822 1823 status = "disabled"; 1824 }; 1825 1826 pcie1: pcie@1c08000 { 1827 device_type = "pci"; 1828 compatible = "qcom,pcie-sm8550"; 1829 reg = <0x0 0x01c08000 0x0 0x3000>, 1830 <0x0 0x40000000 0x0 0xf1d>, 1831 <0x0 0x40000f20 0x0 0xa8>, 1832 <0x0 0x40001000 0x0 0x1000>, 1833 <0x0 0x40100000 0x0 0x100000>; 1834 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1835 #address-cells = <3>; 1836 #size-cells = <2>; 1837 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1838 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1839 bus-range = <0x00 0xff>; 1840 1841 dma-coherent; 1842 1843 linux,pci-domain = <1>; 1844 num-lanes = <2>; 1845 1846 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1854 interrupt-names = "msi0", 1855 "msi1", 1856 "msi2", 1857 "msi3", 1858 "msi4", 1859 "msi5", 1860 "msi6", 1861 "msi7"; 1862 #interrupt-cells = <1>; 1863 interrupt-map-mask = <0 0 0 0x7>; 1864 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1865 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1866 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1867 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1868 1869 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1870 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1871 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1872 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1873 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1874 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1875 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1876 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1877 clock-names = "aux", 1878 "cfg", 1879 "bus_master", 1880 "bus_slave", 1881 "slave_q2a", 1882 "ddrss_sf_tbu", 1883 "noc_aggr", 1884 "cnoc_sf_axi"; 1885 1886 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1887 assigned-clock-rates = <19200000>; 1888 1889 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1890 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1891 interconnect-names = "pcie-mem", "cpu-pcie"; 1892 1893 msi-map = <0x0 &gic_its 0x1480 0x1>, 1894 <0x100 &gic_its 0x1481 0x1>; 1895 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1896 <0x100 &apps_smmu 0x1481 0x1>; 1897 1898 resets = <&gcc GCC_PCIE_1_BCR>, 1899 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1900 reset-names = "pci", "link_down"; 1901 1902 power-domains = <&gcc PCIE_1_GDSC>; 1903 1904 phys = <&pcie1_phy>; 1905 phy-names = "pciephy"; 1906 1907 status = "disabled"; 1908 1909 pcie@0 { 1910 device_type = "pci"; 1911 reg = <0x0 0x0 0x0 0x0 0x0>; 1912 bus-range = <0x01 0xff>; 1913 1914 #address-cells = <3>; 1915 #size-cells = <2>; 1916 ranges; 1917 }; 1918 }; 1919 1920 pcie1_phy: phy@1c0e000 { 1921 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1922 reg = <0x0 0x01c0e000 0x0 0x2000>; 1923 1924 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1925 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1926 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1927 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1928 <&gcc GCC_PCIE_1_PIPE_CLK>; 1929 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1930 "pipe"; 1931 1932 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1933 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1934 reset-names = "phy", "phy_nocsr"; 1935 1936 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1937 assigned-clock-rates = <100000000>; 1938 1939 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1940 1941 #clock-cells = <1>; 1942 clock-output-names = "pcie1_pipe_clk"; 1943 1944 #phy-cells = <0>; 1945 1946 status = "disabled"; 1947 }; 1948 1949 cryptobam: dma-controller@1dc4000 { 1950 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1951 reg = <0x0 0x01dc4000 0x0 0x28000>; 1952 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1953 #dma-cells = <1>; 1954 qcom,ee = <0>; 1955 qcom,num-ees = <4>; 1956 num-channels = <20>; 1957 qcom,controlled-remotely; 1958 iommus = <&apps_smmu 0x480 0x0>, 1959 <&apps_smmu 0x481 0x0>; 1960 }; 1961 1962 crypto: crypto@1dfa000 { 1963 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1964 reg = <0x0 0x01dfa000 0x0 0x6000>; 1965 dmas = <&cryptobam 4>, <&cryptobam 5>; 1966 dma-names = "rx", "tx"; 1967 iommus = <&apps_smmu 0x480 0x0>, 1968 <&apps_smmu 0x481 0x0>; 1969 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1970 interconnect-names = "memory"; 1971 }; 1972 1973 ufs_mem_phy: phy@1d80000 { 1974 compatible = "qcom,sm8550-qmp-ufs-phy"; 1975 reg = <0x0 0x01d80000 0x0 0x2000>; 1976 clocks = <&rpmhcc RPMH_CXO_CLK>, 1977 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1978 <&tcsr TCSR_UFS_CLKREF_EN>; 1979 clock-names = "ref", 1980 "ref_aux", 1981 "qref"; 1982 1983 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1984 1985 resets = <&ufs_mem_hc 0>; 1986 reset-names = "ufsphy"; 1987 1988 #clock-cells = <1>; 1989 #phy-cells = <0>; 1990 1991 status = "disabled"; 1992 }; 1993 1994 ufs_mem_hc: ufs@1d84000 { 1995 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1996 "jedec,ufs-2.0"; 1997 reg = <0x0 0x01d84000 0x0 0x3000>; 1998 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1999 phys = <&ufs_mem_phy>; 2000 phy-names = "ufsphy"; 2001 lanes-per-direction = <2>; 2002 #reset-cells = <1>; 2003 resets = <&gcc GCC_UFS_PHY_BCR>; 2004 reset-names = "rst"; 2005 2006 power-domains = <&gcc UFS_PHY_GDSC>; 2007 required-opps = <&rpmhpd_opp_nom>; 2008 2009 iommus = <&apps_smmu 0x60 0x0>; 2010 dma-coherent; 2011 2012 operating-points-v2 = <&ufs_opp_table>; 2013 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 2014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2015 2016 interconnect-names = "ufs-ddr", "cpu-ufs"; 2017 clock-names = "core_clk", 2018 "bus_aggr_clk", 2019 "iface_clk", 2020 "core_clk_unipro", 2021 "ref_clk", 2022 "tx_lane0_sync_clk", 2023 "rx_lane0_sync_clk", 2024 "rx_lane1_sync_clk"; 2025 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2026 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2027 <&gcc GCC_UFS_PHY_AHB_CLK>, 2028 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2029 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2030 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2031 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2032 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2033 qcom,ice = <&ice>; 2034 2035 status = "disabled"; 2036 2037 ufs_opp_table: opp-table { 2038 compatible = "operating-points-v2"; 2039 2040 opp-75000000 { 2041 opp-hz = /bits/ 64 <75000000>, 2042 /bits/ 64 <0>, 2043 /bits/ 64 <0>, 2044 /bits/ 64 <75000000>, 2045 /bits/ 64 <0>, 2046 /bits/ 64 <0>, 2047 /bits/ 64 <0>, 2048 /bits/ 64 <0>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 }; 2051 2052 opp-150000000 { 2053 opp-hz = /bits/ 64 <150000000>, 2054 /bits/ 64 <0>, 2055 /bits/ 64 <0>, 2056 /bits/ 64 <150000000>, 2057 /bits/ 64 <0>, 2058 /bits/ 64 <0>, 2059 /bits/ 64 <0>, 2060 /bits/ 64 <0>; 2061 required-opps = <&rpmhpd_opp_svs>; 2062 }; 2063 2064 opp-300000000 { 2065 opp-hz = /bits/ 64 <300000000>, 2066 /bits/ 64 <0>, 2067 /bits/ 64 <0>, 2068 /bits/ 64 <300000000>, 2069 /bits/ 64 <0>, 2070 /bits/ 64 <0>, 2071 /bits/ 64 <0>, 2072 /bits/ 64 <0>; 2073 required-opps = <&rpmhpd_opp_nom>; 2074 }; 2075 }; 2076 }; 2077 2078 ice: crypto@1d88000 { 2079 compatible = "qcom,sm8550-inline-crypto-engine", 2080 "qcom,inline-crypto-engine"; 2081 reg = <0 0x01d88000 0 0x8000>; 2082 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2083 }; 2084 2085 tcsr_mutex: hwlock@1f40000 { 2086 compatible = "qcom,tcsr-mutex"; 2087 reg = <0 0x01f40000 0 0x20000>; 2088 #hwlock-cells = <1>; 2089 }; 2090 2091 tcsr: clock-controller@1fc0000 { 2092 compatible = "qcom,sm8550-tcsr", "syscon"; 2093 reg = <0 0x01fc0000 0 0x30000>; 2094 clocks = <&rpmhcc RPMH_CXO_CLK>; 2095 #clock-cells = <1>; 2096 #reset-cells = <1>; 2097 }; 2098 2099 gpu: gpu@3d00000 { 2100 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2101 reg = <0x0 0x03d00000 0x0 0x40000>, 2102 <0x0 0x03d9e000 0x0 0x1000>, 2103 <0x0 0x03d61000 0x0 0x800>; 2104 reg-names = "kgsl_3d0_reg_memory", 2105 "cx_mem", 2106 "cx_dbgc"; 2107 2108 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2109 2110 iommus = <&adreno_smmu 0 0x0>, 2111 <&adreno_smmu 1 0x0>; 2112 2113 operating-points-v2 = <&gpu_opp_table>; 2114 2115 qcom,gmu = <&gmu>; 2116 #cooling-cells = <2>; 2117 2118 status = "disabled"; 2119 2120 zap-shader { 2121 memory-region = <&gpu_micro_code_mem>; 2122 }; 2123 2124 /* Speedbin needs more work on A740+, keep only lower freqs */ 2125 gpu_opp_table: opp-table { 2126 compatible = "operating-points-v2"; 2127 2128 opp-680000000 { 2129 opp-hz = /bits/ 64 <680000000>; 2130 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2131 }; 2132 2133 opp-615000000 { 2134 opp-hz = /bits/ 64 <615000000>; 2135 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2136 }; 2137 2138 opp-550000000 { 2139 opp-hz = /bits/ 64 <550000000>; 2140 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2141 }; 2142 2143 opp-475000000 { 2144 opp-hz = /bits/ 64 <475000000>; 2145 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2146 }; 2147 2148 opp-401000000 { 2149 opp-hz = /bits/ 64 <401000000>; 2150 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2151 }; 2152 2153 opp-348000000 { 2154 opp-hz = /bits/ 64 <348000000>; 2155 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2156 }; 2157 2158 opp-295000000 { 2159 opp-hz = /bits/ 64 <295000000>; 2160 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2161 }; 2162 2163 opp-220000000 { 2164 opp-hz = /bits/ 64 <220000000>; 2165 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2166 }; 2167 }; 2168 }; 2169 2170 gmu: gmu@3d6a000 { 2171 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2172 reg = <0x0 0x03d6a000 0x0 0x35000>, 2173 <0x0 0x03d50000 0x0 0x10000>, 2174 <0x0 0x0b280000 0x0 0x10000>; 2175 reg-names = "gmu", "rscc", "gmu_pdc"; 2176 2177 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2179 interrupt-names = "hfi", "gmu"; 2180 2181 clocks = <&gpucc GPU_CC_AHB_CLK>, 2182 <&gpucc GPU_CC_CX_GMU_CLK>, 2183 <&gpucc GPU_CC_CXO_CLK>, 2184 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2185 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2186 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2187 <&gpucc GPU_CC_DEMET_CLK>; 2188 clock-names = "ahb", 2189 "gmu", 2190 "cxo", 2191 "axi", 2192 "memnoc", 2193 "hub", 2194 "demet"; 2195 2196 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2197 <&gpucc GPU_CC_GX_GDSC>; 2198 power-domain-names = "cx", 2199 "gx"; 2200 2201 iommus = <&adreno_smmu 5 0x0>; 2202 2203 qcom,qmp = <&aoss_qmp>; 2204 2205 operating-points-v2 = <&gmu_opp_table>; 2206 2207 gmu_opp_table: opp-table { 2208 compatible = "operating-points-v2"; 2209 2210 opp-500000000 { 2211 opp-hz = /bits/ 64 <500000000>; 2212 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2213 }; 2214 2215 opp-200000000 { 2216 opp-hz = /bits/ 64 <200000000>; 2217 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2218 }; 2219 }; 2220 }; 2221 2222 gpucc: clock-controller@3d90000 { 2223 compatible = "qcom,sm8550-gpucc"; 2224 reg = <0 0x03d90000 0 0xa000>; 2225 clocks = <&bi_tcxo_div2>, 2226 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2227 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2228 #clock-cells = <1>; 2229 #reset-cells = <1>; 2230 #power-domain-cells = <1>; 2231 }; 2232 2233 adreno_smmu: iommu@3da0000 { 2234 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2235 "qcom,smmu-500", "arm,mmu-500"; 2236 reg = <0x0 0x03da0000 0x0 0x40000>; 2237 #iommu-cells = <2>; 2238 #global-interrupts = <1>; 2239 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2266 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2267 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2268 <&gpucc GPU_CC_AHB_CLK>; 2269 clock-names = "hlos", 2270 "bus", 2271 "iface", 2272 "ahb"; 2273 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2274 dma-coherent; 2275 }; 2276 2277 ipa: ipa@3f40000 { 2278 compatible = "qcom,sm8550-ipa"; 2279 2280 iommus = <&apps_smmu 0x4a0 0x0>, 2281 <&apps_smmu 0x4a2 0x0>; 2282 reg = <0 0x3f40000 0 0x10000>, 2283 <0 0x3f50000 0 0x5000>, 2284 <0 0x3e04000 0 0xfc000>; 2285 reg-names = "ipa-reg", 2286 "ipa-shared", 2287 "gsi"; 2288 2289 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2290 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2291 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2292 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2293 interrupt-names = "ipa", 2294 "gsi", 2295 "ipa-clock-query", 2296 "ipa-setup-ready"; 2297 2298 clocks = <&rpmhcc RPMH_IPA_CLK>; 2299 clock-names = "core"; 2300 2301 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2302 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2303 interconnect-names = "memory", 2304 "config"; 2305 2306 qcom,qmp = <&aoss_qmp>; 2307 2308 qcom,smem-states = <&ipa_smp2p_out 0>, 2309 <&ipa_smp2p_out 1>; 2310 qcom,smem-state-names = "ipa-clock-enabled-valid", 2311 "ipa-clock-enabled"; 2312 2313 status = "disabled"; 2314 }; 2315 2316 remoteproc_mpss: remoteproc@4080000 { 2317 compatible = "qcom,sm8550-mpss-pas"; 2318 reg = <0x0 0x04080000 0x0 0x10000>; 2319 2320 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2321 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2322 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2323 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2324 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2325 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2326 interrupt-names = "wdog", "fatal", "ready", "handover", 2327 "stop-ack", "shutdown-ack"; 2328 2329 clocks = <&rpmhcc RPMH_CXO_CLK>; 2330 clock-names = "xo"; 2331 2332 power-domains = <&rpmhpd RPMHPD_CX>, 2333 <&rpmhpd RPMHPD_MSS>; 2334 power-domain-names = "cx", "mss"; 2335 2336 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2337 2338 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2339 2340 qcom,qmp = <&aoss_qmp>; 2341 2342 qcom,smem-states = <&smp2p_modem_out 0>; 2343 qcom,smem-state-names = "stop"; 2344 2345 status = "disabled"; 2346 2347 glink-edge { 2348 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2349 IPCC_MPROC_SIGNAL_GLINK_QMP 2350 IRQ_TYPE_EDGE_RISING>; 2351 mboxes = <&ipcc IPCC_CLIENT_MPSS 2352 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2353 label = "mpss"; 2354 qcom,remote-pid = <1>; 2355 }; 2356 }; 2357 2358 remoteproc_adsp: remoteproc@6800000 { 2359 compatible = "qcom,sm8550-adsp-pas"; 2360 reg = <0x0 0x06800000 0x0 0x10000>; 2361 2362 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2363 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2364 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2365 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2366 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2367 interrupt-names = "wdog", "fatal", "ready", 2368 "handover", "stop-ack"; 2369 2370 clocks = <&rpmhcc RPMH_CXO_CLK>; 2371 clock-names = "xo"; 2372 2373 power-domains = <&rpmhpd RPMHPD_LCX>, 2374 <&rpmhpd RPMHPD_LMX>; 2375 power-domain-names = "lcx", "lmx"; 2376 2377 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 2378 2379 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2380 2381 qcom,qmp = <&aoss_qmp>; 2382 2383 qcom,smem-states = <&smp2p_adsp_out 0>; 2384 qcom,smem-state-names = "stop"; 2385 2386 status = "disabled"; 2387 2388 remoteproc_adsp_glink: glink-edge { 2389 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2390 IPCC_MPROC_SIGNAL_GLINK_QMP 2391 IRQ_TYPE_EDGE_RISING>; 2392 mboxes = <&ipcc IPCC_CLIENT_LPASS 2393 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2394 2395 label = "lpass"; 2396 qcom,remote-pid = <2>; 2397 2398 fastrpc { 2399 compatible = "qcom,fastrpc"; 2400 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2401 label = "adsp"; 2402 qcom,non-secure-domain; 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 compute-cb@3 { 2407 compatible = "qcom,fastrpc-compute-cb"; 2408 reg = <3>; 2409 iommus = <&apps_smmu 0x1003 0x80>, 2410 <&apps_smmu 0x1063 0x0>; 2411 dma-coherent; 2412 }; 2413 2414 compute-cb@4 { 2415 compatible = "qcom,fastrpc-compute-cb"; 2416 reg = <4>; 2417 iommus = <&apps_smmu 0x1004 0x80>, 2418 <&apps_smmu 0x1064 0x0>; 2419 dma-coherent; 2420 }; 2421 2422 compute-cb@5 { 2423 compatible = "qcom,fastrpc-compute-cb"; 2424 reg = <5>; 2425 iommus = <&apps_smmu 0x1005 0x80>, 2426 <&apps_smmu 0x1065 0x0>; 2427 dma-coherent; 2428 }; 2429 2430 compute-cb@6 { 2431 compatible = "qcom,fastrpc-compute-cb"; 2432 reg = <6>; 2433 iommus = <&apps_smmu 0x1006 0x80>, 2434 <&apps_smmu 0x1066 0x0>; 2435 dma-coherent; 2436 }; 2437 2438 compute-cb@7 { 2439 compatible = "qcom,fastrpc-compute-cb"; 2440 reg = <7>; 2441 iommus = <&apps_smmu 0x1007 0x80>, 2442 <&apps_smmu 0x1067 0x0>; 2443 dma-coherent; 2444 }; 2445 }; 2446 2447 gpr { 2448 compatible = "qcom,gpr"; 2449 qcom,glink-channels = "adsp_apps"; 2450 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2451 qcom,intents = <512 20>; 2452 #address-cells = <1>; 2453 #size-cells = <0>; 2454 2455 q6apm: service@1 { 2456 compatible = "qcom,q6apm"; 2457 reg = <GPR_APM_MODULE_IID>; 2458 #sound-dai-cells = <0>; 2459 qcom,protection-domain = "avs/audio", 2460 "msm/adsp/audio_pd"; 2461 2462 q6apmdai: dais { 2463 compatible = "qcom,q6apm-dais"; 2464 iommus = <&apps_smmu 0x1001 0x80>, 2465 <&apps_smmu 0x1061 0x0>; 2466 }; 2467 2468 q6apmbedai: bedais { 2469 compatible = "qcom,q6apm-lpass-dais"; 2470 #sound-dai-cells = <1>; 2471 }; 2472 }; 2473 2474 q6prm: service@2 { 2475 compatible = "qcom,q6prm"; 2476 reg = <GPR_PRM_MODULE_IID>; 2477 qcom,protection-domain = "avs/audio", 2478 "msm/adsp/audio_pd"; 2479 2480 q6prmcc: clock-controller { 2481 compatible = "qcom,q6prm-lpass-clocks"; 2482 #clock-cells = <2>; 2483 }; 2484 }; 2485 }; 2486 }; 2487 }; 2488 2489 lpass_wsa2macro: codec@6aa0000 { 2490 compatible = "qcom,sm8550-lpass-wsa-macro"; 2491 reg = <0 0x06aa0000 0 0x1000>; 2492 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2493 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2494 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2495 <&lpass_vamacro>; 2496 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2497 2498 #clock-cells = <0>; 2499 clock-output-names = "wsa2-mclk"; 2500 #sound-dai-cells = <1>; 2501 }; 2502 2503 swr3: soundwire@6ab0000 { 2504 compatible = "qcom,soundwire-v2.0.0"; 2505 reg = <0 0x06ab0000 0 0x10000>; 2506 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2507 clocks = <&lpass_wsa2macro>; 2508 clock-names = "iface"; 2509 label = "WSA2"; 2510 2511 pinctrl-0 = <&wsa2_swr_active>; 2512 pinctrl-names = "default"; 2513 2514 qcom,din-ports = <4>; 2515 qcom,dout-ports = <9>; 2516 2517 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2518 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2519 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2522 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2523 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2525 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2526 2527 #address-cells = <2>; 2528 #size-cells = <0>; 2529 #sound-dai-cells = <1>; 2530 status = "disabled"; 2531 }; 2532 2533 lpass_rxmacro: codec@6ac0000 { 2534 compatible = "qcom,sm8550-lpass-rx-macro"; 2535 reg = <0 0x06ac0000 0 0x1000>; 2536 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2537 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2538 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2539 <&lpass_vamacro>; 2540 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2541 2542 #clock-cells = <0>; 2543 clock-output-names = "mclk"; 2544 #sound-dai-cells = <1>; 2545 }; 2546 2547 swr1: soundwire@6ad0000 { 2548 compatible = "qcom,soundwire-v2.0.0"; 2549 reg = <0 0x06ad0000 0 0x10000>; 2550 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&lpass_rxmacro>; 2552 clock-names = "iface"; 2553 label = "RX"; 2554 2555 pinctrl-0 = <&rx_swr_active>; 2556 pinctrl-names = "default"; 2557 2558 qcom,din-ports = <1>; 2559 qcom,dout-ports = <11>; 2560 2561 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2562 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2563 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2564 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2565 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2566 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2567 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2568 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2569 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2570 2571 #address-cells = <2>; 2572 #size-cells = <0>; 2573 #sound-dai-cells = <1>; 2574 status = "disabled"; 2575 }; 2576 2577 lpass_txmacro: codec@6ae0000 { 2578 compatible = "qcom,sm8550-lpass-tx-macro"; 2579 reg = <0 0x06ae0000 0 0x1000>; 2580 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2581 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2582 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2583 <&lpass_vamacro>; 2584 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2585 2586 #clock-cells = <0>; 2587 clock-output-names = "mclk"; 2588 #sound-dai-cells = <1>; 2589 }; 2590 2591 lpass_wsamacro: codec@6b00000 { 2592 compatible = "qcom,sm8550-lpass-wsa-macro"; 2593 reg = <0 0x06b00000 0 0x1000>; 2594 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2595 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2596 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2597 <&lpass_vamacro>; 2598 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2599 2600 #clock-cells = <0>; 2601 clock-output-names = "mclk"; 2602 #sound-dai-cells = <1>; 2603 }; 2604 2605 swr0: soundwire@6b10000 { 2606 compatible = "qcom,soundwire-v2.0.0"; 2607 reg = <0 0x06b10000 0 0x10000>; 2608 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2609 clocks = <&lpass_wsamacro>; 2610 clock-names = "iface"; 2611 label = "WSA"; 2612 2613 pinctrl-0 = <&wsa_swr_active>; 2614 pinctrl-names = "default"; 2615 2616 qcom,din-ports = <4>; 2617 qcom,dout-ports = <9>; 2618 2619 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2620 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2621 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2622 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2623 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2624 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2625 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2626 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2627 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2628 2629 #address-cells = <2>; 2630 #size-cells = <0>; 2631 #sound-dai-cells = <1>; 2632 status = "disabled"; 2633 }; 2634 2635 swr2: soundwire@6d30000 { 2636 compatible = "qcom,soundwire-v2.0.0"; 2637 reg = <0 0x06d30000 0 0x10000>; 2638 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2640 interrupt-names = "core", "wakeup"; 2641 clocks = <&lpass_txmacro>; 2642 clock-names = "iface"; 2643 label = "TX"; 2644 2645 pinctrl-0 = <&tx_swr_active>; 2646 pinctrl-names = "default"; 2647 2648 qcom,din-ports = <4>; 2649 qcom,dout-ports = <0>; 2650 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2651 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2652 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2653 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2654 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2655 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2656 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2657 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2658 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2659 2660 #address-cells = <2>; 2661 #size-cells = <0>; 2662 #sound-dai-cells = <1>; 2663 status = "disabled"; 2664 }; 2665 2666 lpass_vamacro: codec@6d44000 { 2667 compatible = "qcom,sm8550-lpass-va-macro"; 2668 reg = <0 0x06d44000 0 0x1000>; 2669 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2670 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2671 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2672 clock-names = "mclk", "macro", "dcodec"; 2673 2674 #clock-cells = <0>; 2675 clock-output-names = "fsgen"; 2676 #sound-dai-cells = <1>; 2677 }; 2678 2679 lpass_tlmm: pinctrl@6e80000 { 2680 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2681 reg = <0 0x06e80000 0 0x20000>, 2682 <0 0x07250000 0 0x10000>; 2683 gpio-controller; 2684 #gpio-cells = <2>; 2685 gpio-ranges = <&lpass_tlmm 0 0 23>; 2686 2687 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2688 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2689 clock-names = "core", "audio"; 2690 2691 tx_swr_active: tx-swr-active-state { 2692 clk-pins { 2693 pins = "gpio0"; 2694 function = "swr_tx_clk"; 2695 drive-strength = <2>; 2696 slew-rate = <1>; 2697 bias-disable; 2698 }; 2699 2700 data-pins { 2701 pins = "gpio1", "gpio2", "gpio14"; 2702 function = "swr_tx_data"; 2703 drive-strength = <2>; 2704 slew-rate = <1>; 2705 bias-bus-hold; 2706 }; 2707 }; 2708 2709 rx_swr_active: rx-swr-active-state { 2710 clk-pins { 2711 pins = "gpio3"; 2712 function = "swr_rx_clk"; 2713 drive-strength = <2>; 2714 slew-rate = <1>; 2715 bias-disable; 2716 }; 2717 2718 data-pins { 2719 pins = "gpio4", "gpio5"; 2720 function = "swr_rx_data"; 2721 drive-strength = <2>; 2722 slew-rate = <1>; 2723 bias-bus-hold; 2724 }; 2725 }; 2726 2727 dmic01_default: dmic01-default-state { 2728 clk-pins { 2729 pins = "gpio6"; 2730 function = "dmic1_clk"; 2731 drive-strength = <8>; 2732 output-high; 2733 }; 2734 2735 data-pins { 2736 pins = "gpio7"; 2737 function = "dmic1_data"; 2738 drive-strength = <8>; 2739 input-enable; 2740 }; 2741 }; 2742 2743 dmic23_default: dmic23-default-state { 2744 clk-pins { 2745 pins = "gpio8"; 2746 function = "dmic2_clk"; 2747 drive-strength = <8>; 2748 output-high; 2749 }; 2750 2751 data-pins { 2752 pins = "gpio9"; 2753 function = "dmic2_data"; 2754 drive-strength = <8>; 2755 input-enable; 2756 }; 2757 }; 2758 2759 wsa_swr_active: wsa-swr-active-state { 2760 clk-pins { 2761 pins = "gpio10"; 2762 function = "wsa_swr_clk"; 2763 drive-strength = <2>; 2764 slew-rate = <1>; 2765 bias-disable; 2766 }; 2767 2768 data-pins { 2769 pins = "gpio11"; 2770 function = "wsa_swr_data"; 2771 drive-strength = <2>; 2772 slew-rate = <1>; 2773 bias-bus-hold; 2774 }; 2775 }; 2776 2777 wsa2_swr_active: wsa2-swr-active-state { 2778 clk-pins { 2779 pins = "gpio15"; 2780 function = "wsa2_swr_clk"; 2781 drive-strength = <2>; 2782 slew-rate = <1>; 2783 bias-disable; 2784 }; 2785 2786 data-pins { 2787 pins = "gpio16"; 2788 function = "wsa2_swr_data"; 2789 drive-strength = <2>; 2790 slew-rate = <1>; 2791 bias-bus-hold; 2792 }; 2793 }; 2794 }; 2795 2796 lpass_lpiaon_noc: interconnect@7400000 { 2797 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2798 reg = <0 0x07400000 0 0x19080>; 2799 #interconnect-cells = <2>; 2800 qcom,bcm-voters = <&apps_bcm_voter>; 2801 }; 2802 2803 lpass_lpicx_noc: interconnect@7430000 { 2804 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2805 reg = <0 0x07430000 0 0x3a200>; 2806 #interconnect-cells = <2>; 2807 qcom,bcm-voters = <&apps_bcm_voter>; 2808 }; 2809 2810 lpass_ag_noc: interconnect@7e40000 { 2811 compatible = "qcom,sm8550-lpass-ag-noc"; 2812 reg = <0 0x07e40000 0 0xe080>; 2813 #interconnect-cells = <2>; 2814 qcom,bcm-voters = <&apps_bcm_voter>; 2815 }; 2816 2817 sdhc_2: mmc@8804000 { 2818 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2819 reg = <0 0x08804000 0 0x1000>; 2820 2821 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2823 interrupt-names = "hc_irq", "pwr_irq"; 2824 2825 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2826 <&gcc GCC_SDCC2_APPS_CLK>, 2827 <&rpmhcc RPMH_CXO_CLK>; 2828 clock-names = "iface", "core", "xo"; 2829 iommus = <&apps_smmu 0x540 0>; 2830 qcom,dll-config = <0x0007642c>; 2831 qcom,ddr-config = <0x80040868>; 2832 power-domains = <&rpmhpd RPMHPD_CX>; 2833 operating-points-v2 = <&sdhc2_opp_table>; 2834 2835 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2836 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2837 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2838 bus-width = <4>; 2839 dma-coherent; 2840 2841 /* Forbid SDR104/SDR50 - broken hw! */ 2842 sdhci-caps-mask = <0x3 0>; 2843 2844 status = "disabled"; 2845 2846 sdhc2_opp_table: opp-table { 2847 compatible = "operating-points-v2"; 2848 2849 opp-19200000 { 2850 opp-hz = /bits/ 64 <19200000>; 2851 required-opps = <&rpmhpd_opp_min_svs>; 2852 }; 2853 2854 opp-50000000 { 2855 opp-hz = /bits/ 64 <50000000>; 2856 required-opps = <&rpmhpd_opp_low_svs>; 2857 }; 2858 2859 opp-100000000 { 2860 opp-hz = /bits/ 64 <100000000>; 2861 required-opps = <&rpmhpd_opp_svs>; 2862 }; 2863 2864 opp-202000000 { 2865 opp-hz = /bits/ 64 <202000000>; 2866 required-opps = <&rpmhpd_opp_svs_l1>; 2867 }; 2868 }; 2869 }; 2870 2871 videocc: clock-controller@aaf0000 { 2872 compatible = "qcom,sm8550-videocc"; 2873 reg = <0 0x0aaf0000 0 0x10000>; 2874 clocks = <&bi_tcxo_div2>, 2875 <&gcc GCC_VIDEO_AHB_CLK>; 2876 power-domains = <&rpmhpd RPMHPD_MMCX>; 2877 required-opps = <&rpmhpd_opp_low_svs>; 2878 #clock-cells = <1>; 2879 #reset-cells = <1>; 2880 #power-domain-cells = <1>; 2881 }; 2882 2883 cci0: cci@ac15000 { 2884 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 2885 reg = <0 0x0ac15000 0 0x1000>; 2886 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 2887 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 2888 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2889 <&camcc CAM_CC_CPAS_AHB_CLK>, 2890 <&camcc CAM_CC_CCI_0_CLK>; 2891 clock-names = "camnoc_axi", 2892 "cpas_ahb", 2893 "cci"; 2894 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 2895 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 2896 pinctrl-names = "default", "sleep"; 2897 status = "disabled"; 2898 #address-cells = <1>; 2899 #size-cells = <0>; 2900 2901 cci0_i2c0: i2c-bus@0 { 2902 reg = <0>; 2903 clock-frequency = <1000000>; 2904 #address-cells = <1>; 2905 #size-cells = <0>; 2906 }; 2907 2908 cci0_i2c1: i2c-bus@1 { 2909 reg = <1>; 2910 clock-frequency = <1000000>; 2911 #address-cells = <1>; 2912 #size-cells = <0>; 2913 }; 2914 }; 2915 2916 cci1: cci@ac16000 { 2917 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 2918 reg = <0 0x0ac16000 0 0x1000>; 2919 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 2920 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 2921 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2922 <&camcc CAM_CC_CPAS_AHB_CLK>, 2923 <&camcc CAM_CC_CCI_1_CLK>; 2924 clock-names = "camnoc_axi", 2925 "cpas_ahb", 2926 "cci"; 2927 pinctrl-0 = <&cci1_0_default>; 2928 pinctrl-1 = <&cci1_0_sleep>; 2929 pinctrl-names = "default", "sleep"; 2930 status = "disabled"; 2931 #address-cells = <1>; 2932 #size-cells = <0>; 2933 2934 cci1_i2c0: i2c-bus@0 { 2935 reg = <0>; 2936 clock-frequency = <1000000>; 2937 #address-cells = <1>; 2938 #size-cells = <0>; 2939 }; 2940 }; 2941 2942 cci2: cci@ac17000 { 2943 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 2944 reg = <0 0x0ac17000 0 0x1000>; 2945 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 2946 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 2947 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2948 <&camcc CAM_CC_CPAS_AHB_CLK>, 2949 <&camcc CAM_CC_CCI_2_CLK>; 2950 clock-names = "camnoc_axi", 2951 "cpas_ahb", 2952 "cci"; 2953 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 2954 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 2955 pinctrl-names = "default", "sleep"; 2956 status = "disabled"; 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 2960 cci2_i2c0: i2c-bus@0 { 2961 reg = <0>; 2962 clock-frequency = <1000000>; 2963 #address-cells = <1>; 2964 #size-cells = <0>; 2965 }; 2966 2967 cci2_i2c1: i2c-bus@1 { 2968 reg = <1>; 2969 clock-frequency = <1000000>; 2970 #address-cells = <1>; 2971 #size-cells = <0>; 2972 }; 2973 }; 2974 2975 camcc: clock-controller@ade0000 { 2976 compatible = "qcom,sm8550-camcc"; 2977 reg = <0 0x0ade0000 0 0x20000>; 2978 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2979 <&bi_tcxo_div2>, 2980 <&bi_tcxo_ao_div2>, 2981 <&sleep_clk>; 2982 power-domains = <&rpmhpd SM8550_MMCX>; 2983 required-opps = <&rpmhpd_opp_low_svs>; 2984 #clock-cells = <1>; 2985 #reset-cells = <1>; 2986 #power-domain-cells = <1>; 2987 }; 2988 2989 mdss: display-subsystem@ae00000 { 2990 compatible = "qcom,sm8550-mdss"; 2991 reg = <0 0x0ae00000 0 0x1000>; 2992 reg-names = "mdss"; 2993 2994 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2995 interrupt-controller; 2996 #interrupt-cells = <1>; 2997 2998 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2999 <&gcc GCC_DISP_AHB_CLK>, 3000 <&gcc GCC_DISP_HF_AXI_CLK>, 3001 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3002 3003 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3004 3005 power-domains = <&dispcc MDSS_GDSC>; 3006 3007 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; 3008 interconnect-names = "mdp0-mem"; 3009 3010 iommus = <&apps_smmu 0x1c00 0x2>; 3011 3012 #address-cells = <2>; 3013 #size-cells = <2>; 3014 ranges; 3015 3016 status = "disabled"; 3017 3018 mdss_mdp: display-controller@ae01000 { 3019 compatible = "qcom,sm8550-dpu"; 3020 reg = <0 0x0ae01000 0 0x8f000>, 3021 <0 0x0aeb0000 0 0x2008>; 3022 reg-names = "mdp", "vbif"; 3023 3024 interrupt-parent = <&mdss>; 3025 interrupts = <0>; 3026 3027 clocks = <&gcc GCC_DISP_AHB_CLK>, 3028 <&gcc GCC_DISP_HF_AXI_CLK>, 3029 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3030 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3031 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3032 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3033 clock-names = "bus", 3034 "nrt_bus", 3035 "iface", 3036 "lut", 3037 "core", 3038 "vsync"; 3039 3040 power-domains = <&rpmhpd RPMHPD_MMCX>; 3041 3042 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3043 assigned-clock-rates = <19200000>; 3044 3045 operating-points-v2 = <&mdp_opp_table>; 3046 3047 ports { 3048 #address-cells = <1>; 3049 #size-cells = <0>; 3050 3051 port@0 { 3052 reg = <0>; 3053 dpu_intf1_out: endpoint { 3054 remote-endpoint = <&mdss_dsi0_in>; 3055 }; 3056 }; 3057 3058 port@1 { 3059 reg = <1>; 3060 dpu_intf2_out: endpoint { 3061 remote-endpoint = <&mdss_dsi1_in>; 3062 }; 3063 }; 3064 3065 port@2 { 3066 reg = <2>; 3067 dpu_intf0_out: endpoint { 3068 remote-endpoint = <&mdss_dp0_in>; 3069 }; 3070 }; 3071 }; 3072 3073 mdp_opp_table: opp-table { 3074 compatible = "operating-points-v2"; 3075 3076 opp-200000000 { 3077 opp-hz = /bits/ 64 <200000000>; 3078 required-opps = <&rpmhpd_opp_low_svs>; 3079 }; 3080 3081 opp-325000000 { 3082 opp-hz = /bits/ 64 <325000000>; 3083 required-opps = <&rpmhpd_opp_svs>; 3084 }; 3085 3086 opp-375000000 { 3087 opp-hz = /bits/ 64 <375000000>; 3088 required-opps = <&rpmhpd_opp_svs_l1>; 3089 }; 3090 3091 opp-514000000 { 3092 opp-hz = /bits/ 64 <514000000>; 3093 required-opps = <&rpmhpd_opp_nom>; 3094 }; 3095 }; 3096 }; 3097 3098 mdss_dp0: displayport-controller@ae90000 { 3099 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3100 reg = <0 0xae90000 0 0x200>, 3101 <0 0xae90200 0 0x200>, 3102 <0 0xae90400 0 0xc00>, 3103 <0 0xae91000 0 0x400>, 3104 <0 0xae91400 0 0x400>; 3105 interrupt-parent = <&mdss>; 3106 interrupts = <12>; 3107 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3108 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3109 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3110 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3111 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3112 clock-names = "core_iface", 3113 "core_aux", 3114 "ctrl_link", 3115 "ctrl_link_iface", 3116 "stream_pixel"; 3117 3118 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3119 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3120 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3121 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3122 3123 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3124 phy-names = "dp"; 3125 3126 #sound-dai-cells = <0>; 3127 3128 operating-points-v2 = <&dp_opp_table>; 3129 power-domains = <&rpmhpd RPMHPD_MMCX>; 3130 3131 status = "disabled"; 3132 3133 ports { 3134 #address-cells = <1>; 3135 #size-cells = <0>; 3136 3137 port@0 { 3138 reg = <0>; 3139 mdss_dp0_in: endpoint { 3140 remote-endpoint = <&dpu_intf0_out>; 3141 }; 3142 }; 3143 3144 port@1 { 3145 reg = <1>; 3146 mdss_dp0_out: endpoint { 3147 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3148 }; 3149 }; 3150 }; 3151 3152 dp_opp_table: opp-table { 3153 compatible = "operating-points-v2"; 3154 3155 opp-162000000 { 3156 opp-hz = /bits/ 64 <162000000>; 3157 required-opps = <&rpmhpd_opp_low_svs_d1>; 3158 }; 3159 3160 opp-270000000 { 3161 opp-hz = /bits/ 64 <270000000>; 3162 required-opps = <&rpmhpd_opp_low_svs>; 3163 }; 3164 3165 opp-540000000 { 3166 opp-hz = /bits/ 64 <540000000>; 3167 required-opps = <&rpmhpd_opp_svs_l1>; 3168 }; 3169 3170 opp-810000000 { 3171 opp-hz = /bits/ 64 <810000000>; 3172 required-opps = <&rpmhpd_opp_nom>; 3173 }; 3174 }; 3175 }; 3176 3177 mdss_dsi0: dsi@ae94000 { 3178 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3179 reg = <0 0x0ae94000 0 0x400>; 3180 reg-names = "dsi_ctrl"; 3181 3182 interrupt-parent = <&mdss>; 3183 interrupts = <4>; 3184 3185 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3186 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3187 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3188 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3189 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3190 <&gcc GCC_DISP_HF_AXI_CLK>; 3191 clock-names = "byte", 3192 "byte_intf", 3193 "pixel", 3194 "core", 3195 "iface", 3196 "bus"; 3197 3198 power-domains = <&rpmhpd RPMHPD_MMCX>; 3199 3200 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3201 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3202 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3203 <&mdss_dsi0_phy 1>; 3204 3205 operating-points-v2 = <&mdss_dsi_opp_table>; 3206 3207 phys = <&mdss_dsi0_phy>; 3208 phy-names = "dsi"; 3209 3210 #address-cells = <1>; 3211 #size-cells = <0>; 3212 3213 status = "disabled"; 3214 3215 ports { 3216 #address-cells = <1>; 3217 #size-cells = <0>; 3218 3219 port@0 { 3220 reg = <0>; 3221 mdss_dsi0_in: endpoint { 3222 remote-endpoint = <&dpu_intf1_out>; 3223 }; 3224 }; 3225 3226 port@1 { 3227 reg = <1>; 3228 mdss_dsi0_out: endpoint { 3229 }; 3230 }; 3231 }; 3232 3233 mdss_dsi_opp_table: opp-table { 3234 compatible = "operating-points-v2"; 3235 3236 opp-187500000 { 3237 opp-hz = /bits/ 64 <187500000>; 3238 required-opps = <&rpmhpd_opp_low_svs>; 3239 }; 3240 3241 opp-300000000 { 3242 opp-hz = /bits/ 64 <300000000>; 3243 required-opps = <&rpmhpd_opp_svs>; 3244 }; 3245 3246 opp-358000000 { 3247 opp-hz = /bits/ 64 <358000000>; 3248 required-opps = <&rpmhpd_opp_svs_l1>; 3249 }; 3250 }; 3251 }; 3252 3253 mdss_dsi0_phy: phy@ae95000 { 3254 compatible = "qcom,sm8550-dsi-phy-4nm"; 3255 reg = <0 0x0ae95000 0 0x200>, 3256 <0 0x0ae95200 0 0x280>, 3257 <0 0x0ae95500 0 0x400>; 3258 reg-names = "dsi_phy", 3259 "dsi_phy_lane", 3260 "dsi_pll"; 3261 3262 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3263 <&rpmhcc RPMH_CXO_CLK>; 3264 clock-names = "iface", "ref"; 3265 3266 #clock-cells = <1>; 3267 #phy-cells = <0>; 3268 3269 status = "disabled"; 3270 }; 3271 3272 mdss_dsi1: dsi@ae96000 { 3273 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3274 reg = <0 0x0ae96000 0 0x400>; 3275 reg-names = "dsi_ctrl"; 3276 3277 interrupt-parent = <&mdss>; 3278 interrupts = <5>; 3279 3280 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3281 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3282 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3283 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3284 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3285 <&gcc GCC_DISP_HF_AXI_CLK>; 3286 clock-names = "byte", 3287 "byte_intf", 3288 "pixel", 3289 "core", 3290 "iface", 3291 "bus"; 3292 3293 power-domains = <&rpmhpd RPMHPD_MMCX>; 3294 3295 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3296 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3297 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3298 <&mdss_dsi1_phy 1>; 3299 3300 operating-points-v2 = <&mdss_dsi_opp_table>; 3301 3302 phys = <&mdss_dsi1_phy>; 3303 phy-names = "dsi"; 3304 3305 #address-cells = <1>; 3306 #size-cells = <0>; 3307 3308 status = "disabled"; 3309 3310 ports { 3311 #address-cells = <1>; 3312 #size-cells = <0>; 3313 3314 port@0 { 3315 reg = <0>; 3316 mdss_dsi1_in: endpoint { 3317 remote-endpoint = <&dpu_intf2_out>; 3318 }; 3319 }; 3320 3321 port@1 { 3322 reg = <1>; 3323 mdss_dsi1_out: endpoint { 3324 }; 3325 }; 3326 }; 3327 }; 3328 3329 mdss_dsi1_phy: phy@ae97000 { 3330 compatible = "qcom,sm8550-dsi-phy-4nm"; 3331 reg = <0 0x0ae97000 0 0x200>, 3332 <0 0x0ae97200 0 0x280>, 3333 <0 0x0ae97500 0 0x400>; 3334 reg-names = "dsi_phy", 3335 "dsi_phy_lane", 3336 "dsi_pll"; 3337 3338 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3339 <&rpmhcc RPMH_CXO_CLK>; 3340 clock-names = "iface", "ref"; 3341 3342 #clock-cells = <1>; 3343 #phy-cells = <0>; 3344 3345 status = "disabled"; 3346 }; 3347 }; 3348 3349 dispcc: clock-controller@af00000 { 3350 compatible = "qcom,sm8550-dispcc"; 3351 reg = <0 0x0af00000 0 0x20000>; 3352 clocks = <&bi_tcxo_div2>, 3353 <&bi_tcxo_ao_div2>, 3354 <&gcc GCC_DISP_AHB_CLK>, 3355 <&sleep_clk>, 3356 <&mdss_dsi0_phy 0>, 3357 <&mdss_dsi0_phy 1>, 3358 <&mdss_dsi1_phy 0>, 3359 <&mdss_dsi1_phy 1>, 3360 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3361 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3362 <0>, /* dp1 */ 3363 <0>, 3364 <0>, /* dp2 */ 3365 <0>, 3366 <0>, /* dp3 */ 3367 <0>; 3368 power-domains = <&rpmhpd RPMHPD_MMCX>; 3369 required-opps = <&rpmhpd_opp_low_svs>; 3370 #clock-cells = <1>; 3371 #reset-cells = <1>; 3372 #power-domain-cells = <1>; 3373 }; 3374 3375 usb_1_hsphy: phy@88e3000 { 3376 compatible = "qcom,sm8550-snps-eusb2-phy"; 3377 reg = <0x0 0x088e3000 0x0 0x154>; 3378 #phy-cells = <0>; 3379 3380 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3381 clock-names = "ref"; 3382 3383 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3384 3385 status = "disabled"; 3386 }; 3387 3388 usb_dp_qmpphy: phy@88e8000 { 3389 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 3390 reg = <0x0 0x088e8000 0x0 0x3000>; 3391 3392 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3393 <&rpmhcc RPMH_CXO_CLK>, 3394 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3395 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3396 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3397 3398 power-domains = <&gcc USB3_PHY_GDSC>; 3399 3400 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3401 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3402 reset-names = "phy", "common"; 3403 3404 #clock-cells = <1>; 3405 #phy-cells = <1>; 3406 3407 orientation-switch; 3408 3409 status = "disabled"; 3410 3411 ports { 3412 #address-cells = <1>; 3413 #size-cells = <0>; 3414 3415 port@0 { 3416 reg = <0>; 3417 3418 usb_dp_qmpphy_out: endpoint { 3419 }; 3420 }; 3421 3422 port@1 { 3423 reg = <1>; 3424 3425 usb_dp_qmpphy_usb_ss_in: endpoint { 3426 remote-endpoint = <&usb_1_dwc3_ss>; 3427 }; 3428 }; 3429 3430 port@2 { 3431 reg = <2>; 3432 3433 usb_dp_qmpphy_dp_in: endpoint { 3434 remote-endpoint = <&mdss_dp0_out>; 3435 }; 3436 }; 3437 }; 3438 }; 3439 3440 usb_1: usb@a6f8800 { 3441 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3442 reg = <0x0 0x0a6f8800 0x0 0x400>; 3443 #address-cells = <2>; 3444 #size-cells = <2>; 3445 ranges; 3446 3447 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3448 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3449 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3450 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3451 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3452 <&tcsr TCSR_USB3_CLKREF_EN>; 3453 clock-names = "cfg_noc", 3454 "core", 3455 "iface", 3456 "sleep", 3457 "mock_utmi", 3458 "xo"; 3459 3460 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3461 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3462 assigned-clock-rates = <19200000>, <200000000>; 3463 3464 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3465 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3466 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3467 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3468 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3469 interrupt-names = "pwr_event", 3470 "hs_phy_irq", 3471 "dp_hs_phy_irq", 3472 "dm_hs_phy_irq", 3473 "ss_phy_irq"; 3474 3475 power-domains = <&gcc USB30_PRIM_GDSC>; 3476 required-opps = <&rpmhpd_opp_nom>; 3477 3478 resets = <&gcc GCC_USB30_PRIM_BCR>; 3479 3480 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3481 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3482 interconnect-names = "usb-ddr", "apps-usb"; 3483 3484 status = "disabled"; 3485 3486 usb_1_dwc3: usb@a600000 { 3487 compatible = "snps,dwc3"; 3488 reg = <0x0 0x0a600000 0x0 0xcd00>; 3489 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3490 iommus = <&apps_smmu 0x40 0x0>; 3491 phys = <&usb_1_hsphy>, 3492 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3493 phy-names = "usb2-phy", "usb3-phy"; 3494 snps,hird-threshold = /bits/ 8 <0x0>; 3495 snps,usb2-gadget-lpm-disable; 3496 snps,dis_u2_susphy_quirk; 3497 snps,dis_enblslpm_quirk; 3498 snps,dis-u1-entry-quirk; 3499 snps,dis-u2-entry-quirk; 3500 snps,is-utmi-l1-suspend; 3501 snps,usb3_lpm_capable; 3502 snps,usb2-lpm-disable; 3503 snps,has-lpm-erratum; 3504 tx-fifo-resize; 3505 dma-coherent; 3506 usb-role-switch; 3507 3508 ports { 3509 #address-cells = <1>; 3510 #size-cells = <0>; 3511 3512 port@0 { 3513 reg = <0>; 3514 3515 usb_1_dwc3_hs: endpoint { 3516 }; 3517 }; 3518 3519 port@1 { 3520 reg = <1>; 3521 3522 usb_1_dwc3_ss: endpoint { 3523 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 3524 }; 3525 }; 3526 }; 3527 }; 3528 }; 3529 3530 pdc: interrupt-controller@b220000 { 3531 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3532 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3533 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3534 <125 63 1>, <126 716 12>, 3535 <138 251 5>; 3536 #interrupt-cells = <2>; 3537 interrupt-parent = <&intc>; 3538 interrupt-controller; 3539 }; 3540 3541 tsens0: thermal-sensor@c271000 { 3542 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3543 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3544 <0 0x0c222000 0 0x1000>; /* SROT */ 3545 #qcom,sensors = <16>; 3546 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3548 interrupt-names = "uplow", "critical"; 3549 #thermal-sensor-cells = <1>; 3550 }; 3551 3552 tsens1: thermal-sensor@c272000 { 3553 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3554 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3555 <0 0x0c223000 0 0x1000>; /* SROT */ 3556 #qcom,sensors = <16>; 3557 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3558 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3559 interrupt-names = "uplow", "critical"; 3560 #thermal-sensor-cells = <1>; 3561 }; 3562 3563 tsens2: thermal-sensor@c273000 { 3564 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3565 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3566 <0 0x0c224000 0 0x1000>; /* SROT */ 3567 #qcom,sensors = <16>; 3568 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3570 interrupt-names = "uplow", "critical"; 3571 #thermal-sensor-cells = <1>; 3572 }; 3573 3574 aoss_qmp: power-management@c300000 { 3575 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3576 reg = <0 0x0c300000 0 0x400>; 3577 interrupt-parent = <&ipcc>; 3578 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3579 IRQ_TYPE_EDGE_RISING>; 3580 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3581 3582 #clock-cells = <0>; 3583 }; 3584 3585 sram@c3f0000 { 3586 compatible = "qcom,rpmh-stats"; 3587 reg = <0 0x0c3f0000 0 0x400>; 3588 }; 3589 3590 spmi_bus: spmi@c400000 { 3591 compatible = "qcom,spmi-pmic-arb"; 3592 reg = <0 0x0c400000 0 0x3000>, 3593 <0 0x0c500000 0 0x400000>, 3594 <0 0x0c440000 0 0x80000>, 3595 <0 0x0c4c0000 0 0x20000>, 3596 <0 0x0c42d000 0 0x4000>; 3597 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3598 interrupt-names = "periph_irq"; 3599 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3600 qcom,ee = <0>; 3601 qcom,channel = <0>; 3602 qcom,bus-id = <0>; 3603 #address-cells = <2>; 3604 #size-cells = <0>; 3605 interrupt-controller; 3606 #interrupt-cells = <4>; 3607 }; 3608 3609 tlmm: pinctrl@f100000 { 3610 compatible = "qcom,sm8550-tlmm"; 3611 reg = <0 0x0f100000 0 0x300000>; 3612 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3613 gpio-controller; 3614 #gpio-cells = <2>; 3615 interrupt-controller; 3616 #interrupt-cells = <2>; 3617 gpio-ranges = <&tlmm 0 0 211>; 3618 wakeup-parent = <&pdc>; 3619 3620 cci0_0_default: cci0-0-default-state { 3621 sda-pins { 3622 pins = "gpio110"; 3623 function = "cci_i2c_sda"; 3624 drive-strength = <2>; 3625 bias-pull-up = <2200>; 3626 }; 3627 3628 scl-pins { 3629 pins = "gpio111"; 3630 function = "cci_i2c_scl"; 3631 drive-strength = <2>; 3632 bias-pull-up = <2200>; 3633 }; 3634 }; 3635 3636 cci0_0_sleep: cci0-0-sleep-state { 3637 sda-pins { 3638 pins = "gpio110"; 3639 function = "cci_i2c_sda"; 3640 drive-strength = <2>; 3641 bias-pull-down; 3642 }; 3643 3644 scl-pins { 3645 pins = "gpio111"; 3646 function = "cci_i2c_scl"; 3647 drive-strength = <2>; 3648 bias-pull-down; 3649 }; 3650 }; 3651 3652 cci0_1_default: cci0-1-default-state { 3653 sda-pins { 3654 pins = "gpio112"; 3655 function = "cci_i2c_sda"; 3656 drive-strength = <2>; 3657 bias-pull-up = <2200>; 3658 }; 3659 3660 scl-pins { 3661 pins = "gpio113"; 3662 function = "cci_i2c_scl"; 3663 drive-strength = <2>; 3664 bias-pull-up = <2200>; 3665 }; 3666 }; 3667 3668 cci0_1_sleep: cci0-1-sleep-state { 3669 sda-pins { 3670 pins = "gpio112"; 3671 function = "cci_i2c_sda"; 3672 drive-strength = <2>; 3673 bias-pull-down; 3674 }; 3675 3676 scl-pins { 3677 pins = "gpio113"; 3678 function = "cci_i2c_scl"; 3679 drive-strength = <2>; 3680 bias-pull-down; 3681 }; 3682 }; 3683 3684 cci1_0_default: cci1-0-default-state { 3685 sda-pins { 3686 pins = "gpio114"; 3687 function = "cci_i2c_sda"; 3688 drive-strength = <2>; 3689 bias-pull-up = <2200>; 3690 }; 3691 3692 scl-pins { 3693 pins = "gpio115"; 3694 function = "cci_i2c_scl"; 3695 drive-strength = <2>; 3696 bias-pull-up = <2200>; 3697 }; 3698 }; 3699 3700 cci1_0_sleep: cci1-0-sleep-state { 3701 sda-pins { 3702 pins = "gpio114"; 3703 function = "cci_i2c_sda"; 3704 drive-strength = <2>; 3705 bias-pull-down; 3706 }; 3707 3708 scl-pins { 3709 pins = "gpio115"; 3710 function = "cci_i2c_scl"; 3711 drive-strength = <2>; 3712 bias-pull-down; 3713 }; 3714 }; 3715 3716 cci2_0_default: cci2-0-default-state { 3717 sda-pins { 3718 pins = "gpio74"; 3719 function = "cci_i2c_sda"; 3720 drive-strength = <2>; 3721 bias-pull-up = <2200>; 3722 }; 3723 3724 scl-pins { 3725 pins = "gpio75"; 3726 function = "cci_i2c_scl"; 3727 drive-strength = <2>; 3728 bias-pull-up = <2200>; 3729 }; 3730 }; 3731 3732 cci2_0_sleep: cci2-0-sleep-state { 3733 sda-pins { 3734 pins = "gpio74"; 3735 function = "cci_i2c_sda"; 3736 drive-strength = <2>; 3737 bias-pull-down; 3738 }; 3739 3740 scl-pins { 3741 pins = "gpio75"; 3742 function = "cci_i2c_scl"; 3743 drive-strength = <2>; 3744 bias-pull-down; 3745 }; 3746 }; 3747 3748 cci2_1_default: cci2-1-default-state { 3749 sda-pins { 3750 pins = "gpio0"; 3751 function = "cci_i2c_sda"; 3752 drive-strength = <2>; 3753 bias-pull-up = <2200>; 3754 }; 3755 3756 scl-pins { 3757 pins = "gpio1"; 3758 function = "cci_i2c_scl"; 3759 drive-strength = <2>; 3760 bias-pull-up = <2200>; 3761 }; 3762 }; 3763 3764 cci2_1_sleep: cci2-1-sleep-state { 3765 sda-pins { 3766 pins = "gpio0"; 3767 function = "cci_i2c_sda"; 3768 drive-strength = <2>; 3769 bias-pull-down; 3770 }; 3771 3772 scl-pins { 3773 pins = "gpio1"; 3774 function = "cci_i2c_scl"; 3775 drive-strength = <2>; 3776 bias-pull-down; 3777 }; 3778 }; 3779 3780 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3781 /* SDA, SCL */ 3782 pins = "gpio16", "gpio17"; 3783 function = "i2chub0_se0"; 3784 drive-strength = <2>; 3785 bias-pull-up; 3786 }; 3787 3788 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3789 /* SDA, SCL */ 3790 pins = "gpio18", "gpio19"; 3791 function = "i2chub0_se1"; 3792 drive-strength = <2>; 3793 bias-pull-up; 3794 }; 3795 3796 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3797 /* SDA, SCL */ 3798 pins = "gpio20", "gpio21"; 3799 function = "i2chub0_se2"; 3800 drive-strength = <2>; 3801 bias-pull-up; 3802 }; 3803 3804 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3805 /* SDA, SCL */ 3806 pins = "gpio22", "gpio23"; 3807 function = "i2chub0_se3"; 3808 drive-strength = <2>; 3809 bias-pull-up; 3810 }; 3811 3812 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3813 /* SDA, SCL */ 3814 pins = "gpio4", "gpio5"; 3815 function = "i2chub0_se4"; 3816 drive-strength = <2>; 3817 bias-pull-up; 3818 }; 3819 3820 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3821 /* SDA, SCL */ 3822 pins = "gpio6", "gpio7"; 3823 function = "i2chub0_se5"; 3824 drive-strength = <2>; 3825 bias-pull-up; 3826 }; 3827 3828 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3829 /* SDA, SCL */ 3830 pins = "gpio8", "gpio9"; 3831 function = "i2chub0_se6"; 3832 drive-strength = <2>; 3833 bias-pull-up; 3834 }; 3835 3836 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3837 /* SDA, SCL */ 3838 pins = "gpio10", "gpio11"; 3839 function = "i2chub0_se7"; 3840 drive-strength = <2>; 3841 bias-pull-up; 3842 }; 3843 3844 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3845 /* SDA, SCL */ 3846 pins = "gpio206", "gpio207"; 3847 function = "i2chub0_se8"; 3848 drive-strength = <2>; 3849 bias-pull-up; 3850 }; 3851 3852 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3853 /* SDA, SCL */ 3854 pins = "gpio84", "gpio85"; 3855 function = "i2chub0_se9"; 3856 drive-strength = <2>; 3857 bias-pull-up; 3858 }; 3859 3860 pcie0_default_state: pcie0-default-state { 3861 perst-pins { 3862 pins = "gpio94"; 3863 function = "gpio"; 3864 drive-strength = <2>; 3865 bias-pull-down; 3866 }; 3867 3868 clkreq-pins { 3869 pins = "gpio95"; 3870 function = "pcie0_clk_req_n"; 3871 drive-strength = <2>; 3872 bias-pull-up; 3873 }; 3874 3875 wake-pins { 3876 pins = "gpio96"; 3877 function = "gpio"; 3878 drive-strength = <2>; 3879 bias-pull-up; 3880 }; 3881 }; 3882 3883 pcie1_default_state: pcie1-default-state { 3884 perst-pins { 3885 pins = "gpio97"; 3886 function = "gpio"; 3887 drive-strength = <2>; 3888 bias-pull-down; 3889 }; 3890 3891 clkreq-pins { 3892 pins = "gpio98"; 3893 function = "pcie1_clk_req_n"; 3894 drive-strength = <2>; 3895 bias-pull-up; 3896 }; 3897 3898 wake-pins { 3899 pins = "gpio99"; 3900 function = "gpio"; 3901 drive-strength = <2>; 3902 bias-pull-up; 3903 }; 3904 }; 3905 3906 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3907 /* SDA, SCL */ 3908 pins = "gpio28", "gpio29"; 3909 function = "qup1_se0"; 3910 drive-strength = <2>; 3911 bias-pull-up = <2200>; 3912 }; 3913 3914 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3915 /* SDA, SCL */ 3916 pins = "gpio32", "gpio33"; 3917 function = "qup1_se1"; 3918 drive-strength = <2>; 3919 bias-pull-up = <2200>; 3920 }; 3921 3922 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3923 /* SDA, SCL */ 3924 pins = "gpio36", "gpio37"; 3925 function = "qup1_se2"; 3926 drive-strength = <2>; 3927 bias-pull-up = <2200>; 3928 }; 3929 3930 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3931 /* SDA, SCL */ 3932 pins = "gpio40", "gpio41"; 3933 function = "qup1_se3"; 3934 drive-strength = <2>; 3935 bias-pull-up = <2200>; 3936 }; 3937 3938 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3939 /* SDA, SCL */ 3940 pins = "gpio44", "gpio45"; 3941 function = "qup1_se4"; 3942 drive-strength = <2>; 3943 bias-pull-up = <2200>; 3944 }; 3945 3946 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3947 /* SDA, SCL */ 3948 pins = "gpio52", "gpio53"; 3949 function = "qup1_se5"; 3950 drive-strength = <2>; 3951 bias-pull-up = <2200>; 3952 }; 3953 3954 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3955 /* SDA, SCL */ 3956 pins = "gpio48", "gpio49"; 3957 function = "qup1_se6"; 3958 drive-strength = <2>; 3959 bias-pull-up = <2200>; 3960 }; 3961 3962 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3963 scl-pins { 3964 pins = "gpio57"; 3965 function = "qup2_se0_l1_mira"; 3966 drive-strength = <2>; 3967 bias-pull-up = <2200>; 3968 }; 3969 3970 sda-pins { 3971 pins = "gpio56"; 3972 function = "qup2_se0_l0_mira"; 3973 drive-strength = <2>; 3974 bias-pull-up = <2200>; 3975 }; 3976 }; 3977 3978 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3979 /* SDA, SCL */ 3980 pins = "gpio60", "gpio61"; 3981 function = "qup2_se1"; 3982 drive-strength = <2>; 3983 bias-pull-up = <2200>; 3984 }; 3985 3986 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3987 /* SDA, SCL */ 3988 pins = "gpio64", "gpio65"; 3989 function = "qup2_se2"; 3990 drive-strength = <2>; 3991 bias-pull-up = <2200>; 3992 }; 3993 3994 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3995 /* SDA, SCL */ 3996 pins = "gpio68", "gpio69"; 3997 function = "qup2_se3"; 3998 drive-strength = <2>; 3999 bias-pull-up = <2200>; 4000 }; 4001 4002 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4003 /* SDA, SCL */ 4004 pins = "gpio2", "gpio3"; 4005 function = "qup2_se4"; 4006 drive-strength = <2>; 4007 bias-pull-up = <2200>; 4008 }; 4009 4010 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4011 /* SDA, SCL */ 4012 pins = "gpio80", "gpio81"; 4013 function = "qup2_se5"; 4014 drive-strength = <2>; 4015 bias-pull-up = <2200>; 4016 }; 4017 4018 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4019 /* SDA, SCL */ 4020 pins = "gpio72", "gpio106"; 4021 function = "qup2_se7"; 4022 drive-strength = <2>; 4023 bias-pull-up = <2200>; 4024 }; 4025 4026 qup_spi0_cs: qup-spi0-cs-state { 4027 pins = "gpio31"; 4028 function = "qup1_se0"; 4029 drive-strength = <6>; 4030 bias-disable; 4031 }; 4032 4033 qup_spi0_data_clk: qup-spi0-data-clk-state { 4034 /* MISO, MOSI, CLK */ 4035 pins = "gpio28", "gpio29", "gpio30"; 4036 function = "qup1_se0"; 4037 drive-strength = <6>; 4038 bias-disable; 4039 }; 4040 4041 qup_spi1_cs: qup-spi1-cs-state { 4042 pins = "gpio35"; 4043 function = "qup1_se1"; 4044 drive-strength = <6>; 4045 bias-disable; 4046 }; 4047 4048 qup_spi1_data_clk: qup-spi1-data-clk-state { 4049 /* MISO, MOSI, CLK */ 4050 pins = "gpio32", "gpio33", "gpio34"; 4051 function = "qup1_se1"; 4052 drive-strength = <6>; 4053 bias-disable; 4054 }; 4055 4056 qup_spi2_cs: qup-spi2-cs-state { 4057 pins = "gpio39"; 4058 function = "qup1_se2"; 4059 drive-strength = <6>; 4060 bias-disable; 4061 }; 4062 4063 qup_spi2_data_clk: qup-spi2-data-clk-state { 4064 /* MISO, MOSI, CLK */ 4065 pins = "gpio36", "gpio37", "gpio38"; 4066 function = "qup1_se2"; 4067 drive-strength = <6>; 4068 bias-disable; 4069 }; 4070 4071 qup_spi3_cs: qup-spi3-cs-state { 4072 pins = "gpio43"; 4073 function = "qup1_se3"; 4074 drive-strength = <6>; 4075 bias-disable; 4076 }; 4077 4078 qup_spi3_data_clk: qup-spi3-data-clk-state { 4079 /* MISO, MOSI, CLK */ 4080 pins = "gpio40", "gpio41", "gpio42"; 4081 function = "qup1_se3"; 4082 drive-strength = <6>; 4083 bias-disable; 4084 }; 4085 4086 qup_spi4_cs: qup-spi4-cs-state { 4087 pins = "gpio47"; 4088 function = "qup1_se4"; 4089 drive-strength = <6>; 4090 bias-disable; 4091 }; 4092 4093 qup_spi4_data_clk: qup-spi4-data-clk-state { 4094 /* MISO, MOSI, CLK */ 4095 pins = "gpio44", "gpio45", "gpio46"; 4096 function = "qup1_se4"; 4097 drive-strength = <6>; 4098 bias-disable; 4099 }; 4100 4101 qup_spi5_cs: qup-spi5-cs-state { 4102 pins = "gpio55"; 4103 function = "qup1_se5"; 4104 drive-strength = <6>; 4105 bias-disable; 4106 }; 4107 4108 qup_spi5_data_clk: qup-spi5-data-clk-state { 4109 /* MISO, MOSI, CLK */ 4110 pins = "gpio52", "gpio53", "gpio54"; 4111 function = "qup1_se5"; 4112 drive-strength = <6>; 4113 bias-disable; 4114 }; 4115 4116 qup_spi6_cs: qup-spi6-cs-state { 4117 pins = "gpio51"; 4118 function = "qup1_se6"; 4119 drive-strength = <6>; 4120 bias-disable; 4121 }; 4122 4123 qup_spi6_data_clk: qup-spi6-data-clk-state { 4124 /* MISO, MOSI, CLK */ 4125 pins = "gpio48", "gpio49", "gpio50"; 4126 function = "qup1_se6"; 4127 drive-strength = <6>; 4128 bias-disable; 4129 }; 4130 4131 qup_spi8_cs: qup-spi8-cs-state { 4132 pins = "gpio59"; 4133 function = "qup2_se0_l3_mira"; 4134 drive-strength = <6>; 4135 bias-disable; 4136 }; 4137 4138 qup_spi8_data_clk: qup-spi8-data-clk-state { 4139 /* MISO, MOSI, CLK */ 4140 pins = "gpio56", "gpio57", "gpio58"; 4141 function = "qup2_se0_l2_mira"; 4142 drive-strength = <6>; 4143 bias-disable; 4144 }; 4145 4146 qup_spi9_cs: qup-spi9-cs-state { 4147 pins = "gpio63"; 4148 function = "qup2_se1"; 4149 drive-strength = <6>; 4150 bias-disable; 4151 }; 4152 4153 qup_spi9_data_clk: qup-spi9-data-clk-state { 4154 /* MISO, MOSI, CLK */ 4155 pins = "gpio60", "gpio61", "gpio62"; 4156 function = "qup2_se1"; 4157 drive-strength = <6>; 4158 bias-disable; 4159 }; 4160 4161 qup_spi10_cs: qup-spi10-cs-state { 4162 pins = "gpio67"; 4163 function = "qup2_se2"; 4164 drive-strength = <6>; 4165 bias-disable; 4166 }; 4167 4168 qup_spi10_data_clk: qup-spi10-data-clk-state { 4169 /* MISO, MOSI, CLK */ 4170 pins = "gpio64", "gpio65", "gpio66"; 4171 function = "qup2_se2"; 4172 drive-strength = <6>; 4173 bias-disable; 4174 }; 4175 4176 qup_spi11_cs: qup-spi11-cs-state { 4177 pins = "gpio71"; 4178 function = "qup2_se3"; 4179 drive-strength = <6>; 4180 bias-disable; 4181 }; 4182 4183 qup_spi11_data_clk: qup-spi11-data-clk-state { 4184 /* MISO, MOSI, CLK */ 4185 pins = "gpio68", "gpio69", "gpio70"; 4186 function = "qup2_se3"; 4187 drive-strength = <6>; 4188 bias-disable; 4189 }; 4190 4191 qup_spi12_cs: qup-spi12-cs-state { 4192 pins = "gpio119"; 4193 function = "qup2_se4"; 4194 drive-strength = <6>; 4195 bias-disable; 4196 }; 4197 4198 qup_spi12_data_clk: qup-spi12-data-clk-state { 4199 /* MISO, MOSI, CLK */ 4200 pins = "gpio2", "gpio3", "gpio118"; 4201 function = "qup2_se4"; 4202 drive-strength = <6>; 4203 bias-disable; 4204 }; 4205 4206 qup_spi13_cs: qup-spi13-cs-state { 4207 pins = "gpio83"; 4208 function = "qup2_se5"; 4209 drive-strength = <6>; 4210 bias-disable; 4211 }; 4212 4213 qup_spi13_data_clk: qup-spi13-data-clk-state { 4214 /* MISO, MOSI, CLK */ 4215 pins = "gpio80", "gpio81", "gpio82"; 4216 function = "qup2_se5"; 4217 drive-strength = <6>; 4218 bias-disable; 4219 }; 4220 4221 qup_spi15_cs: qup-spi15-cs-state { 4222 pins = "gpio75"; 4223 function = "qup2_se7"; 4224 drive-strength = <6>; 4225 bias-disable; 4226 }; 4227 4228 qup_spi15_data_clk: qup-spi15-data-clk-state { 4229 /* MISO, MOSI, CLK */ 4230 pins = "gpio72", "gpio106", "gpio74"; 4231 function = "qup2_se7"; 4232 drive-strength = <6>; 4233 bias-disable; 4234 }; 4235 4236 qup_uart7_default: qup-uart7-default-state { 4237 /* TX, RX */ 4238 pins = "gpio26", "gpio27"; 4239 function = "qup1_se7"; 4240 drive-strength = <2>; 4241 bias-disable; 4242 }; 4243 4244 qup_uart14_default: qup-uart14-default-state { 4245 /* TX, RX */ 4246 pins = "gpio78", "gpio79"; 4247 function = "qup2_se6"; 4248 drive-strength = <2>; 4249 bias-pull-up; 4250 }; 4251 4252 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4253 /* CTS, RTS */ 4254 pins = "gpio76", "gpio77"; 4255 function = "qup2_se6"; 4256 drive-strength = <2>; 4257 bias-pull-down; 4258 }; 4259 4260 sdc2_sleep: sdc2-sleep-state { 4261 clk-pins { 4262 pins = "sdc2_clk"; 4263 bias-disable; 4264 drive-strength = <2>; 4265 }; 4266 4267 cmd-pins { 4268 pins = "sdc2_cmd"; 4269 bias-pull-up; 4270 drive-strength = <2>; 4271 }; 4272 4273 data-pins { 4274 pins = "sdc2_data"; 4275 bias-pull-up; 4276 drive-strength = <2>; 4277 }; 4278 }; 4279 4280 sdc2_default: sdc2-default-state { 4281 clk-pins { 4282 pins = "sdc2_clk"; 4283 bias-disable; 4284 drive-strength = <16>; 4285 }; 4286 4287 cmd-pins { 4288 pins = "sdc2_cmd"; 4289 bias-pull-up; 4290 drive-strength = <10>; 4291 }; 4292 4293 data-pins { 4294 pins = "sdc2_data"; 4295 bias-pull-up; 4296 drive-strength = <10>; 4297 }; 4298 }; 4299 }; 4300 4301 apps_smmu: iommu@15000000 { 4302 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4303 reg = <0 0x15000000 0 0x100000>; 4304 #iommu-cells = <2>; 4305 #global-interrupts = <1>; 4306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4403 dma-coherent; 4404 }; 4405 4406 intc: interrupt-controller@17100000 { 4407 compatible = "arm,gic-v3"; 4408 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4409 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4410 ranges; 4411 #interrupt-cells = <3>; 4412 interrupt-controller; 4413 #redistributor-regions = <1>; 4414 redistributor-stride = <0 0x40000>; 4415 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4416 #address-cells = <2>; 4417 #size-cells = <2>; 4418 4419 gic_its: msi-controller@17140000 { 4420 compatible = "arm,gic-v3-its"; 4421 reg = <0 0x17140000 0 0x20000>; 4422 msi-controller; 4423 #msi-cells = <1>; 4424 }; 4425 }; 4426 4427 timer@17420000 { 4428 compatible = "arm,armv7-timer-mem"; 4429 reg = <0 0x17420000 0 0x1000>; 4430 ranges = <0 0 0 0x20000000>; 4431 #address-cells = <1>; 4432 #size-cells = <1>; 4433 4434 frame@17421000 { 4435 reg = <0x17421000 0x1000>, 4436 <0x17422000 0x1000>; 4437 frame-number = <0>; 4438 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4440 }; 4441 4442 frame@17423000 { 4443 reg = <0x17423000 0x1000>; 4444 frame-number = <1>; 4445 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4446 status = "disabled"; 4447 }; 4448 4449 frame@17425000 { 4450 reg = <0x17425000 0x1000>; 4451 frame-number = <2>; 4452 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4453 status = "disabled"; 4454 }; 4455 4456 frame@17427000 { 4457 reg = <0x17427000 0x1000>; 4458 frame-number = <3>; 4459 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4460 status = "disabled"; 4461 }; 4462 4463 frame@17429000 { 4464 reg = <0x17429000 0x1000>; 4465 frame-number = <4>; 4466 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4467 status = "disabled"; 4468 }; 4469 4470 frame@1742b000 { 4471 reg = <0x1742b000 0x1000>; 4472 frame-number = <5>; 4473 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4474 status = "disabled"; 4475 }; 4476 4477 frame@1742d000 { 4478 reg = <0x1742d000 0x1000>; 4479 frame-number = <6>; 4480 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4481 status = "disabled"; 4482 }; 4483 }; 4484 4485 apps_rsc: rsc@17a00000 { 4486 label = "apps_rsc"; 4487 compatible = "qcom,rpmh-rsc"; 4488 reg = <0 0x17a00000 0 0x10000>, 4489 <0 0x17a10000 0 0x10000>, 4490 <0 0x17a20000 0 0x10000>, 4491 <0 0x17a30000 0 0x10000>; 4492 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4493 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4494 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4495 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4496 qcom,tcs-offset = <0xd00>; 4497 qcom,drv-id = <2>; 4498 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4499 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4500 power-domains = <&CLUSTER_PD>; 4501 4502 apps_bcm_voter: bcm-voter { 4503 compatible = "qcom,bcm-voter"; 4504 }; 4505 4506 rpmhcc: clock-controller { 4507 compatible = "qcom,sm8550-rpmh-clk"; 4508 #clock-cells = <1>; 4509 clock-names = "xo"; 4510 clocks = <&xo_board>; 4511 }; 4512 4513 rpmhpd: power-controller { 4514 compatible = "qcom,sm8550-rpmhpd"; 4515 #power-domain-cells = <1>; 4516 operating-points-v2 = <&rpmhpd_opp_table>; 4517 4518 rpmhpd_opp_table: opp-table { 4519 compatible = "operating-points-v2"; 4520 4521 rpmhpd_opp_ret: opp-16 { 4522 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4523 }; 4524 4525 rpmhpd_opp_min_svs: opp-48 { 4526 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4527 }; 4528 4529 rpmhpd_opp_low_svs_d2: opp-52 { 4530 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4531 }; 4532 4533 rpmhpd_opp_low_svs_d1: opp-56 { 4534 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4535 }; 4536 4537 rpmhpd_opp_low_svs_d0: opp-60 { 4538 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4539 }; 4540 4541 rpmhpd_opp_low_svs: opp-64 { 4542 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4543 }; 4544 4545 rpmhpd_opp_low_svs_l1: opp-80 { 4546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4547 }; 4548 4549 rpmhpd_opp_svs: opp-128 { 4550 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4551 }; 4552 4553 rpmhpd_opp_svs_l0: opp-144 { 4554 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4555 }; 4556 4557 rpmhpd_opp_svs_l1: opp-192 { 4558 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4559 }; 4560 4561 rpmhpd_opp_nom: opp-256 { 4562 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4563 }; 4564 4565 rpmhpd_opp_nom_l1: opp-320 { 4566 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4567 }; 4568 4569 rpmhpd_opp_nom_l2: opp-336 { 4570 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4571 }; 4572 4573 rpmhpd_opp_turbo: opp-384 { 4574 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4575 }; 4576 4577 rpmhpd_opp_turbo_l1: opp-416 { 4578 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4579 }; 4580 }; 4581 }; 4582 }; 4583 4584 cpufreq_hw: cpufreq@17d91000 { 4585 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 4586 reg = <0 0x17d91000 0 0x1000>, 4587 <0 0x17d92000 0 0x1000>, 4588 <0 0x17d93000 0 0x1000>; 4589 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4590 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4591 clock-names = "xo", "alternate"; 4592 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4595 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4596 #freq-domain-cells = <1>; 4597 #clock-cells = <1>; 4598 }; 4599 4600 pmu@24091000 { 4601 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4602 reg = <0 0x24091000 0 0x1000>; 4603 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4604 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4605 4606 operating-points-v2 = <&llcc_bwmon_opp_table>; 4607 4608 llcc_bwmon_opp_table: opp-table { 4609 compatible = "operating-points-v2"; 4610 4611 opp-0 { 4612 opp-peak-kBps = <2086000>; 4613 }; 4614 4615 opp-1 { 4616 opp-peak-kBps = <2929000>; 4617 }; 4618 4619 opp-2 { 4620 opp-peak-kBps = <5931000>; 4621 }; 4622 4623 opp-3 { 4624 opp-peak-kBps = <6515000>; 4625 }; 4626 4627 opp-4 { 4628 opp-peak-kBps = <7980000>; 4629 }; 4630 4631 opp-5 { 4632 opp-peak-kBps = <10437000>; 4633 }; 4634 4635 opp-6 { 4636 opp-peak-kBps = <12157000>; 4637 }; 4638 4639 opp-7 { 4640 opp-peak-kBps = <14060000>; 4641 }; 4642 4643 opp-8 { 4644 opp-peak-kBps = <16113000>; 4645 }; 4646 }; 4647 }; 4648 4649 pmu@240b6400 { 4650 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4651 reg = <0 0x240b6400 0 0x600>; 4652 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4653 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4654 4655 operating-points-v2 = <&cpu_bwmon_opp_table>; 4656 4657 cpu_bwmon_opp_table: opp-table { 4658 compatible = "operating-points-v2"; 4659 4660 opp-0 { 4661 opp-peak-kBps = <4577000>; 4662 }; 4663 4664 opp-1 { 4665 opp-peak-kBps = <7110000>; 4666 }; 4667 4668 opp-2 { 4669 opp-peak-kBps = <9155000>; 4670 }; 4671 4672 opp-3 { 4673 opp-peak-kBps = <12298000>; 4674 }; 4675 4676 opp-4 { 4677 opp-peak-kBps = <14236000>; 4678 }; 4679 4680 opp-5 { 4681 opp-peak-kBps = <16265000>; 4682 }; 4683 }; 4684 }; 4685 4686 gem_noc: interconnect@24100000 { 4687 compatible = "qcom,sm8550-gem-noc"; 4688 reg = <0 0x24100000 0 0xbb800>; 4689 #interconnect-cells = <2>; 4690 qcom,bcm-voters = <&apps_bcm_voter>; 4691 }; 4692 4693 system-cache-controller@25000000 { 4694 compatible = "qcom,sm8550-llcc"; 4695 reg = <0 0x25000000 0 0x200000>, 4696 <0 0x25200000 0 0x200000>, 4697 <0 0x25400000 0 0x200000>, 4698 <0 0x25600000 0 0x200000>, 4699 <0 0x25800000 0 0x200000>, 4700 <0 0x25a00000 0 0x200000>; 4701 reg-names = "llcc0_base", 4702 "llcc1_base", 4703 "llcc2_base", 4704 "llcc3_base", 4705 "llcc_broadcast_base", 4706 "llcc_broadcast_and_base"; 4707 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4708 }; 4709 4710 nsp_noc: interconnect@320c0000 { 4711 compatible = "qcom,sm8550-nsp-noc"; 4712 reg = <0 0x320c0000 0 0xe080>; 4713 #interconnect-cells = <2>; 4714 qcom,bcm-voters = <&apps_bcm_voter>; 4715 }; 4716 4717 remoteproc_cdsp: remoteproc@32300000 { 4718 compatible = "qcom,sm8550-cdsp-pas"; 4719 reg = <0x0 0x32300000 0x0 0x10000>; 4720 4721 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4722 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4723 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4724 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4725 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4726 interrupt-names = "wdog", "fatal", "ready", 4727 "handover", "stop-ack"; 4728 4729 clocks = <&rpmhcc RPMH_CXO_CLK>; 4730 clock-names = "xo"; 4731 4732 power-domains = <&rpmhpd RPMHPD_CX>, 4733 <&rpmhpd RPMHPD_MXC>, 4734 <&rpmhpd RPMHPD_NSP>; 4735 power-domain-names = "cx", "mxc", "nsp"; 4736 4737 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4738 4739 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4740 4741 qcom,qmp = <&aoss_qmp>; 4742 4743 qcom,smem-states = <&smp2p_cdsp_out 0>; 4744 qcom,smem-state-names = "stop"; 4745 4746 status = "disabled"; 4747 4748 glink-edge { 4749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4750 IPCC_MPROC_SIGNAL_GLINK_QMP 4751 IRQ_TYPE_EDGE_RISING>; 4752 mboxes = <&ipcc IPCC_CLIENT_CDSP 4753 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4754 4755 label = "cdsp"; 4756 qcom,remote-pid = <5>; 4757 4758 fastrpc { 4759 compatible = "qcom,fastrpc"; 4760 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4761 label = "cdsp"; 4762 qcom,non-secure-domain; 4763 #address-cells = <1>; 4764 #size-cells = <0>; 4765 4766 compute-cb@1 { 4767 compatible = "qcom,fastrpc-compute-cb"; 4768 reg = <1>; 4769 iommus = <&apps_smmu 0x1961 0x0>, 4770 <&apps_smmu 0x0c01 0x20>, 4771 <&apps_smmu 0x19c1 0x10>; 4772 dma-coherent; 4773 }; 4774 4775 compute-cb@2 { 4776 compatible = "qcom,fastrpc-compute-cb"; 4777 reg = <2>; 4778 iommus = <&apps_smmu 0x1962 0x0>, 4779 <&apps_smmu 0x0c02 0x20>, 4780 <&apps_smmu 0x19c2 0x10>; 4781 dma-coherent; 4782 }; 4783 4784 compute-cb@3 { 4785 compatible = "qcom,fastrpc-compute-cb"; 4786 reg = <3>; 4787 iommus = <&apps_smmu 0x1963 0x0>, 4788 <&apps_smmu 0x0c03 0x20>, 4789 <&apps_smmu 0x19c3 0x10>; 4790 dma-coherent; 4791 }; 4792 4793 compute-cb@4 { 4794 compatible = "qcom,fastrpc-compute-cb"; 4795 reg = <4>; 4796 iommus = <&apps_smmu 0x1964 0x0>, 4797 <&apps_smmu 0x0c04 0x20>, 4798 <&apps_smmu 0x19c4 0x10>; 4799 dma-coherent; 4800 }; 4801 4802 compute-cb@5 { 4803 compatible = "qcom,fastrpc-compute-cb"; 4804 reg = <5>; 4805 iommus = <&apps_smmu 0x1965 0x0>, 4806 <&apps_smmu 0x0c05 0x20>, 4807 <&apps_smmu 0x19c5 0x10>; 4808 dma-coherent; 4809 }; 4810 4811 compute-cb@6 { 4812 compatible = "qcom,fastrpc-compute-cb"; 4813 reg = <6>; 4814 iommus = <&apps_smmu 0x1966 0x0>, 4815 <&apps_smmu 0x0c06 0x20>, 4816 <&apps_smmu 0x19c6 0x10>; 4817 dma-coherent; 4818 }; 4819 4820 compute-cb@7 { 4821 compatible = "qcom,fastrpc-compute-cb"; 4822 reg = <7>; 4823 iommus = <&apps_smmu 0x1967 0x0>, 4824 <&apps_smmu 0x0c07 0x20>, 4825 <&apps_smmu 0x19c7 0x10>; 4826 dma-coherent; 4827 }; 4828 4829 compute-cb@8 { 4830 compatible = "qcom,fastrpc-compute-cb"; 4831 reg = <8>; 4832 iommus = <&apps_smmu 0x1968 0x0>, 4833 <&apps_smmu 0x0c08 0x20>, 4834 <&apps_smmu 0x19c8 0x10>; 4835 dma-coherent; 4836 }; 4837 4838 /* note: secure cb9 in downstream */ 4839 }; 4840 }; 4841 }; 4842 }; 4843 4844 thermal-zones { 4845 aoss0-thermal { 4846 thermal-sensors = <&tsens0 0>; 4847 4848 trips { 4849 thermal-engine-config { 4850 temperature = <125000>; 4851 hysteresis = <1000>; 4852 type = "passive"; 4853 }; 4854 4855 reset-mon-config { 4856 temperature = <115000>; 4857 hysteresis = <5000>; 4858 type = "passive"; 4859 }; 4860 }; 4861 }; 4862 4863 cpuss0-thermal { 4864 thermal-sensors = <&tsens0 1>; 4865 4866 trips { 4867 thermal-engine-config { 4868 temperature = <125000>; 4869 hysteresis = <1000>; 4870 type = "passive"; 4871 }; 4872 4873 reset-mon-config { 4874 temperature = <115000>; 4875 hysteresis = <5000>; 4876 type = "passive"; 4877 }; 4878 }; 4879 }; 4880 4881 cpuss1-thermal { 4882 thermal-sensors = <&tsens0 2>; 4883 4884 trips { 4885 thermal-engine-config { 4886 temperature = <125000>; 4887 hysteresis = <1000>; 4888 type = "passive"; 4889 }; 4890 4891 reset-mon-config { 4892 temperature = <115000>; 4893 hysteresis = <5000>; 4894 type = "passive"; 4895 }; 4896 }; 4897 }; 4898 4899 cpuss2-thermal { 4900 thermal-sensors = <&tsens0 3>; 4901 4902 trips { 4903 thermal-engine-config { 4904 temperature = <125000>; 4905 hysteresis = <1000>; 4906 type = "passive"; 4907 }; 4908 4909 reset-mon-config { 4910 temperature = <115000>; 4911 hysteresis = <5000>; 4912 type = "passive"; 4913 }; 4914 }; 4915 }; 4916 4917 cpuss3-thermal { 4918 thermal-sensors = <&tsens0 4>; 4919 4920 trips { 4921 thermal-engine-config { 4922 temperature = <125000>; 4923 hysteresis = <1000>; 4924 type = "passive"; 4925 }; 4926 4927 reset-mon-config { 4928 temperature = <115000>; 4929 hysteresis = <5000>; 4930 type = "passive"; 4931 }; 4932 }; 4933 }; 4934 4935 cpu3-top-thermal { 4936 thermal-sensors = <&tsens0 5>; 4937 4938 trips { 4939 cpu3_top_alert0: trip-point0 { 4940 temperature = <90000>; 4941 hysteresis = <2000>; 4942 type = "passive"; 4943 }; 4944 4945 cpu3_top_alert1: trip-point1 { 4946 temperature = <95000>; 4947 hysteresis = <2000>; 4948 type = "passive"; 4949 }; 4950 4951 cpu3_top_crit: cpu-critical { 4952 temperature = <110000>; 4953 hysteresis = <1000>; 4954 type = "critical"; 4955 }; 4956 }; 4957 }; 4958 4959 cpu3-bottom-thermal { 4960 thermal-sensors = <&tsens0 6>; 4961 4962 trips { 4963 cpu3_bottom_alert0: trip-point0 { 4964 temperature = <90000>; 4965 hysteresis = <2000>; 4966 type = "passive"; 4967 }; 4968 4969 cpu3_bottom_alert1: trip-point1 { 4970 temperature = <95000>; 4971 hysteresis = <2000>; 4972 type = "passive"; 4973 }; 4974 4975 cpu3_bottom_crit: cpu-critical { 4976 temperature = <110000>; 4977 hysteresis = <1000>; 4978 type = "critical"; 4979 }; 4980 }; 4981 }; 4982 4983 cpu4-top-thermal { 4984 thermal-sensors = <&tsens0 7>; 4985 4986 trips { 4987 cpu4_top_alert0: trip-point0 { 4988 temperature = <90000>; 4989 hysteresis = <2000>; 4990 type = "passive"; 4991 }; 4992 4993 cpu4_top_alert1: trip-point1 { 4994 temperature = <95000>; 4995 hysteresis = <2000>; 4996 type = "passive"; 4997 }; 4998 4999 cpu4_top_crit: cpu-critical { 5000 temperature = <110000>; 5001 hysteresis = <1000>; 5002 type = "critical"; 5003 }; 5004 }; 5005 }; 5006 5007 cpu4-bottom-thermal { 5008 thermal-sensors = <&tsens0 8>; 5009 5010 trips { 5011 cpu4_bottom_alert0: trip-point0 { 5012 temperature = <90000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu4_bottom_alert1: trip-point1 { 5018 temperature = <95000>; 5019 hysteresis = <2000>; 5020 type = "passive"; 5021 }; 5022 5023 cpu4_bottom_crit: cpu-critical { 5024 temperature = <110000>; 5025 hysteresis = <1000>; 5026 type = "critical"; 5027 }; 5028 }; 5029 }; 5030 5031 cpu5-top-thermal { 5032 thermal-sensors = <&tsens0 9>; 5033 5034 trips { 5035 cpu5_top_alert0: trip-point0 { 5036 temperature = <90000>; 5037 hysteresis = <2000>; 5038 type = "passive"; 5039 }; 5040 5041 cpu5_top_alert1: trip-point1 { 5042 temperature = <95000>; 5043 hysteresis = <2000>; 5044 type = "passive"; 5045 }; 5046 5047 cpu5_top_crit: cpu-critical { 5048 temperature = <110000>; 5049 hysteresis = <1000>; 5050 type = "critical"; 5051 }; 5052 }; 5053 }; 5054 5055 cpu5-bottom-thermal { 5056 thermal-sensors = <&tsens0 10>; 5057 5058 trips { 5059 cpu5_bottom_alert0: trip-point0 { 5060 temperature = <90000>; 5061 hysteresis = <2000>; 5062 type = "passive"; 5063 }; 5064 5065 cpu5_bottom_alert1: trip-point1 { 5066 temperature = <95000>; 5067 hysteresis = <2000>; 5068 type = "passive"; 5069 }; 5070 5071 cpu5_bottom_crit: cpu-critical { 5072 temperature = <110000>; 5073 hysteresis = <1000>; 5074 type = "critical"; 5075 }; 5076 }; 5077 }; 5078 5079 cpu6-top-thermal { 5080 thermal-sensors = <&tsens0 11>; 5081 5082 trips { 5083 cpu6_top_alert0: trip-point0 { 5084 temperature = <90000>; 5085 hysteresis = <2000>; 5086 type = "passive"; 5087 }; 5088 5089 cpu6_top_alert1: trip-point1 { 5090 temperature = <95000>; 5091 hysteresis = <2000>; 5092 type = "passive"; 5093 }; 5094 5095 cpu6_top_crit: cpu-critical { 5096 temperature = <110000>; 5097 hysteresis = <1000>; 5098 type = "critical"; 5099 }; 5100 }; 5101 }; 5102 5103 cpu6-bottom-thermal { 5104 thermal-sensors = <&tsens0 12>; 5105 5106 trips { 5107 cpu6_bottom_alert0: trip-point0 { 5108 temperature = <90000>; 5109 hysteresis = <2000>; 5110 type = "passive"; 5111 }; 5112 5113 cpu6_bottom_alert1: trip-point1 { 5114 temperature = <95000>; 5115 hysteresis = <2000>; 5116 type = "passive"; 5117 }; 5118 5119 cpu6_bottom_crit: cpu-critical { 5120 temperature = <110000>; 5121 hysteresis = <1000>; 5122 type = "critical"; 5123 }; 5124 }; 5125 }; 5126 5127 cpu7-top-thermal { 5128 thermal-sensors = <&tsens0 13>; 5129 5130 trips { 5131 cpu7_top_alert0: trip-point0 { 5132 temperature = <90000>; 5133 hysteresis = <2000>; 5134 type = "passive"; 5135 }; 5136 5137 cpu7_top_alert1: trip-point1 { 5138 temperature = <95000>; 5139 hysteresis = <2000>; 5140 type = "passive"; 5141 }; 5142 5143 cpu7_top_crit: cpu-critical { 5144 temperature = <110000>; 5145 hysteresis = <1000>; 5146 type = "critical"; 5147 }; 5148 }; 5149 }; 5150 5151 cpu7-middle-thermal { 5152 thermal-sensors = <&tsens0 14>; 5153 5154 trips { 5155 cpu7_middle_alert0: trip-point0 { 5156 temperature = <90000>; 5157 hysteresis = <2000>; 5158 type = "passive"; 5159 }; 5160 5161 cpu7_middle_alert1: trip-point1 { 5162 temperature = <95000>; 5163 hysteresis = <2000>; 5164 type = "passive"; 5165 }; 5166 5167 cpu7_middle_crit: cpu-critical { 5168 temperature = <110000>; 5169 hysteresis = <1000>; 5170 type = "critical"; 5171 }; 5172 }; 5173 }; 5174 5175 cpu7-bottom-thermal { 5176 thermal-sensors = <&tsens0 15>; 5177 5178 trips { 5179 cpu7_bottom_alert0: trip-point0 { 5180 temperature = <90000>; 5181 hysteresis = <2000>; 5182 type = "passive"; 5183 }; 5184 5185 cpu7_bottom_alert1: trip-point1 { 5186 temperature = <95000>; 5187 hysteresis = <2000>; 5188 type = "passive"; 5189 }; 5190 5191 cpu7_bottom_crit: cpu-critical { 5192 temperature = <110000>; 5193 hysteresis = <1000>; 5194 type = "critical"; 5195 }; 5196 }; 5197 }; 5198 5199 aoss1-thermal { 5200 thermal-sensors = <&tsens1 0>; 5201 5202 trips { 5203 thermal-engine-config { 5204 temperature = <125000>; 5205 hysteresis = <1000>; 5206 type = "passive"; 5207 }; 5208 5209 reset-mon-config { 5210 temperature = <115000>; 5211 hysteresis = <5000>; 5212 type = "passive"; 5213 }; 5214 }; 5215 }; 5216 5217 cpu0-thermal { 5218 thermal-sensors = <&tsens1 1>; 5219 5220 trips { 5221 cpu0_alert0: trip-point0 { 5222 temperature = <90000>; 5223 hysteresis = <2000>; 5224 type = "passive"; 5225 }; 5226 5227 cpu0_alert1: trip-point1 { 5228 temperature = <95000>; 5229 hysteresis = <2000>; 5230 type = "passive"; 5231 }; 5232 5233 cpu0_crit: cpu-critical { 5234 temperature = <110000>; 5235 hysteresis = <1000>; 5236 type = "critical"; 5237 }; 5238 }; 5239 }; 5240 5241 cpu1-thermal { 5242 thermal-sensors = <&tsens1 2>; 5243 5244 trips { 5245 cpu1_alert0: trip-point0 { 5246 temperature = <90000>; 5247 hysteresis = <2000>; 5248 type = "passive"; 5249 }; 5250 5251 cpu1_alert1: trip-point1 { 5252 temperature = <95000>; 5253 hysteresis = <2000>; 5254 type = "passive"; 5255 }; 5256 5257 cpu1_crit: cpu-critical { 5258 temperature = <110000>; 5259 hysteresis = <1000>; 5260 type = "critical"; 5261 }; 5262 }; 5263 }; 5264 5265 cpu2-thermal { 5266 thermal-sensors = <&tsens1 3>; 5267 5268 trips { 5269 cpu2_alert0: trip-point0 { 5270 temperature = <90000>; 5271 hysteresis = <2000>; 5272 type = "passive"; 5273 }; 5274 5275 cpu2_alert1: trip-point1 { 5276 temperature = <95000>; 5277 hysteresis = <2000>; 5278 type = "passive"; 5279 }; 5280 5281 cpu2_crit: cpu-critical { 5282 temperature = <110000>; 5283 hysteresis = <1000>; 5284 type = "critical"; 5285 }; 5286 }; 5287 }; 5288 5289 cdsp0-thermal { 5290 polling-delay-passive = <10>; 5291 5292 thermal-sensors = <&tsens2 4>; 5293 5294 trips { 5295 thermal-engine-config { 5296 temperature = <125000>; 5297 hysteresis = <1000>; 5298 type = "passive"; 5299 }; 5300 5301 thermal-hal-config { 5302 temperature = <125000>; 5303 hysteresis = <1000>; 5304 type = "passive"; 5305 }; 5306 5307 reset-mon-config { 5308 temperature = <115000>; 5309 hysteresis = <5000>; 5310 type = "passive"; 5311 }; 5312 5313 cdsp0_junction_config: junction-config { 5314 temperature = <95000>; 5315 hysteresis = <5000>; 5316 type = "passive"; 5317 }; 5318 }; 5319 }; 5320 5321 cdsp1-thermal { 5322 polling-delay-passive = <10>; 5323 5324 thermal-sensors = <&tsens2 5>; 5325 5326 trips { 5327 thermal-engine-config { 5328 temperature = <125000>; 5329 hysteresis = <1000>; 5330 type = "passive"; 5331 }; 5332 5333 thermal-hal-config { 5334 temperature = <125000>; 5335 hysteresis = <1000>; 5336 type = "passive"; 5337 }; 5338 5339 reset-mon-config { 5340 temperature = <115000>; 5341 hysteresis = <5000>; 5342 type = "passive"; 5343 }; 5344 5345 cdsp1_junction_config: junction-config { 5346 temperature = <95000>; 5347 hysteresis = <5000>; 5348 type = "passive"; 5349 }; 5350 }; 5351 }; 5352 5353 cdsp2-thermal { 5354 polling-delay-passive = <10>; 5355 5356 thermal-sensors = <&tsens2 6>; 5357 5358 trips { 5359 thermal-engine-config { 5360 temperature = <125000>; 5361 hysteresis = <1000>; 5362 type = "passive"; 5363 }; 5364 5365 thermal-hal-config { 5366 temperature = <125000>; 5367 hysteresis = <1000>; 5368 type = "passive"; 5369 }; 5370 5371 reset-mon-config { 5372 temperature = <115000>; 5373 hysteresis = <5000>; 5374 type = "passive"; 5375 }; 5376 5377 cdsp2_junction_config: junction-config { 5378 temperature = <95000>; 5379 hysteresis = <5000>; 5380 type = "passive"; 5381 }; 5382 }; 5383 }; 5384 5385 cdsp3-thermal { 5386 polling-delay-passive = <10>; 5387 5388 thermal-sensors = <&tsens2 7>; 5389 5390 trips { 5391 thermal-engine-config { 5392 temperature = <125000>; 5393 hysteresis = <1000>; 5394 type = "passive"; 5395 }; 5396 5397 thermal-hal-config { 5398 temperature = <125000>; 5399 hysteresis = <1000>; 5400 type = "passive"; 5401 }; 5402 5403 reset-mon-config { 5404 temperature = <115000>; 5405 hysteresis = <5000>; 5406 type = "passive"; 5407 }; 5408 5409 cdsp3_junction_config: junction-config { 5410 temperature = <95000>; 5411 hysteresis = <5000>; 5412 type = "passive"; 5413 }; 5414 }; 5415 }; 5416 5417 video-thermal { 5418 thermal-sensors = <&tsens1 8>; 5419 5420 trips { 5421 thermal-engine-config { 5422 temperature = <125000>; 5423 hysteresis = <1000>; 5424 type = "passive"; 5425 }; 5426 5427 reset-mon-config { 5428 temperature = <115000>; 5429 hysteresis = <5000>; 5430 type = "passive"; 5431 }; 5432 }; 5433 }; 5434 5435 mem-thermal { 5436 polling-delay-passive = <10>; 5437 5438 thermal-sensors = <&tsens1 9>; 5439 5440 trips { 5441 thermal-engine-config { 5442 temperature = <125000>; 5443 hysteresis = <1000>; 5444 type = "passive"; 5445 }; 5446 5447 ddr_config0: ddr0-config { 5448 temperature = <90000>; 5449 hysteresis = <5000>; 5450 type = "passive"; 5451 }; 5452 5453 reset-mon-config { 5454 temperature = <115000>; 5455 hysteresis = <5000>; 5456 type = "passive"; 5457 }; 5458 }; 5459 }; 5460 5461 modem0-thermal { 5462 thermal-sensors = <&tsens1 10>; 5463 5464 trips { 5465 thermal-engine-config { 5466 temperature = <125000>; 5467 hysteresis = <1000>; 5468 type = "passive"; 5469 }; 5470 5471 mdmss0_config0: mdmss0-config0 { 5472 temperature = <102000>; 5473 hysteresis = <3000>; 5474 type = "passive"; 5475 }; 5476 5477 mdmss0_config1: mdmss0-config1 { 5478 temperature = <105000>; 5479 hysteresis = <3000>; 5480 type = "passive"; 5481 }; 5482 5483 reset-mon-config { 5484 temperature = <115000>; 5485 hysteresis = <5000>; 5486 type = "passive"; 5487 }; 5488 }; 5489 }; 5490 5491 modem1-thermal { 5492 thermal-sensors = <&tsens1 11>; 5493 5494 trips { 5495 thermal-engine-config { 5496 temperature = <125000>; 5497 hysteresis = <1000>; 5498 type = "passive"; 5499 }; 5500 5501 mdmss1_config0: mdmss1-config0 { 5502 temperature = <102000>; 5503 hysteresis = <3000>; 5504 type = "passive"; 5505 }; 5506 5507 mdmss1_config1: mdmss1-config1 { 5508 temperature = <105000>; 5509 hysteresis = <3000>; 5510 type = "passive"; 5511 }; 5512 5513 reset-mon-config { 5514 temperature = <115000>; 5515 hysteresis = <5000>; 5516 type = "passive"; 5517 }; 5518 }; 5519 }; 5520 5521 modem2-thermal { 5522 thermal-sensors = <&tsens1 12>; 5523 5524 trips { 5525 thermal-engine-config { 5526 temperature = <125000>; 5527 hysteresis = <1000>; 5528 type = "passive"; 5529 }; 5530 5531 mdmss2_config0: mdmss2-config0 { 5532 temperature = <102000>; 5533 hysteresis = <3000>; 5534 type = "passive"; 5535 }; 5536 5537 mdmss2_config1: mdmss2-config1 { 5538 temperature = <105000>; 5539 hysteresis = <3000>; 5540 type = "passive"; 5541 }; 5542 5543 reset-mon-config { 5544 temperature = <115000>; 5545 hysteresis = <5000>; 5546 type = "passive"; 5547 }; 5548 }; 5549 }; 5550 5551 modem3-thermal { 5552 thermal-sensors = <&tsens1 13>; 5553 5554 trips { 5555 thermal-engine-config { 5556 temperature = <125000>; 5557 hysteresis = <1000>; 5558 type = "passive"; 5559 }; 5560 5561 mdmss3_config0: mdmss3-config0 { 5562 temperature = <102000>; 5563 hysteresis = <3000>; 5564 type = "passive"; 5565 }; 5566 5567 mdmss3_config1: mdmss3-config1 { 5568 temperature = <105000>; 5569 hysteresis = <3000>; 5570 type = "passive"; 5571 }; 5572 5573 reset-mon-config { 5574 temperature = <115000>; 5575 hysteresis = <5000>; 5576 type = "passive"; 5577 }; 5578 }; 5579 }; 5580 5581 camera0-thermal { 5582 thermal-sensors = <&tsens1 14>; 5583 5584 trips { 5585 thermal-engine-config { 5586 temperature = <125000>; 5587 hysteresis = <1000>; 5588 type = "passive"; 5589 }; 5590 5591 reset-mon-config { 5592 temperature = <115000>; 5593 hysteresis = <5000>; 5594 type = "passive"; 5595 }; 5596 }; 5597 }; 5598 5599 camera1-thermal { 5600 thermal-sensors = <&tsens1 15>; 5601 5602 trips { 5603 thermal-engine-config { 5604 temperature = <125000>; 5605 hysteresis = <1000>; 5606 type = "passive"; 5607 }; 5608 5609 reset-mon-config { 5610 temperature = <115000>; 5611 hysteresis = <5000>; 5612 type = "passive"; 5613 }; 5614 }; 5615 }; 5616 5617 aoss2-thermal { 5618 thermal-sensors = <&tsens2 0>; 5619 5620 trips { 5621 thermal-engine-config { 5622 temperature = <125000>; 5623 hysteresis = <1000>; 5624 type = "passive"; 5625 }; 5626 5627 reset-mon-config { 5628 temperature = <115000>; 5629 hysteresis = <5000>; 5630 type = "passive"; 5631 }; 5632 }; 5633 }; 5634 5635 gpuss-0-thermal { 5636 polling-delay-passive = <10>; 5637 5638 thermal-sensors = <&tsens2 1>; 5639 5640 cooling-maps { 5641 map0 { 5642 trip = <&gpu0_alert0>; 5643 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5644 }; 5645 }; 5646 5647 trips { 5648 gpu0_alert0: trip-point0 { 5649 temperature = <85000>; 5650 hysteresis = <1000>; 5651 type = "passive"; 5652 }; 5653 5654 trip-point1 { 5655 temperature = <90000>; 5656 hysteresis = <1000>; 5657 type = "hot"; 5658 }; 5659 5660 trip-point2 { 5661 temperature = <110000>; 5662 hysteresis = <1000>; 5663 type = "critical"; 5664 }; 5665 }; 5666 }; 5667 5668 gpuss-1-thermal { 5669 polling-delay-passive = <10>; 5670 5671 thermal-sensors = <&tsens2 2>; 5672 5673 cooling-maps { 5674 map0 { 5675 trip = <&gpu1_alert0>; 5676 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5677 }; 5678 }; 5679 5680 trips { 5681 gpu1_alert0: trip-point0 { 5682 temperature = <85000>; 5683 hysteresis = <1000>; 5684 type = "passive"; 5685 }; 5686 5687 trip-point1 { 5688 temperature = <90000>; 5689 hysteresis = <1000>; 5690 type = "hot"; 5691 }; 5692 5693 trip-point2 { 5694 temperature = <110000>; 5695 hysteresis = <1000>; 5696 type = "critical"; 5697 }; 5698 }; 5699 }; 5700 5701 gpuss-2-thermal { 5702 polling-delay-passive = <10>; 5703 5704 thermal-sensors = <&tsens2 3>; 5705 5706 cooling-maps { 5707 map0 { 5708 trip = <&gpu2_alert0>; 5709 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5710 }; 5711 }; 5712 5713 trips { 5714 gpu2_alert0: trip-point0 { 5715 temperature = <85000>; 5716 hysteresis = <1000>; 5717 type = "passive"; 5718 }; 5719 5720 trip-point1 { 5721 temperature = <90000>; 5722 hysteresis = <1000>; 5723 type = "hot"; 5724 }; 5725 5726 trip-point2 { 5727 temperature = <110000>; 5728 hysteresis = <1000>; 5729 type = "critical"; 5730 }; 5731 }; 5732 }; 5733 5734 gpuss-3-thermal { 5735 polling-delay-passive = <10>; 5736 5737 thermal-sensors = <&tsens2 4>; 5738 5739 cooling-maps { 5740 map0 { 5741 trip = <&gpu3_alert0>; 5742 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5743 }; 5744 }; 5745 5746 trips { 5747 gpu3_alert0: trip-point0 { 5748 temperature = <85000>; 5749 hysteresis = <1000>; 5750 type = "passive"; 5751 }; 5752 5753 trip-point1 { 5754 temperature = <90000>; 5755 hysteresis = <1000>; 5756 type = "hot"; 5757 }; 5758 5759 trip-point2 { 5760 temperature = <110000>; 5761 hysteresis = <1000>; 5762 type = "critical"; 5763 }; 5764 }; 5765 }; 5766 5767 gpuss-4-thermal { 5768 polling-delay-passive = <10>; 5769 5770 thermal-sensors = <&tsens2 5>; 5771 5772 cooling-maps { 5773 map0 { 5774 trip = <&gpu4_alert0>; 5775 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5776 }; 5777 }; 5778 5779 trips { 5780 gpu4_alert0: trip-point0 { 5781 temperature = <85000>; 5782 hysteresis = <1000>; 5783 type = "passive"; 5784 }; 5785 5786 trip-point1 { 5787 temperature = <90000>; 5788 hysteresis = <1000>; 5789 type = "hot"; 5790 }; 5791 5792 trip-point2 { 5793 temperature = <110000>; 5794 hysteresis = <1000>; 5795 type = "critical"; 5796 }; 5797 }; 5798 }; 5799 5800 gpuss-5-thermal { 5801 polling-delay-passive = <10>; 5802 5803 thermal-sensors = <&tsens2 6>; 5804 5805 cooling-maps { 5806 map0 { 5807 trip = <&gpu5_alert0>; 5808 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5809 }; 5810 }; 5811 5812 trips { 5813 gpu5_alert0: trip-point0 { 5814 temperature = <85000>; 5815 hysteresis = <1000>; 5816 type = "passive"; 5817 }; 5818 5819 trip-point1 { 5820 temperature = <90000>; 5821 hysteresis = <1000>; 5822 type = "hot"; 5823 }; 5824 5825 trip-point2 { 5826 temperature = <110000>; 5827 hysteresis = <1000>; 5828 type = "critical"; 5829 }; 5830 }; 5831 }; 5832 5833 gpuss-6-thermal { 5834 polling-delay-passive = <10>; 5835 5836 thermal-sensors = <&tsens2 7>; 5837 5838 cooling-maps { 5839 map0 { 5840 trip = <&gpu6_alert0>; 5841 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5842 }; 5843 }; 5844 5845 trips { 5846 gpu6_alert0: trip-point0 { 5847 temperature = <85000>; 5848 hysteresis = <1000>; 5849 type = "passive"; 5850 }; 5851 5852 trip-point1 { 5853 temperature = <90000>; 5854 hysteresis = <1000>; 5855 type = "hot"; 5856 }; 5857 5858 trip-point2 { 5859 temperature = <110000>; 5860 hysteresis = <1000>; 5861 type = "critical"; 5862 }; 5863 }; 5864 }; 5865 5866 gpuss-7-thermal { 5867 polling-delay-passive = <10>; 5868 5869 thermal-sensors = <&tsens2 8>; 5870 5871 cooling-maps { 5872 map0 { 5873 trip = <&gpu7_alert0>; 5874 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5875 }; 5876 }; 5877 5878 trips { 5879 gpu7_alert0: trip-point0 { 5880 temperature = <85000>; 5881 hysteresis = <1000>; 5882 type = "passive"; 5883 }; 5884 5885 trip-point1 { 5886 temperature = <90000>; 5887 hysteresis = <1000>; 5888 type = "hot"; 5889 }; 5890 5891 trip-point2 { 5892 temperature = <110000>; 5893 hysteresis = <1000>; 5894 type = "critical"; 5895 }; 5896 }; 5897 }; 5898 }; 5899 5900 timer { 5901 compatible = "arm,armv8-timer"; 5902 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5903 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5904 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5905 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5906 }; 5907}; 5908