1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8650-camcc.h> 8#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 9#include <dt-bindings/clock/qcom,sm8650-gcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8650-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 compatible = "fixed-factor-clock"; 50 #clock-cells = <0>; 51 52 clocks = <&rpmhcc RPMH_CXO_CLK>; 53 clock-mult = <1>; 54 clock-div = <2>; 55 }; 56 57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 58 compatible = "fixed-factor-clock"; 59 #clock-cells = <0>; 60 61 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 62 clock-mult = <1>; 63 clock-div = <2>; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <2>; 69 #size-cells = <0>; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a520"; 74 reg = <0 0>; 75 76 clocks = <&cpufreq_hw 0>; 77 78 power-domains = <&cpu_pd0>; 79 power-domain-names = "psci"; 80 81 enable-method = "psci"; 82 next-level-cache = <&l2_0>; 83 capacity-dmips-mhz = <1024>; 84 dynamic-power-coefficient = <100>; 85 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 88 #cooling-cells = <2>; 89 90 l2_0: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 96 l3_0: l3-cache { 97 compatible = "cache"; 98 cache-level = <3>; 99 cache-unified; 100 }; 101 }; 102 }; 103 104 cpu1: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a520"; 107 reg = <0 0x100>; 108 109 clocks = <&cpufreq_hw 0>; 110 111 power-domains = <&cpu_pd1>; 112 power-domain-names = "psci"; 113 114 enable-method = "psci"; 115 next-level-cache = <&l2_0>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 121 #cooling-cells = <2>; 122 }; 123 124 cpu2: cpu@200 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a720"; 127 reg = <0 0x200>; 128 129 clocks = <&cpufreq_hw 3>; 130 131 power-domains = <&cpu_pd2>; 132 power-domain-names = "psci"; 133 134 enable-method = "psci"; 135 next-level-cache = <&l2_200>; 136 capacity-dmips-mhz = <1792>; 137 dynamic-power-coefficient = <238>; 138 139 qcom,freq-domain = <&cpufreq_hw 3>; 140 141 #cooling-cells = <2>; 142 143 l2_200: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&l3_0>; 148 }; 149 }; 150 151 cpu3: cpu@300 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a720"; 154 reg = <0 0x300>; 155 156 clocks = <&cpufreq_hw 3>; 157 158 power-domains = <&cpu_pd3>; 159 power-domain-names = "psci"; 160 161 enable-method = "psci"; 162 next-level-cache = <&l2_300>; 163 capacity-dmips-mhz = <1792>; 164 dynamic-power-coefficient = <238>; 165 166 qcom,freq-domain = <&cpufreq_hw 3>; 167 168 #cooling-cells = <2>; 169 170 l2_300: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu4: cpu@400 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a720"; 181 reg = <0 0x400>; 182 183 clocks = <&cpufreq_hw 3>; 184 185 power-domains = <&cpu_pd4>; 186 power-domain-names = "psci"; 187 188 enable-method = "psci"; 189 next-level-cache = <&l2_400>; 190 capacity-dmips-mhz = <1792>; 191 dynamic-power-coefficient = <238>; 192 193 qcom,freq-domain = <&cpufreq_hw 3>; 194 195 #cooling-cells = <2>; 196 197 l2_400: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&l3_0>; 202 }; 203 }; 204 205 cpu5: cpu@500 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-a720"; 208 reg = <0 0x500>; 209 210 clocks = <&cpufreq_hw 1>; 211 212 power-domains = <&cpu_pd5>; 213 power-domain-names = "psci"; 214 215 enable-method = "psci"; 216 next-level-cache = <&l2_500>; 217 capacity-dmips-mhz = <1792>; 218 dynamic-power-coefficient = <238>; 219 220 qcom,freq-domain = <&cpufreq_hw 1>; 221 222 #cooling-cells = <2>; 223 224 l2_500: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 next-level-cache = <&l3_0>; 229 }; 230 }; 231 232 cpu6: cpu@600 { 233 device_type = "cpu"; 234 compatible = "arm,cortex-a720"; 235 reg = <0 0x600>; 236 237 clocks = <&cpufreq_hw 1>; 238 239 power-domains = <&cpu_pd6>; 240 power-domain-names = "psci"; 241 242 enable-method = "psci"; 243 next-level-cache = <&l2_600>; 244 capacity-dmips-mhz = <1792>; 245 dynamic-power-coefficient = <238>; 246 247 qcom,freq-domain = <&cpufreq_hw 1>; 248 249 #cooling-cells = <2>; 250 251 l2_600: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_0>; 256 }; 257 }; 258 259 cpu7: cpu@700 { 260 device_type = "cpu"; 261 compatible = "arm,cortex-x4"; 262 reg = <0 0x700>; 263 264 clocks = <&cpufreq_hw 2>; 265 266 power-domains = <&cpu_pd7>; 267 power-domain-names = "psci"; 268 269 enable-method = "psci"; 270 next-level-cache = <&l2_700>; 271 capacity-dmips-mhz = <1894>; 272 dynamic-power-coefficient = <588>; 273 274 qcom,freq-domain = <&cpufreq_hw 2>; 275 276 #cooling-cells = <2>; 277 278 l2_700: l2-cache { 279 compatible = "cache"; 280 cache-level = <2>; 281 cache-unified; 282 next-level-cache = <&l3_0>; 283 }; 284 }; 285 286 cpu-map { 287 cluster0 { 288 core0 { 289 cpu = <&cpu0>; 290 }; 291 292 core1 { 293 cpu = <&cpu1>; 294 }; 295 296 core2 { 297 cpu = <&cpu2>; 298 }; 299 300 core3 { 301 cpu = <&cpu3>; 302 }; 303 304 core4 { 305 cpu = <&cpu4>; 306 }; 307 308 core5 { 309 cpu = <&cpu5>; 310 }; 311 312 core6 { 313 cpu = <&cpu6>; 314 }; 315 316 core7 { 317 cpu = <&cpu7>; 318 }; 319 }; 320 }; 321 322 idle-states { 323 entry-method = "psci"; 324 325 silver_cpu_sleep_0: cpu-sleep-0-0 { 326 compatible = "arm,idle-state"; 327 idle-state-name = "silver-rail-power-collapse"; 328 arm,psci-suspend-param = <0x40000004>; 329 entry-latency-us = <550>; 330 exit-latency-us = <750>; 331 min-residency-us = <6700>; 332 local-timer-stop; 333 }; 334 335 gold_cpu_sleep_0: cpu-sleep-1-0 { 336 compatible = "arm,idle-state"; 337 idle-state-name = "gold-rail-power-collapse"; 338 arm,psci-suspend-param = <0x40000004>; 339 entry-latency-us = <600>; 340 exit-latency-us = <1300>; 341 min-residency-us = <8136>; 342 local-timer-stop; 343 }; 344 345 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "gold-plus-rail-power-collapse"; 348 arm,psci-suspend-param = <0x40000004>; 349 entry-latency-us = <500>; 350 exit-latency-us = <1350>; 351 min-residency-us = <7480>; 352 local-timer-stop; 353 }; 354 }; 355 356 domain-idle-states { 357 cluster_sleep_0: cluster-sleep-0 { 358 compatible = "domain-idle-state"; 359 arm,psci-suspend-param = <0x41000044>; 360 entry-latency-us = <750>; 361 exit-latency-us = <2350>; 362 min-residency-us = <9144>; 363 }; 364 365 cluster_sleep_1: cluster-sleep-1 { 366 compatible = "domain-idle-state"; 367 arm,psci-suspend-param = <0x4100c344>; 368 entry-latency-us = <2800>; 369 exit-latency-us = <4400>; 370 min-residency-us = <10150>; 371 }; 372 }; 373 }; 374 375 firmware { 376 scm: scm { 377 compatible = "qcom,scm-sm8650", "qcom,scm"; 378 qcom,dload-mode = <&tcsr 0x19000>; 379 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 381 }; 382 }; 383 384 clk_virt: interconnect-0 { 385 compatible = "qcom,sm8650-clk-virt"; 386 #interconnect-cells = <2>; 387 qcom,bcm-voters = <&apps_bcm_voter>; 388 }; 389 390 mc_virt: interconnect-1 { 391 compatible = "qcom,sm8650-mc-virt"; 392 #interconnect-cells = <2>; 393 qcom,bcm-voters = <&apps_bcm_voter>; 394 }; 395 396 memory@a0000000 { 397 device_type = "memory"; 398 /* We expect the bootloader to fill in the size */ 399 reg = <0 0xa0000000 0 0>; 400 }; 401 402 pmu-a520 { 403 compatible = "arm,cortex-a520-pmu"; 404 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 405 }; 406 407 pmu-a720 { 408 compatible = "arm,cortex-a720-pmu"; 409 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 410 }; 411 412 pmu-x4 { 413 compatible = "arm,cortex-x4-pmu"; 414 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 415 }; 416 417 psci { 418 compatible = "arm,psci-1.0"; 419 method = "smc"; 420 421 cpu_pd0: power-domain-cpu0 { 422 #power-domain-cells = <0>; 423 power-domains = <&cluster_pd>; 424 domain-idle-states = <&silver_cpu_sleep_0>; 425 }; 426 427 cpu_pd1: power-domain-cpu1 { 428 #power-domain-cells = <0>; 429 power-domains = <&cluster_pd>; 430 domain-idle-states = <&silver_cpu_sleep_0>; 431 }; 432 433 cpu_pd2: power-domain-cpu2 { 434 #power-domain-cells = <0>; 435 power-domains = <&cluster_pd>; 436 domain-idle-states = <&gold_cpu_sleep_0>; 437 }; 438 439 cpu_pd3: power-domain-cpu3 { 440 #power-domain-cells = <0>; 441 power-domains = <&cluster_pd>; 442 domain-idle-states = <&gold_cpu_sleep_0>; 443 }; 444 445 cpu_pd4: power-domain-cpu4 { 446 #power-domain-cells = <0>; 447 power-domains = <&cluster_pd>; 448 domain-idle-states = <&gold_cpu_sleep_0>; 449 }; 450 451 cpu_pd5: power-domain-cpu5 { 452 #power-domain-cells = <0>; 453 power-domains = <&cluster_pd>; 454 domain-idle-states = <&gold_cpu_sleep_0>; 455 }; 456 457 cpu_pd6: power-domain-cpu6 { 458 #power-domain-cells = <0>; 459 power-domains = <&cluster_pd>; 460 domain-idle-states = <&gold_cpu_sleep_0>; 461 }; 462 463 cpu_pd7: power-domain-cpu7 { 464 #power-domain-cells = <0>; 465 power-domains = <&cluster_pd>; 466 domain-idle-states = <&gold_plus_cpu_sleep_0>; 467 }; 468 469 cluster_pd: power-domain-cluster { 470 #power-domain-cells = <0>; 471 domain-idle-states = <&cluster_sleep_0>, 472 <&cluster_sleep_1>; 473 }; 474 }; 475 476 reserved_memory: reserved-memory { 477 #address-cells = <2>; 478 #size-cells = <2>; 479 ranges; 480 481 hyp_mem: hyp@80000000 { 482 reg = <0 0x80000000 0 0xe00000>; 483 no-map; 484 }; 485 486 cpusys_vm_mem: cpusys-vm@80e00000 { 487 reg = <0 0x80e00000 0 0x400000>; 488 no-map; 489 }; 490 491 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 492 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 493 reg = <0 0x81a00000 0 0x260000>; 494 no-map; 495 }; 496 497 aop_cmd_db_mem: aop-cmd-db@81c60000 { 498 compatible = "qcom,cmd-db"; 499 reg = <0 0x81c60000 0 0x20000>; 500 no-map; 501 }; 502 503 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 504 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 505 reg = <0 0x81c80000 0 0x75000>; 506 no-map; 507 }; 508 509 /* Secdata region can be reused by apps */ 510 511 smem: smem@81d00000 { 512 compatible = "qcom,smem"; 513 reg = <0 0x81d00000 0 0x200000>; 514 hwlocks = <&tcsr_mutex 3>; 515 no-map; 516 }; 517 518 adsp_mhi_mem: adsp-mhi@81f00000 { 519 reg = <0 0x81f00000 0 0x20000>; 520 no-map; 521 }; 522 523 pvmfw_mem: pvmfw@824a0000 { 524 reg = <0 0x824a0000 0 0x100000>; 525 no-map; 526 }; 527 528 global_sync_mem: global-sync@82600000 { 529 reg = <0 0x82600000 0 0x100000>; 530 no-map; 531 }; 532 533 tz_stat_mem: tz-stat@82700000 { 534 reg = <0 0x82700000 0 0x100000>; 535 no-map; 536 }; 537 538 qdss_mem: qdss@82800000 { 539 reg = <0 0x82800000 0 0x2000000>; 540 no-map; 541 }; 542 543 qlink_logging_mem: qlink-logging@84800000 { 544 reg = <0 0x84800000 0 0x200000>; 545 no-map; 546 }; 547 548 mpss_dsm_mem: mpss-dsm@86b00000 { 549 reg = <0 0x86b00000 0 0x4900000>; 550 no-map; 551 }; 552 553 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 554 reg = <0 0x8b400000 0 0x800000>; 555 no-map; 556 }; 557 558 mpss_mem: mpss@8bc00000 { 559 reg = <0 0x8bc00000 0 0xf400000>; 560 no-map; 561 }; 562 563 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 564 reg = <0 0x9b000000 0 0x80000>; 565 no-map; 566 }; 567 568 ipa_fw_mem: ipa-fw@9b080000 { 569 reg = <0 0x9b080000 0 0x10000>; 570 no-map; 571 }; 572 573 ipa_gsi_mem: ipa-gsi@9b090000 { 574 reg = <0 0x9b090000 0 0xa000>; 575 no-map; 576 }; 577 578 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 579 reg = <0 0x9b09a000 0 0x2000>; 580 no-map; 581 }; 582 583 spss_region_mem: spss@9b0a0000 { 584 reg = <0 0x9b0a0000 0 0x1e0000>; 585 no-map; 586 }; 587 588 /* First part of the "SPU secure shared memory" region */ 589 spu_tz_shared_mem: spu-tz-shared@9b280000 { 590 reg = <0 0x9b280000 0 0x60000>; 591 no-map; 592 }; 593 594 /* Second part of the "SPU secure shared memory" region */ 595 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 596 reg = <0 0x9b2e0000 0 0x20000>; 597 no-map; 598 }; 599 600 camera_mem: camera@9b300000 { 601 reg = <0 0x9b300000 0 0x800000>; 602 no-map; 603 }; 604 605 video_mem: video@9bb00000 { 606 reg = <0 0x9bb00000 0 0x800000>; 607 no-map; 608 }; 609 610 cvp_mem: cvp@9c300000 { 611 reg = <0 0x9c300000 0 0x700000>; 612 no-map; 613 }; 614 615 cdsp_mem: cdsp@9ca00000 { 616 reg = <0 0x9ca00000 0 0x1400000>; 617 no-map; 618 }; 619 620 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 621 reg = <0 0x9de00000 0 0x80000>; 622 no-map; 623 }; 624 625 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 626 reg = <0 0x9de80000 0 0x80000>; 627 no-map; 628 }; 629 630 adspslpi_mem: adspslpi@9df00000 { 631 reg = <0 0x9df00000 0 0x4080000>; 632 no-map; 633 }; 634 635 rmtfs_mem: rmtfs@d7c00000 { 636 compatible = "qcom,rmtfs-mem"; 637 reg = <0 0xd7c00000 0 0x400000>; 638 no-map; 639 640 qcom,client-id = <1>; 641 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 642 }; 643 644 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 645 tz_merged_mem: tz-merged@d8000000 { 646 reg = <0 0xd8000000 0 0x800000>; 647 no-map; 648 }; 649 650 hwfence_shbuf: hwfence-shbuf@e6440000 { 651 reg = <0 0xe6440000 0 0x2dd000>; 652 no-map; 653 }; 654 655 trust_ui_vm_mem: trust-ui-vm@f3800000 { 656 reg = <0 0xf3800000 0 0x4400000>; 657 no-map; 658 }; 659 660 oem_vm_mem: oem-vm@f7c00000 { 661 reg = <0 0xf7c00000 0 0x4c00000>; 662 no-map; 663 }; 664 665 llcc_lpi_mem: llcc-lpi@ff800000 { 666 reg = <0 0xff800000 0 0x600000>; 667 no-map; 668 }; 669 }; 670 671 smp2p-adsp { 672 compatible = "qcom,smp2p"; 673 674 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 675 IPCC_MPROC_SIGNAL_SMP2P 676 IRQ_TYPE_EDGE_RISING>; 677 678 mboxes = <&ipcc IPCC_CLIENT_LPASS 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,smem = <443>, <429>; 682 qcom,local-pid = <0>; 683 qcom,remote-pid = <2>; 684 685 smp2p_adsp_out: master-kernel { 686 qcom,entry-name = "master-kernel"; 687 #qcom,smem-state-cells = <1>; 688 }; 689 690 smp2p_adsp_in: slave-kernel { 691 qcom,entry-name = "slave-kernel"; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 }; 695 }; 696 697 smp2p-cdsp { 698 compatible = "qcom,smp2p"; 699 700 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 701 IPCC_MPROC_SIGNAL_SMP2P 702 IRQ_TYPE_EDGE_RISING>; 703 704 mboxes = <&ipcc IPCC_CLIENT_CDSP 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,smem = <94>, <432>; 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <5>; 710 711 smp2p_cdsp_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 smp2p_cdsp_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 }; 721 }; 722 723 smp2p-modem { 724 compatible = "qcom,smp2p"; 725 726 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 727 IPCC_MPROC_SIGNAL_SMP2P 728 IRQ_TYPE_EDGE_RISING>; 729 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,smem = <435>, <428>; 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <1>; 736 737 smp2p_modem_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_modem_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 748 ipa_smp2p_out: ipa-ap-to-modem { 749 qcom,entry-name = "ipa"; 750 #qcom,smem-state-cells = <1>; 751 }; 752 753 ipa_smp2p_in: ipa-modem-to-ap { 754 qcom,entry-name = "ipa"; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 }; 758 }; 759 760 soc: soc@0 { 761 compatible = "simple-bus"; 762 763 #address-cells = <2>; 764 #size-cells = <2>; 765 dma-ranges = <0 0 0 0 0x10 0>; 766 ranges = <0 0 0 0 0x10 0>; 767 768 gcc: clock-controller@100000 { 769 compatible = "qcom,sm8650-gcc"; 770 reg = <0 0x00100000 0 0x1f4200>; 771 772 clocks = <&bi_tcxo_div2>, 773 <&bi_tcxo_ao_div2>, 774 <&sleep_clk>, 775 <&pcie0_phy>, 776 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 777 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 778 <&ufs_mem_phy 0>, 779 <&ufs_mem_phy 1>, 780 <&ufs_mem_phy 2>, 781 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 782 783 #clock-cells = <1>; 784 #reset-cells = <1>; 785 #power-domain-cells = <1>; 786 }; 787 788 ipcc: mailbox@406000 { 789 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 790 reg = <0 0x00406000 0 0x1000>; 791 792 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 793 interrupt-controller; 794 #interrupt-cells = <3>; 795 796 #mbox-cells = <2>; 797 }; 798 799 gpi_dma2: dma-controller@800000 { 800 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 801 reg = <0 0x00800000 0 0x60000>; 802 803 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 815 816 dma-channels = <12>; 817 dma-channel-mask = <0x3f>; 818 #dma-cells = <3>; 819 820 iommus = <&apps_smmu 0x436 0>; 821 822 dma-coherent; 823 824 status = "disabled"; 825 }; 826 827 qupv3_id_1: geniqup@8c0000 { 828 compatible = "qcom,geni-se-qup"; 829 reg = <0 0x008c0000 0 0x2000>; 830 831 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 832 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 833 clock-names = "m-ahb", 834 "s-ahb"; 835 836 iommus = <&apps_smmu 0x423 0>; 837 838 dma-coherent; 839 840 #address-cells = <2>; 841 #size-cells = <2>; 842 ranges; 843 844 status = "disabled"; 845 846 i2c8: i2c@880000 { 847 compatible = "qcom,geni-i2c"; 848 reg = <0 0x00880000 0 0x4000>; 849 850 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 851 852 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 853 clock-names = "se"; 854 855 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 856 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 857 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 858 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 859 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 860 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 861 interconnect-names = "qup-core", 862 "qup-config", 863 "qup-memory"; 864 865 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 866 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 867 dma-names = "tx", 868 "rx"; 869 870 pinctrl-0 = <&qup_i2c8_data_clk>; 871 pinctrl-names = "default"; 872 873 #address-cells = <1>; 874 #size-cells = <0>; 875 876 status = "disabled"; 877 }; 878 879 spi8: spi@880000 { 880 compatible = "qcom,geni-spi"; 881 reg = <0 0x00880000 0 0x4000>; 882 883 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 884 885 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 886 clock-names = "se"; 887 888 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 889 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 890 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 891 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 892 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 893 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 894 interconnect-names = "qup-core", 895 "qup-config", 896 "qup-memory"; 897 898 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 899 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 900 dma-names = "tx", 901 "rx"; 902 903 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 904 pinctrl-names = "default"; 905 906 #address-cells = <1>; 907 #size-cells = <0>; 908 909 status = "disabled"; 910 }; 911 912 i2c9: i2c@884000 { 913 compatible = "qcom,geni-i2c"; 914 reg = <0 0x00884000 0 0x4000>; 915 916 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 917 918 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 919 clock-names = "se"; 920 921 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 922 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 923 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 924 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 925 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 926 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 927 interconnect-names = "qup-core", 928 "qup-config", 929 "qup-memory"; 930 931 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 932 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 933 dma-names = "tx", 934 "rx"; 935 936 pinctrl-0 = <&qup_i2c9_data_clk>; 937 pinctrl-names = "default"; 938 939 #address-cells = <1>; 940 #size-cells = <0>; 941 942 status = "disabled"; 943 }; 944 945 spi9: spi@884000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x00884000 0 0x4000>; 948 949 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 950 951 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 952 clock-names = "se"; 953 954 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 955 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 956 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 957 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 958 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 959 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 960 interconnect-names = "qup-core", 961 "qup-config", 962 "qup-memory"; 963 964 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 965 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 966 dma-names = "tx", 967 "rx"; 968 969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 970 pinctrl-names = "default"; 971 972 #address-cells = <1>; 973 #size-cells = <0>; 974 975 status = "disabled"; 976 }; 977 978 i2c10: i2c@888000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x00888000 0 0x4000>; 981 982 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 983 984 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 985 clock-names = "se"; 986 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 988 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 989 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 990 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 991 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 992 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 993 interconnect-names = "qup-core", 994 "qup-config", 995 "qup-memory"; 996 997 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 998 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 999 dma-names = "tx", 1000 "rx"; 1001 1002 pinctrl-0 = <&qup_i2c10_data_clk>; 1003 pinctrl-names = "default"; 1004 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 1008 status = "disabled"; 1009 }; 1010 1011 spi10: spi@888000 { 1012 compatible = "qcom,geni-spi"; 1013 reg = <0 0x00888000 0 0x4000>; 1014 1015 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1016 1017 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1018 clock-names = "se"; 1019 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1021 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1023 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1024 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1026 interconnect-names = "qup-core", 1027 "qup-config", 1028 "qup-memory"; 1029 1030 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1031 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1032 dma-names = "tx", 1033 "rx"; 1034 1035 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1036 pinctrl-names = "default"; 1037 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 1041 status = "disabled"; 1042 }; 1043 1044 i2c11: i2c@88c000 { 1045 compatible = "qcom,geni-i2c"; 1046 reg = <0 0x0088c000 0 0x4000>; 1047 1048 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1049 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1051 clock-names = "se"; 1052 1053 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1054 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1056 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1057 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 1063 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1064 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1065 dma-names = "tx", 1066 "rx"; 1067 1068 pinctrl-0 = <&qup_i2c11_data_clk>; 1069 pinctrl-names = "default"; 1070 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 status = "disabled"; 1075 }; 1076 1077 spi11: spi@88c000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x0088c000 0 0x4000>; 1080 1081 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1082 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1084 clock-names = "se"; 1085 1086 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1087 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1088 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1089 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1090 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1091 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1092 interconnect-names = "qup-core", 1093 "qup-config", 1094 "qup-memory"; 1095 1096 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1097 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1098 dma-names = "tx", 1099 "rx"; 1100 1101 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1102 pinctrl-names = "default"; 1103 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 1107 status = "disabled"; 1108 }; 1109 1110 i2c12: i2c@890000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0 0x00890000 0 0x4000>; 1113 1114 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1115 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 clock-names = "se"; 1118 1119 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1120 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1121 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1122 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1124 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1125 interconnect-names = "qup-core", 1126 "qup-config", 1127 "qup-memory"; 1128 1129 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1130 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1131 dma-names = "tx", 1132 "rx"; 1133 1134 pinctrl-0 = <&qup_i2c12_data_clk>; 1135 pinctrl-names = "default"; 1136 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 1140 status = "disabled"; 1141 }; 1142 1143 spi12: spi@890000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00890000 0 0x4000>; 1146 1147 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1148 1149 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1150 clock-names = "se"; 1151 1152 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1153 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1154 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1155 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1158 interconnect-names = "qup-core", 1159 "qup-config", 1160 "qup-memory"; 1161 1162 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1163 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1164 dma-names = "tx", 1165 "rx"; 1166 1167 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1168 pinctrl-names = "default"; 1169 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 1173 status = "disabled"; 1174 }; 1175 1176 i2c13: i2c@894000 { 1177 compatible = "qcom,geni-i2c"; 1178 reg = <0 0x00894000 0 0x4000>; 1179 1180 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1181 1182 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1183 clock-names = "se"; 1184 1185 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1186 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1187 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1188 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1189 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1190 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1191 interconnect-names = "qup-core", 1192 "qup-config", 1193 "qup-memory"; 1194 1195 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1196 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1197 dma-names = "tx", 1198 "rx"; 1199 1200 pinctrl-0 = <&qup_i2c13_data_clk>; 1201 pinctrl-names = "default"; 1202 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 status = "disabled"; 1207 }; 1208 1209 spi13: spi@894000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0 0x00894000 0 0x4000>; 1212 1213 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1214 1215 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1216 clock-names = "se"; 1217 1218 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1219 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1220 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1221 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1222 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1224 interconnect-names = "qup-core", 1225 "qup-config", 1226 "qup-memory"; 1227 1228 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1229 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1230 dma-names = "tx", 1231 "rx"; 1232 1233 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1234 pinctrl-names = "default"; 1235 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 1239 status = "disabled"; 1240 }; 1241 1242 uart14: serial@898000 { 1243 compatible = "qcom,geni-uart"; 1244 reg = <0 0x00898000 0 0x4000>; 1245 1246 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1247 1248 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1249 clock-names = "se"; 1250 1251 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1252 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1253 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1254 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1255 interconnect-names = "qup-core", 1256 "qup-config"; 1257 1258 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1259 pinctrl-names = "default"; 1260 1261 status = "disabled"; 1262 }; 1263 1264 uart15: serial@89c000 { 1265 compatible = "qcom,geni-debug-uart"; 1266 reg = <0 0x0089c000 0 0x4000>; 1267 1268 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1269 1270 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1271 clock-names = "se"; 1272 1273 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1274 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1275 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1276 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1277 interconnect-names = "qup-core", 1278 "qup-config"; 1279 1280 pinctrl-0 = <&qup_uart15_default>; 1281 pinctrl-names = "default"; 1282 1283 status = "disabled"; 1284 }; 1285 }; 1286 1287 i2c_master_hub_0: geniqup@9c0000 { 1288 compatible = "qcom,geni-se-i2c-master-hub"; 1289 reg = <0 0x009c0000 0 0x2000>; 1290 1291 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1292 clock-names = "s-ahb"; 1293 1294 #address-cells = <2>; 1295 #size-cells = <2>; 1296 ranges; 1297 1298 status = "disabled"; 1299 1300 i2c_hub_0: i2c@980000 { 1301 compatible = "qcom,geni-i2c-master-hub"; 1302 reg = <0 0x00980000 0 0x4000>; 1303 1304 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1305 1306 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1307 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1308 clock-names = "se", 1309 "core"; 1310 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1312 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1313 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1314 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1315 interconnect-names = "qup-core", 1316 "qup-config"; 1317 1318 pinctrl-0 = <&hub_i2c0_data_clk>; 1319 pinctrl-names = "default"; 1320 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 1324 status = "disabled"; 1325 }; 1326 1327 i2c_hub_1: i2c@984000 { 1328 compatible = "qcom,geni-i2c-master-hub"; 1329 reg = <0 0x00984000 0 0x4000>; 1330 1331 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1332 1333 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1335 clock-names = "se", 1336 "core"; 1337 1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1339 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1340 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1341 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1342 interconnect-names = "qup-core", 1343 "qup-config"; 1344 1345 pinctrl-0 = <&hub_i2c1_data_clk>; 1346 pinctrl-names = "default"; 1347 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 1351 status = "disabled"; 1352 }; 1353 1354 i2c_hub_2: i2c@988000 { 1355 compatible = "qcom,geni-i2c-master-hub"; 1356 reg = <0 0x00988000 0 0x4000>; 1357 1358 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1359 1360 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1361 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1362 clock-names = "se", 1363 "core"; 1364 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1366 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1367 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1368 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1369 interconnect-names = "qup-core", 1370 "qup-config"; 1371 1372 pinctrl-0 = <&hub_i2c2_data_clk>; 1373 pinctrl-names = "default"; 1374 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 1378 status = "disabled"; 1379 }; 1380 1381 i2c_hub_3: i2c@98c000 { 1382 compatible = "qcom,geni-i2c-master-hub"; 1383 reg = <0 0x0098c000 0 0x4000>; 1384 1385 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1386 1387 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1388 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1389 clock-names = "se", 1390 "core"; 1391 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1393 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1394 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1395 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1396 interconnect-names = "qup-core", 1397 "qup-config"; 1398 1399 pinctrl-0 = <&hub_i2c3_data_clk>; 1400 pinctrl-names = "default"; 1401 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 1405 status = "disabled"; 1406 }; 1407 1408 i2c_hub_4: i2c@990000 { 1409 compatible = "qcom,geni-i2c-master-hub"; 1410 reg = <0 0x00990000 0 0x4000>; 1411 1412 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1413 1414 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1415 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1416 clock-names = "se", 1417 "core"; 1418 1419 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1420 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1422 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1423 interconnect-names = "qup-core", 1424 "qup-config"; 1425 1426 pinctrl-0 = <&hub_i2c4_data_clk>; 1427 pinctrl-names = "default"; 1428 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 1432 status = "disabled"; 1433 }; 1434 1435 i2c_hub_5: i2c@994000 { 1436 compatible = "qcom,geni-i2c-master-hub"; 1437 reg = <0 0x00994000 0 0x4000>; 1438 1439 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1440 1441 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1442 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1443 clock-names = "se", 1444 "core"; 1445 1446 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1447 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1449 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1450 interconnect-names = "qup-core", 1451 "qup-config"; 1452 1453 pinctrl-0 = <&hub_i2c5_data_clk>; 1454 pinctrl-names = "default"; 1455 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 1459 status = "disabled"; 1460 }; 1461 1462 i2c_hub_6: i2c@998000 { 1463 compatible = "qcom,geni-i2c-master-hub"; 1464 reg = <0 0x00998000 0 0x4000>; 1465 1466 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1467 1468 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1469 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1470 clock-names = "se", 1471 "core"; 1472 1473 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1474 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1475 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1476 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1477 interconnect-names = "qup-core", 1478 "qup-config"; 1479 1480 pinctrl-0 = <&hub_i2c6_data_clk>; 1481 pinctrl-names = "default"; 1482 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 1486 status = "disabled"; 1487 }; 1488 1489 i2c_hub_7: i2c@99c000 { 1490 compatible = "qcom,geni-i2c-master-hub"; 1491 reg = <0 0x0099c000 0 0x4000>; 1492 1493 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1494 1495 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1496 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1497 clock-names = "se", 1498 "core"; 1499 1500 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1501 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1502 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1503 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1504 interconnect-names = "qup-core", 1505 "qup-config"; 1506 1507 pinctrl-0 = <&hub_i2c7_data_clk>; 1508 pinctrl-names = "default"; 1509 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 1513 status = "disabled"; 1514 }; 1515 1516 i2c_hub_8: i2c@9a0000 { 1517 compatible = "qcom,geni-i2c-master-hub"; 1518 reg = <0 0x009a0000 0 0x4000>; 1519 1520 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1521 1522 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1523 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1524 clock-names = "se", 1525 "core"; 1526 1527 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1528 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1529 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1530 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1531 interconnect-names = "qup-core", 1532 "qup-config"; 1533 1534 pinctrl-0 = <&hub_i2c8_data_clk>; 1535 pinctrl-names = "default"; 1536 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 1540 status = "disabled"; 1541 }; 1542 1543 i2c_hub_9: i2c@9a4000 { 1544 compatible = "qcom,geni-i2c-master-hub"; 1545 reg = <0 0x009a4000 0 0x4000>; 1546 1547 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1548 1549 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1550 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1551 clock-names = "se", 1552 "core"; 1553 1554 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1555 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1556 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1557 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1558 interconnect-names = "qup-core", 1559 "qup-config"; 1560 1561 pinctrl-0 = <&hub_i2c9_data_clk>; 1562 pinctrl-names = "default"; 1563 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 1567 status = "disabled"; 1568 }; 1569 }; 1570 1571 gpi_dma1: dma-controller@a00000 { 1572 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1573 reg = <0 0x00a00000 0 0x60000>; 1574 1575 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1587 1588 dma-channels = <12>; 1589 dma-channel-mask = <0xc>; 1590 #dma-cells = <3>; 1591 1592 iommus = <&apps_smmu 0xb6 0>; 1593 dma-coherent; 1594 1595 status = "disabled"; 1596 }; 1597 1598 qupv3_id_0: geniqup@ac0000 { 1599 compatible = "qcom,geni-se-qup"; 1600 reg = <0 0x00ac0000 0 0x2000>; 1601 1602 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1603 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1604 clock-names = "m-ahb", 1605 "s-ahb"; 1606 1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1608 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1609 interconnect-names = "qup-core"; 1610 1611 iommus = <&apps_smmu 0xa3 0>; 1612 1613 dma-coherent; 1614 1615 #address-cells = <2>; 1616 #size-cells = <2>; 1617 ranges; 1618 1619 status = "disabled"; 1620 1621 i2c0: i2c@a80000 { 1622 compatible = "qcom,geni-i2c"; 1623 reg = <0 0x00a80000 0 0x4000>; 1624 1625 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1626 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1628 clock-names = "se"; 1629 1630 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1631 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1632 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1633 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1634 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1635 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1636 interconnect-names = "qup-core", 1637 "qup-config", 1638 "qup-memory"; 1639 1640 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1641 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1642 dma-names = "tx", 1643 "rx"; 1644 1645 pinctrl-0 = <&qup_i2c0_data_clk>; 1646 pinctrl-names = "default"; 1647 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 1651 status = "disabled"; 1652 }; 1653 1654 spi0: spi@a80000 { 1655 compatible = "qcom,geni-spi"; 1656 reg = <0 0x00a80000 0 0x4000>; 1657 1658 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1659 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1661 clock-names = "se"; 1662 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1664 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1665 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1666 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1667 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1668 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1669 interconnect-names = "qup-core", 1670 "qup-config", 1671 "qup-memory"; 1672 1673 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1674 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1675 dma-names = "tx", 1676 "rx"; 1677 1678 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1679 pinctrl-names = "default"; 1680 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 1684 status = "disabled"; 1685 }; 1686 1687 i2c1: i2c@a84000 { 1688 compatible = "qcom,geni-i2c"; 1689 reg = <0 0x00a84000 0 0x4000>; 1690 1691 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1692 1693 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1694 clock-names = "se"; 1695 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1697 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1698 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1699 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1700 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1701 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1702 interconnect-names = "qup-core", 1703 "qup-config", 1704 "qup-memory"; 1705 1706 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1707 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1708 dma-names = "tx", 1709 "rx"; 1710 1711 pinctrl-0 = <&qup_i2c1_data_clk>; 1712 pinctrl-names = "default"; 1713 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 1717 status = "disabled"; 1718 }; 1719 1720 spi1: spi@a84000 { 1721 compatible = "qcom,geni-spi"; 1722 reg = <0 0x00a84000 0 0x4000>; 1723 1724 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1725 1726 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1727 clock-names = "se"; 1728 1729 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1730 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1731 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1732 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1733 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1734 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1735 interconnect-names = "qup-core", 1736 "qup-config", 1737 "qup-memory"; 1738 1739 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1740 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1741 dma-names = "tx", 1742 "rx"; 1743 1744 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1745 pinctrl-names = "default"; 1746 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 1750 status = "disabled"; 1751 }; 1752 1753 i2c2: i2c@a88000 { 1754 compatible = "qcom,geni-i2c"; 1755 reg = <0 0x00a88000 0 0x4000>; 1756 1757 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1758 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1760 clock-names = "se"; 1761 1762 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1763 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1764 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1765 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1766 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1768 interconnect-names = "qup-core", 1769 "qup-config", 1770 "qup-memory"; 1771 1772 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1773 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1774 dma-names = "tx", 1775 "rx"; 1776 1777 pinctrl-0 = <&qup_i2c2_data_clk>; 1778 pinctrl-names = "default"; 1779 1780 #address-cells = <1>; 1781 #size-cells = <0>; 1782 1783 status = "disabled"; 1784 }; 1785 1786 spi2: spi@a88000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0 0x00a88000 0 0x4000>; 1789 1790 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1791 1792 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1793 clock-names = "se"; 1794 1795 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1796 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1797 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1798 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1799 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1800 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1801 interconnect-names = "qup-core", 1802 "qup-config", 1803 "qup-memory"; 1804 1805 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1806 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1807 dma-names = "tx", 1808 "rx"; 1809 1810 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1811 pinctrl-names = "default"; 1812 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 1816 status = "disabled"; 1817 }; 1818 1819 i2c3: i2c@a8c000 { 1820 compatible = "qcom,geni-i2c"; 1821 reg = <0 0x00a8c000 0 0x4000>; 1822 1823 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1824 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1826 clock-names = "se"; 1827 1828 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1829 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1830 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1831 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1832 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1833 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1834 interconnect-names = "qup-core", 1835 "qup-config", 1836 "qup-memory"; 1837 1838 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1839 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1840 dma-names = "tx", 1841 "rx"; 1842 1843 pinctrl-0 = <&qup_i2c3_data_clk>; 1844 pinctrl-names = "default"; 1845 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 1849 status = "disabled"; 1850 }; 1851 1852 spi3: spi@a8c000 { 1853 compatible = "qcom,geni-spi"; 1854 reg = <0 0x00a8c000 0 0x4000>; 1855 1856 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1857 1858 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1859 clock-names = "se"; 1860 1861 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1862 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1863 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1864 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1865 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1866 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1867 interconnect-names = "qup-core", 1868 "qup-config", 1869 "qup-memory"; 1870 1871 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1872 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1873 dma-names = "tx", 1874 "rx"; 1875 1876 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1877 pinctrl-names = "default"; 1878 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 1882 status = "disabled"; 1883 }; 1884 1885 i2c4: i2c@a90000 { 1886 compatible = "qcom,geni-i2c"; 1887 reg = <0 0x00a90000 0 0x4000>; 1888 1889 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1890 1891 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1892 clock-names = "se"; 1893 1894 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1895 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1896 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1897 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1898 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1900 interconnect-names = "qup-core", 1901 "qup-config", 1902 "qup-memory"; 1903 1904 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1905 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1906 dma-names = "tx", 1907 "rx"; 1908 1909 pinctrl-0 = <&qup_i2c4_data_clk>; 1910 pinctrl-names = "default"; 1911 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 1915 status = "disabled"; 1916 }; 1917 1918 spi4: spi@a90000 { 1919 compatible = "qcom,geni-spi"; 1920 reg = <0 0x00a90000 0 0x4000>; 1921 1922 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1923 1924 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1925 clock-names = "se"; 1926 1927 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1928 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1929 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1930 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1931 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1932 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1933 interconnect-names = "qup-core", 1934 "qup-config", 1935 "qup-memory"; 1936 1937 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1938 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1939 dma-names = "tx", 1940 "rx"; 1941 1942 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1943 pinctrl-names = "default"; 1944 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 1948 status = "disabled"; 1949 }; 1950 1951 i2c5: i2c@a94000 { 1952 compatible = "qcom,geni-i2c"; 1953 reg = <0 0x00a94000 0 0x4000>; 1954 1955 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1956 1957 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1958 clock-names = "se"; 1959 1960 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1961 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1962 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1963 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1964 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1965 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1966 interconnect-names = "qup-core", 1967 "qup-config", 1968 "qup-memory"; 1969 1970 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1971 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1972 dma-names = "tx", 1973 "rx"; 1974 1975 pinctrl-0 = <&qup_i2c5_data_clk>; 1976 pinctrl-names = "default"; 1977 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 1981 status = "disabled"; 1982 }; 1983 1984 spi5: spi@a94000 { 1985 compatible = "qcom,geni-spi"; 1986 reg = <0 0x00a94000 0 0x4000>; 1987 1988 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1989 1990 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1991 clock-names = "se"; 1992 1993 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1994 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1995 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1996 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1997 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1998 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1999 interconnect-names = "qup-core", 2000 "qup-config", 2001 "qup-memory"; 2002 2003 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2004 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2005 dma-names = "tx", 2006 "rx"; 2007 2008 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2009 pinctrl-names = "default"; 2010 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 2014 status = "disabled"; 2015 }; 2016 2017 i2c6: i2c@a98000 { 2018 compatible = "qcom,geni-i2c"; 2019 reg = <0 0x00a98000 0 0x4000>; 2020 2021 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2022 2023 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2024 clock-names = "se"; 2025 2026 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2027 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2028 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2029 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2030 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2031 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2032 interconnect-names = "qup-core", 2033 "qup-config", 2034 "qup-memory"; 2035 2036 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2037 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2038 dma-names = "tx", 2039 "rx"; 2040 2041 pinctrl-0 = <&qup_i2c6_data_clk>; 2042 pinctrl-names = "default"; 2043 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 2047 status = "disabled"; 2048 }; 2049 2050 spi6: spi@a98000 { 2051 compatible = "qcom,geni-spi"; 2052 reg = <0 0x00a98000 0 0x4000>; 2053 2054 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2055 2056 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2057 clock-names = "se"; 2058 2059 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2060 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2061 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2062 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2063 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2064 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2065 interconnect-names = "qup-core", 2066 "qup-config", 2067 "qup-memory"; 2068 2069 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2070 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2071 dma-names = "tx", 2072 "rx"; 2073 2074 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2075 pinctrl-names = "default"; 2076 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 2080 status = "disabled"; 2081 }; 2082 2083 i2c7: i2c@a9c000 { 2084 compatible = "qcom,geni-i2c"; 2085 reg = <0 0x00a9c000 0 0x4000>; 2086 2087 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2088 2089 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2090 clock-names = "se"; 2091 2092 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2093 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2094 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2095 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2096 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2097 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2098 interconnect-names = "qup-core", 2099 "qup-config", 2100 "qup-memory"; 2101 2102 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2103 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2104 dma-names = "tx", 2105 "rx"; 2106 2107 pinctrl-0 = <&qup_i2c7_data_clk>; 2108 pinctrl-names = "default"; 2109 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 status = "disabled"; 2114 }; 2115 2116 spi7: spi@a9c000 { 2117 compatible = "qcom,geni-spi"; 2118 reg = <0 0x00a9c000 0 0x4000>; 2119 2120 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2121 2122 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2123 clock-names = "se"; 2124 2125 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2126 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2127 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2128 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2129 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2130 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2131 interconnect-names = "qup-core", 2132 "qup-config", 2133 "qup-memory"; 2134 2135 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2136 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2137 dma-names = "tx", 2138 "rx"; 2139 2140 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2141 pinctrl-names = "default"; 2142 2143 #address-cells = <1>; 2144 #size-cells = <0>; 2145 2146 status = "disabled"; 2147 }; 2148 }; 2149 2150 cnoc_main: interconnect@1500000 { 2151 compatible = "qcom,sm8650-cnoc-main"; 2152 reg = <0 0x01500000 0 0x14080>; 2153 2154 qcom,bcm-voters = <&apps_bcm_voter>; 2155 2156 #interconnect-cells = <2>; 2157 }; 2158 2159 config_noc: interconnect@1600000 { 2160 compatible = "qcom,sm8650-config-noc"; 2161 reg = <0 0x01600000 0 0x6200>; 2162 2163 qcom,bcm-voters = <&apps_bcm_voter>; 2164 2165 #interconnect-cells = <2>; 2166 }; 2167 2168 system_noc: interconnect@1680000 { 2169 compatible = "qcom,sm8650-system-noc"; 2170 reg = <0 0x01680000 0 0x1d080>; 2171 2172 qcom,bcm-voters = <&apps_bcm_voter>; 2173 2174 #interconnect-cells = <2>; 2175 }; 2176 2177 pcie_noc: interconnect@16c0000 { 2178 compatible = "qcom,sm8650-pcie-anoc"; 2179 reg = <0 0x016c0000 0 0x12200>; 2180 2181 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2182 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 2183 2184 qcom,bcm-voters = <&apps_bcm_voter>; 2185 2186 #interconnect-cells = <2>; 2187 }; 2188 2189 aggre1_noc: interconnect@16e0000 { 2190 compatible = "qcom,sm8650-aggre1-noc"; 2191 reg = <0 0x016e0000 0 0x16400>; 2192 2193 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2194 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2195 2196 qcom,bcm-voters = <&apps_bcm_voter>; 2197 2198 #interconnect-cells = <2>; 2199 }; 2200 2201 aggre2_noc: interconnect@1700000 { 2202 compatible = "qcom,sm8650-aggre2-noc"; 2203 reg = <0 0x01700000 0 0x1e400>; 2204 2205 clocks = <&rpmhcc RPMH_IPA_CLK>; 2206 2207 qcom,bcm-voters = <&apps_bcm_voter>; 2208 2209 #interconnect-cells = <2>; 2210 }; 2211 2212 mmss_noc: interconnect@1780000 { 2213 compatible = "qcom,sm8650-mmss-noc"; 2214 reg = <0 0x01780000 0 0x5b800>; 2215 2216 qcom,bcm-voters = <&apps_bcm_voter>; 2217 2218 #interconnect-cells = <2>; 2219 }; 2220 2221 rng: rng@10c3000 { 2222 compatible = "qcom,sm8650-trng", "qcom,trng"; 2223 reg = <0 0x010c3000 0 0x1000>; 2224 }; 2225 2226 pcie0: pcie@1c00000 { 2227 device_type = "pci"; 2228 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2229 reg = <0 0x01c00000 0 0x3000>, 2230 <0 0x60000000 0 0xf1d>, 2231 <0 0x60000f20 0 0xa8>, 2232 <0 0x60001000 0 0x1000>, 2233 <0 0x60100000 0 0x100000>; 2234 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2235 2236 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2244 interrupt-names = "msi0", 2245 "msi1", 2246 "msi2", 2247 "msi3", 2248 "msi4", 2249 "msi5", 2250 "msi6", 2251 "msi7"; 2252 2253 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2254 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2255 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2256 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2257 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2258 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2259 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2260 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2261 clock-names = "aux", 2262 "cfg", 2263 "bus_master", 2264 "bus_slave", 2265 "slave_q2a", 2266 "ddrss_sf_tbu", 2267 "noc_aggr", 2268 "cnoc_sf_axi"; 2269 2270 resets = <&gcc GCC_PCIE_0_BCR>; 2271 reset-names = "pci"; 2272 2273 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2275 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2276 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 2277 interconnect-names = "pcie-mem", 2278 "cpu-pcie"; 2279 2280 power-domains = <&gcc PCIE_0_GDSC>; 2281 2282 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2283 <0x100 &apps_smmu 0x1401 0x1>; 2284 2285 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2286 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2287 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2288 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2289 interrupt-map-mask = <0 0 0 0x7>; 2290 #interrupt-cells = <1>; 2291 2292 msi-map = <0x0 &gic_its 0x1400 0x1>, 2293 <0x100 &gic_its 0x1401 0x1>; 2294 msi-map-mask = <0xff00>; 2295 2296 linux,pci-domain = <0>; 2297 num-lanes = <2>; 2298 bus-range = <0 0xff>; 2299 2300 phys = <&pcie0_phy>; 2301 phy-names = "pciephy"; 2302 2303 #address-cells = <3>; 2304 #size-cells = <2>; 2305 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 2306 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 2307 2308 dma-coherent; 2309 2310 status = "disabled"; 2311 2312 pcieport0: pcie@0 { 2313 device_type = "pci"; 2314 reg = <0x0 0x0 0x0 0x0 0x0>; 2315 bus-range = <0x01 0xff>; 2316 2317 #address-cells = <3>; 2318 #size-cells = <2>; 2319 ranges; 2320 }; 2321 }; 2322 2323 pcie0_phy: phy@1c06000 { 2324 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 2325 reg = <0 0x01c06000 0 0x2000>; 2326 2327 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2328 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2329 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2330 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2331 <&gcc GCC_PCIE_0_PIPE_CLK>; 2332 clock-names = "aux", 2333 "cfg_ahb", 2334 "ref", 2335 "rchng", 2336 "pipe"; 2337 2338 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2339 assigned-clock-rates = <100000000>; 2340 2341 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2342 reset-names = "phy"; 2343 2344 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2345 2346 #clock-cells = <0>; 2347 clock-output-names = "pcie0_pipe_clk"; 2348 2349 #phy-cells = <0>; 2350 2351 status = "disabled"; 2352 }; 2353 2354 pcie1: pcie@1c08000 { 2355 device_type = "pci"; 2356 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2357 reg = <0 0x01c08000 0 0x3000>, 2358 <0 0x40000000 0 0xf1d>, 2359 <0 0x40000f20 0 0xa8>, 2360 <0 0x40001000 0 0x1000>, 2361 <0 0x40100000 0 0x100000>; 2362 reg-names = "parf", 2363 "dbi", 2364 "elbi", 2365 "atu", 2366 "config"; 2367 2368 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2376 interrupt-names = "msi0", 2377 "msi1", 2378 "msi2", 2379 "msi3", 2380 "msi4", 2381 "msi5", 2382 "msi6", 2383 "msi7"; 2384 2385 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2386 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2387 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2388 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2389 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2390 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2391 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2392 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2393 clock-names = "aux", 2394 "cfg", 2395 "bus_master", 2396 "bus_slave", 2397 "slave_q2a", 2398 "ddrss_sf_tbu", 2399 "noc_aggr", 2400 "cnoc_sf_axi"; 2401 2402 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2403 assigned-clock-rates = <19200000>; 2404 2405 resets = <&gcc GCC_PCIE_1_BCR>, 2406 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2407 reset-names = "pci", 2408 "link_down"; 2409 2410 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2412 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2413 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2414 interconnect-names = "pcie-mem", 2415 "cpu-pcie"; 2416 2417 power-domains = <&gcc PCIE_1_GDSC>; 2418 2419 iommu-map = <0 &apps_smmu 0x1480 0x1>, 2420 <0x100 &apps_smmu 0x1481 0x1>; 2421 2422 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2423 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2424 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2425 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2426 interrupt-map-mask = <0 0 0 0x7>; 2427 #interrupt-cells = <1>; 2428 2429 msi-map = <0x0 &gic_its 0x1480 0x1>, 2430 <0x100 &gic_its 0x1481 0x1>; 2431 msi-map-mask = <0xff00>; 2432 2433 linux,pci-domain = <1>; 2434 num-lanes = <2>; 2435 bus-range = <0 0xff>; 2436 2437 phys = <&pcie1_phy>; 2438 phy-names = "pciephy"; 2439 2440 dma-coherent; 2441 2442 #address-cells = <3>; 2443 #size-cells = <2>; 2444 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 2445 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 2446 2447 status = "disabled"; 2448 2449 pcie@0 { 2450 device_type = "pci"; 2451 reg = <0x0 0x0 0x0 0x0 0x0>; 2452 bus-range = <0x01 0xff>; 2453 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 ranges; 2457 }; 2458 }; 2459 2460 pcie1_phy: phy@1c0e000 { 2461 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 2462 reg = <0 0x01c0e000 0 0x2000>; 2463 2464 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2465 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2466 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2467 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2468 <&gcc GCC_PCIE_1_PIPE_CLK>; 2469 clock-names = "aux", 2470 "cfg_ahb", 2471 "ref", 2472 "rchng", 2473 "pipe"; 2474 2475 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2476 assigned-clock-rates = <100000000>; 2477 2478 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2479 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2480 reset-names = "phy", 2481 "phy_nocsr"; 2482 2483 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2484 2485 #clock-cells = <1>; 2486 clock-output-names = "pcie1_pipe_clk"; 2487 2488 #phy-cells = <0>; 2489 2490 status = "disabled"; 2491 }; 2492 2493 cryptobam: dma-controller@1dc4000 { 2494 compatible = "qcom,bam-v1.7.0"; 2495 reg = <0 0x01dc4000 0 0x28000>; 2496 2497 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2498 2499 #dma-cells = <1>; 2500 2501 iommus = <&apps_smmu 0x480 0>, 2502 <&apps_smmu 0x481 0>; 2503 2504 qcom,ee = <0>; 2505 qcom,num-ees = <4>; 2506 num-channels = <20>; 2507 qcom,controlled-remotely; 2508 }; 2509 2510 crypto: crypto@1dfa000 { 2511 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 2512 reg = <0 0x01dfa000 0 0x6000>; 2513 2514 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2515 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2516 interconnect-names = "memory"; 2517 2518 dmas = <&cryptobam 4>, <&cryptobam 5>; 2519 dma-names = "rx", "tx"; 2520 2521 iommus = <&apps_smmu 0x480 0>, 2522 <&apps_smmu 0x481 0>; 2523 }; 2524 2525 ufs_mem_phy: phy@1d80000 { 2526 compatible = "qcom,sm8650-qmp-ufs-phy"; 2527 reg = <0 0x01d80000 0 0x2000>; 2528 2529 clocks = <&rpmhcc RPMH_CXO_CLK>, 2530 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2531 <&tcsr TCSR_UFS_CLKREF_EN>; 2532 clock-names = "ref", 2533 "ref_aux", 2534 "qref"; 2535 2536 resets = <&ufs_mem_hc 0>; 2537 reset-names = "ufsphy"; 2538 2539 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2540 2541 #clock-cells = <1>; 2542 #phy-cells = <0>; 2543 2544 status = "disabled"; 2545 }; 2546 2547 ufs_mem_hc: ufs@1d84000 { 2548 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2549 reg = <0 0x01d84000 0 0x3000>; 2550 2551 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2552 2553 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2554 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2555 <&gcc GCC_UFS_PHY_AHB_CLK>, 2556 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2557 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2558 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2559 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2560 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2561 clock-names = "core_clk", 2562 "bus_aggr_clk", 2563 "iface_clk", 2564 "core_clk_unipro", 2565 "ref_clk", 2566 "tx_lane0_sync_clk", 2567 "rx_lane0_sync_clk", 2568 "rx_lane1_sync_clk"; 2569 freq-table-hz = <100000000 403000000>, 2570 <0 0>, 2571 <0 0>, 2572 <100000000 403000000>, 2573 <100000000 403000000>, 2574 <0 0>, 2575 <0 0>, 2576 <0 0>; 2577 2578 resets = <&gcc GCC_UFS_PHY_BCR>; 2579 reset-names = "rst"; 2580 2581 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2582 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2584 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2585 interconnect-names = "ufs-ddr", 2586 "cpu-ufs"; 2587 2588 power-domains = <&gcc UFS_PHY_GDSC>; 2589 required-opps = <&rpmhpd_opp_nom>; 2590 2591 iommus = <&apps_smmu 0x60 0>; 2592 2593 lanes-per-direction = <2>; 2594 qcom,ice = <&ice>; 2595 2596 phys = <&ufs_mem_phy>; 2597 phy-names = "ufsphy"; 2598 2599 #reset-cells = <1>; 2600 2601 status = "disabled"; 2602 }; 2603 2604 ice: crypto@1d88000 { 2605 compatible = "qcom,sm8650-inline-crypto-engine", 2606 "qcom,inline-crypto-engine"; 2607 reg = <0 0x01d88000 0 0x8000>; 2608 2609 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2610 }; 2611 2612 tcsr_mutex: hwlock@1f40000 { 2613 compatible = "qcom,tcsr-mutex"; 2614 reg = <0 0x01f40000 0 0x20000>; 2615 2616 #hwlock-cells = <1>; 2617 }; 2618 2619 tcsr: clock-controller@1fc0000 { 2620 compatible = "qcom,sm8650-tcsr", "syscon"; 2621 reg = <0 0x01fc0000 0 0xa0000>; 2622 2623 clocks = <&rpmhcc RPMH_CXO_CLK>; 2624 2625 #clock-cells = <1>; 2626 #reset-cells = <1>; 2627 }; 2628 2629 gpu: gpu@3d00000 { 2630 compatible = "qcom,adreno-43051401", "qcom,adreno"; 2631 reg = <0x0 0x03d00000 0x0 0x40000>, 2632 <0x0 0x03d9e000 0x0 0x2000>, 2633 <0x0 0x03d61000 0x0 0x800>; 2634 reg-names = "kgsl_3d0_reg_memory", 2635 "cx_mem", 2636 "cx_dbgc"; 2637 2638 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2639 2640 iommus = <&adreno_smmu 0 0x0>, 2641 <&adreno_smmu 1 0x0>; 2642 2643 operating-points-v2 = <&gpu_opp_table>; 2644 2645 qcom,gmu = <&gmu>; 2646 #cooling-cells = <2>; 2647 2648 status = "disabled"; 2649 2650 zap-shader { 2651 memory-region = <&gpu_micro_code_mem>; 2652 }; 2653 2654 /* Speedbin needs more work on A740+, keep only lower freqs */ 2655 gpu_opp_table: opp-table { 2656 compatible = "operating-points-v2"; 2657 2658 opp-231000000 { 2659 opp-hz = /bits/ 64 <231000000>; 2660 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2661 }; 2662 2663 opp-310000000 { 2664 opp-hz = /bits/ 64 <310000000>; 2665 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2666 }; 2667 2668 opp-366000000 { 2669 opp-hz = /bits/ 64 <366000000>; 2670 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2671 }; 2672 2673 opp-422000000 { 2674 opp-hz = /bits/ 64 <422000000>; 2675 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2676 }; 2677 2678 opp-500000000 { 2679 opp-hz = /bits/ 64 <500000000>; 2680 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2681 }; 2682 2683 opp-578000000 { 2684 opp-hz = /bits/ 64 <578000000>; 2685 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2686 }; 2687 2688 opp-629000000 { 2689 opp-hz = /bits/ 64 <629000000>; 2690 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2691 }; 2692 2693 opp-680000000 { 2694 opp-hz = /bits/ 64 <680000000>; 2695 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2696 }; 2697 2698 opp-720000000 { 2699 opp-hz = /bits/ 64 <720000000>; 2700 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2701 }; 2702 2703 opp-770000000 { 2704 opp-hz = /bits/ 64 <770000000>; 2705 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2706 }; 2707 2708 opp-834000000 { 2709 opp-hz = /bits/ 64 <834000000>; 2710 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2711 }; 2712 }; 2713 }; 2714 2715 gmu: gmu@3d6a000 { 2716 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 2717 reg = <0x0 0x03d6a000 0x0 0x35000>, 2718 <0x0 0x03d50000 0x0 0x10000>, 2719 <0x0 0x0b280000 0x0 0x10000>; 2720 reg-names = "gmu", "rscc", "gmu_pdc"; 2721 2722 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2724 interrupt-names = "hfi", "gmu"; 2725 2726 clocks = <&gpucc GPU_CC_AHB_CLK>, 2727 <&gpucc GPU_CC_CX_GMU_CLK>, 2728 <&gpucc GPU_CC_CXO_CLK>, 2729 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2730 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2731 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2732 <&gpucc GPU_CC_DEMET_CLK>; 2733 clock-names = "ahb", 2734 "gmu", 2735 "cxo", 2736 "axi", 2737 "memnoc", 2738 "hub", 2739 "demet"; 2740 2741 power-domains = <&gpucc GPU_CX_GDSC>, 2742 <&gpucc GPU_GX_GDSC>; 2743 power-domain-names = "cx", 2744 "gx"; 2745 2746 iommus = <&adreno_smmu 5 0x0>; 2747 2748 qcom,qmp = <&aoss_qmp>; 2749 2750 operating-points-v2 = <&gmu_opp_table>; 2751 2752 gmu_opp_table: opp-table { 2753 compatible = "operating-points-v2"; 2754 2755 opp-260000000 { 2756 opp-hz = /bits/ 64 <260000000>; 2757 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2758 }; 2759 2760 opp-625000000 { 2761 opp-hz = /bits/ 64 <625000000>; 2762 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2763 }; 2764 }; 2765 }; 2766 2767 gpucc: clock-controller@3d90000 { 2768 compatible = "qcom,sm8650-gpucc"; 2769 reg = <0 0x03d90000 0 0xa000>; 2770 2771 clocks = <&bi_tcxo_div2>, 2772 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2773 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2774 2775 #clock-cells = <1>; 2776 #reset-cells = <1>; 2777 #power-domain-cells = <1>; 2778 }; 2779 2780 adreno_smmu: iommu@3da0000 { 2781 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 2782 "qcom,smmu-500", "arm,mmu-500"; 2783 reg = <0x0 0x03da0000 0x0 0x40000>; 2784 #iommu-cells = <2>; 2785 #global-interrupts = <1>; 2786 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2803 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2804 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2805 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2806 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2807 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2812 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2813 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2814 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2815 <&gpucc GPU_CC_AHB_CLK>; 2816 clock-names = "hlos", 2817 "bus", 2818 "iface", 2819 "ahb"; 2820 power-domains = <&gpucc GPU_CX_GDSC>; 2821 dma-coherent; 2822 }; 2823 2824 ipa: ipa@3f40000 { 2825 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 2826 2827 iommus = <&apps_smmu 0x4a0 0x0>, 2828 <&apps_smmu 0x4a2 0x0>; 2829 reg = <0 0x3f40000 0 0x10000>, 2830 <0 0x3f50000 0 0x5000>, 2831 <0 0x3e04000 0 0xfc000>; 2832 reg-names = "ipa-reg", 2833 "ipa-shared", 2834 "gsi"; 2835 2836 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2837 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2838 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2839 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2840 interrupt-names = "ipa", 2841 "gsi", 2842 "ipa-clock-query", 2843 "ipa-setup-ready"; 2844 2845 clocks = <&rpmhcc RPMH_IPA_CLK>; 2846 clock-names = "core"; 2847 2848 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2849 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2850 interconnect-names = "memory", 2851 "config"; 2852 2853 qcom,qmp = <&aoss_qmp>; 2854 2855 qcom,smem-states = <&ipa_smp2p_out 0>, 2856 <&ipa_smp2p_out 1>; 2857 qcom,smem-state-names = "ipa-clock-enabled-valid", 2858 "ipa-clock-enabled"; 2859 2860 status = "disabled"; 2861 }; 2862 2863 remoteproc_mpss: remoteproc@4080000 { 2864 compatible = "qcom,sm8650-mpss-pas"; 2865 reg = <0x0 0x04080000 0x0 0x10000>; 2866 2867 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2868 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2869 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2870 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2871 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2872 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2873 interrupt-names = "wdog", 2874 "fatal", 2875 "ready", 2876 "handover", 2877 "stop-ack", 2878 "shutdown-ack"; 2879 2880 clocks = <&rpmhcc RPMH_CXO_CLK>; 2881 clock-names = "xo"; 2882 2883 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2884 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2885 2886 power-domains = <&rpmhpd RPMHPD_CX>, 2887 <&rpmhpd RPMHPD_MSS>; 2888 power-domain-names = "cx", 2889 "mss"; 2890 2891 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2892 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 2893 <&qlink_logging_mem>; 2894 2895 qcom,qmp = <&aoss_qmp>; 2896 2897 qcom,smem-states = <&smp2p_modem_out 0>; 2898 qcom,smem-state-names = "stop"; 2899 2900 status = "disabled"; 2901 2902 glink-edge { 2903 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2904 IPCC_MPROC_SIGNAL_GLINK_QMP 2905 IRQ_TYPE_EDGE_RISING>; 2906 2907 mboxes = <&ipcc IPCC_CLIENT_MPSS 2908 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2909 2910 qcom,remote-pid = <1>; 2911 2912 label = "mpss"; 2913 }; 2914 }; 2915 2916 remoteproc_adsp: remoteproc@6800000 { 2917 compatible = "qcom,sm8650-adsp-pas"; 2918 reg = <0x0 0x06800000 0x0 0x10000>; 2919 2920 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2921 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2922 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2923 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2924 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2925 interrupt-names = "wdog", 2926 "fatal", 2927 "ready", 2928 "handover", 2929 "stop-ack"; 2930 2931 clocks = <&rpmhcc RPMH_CXO_CLK>; 2932 clock-names = "xo"; 2933 2934 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2935 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2936 2937 power-domains = <&rpmhpd RPMHPD_LCX>, 2938 <&rpmhpd RPMHPD_LMX>; 2939 power-domain-names = "lcx", 2940 "lmx"; 2941 2942 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2943 2944 qcom,qmp = <&aoss_qmp>; 2945 2946 qcom,smem-states = <&smp2p_adsp_out 0>; 2947 qcom,smem-state-names = "stop"; 2948 2949 status = "disabled"; 2950 2951 remoteproc_adsp_glink: glink-edge { 2952 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2953 IPCC_MPROC_SIGNAL_GLINK_QMP 2954 IRQ_TYPE_EDGE_RISING>; 2955 2956 mboxes = <&ipcc IPCC_CLIENT_LPASS 2957 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2958 2959 qcom,remote-pid = <2>; 2960 2961 label = "lpass"; 2962 2963 fastrpc { 2964 compatible = "qcom,fastrpc"; 2965 2966 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2967 2968 label = "adsp"; 2969 2970 qcom,non-secure-domain; 2971 2972 #address-cells = <1>; 2973 #size-cells = <0>; 2974 2975 compute-cb@3 { 2976 compatible = "qcom,fastrpc-compute-cb"; 2977 reg = <3>; 2978 2979 iommus = <&apps_smmu 0x1003 0x80>, 2980 <&apps_smmu 0x1043 0x20>; 2981 dma-coherent; 2982 }; 2983 2984 compute-cb@4 { 2985 compatible = "qcom,fastrpc-compute-cb"; 2986 reg = <4>; 2987 2988 iommus = <&apps_smmu 0x1004 0x80>, 2989 <&apps_smmu 0x1044 0x20>; 2990 dma-coherent; 2991 }; 2992 2993 compute-cb@5 { 2994 compatible = "qcom,fastrpc-compute-cb"; 2995 reg = <5>; 2996 2997 iommus = <&apps_smmu 0x1005 0x80>, 2998 <&apps_smmu 0x1045 0x20>; 2999 dma-coherent; 3000 }; 3001 3002 compute-cb@6 { 3003 compatible = "qcom,fastrpc-compute-cb"; 3004 reg = <6>; 3005 3006 iommus = <&apps_smmu 0x1006 0x80>, 3007 <&apps_smmu 0x1046 0x20>; 3008 dma-coherent; 3009 }; 3010 3011 compute-cb@7 { 3012 compatible = "qcom,fastrpc-compute-cb"; 3013 reg = <7>; 3014 3015 iommus = <&apps_smmu 0x1007 0x40>, 3016 <&apps_smmu 0x1067 0x0>, 3017 <&apps_smmu 0x1087 0x0>; 3018 dma-coherent; 3019 }; 3020 }; 3021 3022 gpr { 3023 compatible = "qcom,gpr"; 3024 qcom,glink-channels = "adsp_apps"; 3025 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3026 qcom,intents = <512 20>; 3027 #address-cells = <1>; 3028 #size-cells = <0>; 3029 3030 q6apm: service@1 { 3031 compatible = "qcom,q6apm"; 3032 reg = <GPR_APM_MODULE_IID>; 3033 #sound-dai-cells = <0>; 3034 qcom,protection-domain = "avs/audio", 3035 "msm/adsp/audio_pd"; 3036 3037 q6apmbedai: bedais { 3038 compatible = "qcom,q6apm-lpass-dais"; 3039 #sound-dai-cells = <1>; 3040 }; 3041 3042 q6apmdai: dais { 3043 compatible = "qcom,q6apm-dais"; 3044 iommus = <&apps_smmu 0x1001 0x80>, 3045 <&apps_smmu 0x1061 0x0>; 3046 }; 3047 }; 3048 3049 q6prm: service@2 { 3050 compatible = "qcom,q6prm"; 3051 reg = <GPR_PRM_MODULE_IID>; 3052 qcom,protection-domain = "avs/audio", 3053 "msm/adsp/audio_pd"; 3054 3055 q6prmcc: clock-controller { 3056 compatible = "qcom,q6prm-lpass-clocks"; 3057 #clock-cells = <2>; 3058 }; 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 lpass_wsa2macro: codec@6aa0000 { 3065 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3066 reg = <0 0x06aa0000 0 0x1000>; 3067 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3068 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3069 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3070 <&lpass_vamacro>; 3071 clock-names = "mclk", 3072 "macro", 3073 "dcodec", 3074 "fsgen"; 3075 3076 #clock-cells = <0>; 3077 clock-output-names = "wsa2-mclk"; 3078 #sound-dai-cells = <1>; 3079 }; 3080 3081 swr3: soundwire@6ab0000 { 3082 compatible = "qcom,soundwire-v2.0.0"; 3083 reg = <0 0x06ab0000 0 0x10000>; 3084 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 3085 clocks = <&lpass_wsa2macro>; 3086 clock-names = "iface"; 3087 label = "WSA2"; 3088 3089 pinctrl-0 = <&wsa2_swr_active>; 3090 pinctrl-names = "default"; 3091 3092 qcom,din-ports = <4>; 3093 qcom,dout-ports = <9>; 3094 3095 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3096 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3097 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3098 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3099 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3100 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3101 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3102 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3103 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3104 3105 #address-cells = <2>; 3106 #size-cells = <0>; 3107 #sound-dai-cells = <1>; 3108 status = "disabled"; 3109 }; 3110 3111 lpass_rxmacro: codec@6ac0000 { 3112 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 3113 reg = <0 0x06ac0000 0 0x1000>; 3114 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3115 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3116 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3117 <&lpass_vamacro>; 3118 clock-names = "mclk", 3119 "macro", 3120 "dcodec", 3121 "fsgen"; 3122 3123 #clock-cells = <0>; 3124 clock-output-names = "mclk"; 3125 #sound-dai-cells = <1>; 3126 }; 3127 3128 swr1: soundwire@6ad0000 { 3129 compatible = "qcom,soundwire-v2.0.0"; 3130 reg = <0 0x06ad0000 0 0x10000>; 3131 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3132 clocks = <&lpass_rxmacro>; 3133 clock-names = "iface"; 3134 label = "RX"; 3135 3136 pinctrl-0 = <&rx_swr_active>; 3137 pinctrl-names = "default"; 3138 3139 qcom,din-ports = <0>; 3140 qcom,dout-ports = <11>; 3141 3142 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 3143 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 3144 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 3145 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 3146 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 3147 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 3148 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 3149 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 3150 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 3151 3152 #address-cells = <2>; 3153 #size-cells = <0>; 3154 #sound-dai-cells = <1>; 3155 status = "disabled"; 3156 }; 3157 3158 lpass_txmacro: codec@6ae0000 { 3159 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3160 reg = <0 0x06ae0000 0 0x1000>; 3161 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3162 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3163 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3164 <&lpass_vamacro>; 3165 clock-names = "mclk", 3166 "macro", 3167 "dcodec", 3168 "fsgen"; 3169 3170 #clock-cells = <0>; 3171 clock-output-names = "mclk"; 3172 #sound-dai-cells = <1>; 3173 }; 3174 3175 lpass_wsamacro: codec@6b00000 { 3176 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3177 reg = <0 0x06b00000 0 0x1000>; 3178 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3179 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3180 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3181 <&lpass_vamacro>; 3182 clock-names = "mclk", 3183 "macro", 3184 "dcodec", 3185 "fsgen"; 3186 3187 #clock-cells = <0>; 3188 clock-output-names = "mclk"; 3189 #sound-dai-cells = <1>; 3190 }; 3191 3192 swr0: soundwire@6b10000 { 3193 compatible = "qcom,soundwire-v2.0.0"; 3194 reg = <0 0x06b10000 0 0x10000>; 3195 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3196 clocks = <&lpass_wsamacro>; 3197 clock-names = "iface"; 3198 label = "WSA"; 3199 3200 pinctrl-0 = <&wsa_swr_active>; 3201 pinctrl-names = "default"; 3202 3203 qcom,din-ports = <4>; 3204 qcom,dout-ports = <9>; 3205 3206 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3207 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3208 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3209 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3210 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3211 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3212 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3213 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3214 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3215 3216 #address-cells = <2>; 3217 #size-cells = <0>; 3218 #sound-dai-cells = <1>; 3219 status = "disabled"; 3220 }; 3221 3222 swr2: soundwire@6d30000 { 3223 compatible = "qcom,soundwire-v2.0.0"; 3224 reg = <0 0x06d30000 0 0x10000>; 3225 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3227 interrupt-names = "core", "wakeup"; 3228 clocks = <&lpass_txmacro>; 3229 clock-names = "iface"; 3230 label = "TX"; 3231 3232 pinctrl-0 = <&tx_swr_active>; 3233 pinctrl-names = "default"; 3234 3235 qcom,din-ports = <4>; 3236 qcom,dout-ports = <0>; 3237 3238 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3239 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3240 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3241 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3242 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3243 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3244 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3245 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3246 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3247 3248 #address-cells = <2>; 3249 #size-cells = <0>; 3250 #sound-dai-cells = <1>; 3251 status = "disabled"; 3252 }; 3253 3254 lpass_vamacro: codec@6d44000 { 3255 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3256 reg = <0 0x06d44000 0 0x1000>; 3257 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3258 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3259 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3260 clock-names = "mclk", 3261 "macro", 3262 "dcodec"; 3263 3264 #clock-cells = <0>; 3265 clock-output-names = "fsgen"; 3266 #sound-dai-cells = <1>; 3267 }; 3268 3269 lpass_tlmm: pinctrl@6e80000 { 3270 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 3271 reg = <0 0x06e80000 0 0x20000>; 3272 3273 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3274 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3275 clock-names = "core", "audio"; 3276 3277 gpio-controller; 3278 #gpio-cells = <2>; 3279 gpio-ranges = <&lpass_tlmm 0 0 23>; 3280 3281 tx_swr_active: tx-swr-active-state { 3282 clk-pins { 3283 pins = "gpio0"; 3284 function = "swr_tx_clk"; 3285 drive-strength = <2>; 3286 slew-rate = <1>; 3287 bias-disable; 3288 }; 3289 3290 data-pins { 3291 pins = "gpio1", "gpio2", "gpio14"; 3292 function = "swr_tx_data"; 3293 drive-strength = <2>; 3294 slew-rate = <1>; 3295 bias-bus-hold; 3296 }; 3297 }; 3298 3299 rx_swr_active: rx-swr-active-state { 3300 clk-pins { 3301 pins = "gpio3"; 3302 function = "swr_rx_clk"; 3303 drive-strength = <2>; 3304 slew-rate = <1>; 3305 bias-disable; 3306 }; 3307 3308 data-pins { 3309 pins = "gpio4", "gpio5"; 3310 function = "swr_rx_data"; 3311 drive-strength = <2>; 3312 slew-rate = <1>; 3313 bias-bus-hold; 3314 }; 3315 }; 3316 3317 dmic01_default: dmic01-default-state { 3318 clk-pins { 3319 pins = "gpio6"; 3320 function = "dmic1_clk"; 3321 drive-strength = <8>; 3322 output-high; 3323 }; 3324 3325 data-pins { 3326 pins = "gpio7"; 3327 function = "dmic1_data"; 3328 drive-strength = <8>; 3329 input-enable; 3330 }; 3331 }; 3332 3333 dmic23_default: dmic23-default-state { 3334 clk-pins { 3335 pins = "gpio8"; 3336 function = "dmic2_clk"; 3337 drive-strength = <8>; 3338 output-high; 3339 }; 3340 3341 data-pins { 3342 pins = "gpio9"; 3343 function = "dmic2_data"; 3344 drive-strength = <8>; 3345 input-enable; 3346 }; 3347 }; 3348 3349 wsa_swr_active: wsa-swr-active-state { 3350 clk-pins { 3351 pins = "gpio10"; 3352 function = "wsa_swr_clk"; 3353 drive-strength = <2>; 3354 slew-rate = <1>; 3355 bias-disable; 3356 }; 3357 3358 data-pins { 3359 pins = "gpio11"; 3360 function = "wsa_swr_data"; 3361 drive-strength = <2>; 3362 slew-rate = <1>; 3363 bias-bus-hold; 3364 }; 3365 }; 3366 3367 wsa2_swr_active: wsa2-swr-active-state { 3368 clk-pins { 3369 pins = "gpio15"; 3370 function = "wsa2_swr_clk"; 3371 drive-strength = <2>; 3372 slew-rate = <1>; 3373 bias-disable; 3374 }; 3375 3376 data-pins { 3377 pins = "gpio16"; 3378 function = "wsa2_swr_data"; 3379 drive-strength = <2>; 3380 slew-rate = <1>; 3381 bias-bus-hold; 3382 }; 3383 }; 3384 }; 3385 3386 lpass_lpiaon_noc: interconnect@7400000 { 3387 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 3388 reg = <0 0x07400000 0 0x19080>; 3389 3390 #interconnect-cells = <2>; 3391 3392 qcom,bcm-voters = <&apps_bcm_voter>; 3393 }; 3394 3395 lpass_lpicx_noc: interconnect@7430000 { 3396 compatible = "qcom,sm8650-lpass-lpicx-noc"; 3397 reg = <0 0x07430000 0 0x3a200>; 3398 3399 #interconnect-cells = <2>; 3400 3401 qcom,bcm-voters = <&apps_bcm_voter>; 3402 }; 3403 3404 lpass_ag_noc: interconnect@7e40000 { 3405 compatible = "qcom,sm8650-lpass-ag-noc"; 3406 reg = <0 0x07e40000 0 0xe080>; 3407 3408 #interconnect-cells = <2>; 3409 3410 qcom,bcm-voters = <&apps_bcm_voter>; 3411 }; 3412 3413 sdhc_2: mmc@8804000 { 3414 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 3415 reg = <0 0x08804000 0 0x1000>; 3416 3417 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3419 interrupt-names = "hc_irq", 3420 "pwr_irq"; 3421 3422 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3423 <&gcc GCC_SDCC2_APPS_CLK>, 3424 <&rpmhcc RPMH_CXO_CLK>; 3425 clock-names = "iface", 3426 "core", 3427 "xo"; 3428 3429 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3430 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3432 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 3433 interconnect-names = "sdhc-ddr", 3434 "cpu-sdhc"; 3435 3436 power-domains = <&rpmhpd RPMHPD_CX>; 3437 operating-points-v2 = <&sdhc2_opp_table>; 3438 3439 iommus = <&apps_smmu 0x540 0>; 3440 3441 bus-width = <4>; 3442 3443 /* Forbid SDR104/SDR50 - broken hw! */ 3444 sdhci-caps-mask = <0x3 0>; 3445 3446 qcom,dll-config = <0x0007642c>; 3447 qcom,ddr-config = <0x80040868>; 3448 3449 dma-coherent; 3450 3451 status = "disabled"; 3452 3453 sdhc2_opp_table: opp-table { 3454 compatible = "operating-points-v2"; 3455 3456 opp-19200000 { 3457 opp-hz = /bits/ 64 <19200000>; 3458 required-opps = <&rpmhpd_opp_min_svs>; 3459 }; 3460 3461 opp-50000000 { 3462 opp-hz = /bits/ 64 <50000000>; 3463 required-opps = <&rpmhpd_opp_low_svs>; 3464 }; 3465 3466 opp-100000000 { 3467 opp-hz = /bits/ 64 <100000000>; 3468 required-opps = <&rpmhpd_opp_svs>; 3469 }; 3470 3471 opp-202000000 { 3472 opp-hz = /bits/ 64 <202000000>; 3473 required-opps = <&rpmhpd_opp_svs_l1>; 3474 }; 3475 }; 3476 }; 3477 3478 videocc: clock-controller@aaf0000 { 3479 compatible = "qcom,sm8650-videocc"; 3480 reg = <0 0x0aaf0000 0 0x10000>; 3481 clocks = <&bi_tcxo_div2>, 3482 <&gcc GCC_VIDEO_AHB_CLK>; 3483 power-domains = <&rpmhpd RPMHPD_MMCX>; 3484 #clock-cells = <1>; 3485 #reset-cells = <1>; 3486 #power-domain-cells = <1>; 3487 }; 3488 3489 cci0: cci@ac15000 { 3490 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3491 reg = <0 0x0ac15000 0 0x1000>; 3492 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 3493 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3494 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3495 <&camcc CAM_CC_CPAS_AHB_CLK>, 3496 <&camcc CAM_CC_CCI_0_CLK>; 3497 clock-names = "camnoc_axi", 3498 "cpas_ahb", 3499 "cci"; 3500 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3501 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3502 pinctrl-names = "default", "sleep"; 3503 status = "disabled"; 3504 #address-cells = <1>; 3505 #size-cells = <0>; 3506 3507 cci0_i2c0: i2c-bus@0 { 3508 reg = <0>; 3509 clock-frequency = <1000000>; 3510 #address-cells = <1>; 3511 #size-cells = <0>; 3512 }; 3513 3514 cci0_i2c1: i2c-bus@1 { 3515 reg = <1>; 3516 clock-frequency = <1000000>; 3517 #address-cells = <1>; 3518 #size-cells = <0>; 3519 }; 3520 }; 3521 3522 cci1: cci@ac16000 { 3523 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3524 reg = <0 0x0ac16000 0 0x1000>; 3525 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 3526 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3527 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3528 <&camcc CAM_CC_CPAS_AHB_CLK>, 3529 <&camcc CAM_CC_CCI_1_CLK>; 3530 clock-names = "camnoc_axi", 3531 "cpas_ahb", 3532 "cci"; 3533 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 3534 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 3535 pinctrl-names = "default", "sleep"; 3536 status = "disabled"; 3537 #address-cells = <1>; 3538 #size-cells = <0>; 3539 3540 cci1_i2c0: i2c-bus@0 { 3541 reg = <0>; 3542 clock-frequency = <1000000>; 3543 #address-cells = <1>; 3544 #size-cells = <0>; 3545 }; 3546 3547 cci1_i2c1: i2c-bus@1 { 3548 reg = <1>; 3549 clock-frequency = <1000000>; 3550 #address-cells = <1>; 3551 #size-cells = <0>; 3552 }; 3553 }; 3554 3555 cci2: cci@ac17000 { 3556 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3557 reg = <0 0x0ac17000 0 0x1000>; 3558 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 3559 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3560 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3561 <&camcc CAM_CC_CPAS_AHB_CLK>, 3562 <&camcc CAM_CC_CCI_2_CLK>; 3563 clock-names = "camnoc_axi", 3564 "cpas_ahb", 3565 "cci"; 3566 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3567 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3568 pinctrl-names = "default", "sleep"; 3569 status = "disabled"; 3570 #address-cells = <1>; 3571 #size-cells = <0>; 3572 3573 cci2_i2c0: i2c-bus@0 { 3574 reg = <0>; 3575 clock-frequency = <1000000>; 3576 #address-cells = <1>; 3577 #size-cells = <0>; 3578 }; 3579 3580 cci2_i2c1: i2c-bus@1 { 3581 reg = <1>; 3582 clock-frequency = <1000000>; 3583 #address-cells = <1>; 3584 #size-cells = <0>; 3585 }; 3586 }; 3587 3588 camcc: clock-controller@ade0000 { 3589 compatible = "qcom,sm8650-camcc"; 3590 reg = <0 0x0ade0000 0 0x20000>; 3591 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3592 <&bi_tcxo_div2>, 3593 <&bi_tcxo_ao_div2>, 3594 <&sleep_clk>; 3595 power-domains = <&rpmhpd RPMHPD_MMCX>; 3596 #clock-cells = <1>; 3597 #reset-cells = <1>; 3598 #power-domain-cells = <1>; 3599 }; 3600 3601 mdss: display-subsystem@ae00000 { 3602 compatible = "qcom,sm8650-mdss"; 3603 reg = <0 0x0ae00000 0 0x1000>; 3604 reg-names = "mdss"; 3605 3606 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3607 3608 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3609 <&gcc GCC_DISP_HF_AXI_CLK>, 3610 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3611 3612 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3613 3614 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3616 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3617 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3618 interconnect-names = "mdp0-mem", 3619 "cpu-cfg"; 3620 3621 power-domains = <&dispcc MDSS_GDSC>; 3622 3623 iommus = <&apps_smmu 0x1c00 0x2>; 3624 3625 interrupt-controller; 3626 #interrupt-cells = <1>; 3627 3628 #address-cells = <2>; 3629 #size-cells = <2>; 3630 ranges; 3631 3632 status = "disabled"; 3633 3634 mdss_mdp: display-controller@ae01000 { 3635 compatible = "qcom,sm8650-dpu"; 3636 reg = <0 0x0ae01000 0 0x8f000>, 3637 <0 0x0aeb0000 0 0x2008>; 3638 reg-names = "mdp", 3639 "vbif"; 3640 3641 interrupts-extended = <&mdss 0>; 3642 3643 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3644 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3645 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3646 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3647 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3648 clock-names = "nrt_bus", 3649 "iface", 3650 "lut", 3651 "core", 3652 "vsync"; 3653 3654 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3655 assigned-clock-rates = <19200000>; 3656 3657 operating-points-v2 = <&mdp_opp_table>; 3658 3659 power-domains = <&rpmhpd RPMHPD_MMCX>; 3660 3661 ports { 3662 #address-cells = <1>; 3663 #size-cells = <0>; 3664 3665 port@0 { 3666 reg = <0>; 3667 3668 dpu_intf1_out: endpoint { 3669 remote-endpoint = <&mdss_dsi0_in>; 3670 }; 3671 }; 3672 3673 port@1 { 3674 reg = <1>; 3675 3676 dpu_intf2_out: endpoint { 3677 remote-endpoint = <&mdss_dsi1_in>; 3678 }; 3679 }; 3680 3681 port@2 { 3682 reg = <2>; 3683 3684 dpu_intf0_out: endpoint { 3685 remote-endpoint = <&mdss_dp0_in>; 3686 }; 3687 }; 3688 }; 3689 3690 mdp_opp_table: opp-table { 3691 compatible = "operating-points-v2"; 3692 3693 opp-200000000 { 3694 opp-hz = /bits/ 64 <200000000>; 3695 required-opps = <&rpmhpd_opp_low_svs>; 3696 }; 3697 3698 opp-325000000 { 3699 opp-hz = /bits/ 64 <325000000>; 3700 required-opps = <&rpmhpd_opp_svs>; 3701 }; 3702 3703 opp-375000000 { 3704 opp-hz = /bits/ 64 <375000000>; 3705 required-opps = <&rpmhpd_opp_svs_l1>; 3706 }; 3707 3708 opp-514000000 { 3709 opp-hz = /bits/ 64 <514000000>; 3710 required-opps = <&rpmhpd_opp_nom>; 3711 }; 3712 }; 3713 }; 3714 3715 mdss_dsi0: dsi@ae94000 { 3716 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3717 reg = <0 0x0ae94000 0 0x400>; 3718 reg-names = "dsi_ctrl"; 3719 3720 interrupts-extended = <&mdss 4>; 3721 3722 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3723 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3724 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3725 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3726 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3727 <&gcc GCC_DISP_HF_AXI_CLK>; 3728 clock-names = "byte", 3729 "byte_intf", 3730 "pixel", 3731 "core", 3732 "iface", 3733 "bus"; 3734 3735 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3736 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3737 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3738 <&mdss_dsi0_phy 1>; 3739 3740 operating-points-v2 = <&mdss_dsi_opp_table>; 3741 3742 power-domains = <&rpmhpd RPMHPD_MMCX>; 3743 3744 phys = <&mdss_dsi0_phy>; 3745 phy-names = "dsi"; 3746 3747 #address-cells = <1>; 3748 #size-cells = <0>; 3749 3750 status = "disabled"; 3751 3752 ports { 3753 #address-cells = <1>; 3754 #size-cells = <0>; 3755 3756 port@0 { 3757 reg = <0>; 3758 3759 mdss_dsi0_in: endpoint { 3760 remote-endpoint = <&dpu_intf1_out>; 3761 }; 3762 }; 3763 3764 port@1 { 3765 reg = <1>; 3766 3767 mdss_dsi0_out: endpoint { 3768 }; 3769 }; 3770 }; 3771 3772 mdss_dsi_opp_table: opp-table { 3773 compatible = "operating-points-v2"; 3774 3775 opp-187500000 { 3776 opp-hz = /bits/ 64 <187500000>; 3777 required-opps = <&rpmhpd_opp_low_svs>; 3778 }; 3779 3780 opp-300000000 { 3781 opp-hz = /bits/ 64 <300000000>; 3782 required-opps = <&rpmhpd_opp_svs>; 3783 }; 3784 3785 opp-358000000 { 3786 opp-hz = /bits/ 64 <358000000>; 3787 required-opps = <&rpmhpd_opp_svs_l1>; 3788 }; 3789 }; 3790 }; 3791 3792 mdss_dsi0_phy: phy@ae95000 { 3793 compatible = "qcom,sm8650-dsi-phy-4nm"; 3794 reg = <0 0x0ae95000 0 0x200>, 3795 <0 0x0ae95200 0 0x280>, 3796 <0 0x0ae95500 0 0x400>; 3797 reg-names = "dsi_phy", 3798 "dsi_phy_lane", 3799 "dsi_pll"; 3800 3801 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3802 <&rpmhcc RPMH_CXO_CLK>; 3803 clock-names = "iface", 3804 "ref"; 3805 3806 #clock-cells = <1>; 3807 #phy-cells = <0>; 3808 3809 status = "disabled"; 3810 }; 3811 3812 mdss_dsi1: dsi@ae96000 { 3813 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3814 reg = <0 0x0ae96000 0 0x400>; 3815 reg-names = "dsi_ctrl"; 3816 3817 interrupts-extended = <&mdss 5>; 3818 3819 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3820 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3821 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3822 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3823 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3824 <&gcc GCC_DISP_HF_AXI_CLK>; 3825 clock-names = "byte", 3826 "byte_intf", 3827 "pixel", 3828 "core", 3829 "iface", 3830 "bus"; 3831 3832 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3833 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3834 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3835 <&mdss_dsi1_phy 1>; 3836 3837 operating-points-v2 = <&mdss_dsi_opp_table>; 3838 3839 power-domains = <&rpmhpd RPMHPD_MMCX>; 3840 3841 phys = <&mdss_dsi1_phy>; 3842 phy-names = "dsi"; 3843 3844 #address-cells = <1>; 3845 #size-cells = <0>; 3846 3847 status = "disabled"; 3848 3849 ports { 3850 #address-cells = <1>; 3851 #size-cells = <0>; 3852 3853 port@0 { 3854 reg = <0>; 3855 3856 mdss_dsi1_in: endpoint { 3857 remote-endpoint = <&dpu_intf2_out>; 3858 }; 3859 }; 3860 3861 port@1 { 3862 reg = <1>; 3863 3864 mdss_dsi1_out: endpoint { 3865 }; 3866 }; 3867 }; 3868 }; 3869 3870 mdss_dsi1_phy: phy@ae97000 { 3871 compatible = "qcom,sm8650-dsi-phy-4nm"; 3872 reg = <0 0x0ae97000 0 0x200>, 3873 <0 0x0ae97200 0 0x280>, 3874 <0 0x0ae97500 0 0x400>; 3875 reg-names = "dsi_phy", 3876 "dsi_phy_lane", 3877 "dsi_pll"; 3878 3879 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3880 <&rpmhcc RPMH_CXO_CLK>; 3881 clock-names = "iface", 3882 "ref"; 3883 3884 #clock-cells = <1>; 3885 #phy-cells = <0>; 3886 3887 status = "disabled"; 3888 }; 3889 3890 mdss_dp0: displayport-controller@af54000 { 3891 compatible = "qcom,sm8650-dp"; 3892 reg = <0 0xaf54000 0 0x104>, 3893 <0 0xaf54200 0 0xc0>, 3894 <0 0xaf55000 0 0x770>, 3895 <0 0xaf56000 0 0x9c>, 3896 <0 0xaf57000 0 0x9c>; 3897 3898 interrupts-extended = <&mdss 12>; 3899 3900 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3901 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3902 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3903 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3904 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3905 clock-names = "core_iface", 3906 "core_aux", 3907 "ctrl_link", 3908 "ctrl_link_iface", 3909 "stream_pixel"; 3910 3911 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3912 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3913 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3914 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3915 3916 operating-points-v2 = <&dp_opp_table>; 3917 3918 power-domains = <&rpmhpd RPMHPD_MMCX>; 3919 3920 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3921 phy-names = "dp"; 3922 3923 #sound-dai-cells = <0>; 3924 3925 status = "disabled"; 3926 3927 dp_opp_table: opp-table { 3928 compatible = "operating-points-v2"; 3929 3930 opp-162000000 { 3931 opp-hz = /bits/ 64 <162000000>; 3932 required-opps = <&rpmhpd_opp_low_svs_d1>; 3933 }; 3934 3935 opp-270000000 { 3936 opp-hz = /bits/ 64 <270000000>; 3937 required-opps = <&rpmhpd_opp_low_svs>; 3938 }; 3939 3940 opp-540000000 { 3941 opp-hz = /bits/ 64 <540000000>; 3942 required-opps = <&rpmhpd_opp_svs_l1>; 3943 }; 3944 3945 opp-810000000 { 3946 opp-hz = /bits/ 64 <810000000>; 3947 required-opps = <&rpmhpd_opp_nom>; 3948 }; 3949 }; 3950 3951 ports { 3952 #address-cells = <1>; 3953 #size-cells = <0>; 3954 3955 port@0 { 3956 reg = <0>; 3957 3958 mdss_dp0_in: endpoint { 3959 remote-endpoint = <&dpu_intf0_out>; 3960 }; 3961 }; 3962 3963 port@1 { 3964 reg = <1>; 3965 3966 mdss_dp0_out: endpoint { 3967 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3968 }; 3969 }; 3970 }; 3971 }; 3972 }; 3973 3974 dispcc: clock-controller@af00000 { 3975 compatible = "qcom,sm8650-dispcc"; 3976 reg = <0 0x0af00000 0 0x20000>; 3977 3978 clocks = <&bi_tcxo_div2>, 3979 <&bi_tcxo_ao_div2>, 3980 <&gcc GCC_DISP_AHB_CLK>, 3981 <&sleep_clk>, 3982 <&mdss_dsi0_phy 0>, 3983 <&mdss_dsi0_phy 1>, 3984 <&mdss_dsi1_phy 0>, 3985 <&mdss_dsi1_phy 1>, 3986 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3987 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3988 <0>, /* dp1 */ 3989 <0>, 3990 <0>, /* dp2 */ 3991 <0>, 3992 <0>, /* dp3 */ 3993 <0>; 3994 3995 power-domains = <&rpmhpd RPMHPD_MMCX>; 3996 required-opps = <&rpmhpd_opp_low_svs>; 3997 3998 #clock-cells = <1>; 3999 #reset-cells = <1>; 4000 #power-domain-cells = <1>; 4001 4002 status = "disabled"; 4003 }; 4004 4005 usb_1_hsphy: phy@88e3000 { 4006 compatible = "qcom,sm8650-snps-eusb2-phy", 4007 "qcom,sm8550-snps-eusb2-phy"; 4008 reg = <0 0x088e3000 0 0x154>; 4009 4010 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4011 clock-names = "ref"; 4012 4013 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4014 4015 #phy-cells = <0>; 4016 4017 status = "disabled"; 4018 }; 4019 4020 usb_dp_qmpphy: phy@88e8000 { 4021 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 4022 reg = <0 0x088e8000 0 0x3000>; 4023 4024 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4025 <&rpmhcc RPMH_CXO_CLK>, 4026 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4027 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4028 clock-names = "aux", 4029 "ref", 4030 "com_aux", 4031 "usb3_pipe"; 4032 4033 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4034 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4035 reset-names = "phy", 4036 "common"; 4037 4038 power-domains = <&gcc USB3_PHY_GDSC>; 4039 4040 #clock-cells = <1>; 4041 #phy-cells = <1>; 4042 4043 orientation-switch; 4044 4045 status = "disabled"; 4046 4047 ports { 4048 #address-cells = <1>; 4049 #size-cells = <0>; 4050 4051 port@0 { 4052 reg = <0>; 4053 4054 usb_dp_qmpphy_out: endpoint { 4055 }; 4056 }; 4057 4058 port@1 { 4059 reg = <1>; 4060 4061 usb_dp_qmpphy_usb_ss_in: endpoint { 4062 remote-endpoint = <&usb_1_dwc3_ss>; 4063 }; 4064 }; 4065 4066 port@2 { 4067 reg = <2>; 4068 4069 usb_dp_qmpphy_dp_in: endpoint { 4070 remote-endpoint = <&mdss_dp0_out>; 4071 }; 4072 }; 4073 }; 4074 }; 4075 4076 usb_1: usb@a6f8800 { 4077 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 4078 reg = <0 0x0a6f8800 0 0x400>; 4079 4080 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4081 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4082 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 4083 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 4084 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4085 interrupt-names = "pwr_event", 4086 "hs_phy_irq", 4087 "dp_hs_phy_irq", 4088 "dm_hs_phy_irq", 4089 "ss_phy_irq"; 4090 4091 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4092 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4093 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4094 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4095 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4096 <&tcsr TCSR_USB3_CLKREF_EN>; 4097 clock-names = "cfg_noc", 4098 "core", 4099 "iface", 4100 "sleep", 4101 "mock_utmi", 4102 "xo"; 4103 4104 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4105 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4106 assigned-clock-rates = <19200000>, <200000000>; 4107 4108 resets = <&gcc GCC_USB30_PRIM_BCR>; 4109 4110 power-domains = <&gcc USB30_PRIM_GDSC>; 4111 required-opps = <&rpmhpd_opp_nom>; 4112 4113 #address-cells = <2>; 4114 #size-cells = <2>; 4115 ranges; 4116 4117 status = "disabled"; 4118 4119 usb_1_dwc3: usb@a600000 { 4120 compatible = "snps,dwc3"; 4121 reg = <0 0x0a600000 0 0xcd00>; 4122 4123 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4124 4125 iommus = <&apps_smmu 0x40 0>; 4126 4127 phys = <&usb_1_hsphy>, 4128 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 4129 phy-names = "usb2-phy", 4130 "usb3-phy"; 4131 4132 snps,hird-threshold = /bits/ 8 <0x0>; 4133 snps,usb2-gadget-lpm-disable; 4134 snps,dis_u2_susphy_quirk; 4135 snps,dis_enblslpm_quirk; 4136 snps,dis-u1-entry-quirk; 4137 snps,dis-u2-entry-quirk; 4138 snps,is-utmi-l1-suspend; 4139 snps,usb3_lpm_capable; 4140 snps,usb2-lpm-disable; 4141 snps,has-lpm-erratum; 4142 tx-fifo-resize; 4143 4144 dma-coherent; 4145 4146 ports { 4147 #address-cells = <1>; 4148 #size-cells = <0>; 4149 4150 port@0 { 4151 reg = <0>; 4152 4153 usb_1_dwc3_hs: endpoint { 4154 }; 4155 }; 4156 4157 port@1 { 4158 reg = <1>; 4159 4160 usb_1_dwc3_ss: endpoint { 4161 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4162 }; 4163 }; 4164 }; 4165 }; 4166 }; 4167 4168 pdc: interrupt-controller@b220000 { 4169 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 4170 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4171 4172 interrupt-parent = <&intc>; 4173 4174 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4175 <125 63 1>, <126 716 12>, 4176 <138 251 5>, <143 244 4>; 4177 4178 #interrupt-cells = <2>; 4179 interrupt-controller; 4180 }; 4181 4182 tsens0: thermal-sensor@c228000 { 4183 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4184 reg = <0 0x0c228000 0 0x1000>, /* TM */ 4185 <0 0x0c222000 0 0x1000>; /* SROT */ 4186 4187 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4189 interrupt-names = "uplow", 4190 "critical"; 4191 4192 #qcom,sensors = <15>; 4193 4194 #thermal-sensor-cells = <1>; 4195 }; 4196 4197 tsens1: thermal-sensor@c229000 { 4198 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4199 reg = <0 0x0c229000 0 0x1000>, /* TM */ 4200 <0 0x0c223000 0 0x1000>; /* SROT */ 4201 4202 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 4204 interrupt-names = "uplow", 4205 "critical"; 4206 4207 #qcom,sensors = <16>; 4208 4209 #thermal-sensor-cells = <1>; 4210 }; 4211 4212 tsens2: thermal-sensor@c22a000 { 4213 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4214 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 4215 <0 0x0c224000 0 0x1000>; /* SROT */ 4216 4217 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 4219 interrupt-names = "uplow", 4220 "critical"; 4221 4222 #qcom,sensors = <13>; 4223 4224 #thermal-sensor-cells = <1>; 4225 }; 4226 4227 aoss_qmp: power-management@c300000 { 4228 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 4229 reg = <0 0x0c300000 0 0x400>; 4230 4231 interrupt-parent = <&ipcc>; 4232 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4233 IRQ_TYPE_EDGE_RISING>; 4234 4235 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4236 4237 #clock-cells = <0>; 4238 }; 4239 4240 sram@c3f0000 { 4241 compatible = "qcom,rpmh-stats"; 4242 reg = <0 0x0c3f0000 0 0x400>; 4243 }; 4244 4245 spmi_bus: spmi@c400000 { 4246 compatible = "qcom,spmi-pmic-arb"; 4247 reg = <0 0x0c400000 0 0x3000>, 4248 <0 0x0c500000 0 0x400000>, 4249 <0 0x0c440000 0 0x80000>, 4250 <0 0x0c4c0000 0 0x20000>, 4251 <0 0x0c42d000 0 0x4000>; 4252 reg-names = "core", 4253 "chnls", 4254 "obsrvr", 4255 "intr", 4256 "cnfg"; 4257 4258 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4259 interrupt-names = "periph_irq"; 4260 4261 qcom,ee = <0>; 4262 qcom,channel = <0>; 4263 qcom,bus-id = <0>; 4264 4265 interrupt-controller; 4266 #interrupt-cells = <4>; 4267 4268 #address-cells = <2>; 4269 #size-cells = <0>; 4270 }; 4271 4272 tlmm: pinctrl@f100000 { 4273 compatible = "qcom,sm8650-tlmm"; 4274 reg = <0 0x0f100000 0 0x300000>; 4275 4276 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4277 4278 gpio-controller; 4279 #gpio-cells = <2>; 4280 4281 interrupt-controller; 4282 #interrupt-cells = <2>; 4283 4284 gpio-ranges = <&tlmm 0 0 211>; 4285 4286 wakeup-parent = <&pdc>; 4287 4288 cci0_0_default: cci0-0-default-state { 4289 sda-pins { 4290 pins = "gpio113"; 4291 function = "cci_i2c_sda"; 4292 drive-strength = <2>; 4293 bias-pull-up = <2200>; 4294 }; 4295 4296 scl-pins { 4297 pins = "gpio114"; 4298 function = "cci_i2c_scl"; 4299 drive-strength = <2>; 4300 bias-pull-up = <2200>; 4301 }; 4302 }; 4303 4304 cci0_0_sleep: cci0-0-sleep-state { 4305 sda-pins { 4306 pins = "gpio113"; 4307 function = "cci_i2c_sda"; 4308 drive-strength = <2>; 4309 bias-pull-down; 4310 }; 4311 4312 scl-pins { 4313 pins = "gpio114"; 4314 function = "cci_i2c_scl"; 4315 drive-strength = <2>; 4316 bias-pull-down; 4317 }; 4318 }; 4319 4320 cci0_1_default: cci0-1-default-state { 4321 sda-pins { 4322 pins = "gpio115"; 4323 function = "cci_i2c_sda"; 4324 drive-strength = <2>; 4325 bias-pull-up = <2200>; 4326 }; 4327 4328 scl-pins { 4329 pins = "gpio116"; 4330 function = "cci_i2c_scl"; 4331 drive-strength = <2>; 4332 bias-pull-up = <2200>; 4333 }; 4334 }; 4335 4336 cci0_1_sleep: cci0-1-sleep-state { 4337 sda-pins { 4338 pins = "gpio115"; 4339 function = "cci_i2c_sda"; 4340 drive-strength = <2>; 4341 bias-pull-down; 4342 }; 4343 4344 scl-pins { 4345 pins = "gpio116"; 4346 function = "cci_i2c_scl"; 4347 drive-strength = <2>; 4348 bias-pull-down; 4349 }; 4350 }; 4351 4352 cci1_0_default: cci1-0-default-state { 4353 sda-pins { 4354 pins = "gpio117"; 4355 function = "cci_i2c_sda"; 4356 drive-strength = <2>; 4357 bias-pull-up = <2200>; 4358 }; 4359 4360 scl-pins { 4361 pins = "gpio118"; 4362 function = "cci_i2c_scl"; 4363 drive-strength = <2>; 4364 bias-pull-up = <2200>; 4365 }; 4366 }; 4367 4368 cci1_0_sleep: cci1-0-sleep-state { 4369 sda-pins { 4370 pins = "gpio117"; 4371 function = "cci_i2c_sda"; 4372 drive-strength = <2>; 4373 bias-pull-down; 4374 }; 4375 4376 scl-pins { 4377 pins = "gpio118"; 4378 function = "cci_i2c_scl"; 4379 drive-strength = <2>; 4380 bias-pull-down; 4381 }; 4382 }; 4383 4384 cci1_1_default: cci1-1-default-state { 4385 sda-pins { 4386 pins = "gpio12"; 4387 function = "cci_i2c_sda"; 4388 drive-strength = <2>; 4389 bias-pull-up = <2200>; 4390 }; 4391 4392 scl-pins { 4393 pins = "gpio13"; 4394 function = "cci_i2c_scl"; 4395 drive-strength = <2>; 4396 bias-pull-up = <2200>; 4397 }; 4398 }; 4399 4400 cci1_1_sleep: cci1-1-sleep-state { 4401 sda-pins { 4402 pins = "gpio12"; 4403 function = "cci_i2c_sda"; 4404 drive-strength = <2>; 4405 bias-pull-down; 4406 }; 4407 4408 scl-pins { 4409 pins = "gpio13"; 4410 function = "cci_i2c_scl"; 4411 drive-strength = <2>; 4412 bias-pull-down; 4413 }; 4414 }; 4415 4416 cci2_0_default: cci2-0-default-state { 4417 sda-pins { 4418 pins = "gpio112"; 4419 function = "cci_i2c_sda"; 4420 drive-strength = <2>; 4421 bias-pull-up = <2200>; 4422 }; 4423 4424 scl-pins { 4425 pins = "gpio153"; 4426 function = "cci_i2c_scl"; 4427 drive-strength = <2>; 4428 bias-pull-up = <2200>; 4429 }; 4430 }; 4431 4432 cci2_0_sleep: cci2-0-sleep-state { 4433 sda-pins { 4434 pins = "gpio112"; 4435 function = "cci_i2c_sda"; 4436 drive-strength = <2>; 4437 bias-pull-down; 4438 }; 4439 4440 scl-pins { 4441 pins = "gpio153"; 4442 function = "cci_i2c_scl"; 4443 drive-strength = <2>; 4444 bias-pull-down; 4445 }; 4446 }; 4447 4448 cci2_1_default: cci2-1-default-state { 4449 sda-pins { 4450 pins = "gpio119"; 4451 function = "cci_i2c_sda"; 4452 drive-strength = <2>; 4453 bias-pull-up = <2200>; 4454 }; 4455 4456 scl-pins { 4457 pins = "gpio120"; 4458 function = "cci_i2c_scl"; 4459 drive-strength = <2>; 4460 bias-pull-up = <2200>; 4461 }; 4462 }; 4463 4464 cci2_1_sleep: cci2-1-sleep-state { 4465 sda-pins { 4466 pins = "gpio119"; 4467 function = "cci_i2c_sda"; 4468 drive-strength = <2>; 4469 bias-pull-down; 4470 }; 4471 4472 scl-pins { 4473 pins = "gpio120"; 4474 function = "cci_i2c_scl"; 4475 drive-strength = <2>; 4476 bias-pull-down; 4477 }; 4478 }; 4479 4480 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4481 /* SDA, SCL */ 4482 pins = "gpio64", "gpio65"; 4483 function = "i2chub0_se0"; 4484 drive-strength = <2>; 4485 bias-pull-up; 4486 }; 4487 4488 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4489 /* SDA, SCL */ 4490 pins = "gpio66", "gpio67"; 4491 function = "i2chub0_se1"; 4492 drive-strength = <2>; 4493 bias-pull-up; 4494 }; 4495 4496 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4497 /* SDA, SCL */ 4498 pins = "gpio68", "gpio69"; 4499 function = "i2chub0_se2"; 4500 drive-strength = <2>; 4501 bias-pull-up; 4502 }; 4503 4504 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4505 /* SDA, SCL */ 4506 pins = "gpio70", "gpio71"; 4507 function = "i2chub0_se3"; 4508 drive-strength = <2>; 4509 bias-pull-up; 4510 }; 4511 4512 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4513 /* SDA, SCL */ 4514 pins = "gpio72", "gpio73"; 4515 function = "i2chub0_se4"; 4516 drive-strength = <2>; 4517 bias-pull-up; 4518 }; 4519 4520 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4521 /* SDA, SCL */ 4522 pins = "gpio74", "gpio75"; 4523 function = "i2chub0_se5"; 4524 drive-strength = <2>; 4525 bias-pull-up; 4526 }; 4527 4528 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4529 /* SDA, SCL */ 4530 pins = "gpio76", "gpio77"; 4531 function = "i2chub0_se6"; 4532 drive-strength = <2>; 4533 bias-pull-up; 4534 }; 4535 4536 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4537 /* SDA, SCL */ 4538 pins = "gpio78", "gpio79"; 4539 function = "i2chub0_se7"; 4540 drive-strength = <2>; 4541 bias-pull-up; 4542 }; 4543 4544 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4545 /* SDA, SCL */ 4546 pins = "gpio206", "gpio207"; 4547 function = "i2chub0_se8"; 4548 drive-strength = <2>; 4549 bias-pull-up; 4550 }; 4551 4552 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4553 /* SDA, SCL */ 4554 pins = "gpio80", "gpio81"; 4555 function = "i2chub0_se9"; 4556 drive-strength = <2>; 4557 bias-pull-up; 4558 }; 4559 4560 pcie0_default_state: pcie0-default-state { 4561 perst-pins { 4562 pins = "gpio94"; 4563 function = "gpio"; 4564 drive-strength = <2>; 4565 bias-pull-down; 4566 }; 4567 4568 clkreq-pins { 4569 pins = "gpio95"; 4570 function = "pcie0_clk_req_n"; 4571 drive-strength = <2>; 4572 bias-pull-up; 4573 }; 4574 4575 wake-pins { 4576 pins = "gpio96"; 4577 function = "gpio"; 4578 drive-strength = <2>; 4579 bias-pull-up; 4580 }; 4581 }; 4582 4583 pcie1_default_state: pcie1-default-state { 4584 perst-pins { 4585 pins = "gpio97"; 4586 function = "gpio"; 4587 drive-strength = <2>; 4588 bias-pull-down; 4589 }; 4590 4591 clkreq-pins { 4592 pins = "gpio98"; 4593 function = "pcie1_clk_req_n"; 4594 drive-strength = <2>; 4595 bias-pull-up; 4596 }; 4597 4598 wake-pins { 4599 pins = "gpio99"; 4600 function = "gpio"; 4601 drive-strength = <2>; 4602 bias-pull-up; 4603 }; 4604 }; 4605 4606 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4607 /* SDA, SCL */ 4608 pins = "gpio32", "gpio33"; 4609 function = "qup1_se0"; 4610 drive-strength = <2>; 4611 bias-pull-up; 4612 }; 4613 4614 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4615 /* SDA, SCL */ 4616 pins = "gpio36", "gpio37"; 4617 function = "qup1_se1"; 4618 drive-strength = <2>; 4619 bias-pull-up; 4620 }; 4621 4622 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4623 /* SDA, SCL */ 4624 pins = "gpio40", "gpio41"; 4625 function = "qup1_se2"; 4626 drive-strength = <2>; 4627 bias-pull-up; 4628 }; 4629 4630 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4631 /* SDA, SCL */ 4632 pins = "gpio44", "gpio45"; 4633 function = "qup1_se3"; 4634 drive-strength = <2>; 4635 bias-pull-up; 4636 }; 4637 4638 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4639 /* SDA, SCL */ 4640 pins = "gpio48", "gpio49"; 4641 function = "qup1_se4"; 4642 drive-strength = <2>; 4643 bias-pull-up; 4644 }; 4645 4646 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4647 /* SDA, SCL */ 4648 pins = "gpio52", "gpio53"; 4649 function = "qup1_se5"; 4650 drive-strength = <2>; 4651 bias-pull-up; 4652 }; 4653 4654 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4655 /* SDA, SCL */ 4656 pins = "gpio56", "gpio57"; 4657 function = "qup1_se6"; 4658 drive-strength = <2>; 4659 bias-pull-up; 4660 }; 4661 4662 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4663 /* SDA, SCL */ 4664 pins = "gpio60", "gpio61"; 4665 function = "qup1_se7"; 4666 drive-strength = <2>; 4667 bias-pull-up; 4668 }; 4669 4670 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4671 /* SDA, SCL */ 4672 pins = "gpio0", "gpio1"; 4673 function = "qup2_se0"; 4674 drive-strength = <2>; 4675 bias-pull-up; 4676 }; 4677 4678 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4679 /* SDA, SCL */ 4680 pins = "gpio4", "gpio5"; 4681 function = "qup2_se1"; 4682 drive-strength = <2>; 4683 bias-pull-up; 4684 }; 4685 4686 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4687 /* SDA, SCL */ 4688 pins = "gpio8", "gpio9"; 4689 function = "qup2_se2"; 4690 drive-strength = <2>; 4691 bias-pull-up; 4692 }; 4693 4694 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4695 /* SDA, SCL */ 4696 pins = "gpio12", "gpio13"; 4697 function = "qup2_se3"; 4698 drive-strength = <2>; 4699 bias-pull-up; 4700 }; 4701 4702 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4703 /* SDA, SCL */ 4704 pins = "gpio16", "gpio17"; 4705 function = "qup2_se4"; 4706 drive-strength = <2>; 4707 bias-pull-up; 4708 }; 4709 4710 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4711 /* SDA, SCL */ 4712 pins = "gpio20", "gpio21"; 4713 function = "qup2_se5"; 4714 drive-strength = <2>; 4715 bias-pull-up; 4716 }; 4717 4718 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4719 /* SDA, SCL */ 4720 pins = "gpio24", "gpio25"; 4721 function = "qup2_se6"; 4722 drive-strength = <2>; 4723 bias-pull-up; 4724 }; 4725 4726 qup_spi0_cs: qup-spi0-cs-state { 4727 pins = "gpio35"; 4728 function = "qup1_se0"; 4729 drive-strength = <6>; 4730 bias-disable; 4731 }; 4732 4733 qup_spi0_data_clk: qup-spi0-data-clk-state { 4734 /* MISO, MOSI, CLK */ 4735 pins = "gpio32", "gpio33", "gpio34"; 4736 function = "qup1_se0"; 4737 drive-strength = <6>; 4738 bias-disable; 4739 }; 4740 4741 qup_spi1_cs: qup-spi1-cs-state { 4742 pins = "gpio39"; 4743 function = "qup1_se1"; 4744 drive-strength = <6>; 4745 bias-disable; 4746 }; 4747 4748 qup_spi1_data_clk: qup-spi1-data-clk-state { 4749 /* MISO, MOSI, CLK */ 4750 pins = "gpio36", "gpio37", "gpio38"; 4751 function = "qup1_se1"; 4752 drive-strength = <6>; 4753 bias-disable; 4754 }; 4755 4756 qup_spi2_cs: qup-spi2-cs-state { 4757 pins = "gpio43"; 4758 function = "qup1_se2"; 4759 drive-strength = <6>; 4760 bias-disable; 4761 }; 4762 4763 qup_spi2_data_clk: qup-spi2-data-clk-state { 4764 /* MISO, MOSI, CLK */ 4765 pins = "gpio40", "gpio41", "gpio42"; 4766 function = "qup1_se2"; 4767 drive-strength = <6>; 4768 bias-disable; 4769 }; 4770 4771 qup_spi3_cs: qup-spi3-cs-state { 4772 pins = "gpio47"; 4773 function = "qup1_se3"; 4774 drive-strength = <6>; 4775 bias-disable; 4776 }; 4777 4778 qup_spi3_data_clk: qup-spi3-data-clk-state { 4779 /* MISO, MOSI, CLK */ 4780 pins = "gpio44", "gpio45", "gpio46"; 4781 function = "qup1_se3"; 4782 drive-strength = <6>; 4783 bias-disable; 4784 }; 4785 4786 qup_spi4_cs: qup-spi4-cs-state { 4787 pins = "gpio51"; 4788 function = "qup1_se4"; 4789 drive-strength = <6>; 4790 bias-disable; 4791 }; 4792 4793 qup_spi4_data_clk: qup-spi4-data-clk-state { 4794 /* MISO, MOSI, CLK */ 4795 pins = "gpio48", "gpio49", "gpio50"; 4796 function = "qup1_se4"; 4797 drive-strength = <6>; 4798 bias-disable; 4799 }; 4800 4801 qup_spi5_cs: qup-spi5-cs-state { 4802 pins = "gpio55"; 4803 function = "qup1_se5"; 4804 drive-strength = <6>; 4805 bias-disable; 4806 }; 4807 4808 qup_spi5_data_clk: qup-spi5-data-clk-state { 4809 /* MISO, MOSI, CLK */ 4810 pins = "gpio52", "gpio53", "gpio54"; 4811 function = "qup1_se5"; 4812 drive-strength = <6>; 4813 bias-disable; 4814 }; 4815 4816 qup_spi6_cs: qup-spi6-cs-state { 4817 pins = "gpio59"; 4818 function = "qup1_se6"; 4819 drive-strength = <6>; 4820 bias-disable; 4821 }; 4822 4823 qup_spi6_data_clk: qup-spi6-data-clk-state { 4824 /* MISO, MOSI, CLK */ 4825 pins = "gpio56", "gpio57", "gpio58"; 4826 function = "qup1_se6"; 4827 drive-strength = <6>; 4828 bias-disable; 4829 }; 4830 4831 qup_spi7_cs: qup-spi7-cs-state { 4832 pins = "gpio63"; 4833 function = "qup1_se7"; 4834 drive-strength = <6>; 4835 bias-disable; 4836 }; 4837 4838 qup_spi7_data_clk: qup-spi7-data-clk-state { 4839 /* MISO, MOSI, CLK */ 4840 pins = "gpio60", "gpio61", "gpio62"; 4841 function = "qup1_se7"; 4842 drive-strength = <6>; 4843 bias-disable; 4844 }; 4845 4846 qup_spi8_cs: qup-spi8-cs-state { 4847 pins = "gpio3"; 4848 function = "qup2_se0"; 4849 drive-strength = <6>; 4850 bias-disable; 4851 }; 4852 4853 qup_spi8_data_clk: qup-spi8-data-clk-state { 4854 /* MISO, MOSI, CLK */ 4855 pins = "gpio0", "gpio1", "gpio2"; 4856 function = "qup2_se0"; 4857 drive-strength = <6>; 4858 bias-disable; 4859 }; 4860 4861 qup_spi9_cs: qup-spi9-cs-state { 4862 pins = "gpio7"; 4863 function = "qup2_se1"; 4864 drive-strength = <6>; 4865 bias-disable; 4866 }; 4867 4868 qup_spi9_data_clk: qup-spi9-data-clk-state { 4869 /* MISO, MOSI, CLK */ 4870 pins = "gpio4", "gpio5", "gpio6"; 4871 function = "qup2_se1"; 4872 drive-strength = <6>; 4873 bias-disable; 4874 }; 4875 4876 qup_spi10_cs: qup-spi10-cs-state { 4877 pins = "gpio11"; 4878 function = "qup2_se2"; 4879 drive-strength = <6>; 4880 bias-disable; 4881 }; 4882 4883 qup_spi10_data_clk: qup-spi10-data-clk-state { 4884 /* MISO, MOSI, CLK */ 4885 pins = "gpio8", "gpio9", "gpio10"; 4886 function = "qup2_se2"; 4887 drive-strength = <6>; 4888 bias-disable; 4889 }; 4890 4891 qup_spi11_cs: qup-spi11-cs-state { 4892 pins = "gpio15"; 4893 function = "qup2_se3"; 4894 drive-strength = <6>; 4895 bias-disable; 4896 }; 4897 4898 qup_spi11_data_clk: qup-spi11-data-clk-state { 4899 /* MISO, MOSI, CLK */ 4900 pins = "gpio12", "gpio13", "gpio14"; 4901 function = "qup2_se3"; 4902 drive-strength = <6>; 4903 bias-disable; 4904 }; 4905 4906 qup_spi12_cs: qup-spi12-cs-state { 4907 pins = "gpio19"; 4908 function = "qup2_se4"; 4909 drive-strength = <6>; 4910 bias-disable; 4911 }; 4912 4913 qup_spi12_data_clk: qup-spi12-data-clk-state { 4914 /* MISO, MOSI, CLK */ 4915 pins = "gpio16", "gpio17", "gpio18"; 4916 function = "qup2_se4"; 4917 drive-strength = <6>; 4918 bias-disable; 4919 }; 4920 4921 qup_spi13_cs: qup-spi13-cs-state { 4922 pins = "gpio23"; 4923 function = "qup2_se5"; 4924 drive-strength = <6>; 4925 bias-disable; 4926 }; 4927 4928 qup_spi13_data_clk: qup-spi13-data-clk-state { 4929 /* MISO, MOSI, CLK */ 4930 pins = "gpio20", "gpio21", "gpio22"; 4931 function = "qup2_se5"; 4932 drive-strength = <6>; 4933 bias-disable; 4934 }; 4935 4936 qup_spi14_cs: qup-spi14-cs-state { 4937 pins = "gpio27"; 4938 function = "qup2_se6"; 4939 drive-strength = <6>; 4940 bias-disable; 4941 }; 4942 4943 qup_spi14_data_clk: qup-spi14-data-clk-state { 4944 /* MISO, MOSI, CLK */ 4945 pins = "gpio24", "gpio25", "gpio26"; 4946 function = "qup2_se6"; 4947 drive-strength = <6>; 4948 bias-disable; 4949 }; 4950 4951 qup_uart14_default: qup-uart14-default-state { 4952 /* TX, RX */ 4953 pins = "gpio26", "gpio27"; 4954 function = "qup2_se6"; 4955 drive-strength = <2>; 4956 bias-pull-up; 4957 }; 4958 4959 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4960 /* CTS, RTS */ 4961 pins = "gpio24", "gpio25"; 4962 function = "qup2_se6"; 4963 drive-strength = <2>; 4964 bias-pull-down; 4965 }; 4966 4967 qup_uart15_default: qup-uart15-default-state { 4968 /* TX, RX */ 4969 pins = "gpio30", "gpio31"; 4970 function = "qup2_se7"; 4971 drive-strength = <2>; 4972 bias-disable; 4973 }; 4974 4975 sdc2_sleep: sdc2-sleep-state { 4976 clk-pins { 4977 pins = "sdc2_clk"; 4978 drive-strength = <2>; 4979 bias-disable; 4980 }; 4981 4982 cmd-pins { 4983 pins = "sdc2_cmd"; 4984 drive-strength = <2>; 4985 bias-pull-up; 4986 }; 4987 4988 data-pins { 4989 pins = "sdc2_data"; 4990 drive-strength = <2>; 4991 bias-pull-up; 4992 }; 4993 }; 4994 4995 sdc2_default: sdc2-default-state { 4996 clk-pins { 4997 pins = "sdc2_clk"; 4998 drive-strength = <16>; 4999 bias-disable; 5000 }; 5001 5002 cmd-pins { 5003 pins = "sdc2_cmd"; 5004 drive-strength = <10>; 5005 bias-pull-up; 5006 }; 5007 5008 data-pins { 5009 pins = "sdc2_data"; 5010 drive-strength = <10>; 5011 bias-pull-up; 5012 }; 5013 }; 5014 }; 5015 5016 apps_smmu: iommu@15000000 { 5017 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5018 reg = <0 0x15000000 0 0x100000>; 5019 5020 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 5117 5118 #iommu-cells = <2>; 5119 #global-interrupts = <1>; 5120 5121 dma-coherent; 5122 }; 5123 5124 intc: interrupt-controller@17100000 { 5125 compatible = "arm,gic-v3"; 5126 reg = <0 0x17100000 0 0x10000>, /* GICD */ 5127 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 5128 5129 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5130 5131 #interrupt-cells = <3>; 5132 interrupt-controller; 5133 5134 #redistributor-regions = <1>; 5135 redistributor-stride = <0 0x40000>; 5136 5137 #address-cells = <2>; 5138 #size-cells = <2>; 5139 ranges; 5140 5141 gic_its: msi-controller@17140000 { 5142 compatible = "arm,gic-v3-its"; 5143 reg = <0 0x17140000 0 0x20000>; 5144 5145 msi-controller; 5146 #msi-cells = <1>; 5147 }; 5148 }; 5149 5150 timer@17420000 { 5151 compatible = "arm,armv7-timer-mem"; 5152 reg = <0 0x17420000 0 0x1000>; 5153 5154 ranges = <0 0 0 0x20000000>; 5155 #address-cells = <1>; 5156 #size-cells = <1>; 5157 5158 frame@17421000 { 5159 reg = <0x17421000 0x1000>, 5160 <0x17422000 0x1000>; 5161 5162 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5164 5165 frame-number = <0>; 5166 }; 5167 5168 frame@17423000 { 5169 reg = <0x17423000 0x1000>; 5170 5171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5172 5173 frame-number = <1>; 5174 5175 status = "disabled"; 5176 }; 5177 5178 frame@17425000 { 5179 reg = <0x17425000 0x1000>; 5180 5181 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5182 5183 frame-number = <2>; 5184 5185 status = "disabled"; 5186 }; 5187 5188 frame@17427000 { 5189 reg = <0x17427000 0x1000>; 5190 5191 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5192 5193 frame-number = <3>; 5194 5195 status = "disabled"; 5196 }; 5197 5198 frame@17429000 { 5199 reg = <0x17429000 0x1000>; 5200 5201 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5202 5203 frame-number = <4>; 5204 5205 status = "disabled"; 5206 }; 5207 5208 frame@1742b000 { 5209 reg = <0x1742b000 0x1000>; 5210 5211 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5212 5213 frame-number = <5>; 5214 5215 status = "disabled"; 5216 }; 5217 5218 frame@1742d000 { 5219 reg = <0x1742d000 0x1000>; 5220 5221 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5222 5223 frame-number = <6>; 5224 5225 status = "disabled"; 5226 }; 5227 }; 5228 5229 apps_rsc: rsc@17a00000 { 5230 compatible = "qcom,rpmh-rsc"; 5231 reg = <0 0x17a00000 0 0x10000>, 5232 <0 0x17a10000 0 0x10000>, 5233 <0 0x17a20000 0 0x10000>, 5234 <0 0x17a30000 0 0x10000>; 5235 reg-names = "drv-0", 5236 "drv-1", 5237 "drv-2"; 5238 5239 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5240 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5241 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5242 5243 power-domains = <&cluster_pd>; 5244 5245 qcom,tcs-offset = <0xd00>; 5246 qcom,drv-id = <2>; 5247 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5248 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5249 5250 label = "apps_rsc"; 5251 5252 apps_bcm_voter: bcm-voter { 5253 compatible = "qcom,bcm-voter"; 5254 }; 5255 5256 rpmhcc: clock-controller { 5257 compatible = "qcom,sm8650-rpmh-clk"; 5258 5259 clocks = <&xo_board>; 5260 clock-names = "xo"; 5261 5262 #clock-cells = <1>; 5263 }; 5264 5265 rpmhpd: power-controller { 5266 compatible = "qcom,sm8650-rpmhpd"; 5267 5268 operating-points-v2 = <&rpmhpd_opp_table>; 5269 5270 #power-domain-cells = <1>; 5271 5272 rpmhpd_opp_table: opp-table { 5273 compatible = "operating-points-v2"; 5274 5275 rpmhpd_opp_ret: opp-16 { 5276 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5277 }; 5278 5279 rpmhpd_opp_min_svs: opp-48 { 5280 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5281 }; 5282 5283 rpmhpd_opp_low_svs_d2: opp-52 { 5284 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5285 }; 5286 5287 rpmhpd_opp_low_svs_d1: opp-56 { 5288 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5289 }; 5290 5291 rpmhpd_opp_low_svs_d0: opp-60 { 5292 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5293 }; 5294 5295 rpmhpd_opp_low_svs: opp-64 { 5296 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5297 }; 5298 5299 rpmhpd_opp_low_svs_l1: opp-80 { 5300 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5301 }; 5302 5303 rpmhpd_opp_svs: opp-128 { 5304 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5305 }; 5306 5307 rpmhpd_opp_svs_l0: opp-144 { 5308 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5309 }; 5310 5311 rpmhpd_opp_svs_l1: opp-192 { 5312 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5313 }; 5314 5315 rpmhpd_opp_nom: opp-256 { 5316 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5317 }; 5318 5319 rpmhpd_opp_nom_l1: opp-320 { 5320 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5321 }; 5322 5323 rpmhpd_opp_nom_l2: opp-336 { 5324 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5325 }; 5326 5327 rpmhpd_opp_turbo: opp-384 { 5328 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5329 }; 5330 5331 rpmhpd_opp_turbo_l1: opp-416 { 5332 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5333 }; 5334 }; 5335 }; 5336 }; 5337 5338 cpufreq_hw: cpufreq@17d91000 { 5339 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 5340 reg = <0 0x17d91000 0 0x1000>, 5341 <0 0x17d92000 0 0x1000>, 5342 <0 0x17d93000 0 0x1000>, 5343 <0 0x17d94000 0 0x1000>; 5344 reg-names = "freq-domain0", 5345 "freq-domain1", 5346 "freq-domain2", 5347 "freq-domain3"; 5348 5349 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 5352 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 5353 interrupt-names = "dcvsh-irq-0", 5354 "dcvsh-irq-1", 5355 "dcvsh-irq-2", 5356 "dcvsh-irq-3"; 5357 5358 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5359 clock-names = "xo", "alternate"; 5360 5361 #freq-domain-cells = <1>; 5362 #clock-cells = <1>; 5363 }; 5364 5365 pmu@24091000 { 5366 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5367 reg = <0 0x24091000 0 0x1000>; 5368 5369 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5370 5371 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5372 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5373 5374 operating-points-v2 = <&llcc_bwmon_opp_table>; 5375 5376 llcc_bwmon_opp_table: opp-table { 5377 compatible = "operating-points-v2"; 5378 5379 opp-0 { 5380 opp-peak-kBps = <2086000>; 5381 }; 5382 5383 opp-1 { 5384 opp-peak-kBps = <2929000>; 5385 }; 5386 5387 opp-2 { 5388 opp-peak-kBps = <5931000>; 5389 }; 5390 5391 opp-3 { 5392 opp-peak-kBps = <6515000>; 5393 }; 5394 5395 opp-4 { 5396 opp-peak-kBps = <7980000>; 5397 }; 5398 5399 opp-5 { 5400 opp-peak-kBps = <10437000>; 5401 }; 5402 5403 opp-6 { 5404 opp-peak-kBps = <12157000>; 5405 }; 5406 5407 opp-7 { 5408 opp-peak-kBps = <14060000>; 5409 }; 5410 5411 opp-8 { 5412 opp-peak-kBps = <16113000>; 5413 }; 5414 }; 5415 }; 5416 5417 pmu@240b7400 { 5418 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 5419 reg = <0 0x240b7400 0 0x600>; 5420 5421 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5422 5423 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5424 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5425 5426 operating-points-v2 = <&cpu_bwmon_opp_table>; 5427 5428 cpu_bwmon_opp_table: opp-table { 5429 compatible = "operating-points-v2"; 5430 5431 opp-0 { 5432 opp-peak-kBps = <4577000>; 5433 }; 5434 5435 opp-1 { 5436 opp-peak-kBps = <7110000>; 5437 }; 5438 5439 opp-2 { 5440 opp-peak-kBps = <9155000>; 5441 }; 5442 5443 opp-3 { 5444 opp-peak-kBps = <12298000>; 5445 }; 5446 5447 opp-4 { 5448 opp-peak-kBps = <14236000>; 5449 }; 5450 5451 opp-5 { 5452 opp-peak-kBps = <16265000>; 5453 }; 5454 }; 5455 }; 5456 5457 gem_noc: interconnect@24100000 { 5458 compatible = "qcom,sm8650-gem-noc"; 5459 reg = <0 0x24100000 0 0xc5080>; 5460 5461 qcom,bcm-voters = <&apps_bcm_voter>; 5462 5463 #interconnect-cells = <2>; 5464 }; 5465 5466 system-cache-controller@25000000 { 5467 compatible = "qcom,sm8650-llcc"; 5468 reg = <0 0x25000000 0 0x200000>, 5469 <0 0x25400000 0 0x200000>, 5470 <0 0x25200000 0 0x200000>, 5471 <0 0x25600000 0 0x200000>, 5472 <0 0x25800000 0 0x200000>, 5473 <0 0x25a00000 0 0x200000>; 5474 reg-names = "llcc0_base", 5475 "llcc1_base", 5476 "llcc2_base", 5477 "llcc3_base", 5478 "llcc_broadcast_base", 5479 "llcc_broadcast_and_base"; 5480 5481 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5482 }; 5483 5484 nsp_noc: interconnect@320c0000 { 5485 compatible = "qcom,sm8650-nsp-noc"; 5486 reg = <0 0x320c0000 0 0xf080>; 5487 5488 qcom,bcm-voters = <&apps_bcm_voter>; 5489 5490 #interconnect-cells = <2>; 5491 }; 5492 5493 remoteproc_cdsp: remoteproc@32300000 { 5494 compatible = "qcom,sm8650-cdsp-pas"; 5495 reg = <0x0 0x32300000 0x0 0x10000>; 5496 5497 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5498 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5499 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5500 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5501 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5502 interrupt-names = "wdog", 5503 "fatal", 5504 "ready", 5505 "handover", 5506 "stop-ack"; 5507 5508 clocks = <&rpmhcc RPMH_CXO_CLK>; 5509 clock-names = "xo"; 5510 5511 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5512 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5513 5514 power-domains = <&rpmhpd RPMHPD_CX>, 5515 <&rpmhpd RPMHPD_MXC>, 5516 <&rpmhpd RPMHPD_NSP>; 5517 power-domain-names = "cx", 5518 "mxc", 5519 "nsp"; 5520 5521 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 5522 5523 qcom,qmp = <&aoss_qmp>; 5524 5525 qcom,smem-states = <&smp2p_cdsp_out 0>; 5526 qcom,smem-state-names = "stop"; 5527 5528 status = "disabled"; 5529 5530 glink-edge { 5531 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5532 IPCC_MPROC_SIGNAL_GLINK_QMP 5533 IRQ_TYPE_EDGE_RISING>; 5534 5535 mboxes = <&ipcc IPCC_CLIENT_CDSP 5536 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5537 5538 qcom,remote-pid = <5>; 5539 5540 label = "cdsp"; 5541 5542 fastrpc { 5543 compatible = "qcom,fastrpc"; 5544 5545 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5546 5547 label = "cdsp"; 5548 5549 qcom,non-secure-domain; 5550 5551 #address-cells = <1>; 5552 #size-cells = <0>; 5553 5554 compute-cb@1 { 5555 compatible = "qcom,fastrpc-compute-cb"; 5556 reg = <1>; 5557 5558 iommus = <&apps_smmu 0x1961 0x0>, 5559 <&apps_smmu 0x0c01 0x20>, 5560 <&apps_smmu 0x19c1 0x0>; 5561 dma-coherent; 5562 }; 5563 5564 compute-cb@2 { 5565 compatible = "qcom,fastrpc-compute-cb"; 5566 reg = <2>; 5567 5568 iommus = <&apps_smmu 0x1962 0x0>, 5569 <&apps_smmu 0x0c02 0x20>, 5570 <&apps_smmu 0x19c2 0x0>; 5571 dma-coherent; 5572 }; 5573 5574 compute-cb@3 { 5575 compatible = "qcom,fastrpc-compute-cb"; 5576 reg = <3>; 5577 5578 iommus = <&apps_smmu 0x1963 0x0>, 5579 <&apps_smmu 0x0c03 0x20>, 5580 <&apps_smmu 0x19c3 0x0>; 5581 dma-coherent; 5582 }; 5583 5584 compute-cb@4 { 5585 compatible = "qcom,fastrpc-compute-cb"; 5586 reg = <4>; 5587 5588 iommus = <&apps_smmu 0x1964 0x0>, 5589 <&apps_smmu 0x0c04 0x20>, 5590 <&apps_smmu 0x19c4 0x0>; 5591 dma-coherent; 5592 }; 5593 5594 compute-cb@5 { 5595 compatible = "qcom,fastrpc-compute-cb"; 5596 reg = <5>; 5597 5598 iommus = <&apps_smmu 0x1965 0x0>, 5599 <&apps_smmu 0x0c05 0x20>, 5600 <&apps_smmu 0x19c5 0x0>; 5601 dma-coherent; 5602 }; 5603 5604 compute-cb@6 { 5605 compatible = "qcom,fastrpc-compute-cb"; 5606 reg = <6>; 5607 5608 iommus = <&apps_smmu 0x1966 0x0>, 5609 <&apps_smmu 0x0c06 0x20>, 5610 <&apps_smmu 0x19c6 0x0>; 5611 dma-coherent; 5612 }; 5613 5614 compute-cb@7 { 5615 compatible = "qcom,fastrpc-compute-cb"; 5616 reg = <7>; 5617 5618 iommus = <&apps_smmu 0x1967 0x0>, 5619 <&apps_smmu 0x0c07 0x20>, 5620 <&apps_smmu 0x19c7 0x0>; 5621 dma-coherent; 5622 }; 5623 5624 compute-cb@8 { 5625 compatible = "qcom,fastrpc-compute-cb"; 5626 reg = <8>; 5627 5628 iommus = <&apps_smmu 0x1968 0x0>, 5629 <&apps_smmu 0x0c08 0x20>, 5630 <&apps_smmu 0x19c8 0x0>; 5631 dma-coherent; 5632 }; 5633 5634 /* note: secure cb9 in downstream */ 5635 5636 compute-cb@12 { 5637 compatible = "qcom,fastrpc-compute-cb"; 5638 reg = <12>; 5639 5640 iommus = <&apps_smmu 0x196c 0x0>, 5641 <&apps_smmu 0x0c0c 0x20>, 5642 <&apps_smmu 0x19cc 0x0>; 5643 dma-coherent; 5644 }; 5645 5646 compute-cb@13 { 5647 compatible = "qcom,fastrpc-compute-cb"; 5648 reg = <13>; 5649 5650 iommus = <&apps_smmu 0x196d 0x0>, 5651 <&apps_smmu 0x0c0d 0x20>, 5652 <&apps_smmu 0x19cd 0x0>; 5653 dma-coherent; 5654 }; 5655 5656 compute-cb@14 { 5657 compatible = "qcom,fastrpc-compute-cb"; 5658 reg = <14>; 5659 5660 iommus = <&apps_smmu 0x196e 0x0>, 5661 <&apps_smmu 0x0c0e 0x20>, 5662 <&apps_smmu 0x19ce 0x0>; 5663 dma-coherent; 5664 }; 5665 }; 5666 }; 5667 }; 5668 }; 5669 5670 thermal-zones { 5671 aoss0-thermal { 5672 thermal-sensors = <&tsens0 0>; 5673 5674 trips { 5675 trip-point0 { 5676 temperature = <90000>; 5677 hysteresis = <2000>; 5678 type = "hot"; 5679 }; 5680 5681 aoss0-critical { 5682 temperature = <110000>; 5683 hysteresis = <0>; 5684 type = "critical"; 5685 }; 5686 }; 5687 }; 5688 5689 cpuss0-thermal { 5690 thermal-sensors = <&tsens0 1>; 5691 5692 trips { 5693 trip-point0 { 5694 temperature = <90000>; 5695 hysteresis = <2000>; 5696 type = "hot"; 5697 }; 5698 5699 cpuss0-critical { 5700 temperature = <110000>; 5701 hysteresis = <0>; 5702 type = "critical"; 5703 }; 5704 }; 5705 }; 5706 5707 cpuss1-thermal { 5708 thermal-sensors = <&tsens0 2>; 5709 5710 trips { 5711 trip-point0 { 5712 temperature = <90000>; 5713 hysteresis = <2000>; 5714 type = "hot"; 5715 }; 5716 5717 cpuss1-critical { 5718 temperature = <110000>; 5719 hysteresis = <0>; 5720 type = "critical"; 5721 }; 5722 }; 5723 }; 5724 5725 cpuss2-thermal { 5726 thermal-sensors = <&tsens0 3>; 5727 5728 trips { 5729 trip-point0 { 5730 temperature = <90000>; 5731 hysteresis = <2000>; 5732 type = "hot"; 5733 }; 5734 5735 cpuss2-critical { 5736 temperature = <110000>; 5737 hysteresis = <0>; 5738 type = "critical"; 5739 }; 5740 }; 5741 }; 5742 5743 cpuss3-thermal { 5744 thermal-sensors = <&tsens0 4>; 5745 5746 trips { 5747 trip-point0 { 5748 temperature = <90000>; 5749 hysteresis = <2000>; 5750 type = "hot"; 5751 }; 5752 5753 cpuss3-critical { 5754 temperature = <110000>; 5755 hysteresis = <0>; 5756 type = "critical"; 5757 }; 5758 }; 5759 }; 5760 5761 cpu2-top-thermal { 5762 thermal-sensors = <&tsens0 5>; 5763 5764 trips { 5765 trip-point0 { 5766 temperature = <90000>; 5767 hysteresis = <2000>; 5768 type = "passive"; 5769 }; 5770 5771 trip-point1 { 5772 temperature = <95000>; 5773 hysteresis = <2000>; 5774 type = "passive"; 5775 }; 5776 5777 cpu2-critical { 5778 temperature = <110000>; 5779 hysteresis = <1000>; 5780 type = "critical"; 5781 }; 5782 }; 5783 }; 5784 5785 cpu2-bottom-thermal { 5786 thermal-sensors = <&tsens0 6>; 5787 5788 trips { 5789 trip-point0 { 5790 temperature = <90000>; 5791 hysteresis = <2000>; 5792 type = "passive"; 5793 }; 5794 5795 trip-point1 { 5796 temperature = <95000>; 5797 hysteresis = <2000>; 5798 type = "passive"; 5799 }; 5800 5801 cpu2-critical { 5802 temperature = <110000>; 5803 hysteresis = <1000>; 5804 type = "critical"; 5805 }; 5806 }; 5807 }; 5808 5809 cpu3-top-thermal { 5810 thermal-sensors = <&tsens0 7>; 5811 5812 trips { 5813 trip-point0 { 5814 temperature = <90000>; 5815 hysteresis = <2000>; 5816 type = "passive"; 5817 }; 5818 5819 trip-point1 { 5820 temperature = <95000>; 5821 hysteresis = <2000>; 5822 type = "passive"; 5823 }; 5824 5825 cpu3-critical { 5826 temperature = <110000>; 5827 hysteresis = <1000>; 5828 type = "critical"; 5829 }; 5830 }; 5831 }; 5832 5833 cpu3-bottom-thermal { 5834 thermal-sensors = <&tsens0 8>; 5835 5836 trips { 5837 trip-point0 { 5838 temperature = <90000>; 5839 hysteresis = <2000>; 5840 type = "passive"; 5841 }; 5842 5843 trip-point1 { 5844 temperature = <95000>; 5845 hysteresis = <2000>; 5846 type = "passive"; 5847 }; 5848 5849 cpu3-critical { 5850 temperature = <110000>; 5851 hysteresis = <1000>; 5852 type = "critical"; 5853 }; 5854 }; 5855 }; 5856 5857 cpu4-top-thermal { 5858 thermal-sensors = <&tsens0 9>; 5859 5860 trips { 5861 trip-point0 { 5862 temperature = <90000>; 5863 hysteresis = <2000>; 5864 type = "passive"; 5865 }; 5866 5867 trip-point1 { 5868 temperature = <95000>; 5869 hysteresis = <2000>; 5870 type = "passive"; 5871 }; 5872 5873 cpu4-critical { 5874 temperature = <110000>; 5875 hysteresis = <1000>; 5876 type = "critical"; 5877 }; 5878 }; 5879 }; 5880 5881 cpu4-bottom-thermal { 5882 thermal-sensors = <&tsens0 10>; 5883 5884 trips { 5885 trip-point0 { 5886 temperature = <90000>; 5887 hysteresis = <2000>; 5888 type = "passive"; 5889 }; 5890 5891 trip-point1 { 5892 temperature = <95000>; 5893 hysteresis = <2000>; 5894 type = "passive"; 5895 }; 5896 5897 cpu4-critical { 5898 temperature = <110000>; 5899 hysteresis = <1000>; 5900 type = "critical"; 5901 }; 5902 }; 5903 }; 5904 5905 cpu5-top-thermal { 5906 thermal-sensors = <&tsens0 11>; 5907 5908 trips { 5909 trip-point0 { 5910 temperature = <90000>; 5911 hysteresis = <2000>; 5912 type = "passive"; 5913 }; 5914 5915 trip-point1 { 5916 temperature = <95000>; 5917 hysteresis = <2000>; 5918 type = "passive"; 5919 }; 5920 5921 cpu5-critical { 5922 temperature = <110000>; 5923 hysteresis = <1000>; 5924 type = "critical"; 5925 }; 5926 }; 5927 }; 5928 5929 cpu5-bottom-thermal { 5930 thermal-sensors = <&tsens0 12>; 5931 5932 trips { 5933 trip-point0 { 5934 temperature = <90000>; 5935 hysteresis = <2000>; 5936 type = "passive"; 5937 }; 5938 5939 trip-point1 { 5940 temperature = <95000>; 5941 hysteresis = <2000>; 5942 type = "passive"; 5943 }; 5944 5945 cpu5-critical { 5946 temperature = <110000>; 5947 hysteresis = <1000>; 5948 type = "critical"; 5949 }; 5950 }; 5951 }; 5952 5953 cpu6-top-thermal { 5954 thermal-sensors = <&tsens0 13>; 5955 5956 trips { 5957 trip-point0 { 5958 temperature = <90000>; 5959 hysteresis = <2000>; 5960 type = "passive"; 5961 }; 5962 5963 trip-point1 { 5964 temperature = <95000>; 5965 hysteresis = <2000>; 5966 type = "passive"; 5967 }; 5968 5969 cpu6-critical { 5970 temperature = <110000>; 5971 hysteresis = <1000>; 5972 type = "critical"; 5973 }; 5974 }; 5975 }; 5976 5977 cpu6-bottom-thermal { 5978 thermal-sensors = <&tsens0 14>; 5979 5980 trips { 5981 trip-point0 { 5982 temperature = <90000>; 5983 hysteresis = <2000>; 5984 type = "passive"; 5985 }; 5986 5987 trip-point1 { 5988 temperature = <95000>; 5989 hysteresis = <2000>; 5990 type = "passive"; 5991 }; 5992 5993 cpu6-critical { 5994 temperature = <110000>; 5995 hysteresis = <1000>; 5996 type = "critical"; 5997 }; 5998 }; 5999 }; 6000 6001 aoss1-thermal { 6002 thermal-sensors = <&tsens1 0>; 6003 6004 trips { 6005 trip-point0 { 6006 temperature = <90000>; 6007 hysteresis = <2000>; 6008 type = "hot"; 6009 }; 6010 6011 aoss1-critical { 6012 temperature = <110000>; 6013 hysteresis = <0>; 6014 type = "critical"; 6015 }; 6016 }; 6017 }; 6018 6019 cpu7-top-thermal { 6020 thermal-sensors = <&tsens1 1>; 6021 6022 trips { 6023 trip-point0 { 6024 temperature = <90000>; 6025 hysteresis = <2000>; 6026 type = "passive"; 6027 }; 6028 6029 trip-point1 { 6030 temperature = <95000>; 6031 hysteresis = <2000>; 6032 type = "passive"; 6033 }; 6034 6035 cpu7-critical { 6036 temperature = <110000>; 6037 hysteresis = <1000>; 6038 type = "critical"; 6039 }; 6040 }; 6041 }; 6042 6043 cpu7-middle-thermal { 6044 thermal-sensors = <&tsens1 2>; 6045 6046 trips { 6047 trip-point0 { 6048 temperature = <90000>; 6049 hysteresis = <2000>; 6050 type = "passive"; 6051 }; 6052 6053 trip-point1 { 6054 temperature = <95000>; 6055 hysteresis = <2000>; 6056 type = "passive"; 6057 }; 6058 6059 cpu7-critical { 6060 temperature = <110000>; 6061 hysteresis = <1000>; 6062 type = "critical"; 6063 }; 6064 }; 6065 }; 6066 6067 cpu7-bottom-thermal { 6068 thermal-sensors = <&tsens1 3>; 6069 6070 trips { 6071 trip-point0 { 6072 temperature = <90000>; 6073 hysteresis = <2000>; 6074 type = "passive"; 6075 }; 6076 6077 trip-point1 { 6078 temperature = <95000>; 6079 hysteresis = <2000>; 6080 type = "passive"; 6081 }; 6082 6083 cpu7-critical { 6084 temperature = <110000>; 6085 hysteresis = <1000>; 6086 type = "critical"; 6087 }; 6088 }; 6089 }; 6090 6091 cpu0-thermal { 6092 thermal-sensors = <&tsens1 4>; 6093 6094 trips { 6095 trip-point0 { 6096 temperature = <90000>; 6097 hysteresis = <2000>; 6098 type = "passive"; 6099 }; 6100 6101 trip-point1 { 6102 temperature = <95000>; 6103 hysteresis = <2000>; 6104 type = "passive"; 6105 }; 6106 6107 cpu0-critical { 6108 temperature = <110000>; 6109 hysteresis = <1000>; 6110 type = "critical"; 6111 }; 6112 }; 6113 }; 6114 6115 cpu1-thermal { 6116 thermal-sensors = <&tsens1 5>; 6117 6118 trips { 6119 trip-point0 { 6120 temperature = <90000>; 6121 hysteresis = <2000>; 6122 type = "passive"; 6123 }; 6124 6125 trip-point1 { 6126 temperature = <95000>; 6127 hysteresis = <2000>; 6128 type = "passive"; 6129 }; 6130 6131 cpu1-critical { 6132 temperature = <110000>; 6133 hysteresis = <1000>; 6134 type = "critical"; 6135 }; 6136 }; 6137 }; 6138 6139 nsphvx0-thermal { 6140 polling-delay-passive = <10>; 6141 6142 thermal-sensors = <&tsens2 6>; 6143 6144 trips { 6145 trip-point0 { 6146 temperature = <90000>; 6147 hysteresis = <2000>; 6148 type = "hot"; 6149 }; 6150 6151 nsphvx1-critical { 6152 temperature = <110000>; 6153 hysteresis = <0>; 6154 type = "critical"; 6155 }; 6156 }; 6157 }; 6158 6159 nsphvx1-thermal { 6160 polling-delay-passive = <10>; 6161 6162 thermal-sensors = <&tsens2 7>; 6163 6164 trips { 6165 trip-point0 { 6166 temperature = <90000>; 6167 hysteresis = <2000>; 6168 type = "hot"; 6169 }; 6170 6171 nsphvx1-critical { 6172 temperature = <110000>; 6173 hysteresis = <0>; 6174 type = "critical"; 6175 }; 6176 }; 6177 }; 6178 6179 nsphmx0-thermal { 6180 polling-delay-passive = <10>; 6181 6182 thermal-sensors = <&tsens2 8>; 6183 6184 trips { 6185 trip-point0 { 6186 temperature = <90000>; 6187 hysteresis = <2000>; 6188 type = "hot"; 6189 }; 6190 6191 nsphmx0-critical { 6192 temperature = <110000>; 6193 hysteresis = <0>; 6194 type = "critical"; 6195 }; 6196 }; 6197 }; 6198 6199 nsphmx1-thermal { 6200 polling-delay-passive = <10>; 6201 6202 thermal-sensors = <&tsens2 9>; 6203 6204 trips { 6205 trip-point0 { 6206 temperature = <90000>; 6207 hysteresis = <2000>; 6208 type = "hot"; 6209 }; 6210 6211 nsphmx1-critical { 6212 temperature = <110000>; 6213 hysteresis = <0>; 6214 type = "critical"; 6215 }; 6216 }; 6217 }; 6218 6219 nsphmx2-thermal { 6220 polling-delay-passive = <10>; 6221 6222 thermal-sensors = <&tsens2 10>; 6223 6224 trips { 6225 trip-point0 { 6226 temperature = <90000>; 6227 hysteresis = <2000>; 6228 type = "hot"; 6229 }; 6230 6231 nsphmx2-critical { 6232 temperature = <110000>; 6233 hysteresis = <0>; 6234 type = "critical"; 6235 }; 6236 }; 6237 }; 6238 6239 nsphmx3-thermal { 6240 polling-delay-passive = <10>; 6241 6242 thermal-sensors = <&tsens2 11>; 6243 6244 trips { 6245 trip-point0 { 6246 temperature = <90000>; 6247 hysteresis = <2000>; 6248 type = "hot"; 6249 }; 6250 6251 nsphmx3-critical { 6252 temperature = <110000>; 6253 hysteresis = <0>; 6254 type = "critical"; 6255 }; 6256 }; 6257 }; 6258 6259 video-thermal { 6260 polling-delay-passive = <10>; 6261 6262 thermal-sensors = <&tsens1 12>; 6263 6264 trips { 6265 trip-point0 { 6266 temperature = <90000>; 6267 hysteresis = <2000>; 6268 type = "hot"; 6269 }; 6270 6271 video-critical { 6272 temperature = <110000>; 6273 hysteresis = <0>; 6274 type = "critical"; 6275 }; 6276 }; 6277 }; 6278 6279 ddr-thermal { 6280 polling-delay-passive = <10>; 6281 6282 thermal-sensors = <&tsens1 13>; 6283 6284 trips { 6285 trip-point0 { 6286 temperature = <90000>; 6287 hysteresis = <2000>; 6288 type = "hot"; 6289 }; 6290 6291 ddr-critical { 6292 temperature = <110000>; 6293 hysteresis = <0>; 6294 type = "critical"; 6295 }; 6296 }; 6297 }; 6298 6299 camera0-thermal { 6300 thermal-sensors = <&tsens1 14>; 6301 6302 trips { 6303 trip-point0 { 6304 temperature = <90000>; 6305 hysteresis = <2000>; 6306 type = "hot"; 6307 }; 6308 6309 camera0-critical { 6310 temperature = <110000>; 6311 hysteresis = <0>; 6312 type = "critical"; 6313 }; 6314 }; 6315 }; 6316 6317 camera1-thermal { 6318 thermal-sensors = <&tsens1 15>; 6319 6320 trips { 6321 trip-point0 { 6322 temperature = <90000>; 6323 hysteresis = <2000>; 6324 type = "hot"; 6325 }; 6326 6327 camera1-critical { 6328 temperature = <110000>; 6329 hysteresis = <0>; 6330 type = "critical"; 6331 }; 6332 }; 6333 }; 6334 6335 aoss2-thermal { 6336 thermal-sensors = <&tsens2 0>; 6337 6338 trips { 6339 trip-point0 { 6340 temperature = <90000>; 6341 hysteresis = <2000>; 6342 type = "hot"; 6343 }; 6344 6345 aoss2-critical { 6346 temperature = <110000>; 6347 hysteresis = <0>; 6348 type = "critical"; 6349 }; 6350 }; 6351 }; 6352 6353 gpuss0-thermal { 6354 polling-delay-passive = <10>; 6355 6356 thermal-sensors = <&tsens2 1>; 6357 6358 cooling-maps { 6359 map0 { 6360 trip = <&gpu0_alert0>; 6361 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6362 }; 6363 }; 6364 6365 trips { 6366 gpu0_alert0: trip-point0 { 6367 temperature = <95000>; 6368 hysteresis = <1000>; 6369 type = "passive"; 6370 }; 6371 6372 trip-point1 { 6373 temperature = <110000>; 6374 hysteresis = <1000>; 6375 type = "hot"; 6376 }; 6377 6378 trip-point2 { 6379 temperature = <115000>; 6380 hysteresis = <0>; 6381 type = "critical"; 6382 }; 6383 }; 6384 }; 6385 6386 gpuss1-thermal { 6387 polling-delay-passive = <10>; 6388 6389 thermal-sensors = <&tsens2 2>; 6390 6391 cooling-maps { 6392 map0 { 6393 trip = <&gpu1_alert0>; 6394 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6395 }; 6396 }; 6397 6398 trips { 6399 gpu1_alert0: trip-point0 { 6400 temperature = <95000>; 6401 hysteresis = <1000>; 6402 type = "passive"; 6403 }; 6404 6405 trip-point1 { 6406 temperature = <110000>; 6407 hysteresis = <1000>; 6408 type = "hot"; 6409 }; 6410 6411 trip-point2 { 6412 temperature = <115000>; 6413 hysteresis = <0>; 6414 type = "critical"; 6415 }; 6416 }; 6417 }; 6418 6419 gpuss2-thermal { 6420 polling-delay-passive = <10>; 6421 6422 thermal-sensors = <&tsens2 3>; 6423 6424 cooling-maps { 6425 map0 { 6426 trip = <&gpu2_alert0>; 6427 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6428 }; 6429 }; 6430 6431 trips { 6432 gpu2_alert0: trip-point0 { 6433 temperature = <95000>; 6434 hysteresis = <1000>; 6435 type = "passive"; 6436 }; 6437 6438 trip-point1 { 6439 temperature = <110000>; 6440 hysteresis = <1000>; 6441 type = "hot"; 6442 }; 6443 6444 trip-point2 { 6445 temperature = <115000>; 6446 hysteresis = <0>; 6447 type = "critical"; 6448 }; 6449 }; 6450 }; 6451 6452 gpuss3-thermal { 6453 polling-delay-passive = <10>; 6454 6455 thermal-sensors = <&tsens2 4>; 6456 6457 cooling-maps { 6458 map0 { 6459 trip = <&gpu3_alert0>; 6460 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6461 }; 6462 }; 6463 6464 trips { 6465 gpu3_alert0: trip-point0 { 6466 temperature = <95000>; 6467 hysteresis = <1000>; 6468 type = "passive"; 6469 }; 6470 6471 trip-point1 { 6472 temperature = <110000>; 6473 hysteresis = <1000>; 6474 type = "hot"; 6475 }; 6476 6477 trip-point2 { 6478 temperature = <115000>; 6479 hysteresis = <0>; 6480 type = "critical"; 6481 }; 6482 }; 6483 }; 6484 6485 gpuss4-thermal { 6486 polling-delay-passive = <10>; 6487 6488 thermal-sensors = <&tsens2 5>; 6489 6490 cooling-maps { 6491 map0 { 6492 trip = <&gpu4_alert0>; 6493 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6494 }; 6495 }; 6496 6497 trips { 6498 gpu4_alert0: trip-point0 { 6499 temperature = <95000>; 6500 hysteresis = <1000>; 6501 type = "passive"; 6502 }; 6503 6504 trip-point1 { 6505 temperature = <110000>; 6506 hysteresis = <1000>; 6507 type = "hot"; 6508 }; 6509 6510 trip-point2 { 6511 temperature = <115000>; 6512 hysteresis = <0>; 6513 type = "critical"; 6514 }; 6515 }; 6516 }; 6517 6518 gpuss5-thermal { 6519 polling-delay-passive = <10>; 6520 6521 thermal-sensors = <&tsens2 6>; 6522 6523 cooling-maps { 6524 map0 { 6525 trip = <&gpu5_alert0>; 6526 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6527 }; 6528 }; 6529 6530 trips { 6531 gpu5_alert0: trip-point0 { 6532 temperature = <95000>; 6533 hysteresis = <1000>; 6534 type = "passive"; 6535 }; 6536 6537 trip-point1 { 6538 temperature = <110000>; 6539 hysteresis = <1000>; 6540 type = "hot"; 6541 }; 6542 6543 trip-point2 { 6544 temperature = <115000>; 6545 hysteresis = <0>; 6546 type = "critical"; 6547 }; 6548 }; 6549 }; 6550 6551 gpuss6-thermal { 6552 polling-delay-passive = <10>; 6553 6554 thermal-sensors = <&tsens2 7>; 6555 6556 cooling-maps { 6557 map0 { 6558 trip = <&gpu6_alert0>; 6559 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6560 }; 6561 }; 6562 6563 trips { 6564 gpu6_alert0: trip-point0 { 6565 temperature = <95000>; 6566 hysteresis = <1000>; 6567 type = "passive"; 6568 }; 6569 6570 trip-point1 { 6571 temperature = <110000>; 6572 hysteresis = <1000>; 6573 type = "hot"; 6574 }; 6575 6576 trip-point2 { 6577 temperature = <115000>; 6578 hysteresis = <0>; 6579 type = "critical"; 6580 }; 6581 }; 6582 }; 6583 6584 gpuss7-thermal { 6585 polling-delay-passive = <10>; 6586 6587 thermal-sensors = <&tsens2 8>; 6588 6589 cooling-maps { 6590 map0 { 6591 trip = <&gpu7_alert0>; 6592 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6593 }; 6594 }; 6595 6596 trips { 6597 gpu7_alert0: trip-point0 { 6598 temperature = <95000>; 6599 hysteresis = <1000>; 6600 type = "passive"; 6601 }; 6602 6603 trip-point1 { 6604 temperature = <110000>; 6605 hysteresis = <1000>; 6606 type = "hot"; 6607 }; 6608 6609 trip-point2 { 6610 temperature = <115000>; 6611 hysteresis = <0>; 6612 type = "critical"; 6613 }; 6614 }; 6615 }; 6616 6617 modem0-thermal { 6618 thermal-sensors = <&tsens2 9>; 6619 6620 trips { 6621 trip-point0 { 6622 temperature = <90000>; 6623 hysteresis = <2000>; 6624 type = "hot"; 6625 }; 6626 6627 modem0-critical { 6628 temperature = <110000>; 6629 hysteresis = <0>; 6630 type = "critical"; 6631 }; 6632 }; 6633 }; 6634 6635 modem1-thermal { 6636 thermal-sensors = <&tsens2 10>; 6637 6638 trips { 6639 trip-point0 { 6640 temperature = <90000>; 6641 hysteresis = <2000>; 6642 type = "hot"; 6643 }; 6644 6645 modem1-critical { 6646 temperature = <110000>; 6647 hysteresis = <0>; 6648 type = "critical"; 6649 }; 6650 }; 6651 }; 6652 6653 modem2-thermal { 6654 thermal-sensors = <&tsens2 11>; 6655 6656 trips { 6657 trip-point0 { 6658 temperature = <90000>; 6659 hysteresis = <2000>; 6660 type = "hot"; 6661 }; 6662 6663 modem2-critical { 6664 temperature = <110000>; 6665 hysteresis = <0>; 6666 type = "critical"; 6667 }; 6668 }; 6669 }; 6670 6671 modem3-thermal { 6672 thermal-sensors = <&tsens2 12>; 6673 6674 trips { 6675 trip-point0 { 6676 temperature = <90000>; 6677 hysteresis = <2000>; 6678 type = "hot"; 6679 }; 6680 6681 modem3-critical { 6682 temperature = <110000>; 6683 hysteresis = <0>; 6684 type = "critical"; 6685 }; 6686 }; 6687 }; 6688 }; 6689 6690 timer { 6691 compatible = "arm,armv8-timer"; 6692 6693 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6694 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6695 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6696 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6697 }; 6698}; 6699