1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver
4 //
5 // Copyright(c) 2023 Realtek Semiconductor Corp.
6 //
7 //
8
9 #include <linux/bitops.h>
10 #include <sound/core.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <sound/initval.h>
14 #include <sound/jack.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <sound/pcm.h>
19 #include <linux/pm_runtime.h>
20 #include <sound/pcm_params.h>
21 #include <linux/soundwire/sdw_registers.h>
22 #include <linux/slab.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/tlv.h>
25
26 #include "rt722-sdca.h"
27
rt722_sdca_index_write(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int value)28 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
29 unsigned int nid, unsigned int reg, unsigned int value)
30 {
31 struct regmap *regmap = rt722->mbq_regmap;
32 unsigned int addr = (nid << 20) | reg;
33 int ret;
34
35 ret = regmap_write(regmap, addr, value);
36 if (ret < 0)
37 dev_err(&rt722->slave->dev,
38 "%s: Failed to set private value: %06x <= %04x ret=%d\n",
39 __func__, addr, value, ret);
40
41 return ret;
42 }
43
rt722_sdca_index_read(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int * value)44 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
45 unsigned int nid, unsigned int reg, unsigned int *value)
46 {
47 int ret;
48 struct regmap *regmap = rt722->mbq_regmap;
49 unsigned int addr = (nid << 20) | reg;
50
51 ret = regmap_read(regmap, addr, value);
52 if (ret < 0)
53 dev_err(&rt722->slave->dev,
54 "%s: Failed to get private value: %06x => %04x ret=%d\n",
55 __func__, addr, *value, ret);
56
57 return ret;
58 }
59
rt722_sdca_index_update_bits(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int mask,unsigned int val)60 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722,
61 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
62 {
63 unsigned int tmp;
64 int ret;
65
66 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp);
67 if (ret < 0)
68 return ret;
69
70 set_mask_bits(&tmp, mask, val);
71 return rt722_sdca_index_write(rt722, nid, reg, tmp);
72 }
73
rt722_sdca_btn_type(unsigned char * buffer)74 static int rt722_sdca_btn_type(unsigned char *buffer)
75 {
76 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) ||
77 (*(buffer + 1) == 0x10))
78 return SND_JACK_BTN_2;
79 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) ||
80 (*(buffer + 1) == 0x20))
81 return SND_JACK_BTN_3;
82 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) ||
83 (*(buffer + 1) == 0x40))
84 return SND_JACK_BTN_0;
85 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) ||
86 (*(buffer + 1) == 0x80))
87 return SND_JACK_BTN_1;
88
89 return 0;
90 }
91
rt722_sdca_button_detect(struct rt722_sdca_priv * rt722)92 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722)
93 {
94 unsigned int btn_type = 0, offset, idx, val, owner;
95 int ret;
96 unsigned char buf[3];
97
98 /* get current UMP message owner */
99 ret = regmap_read(rt722->regmap,
100 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
101 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner);
102 if (ret < 0)
103 return 0;
104
105 /* if owner is device then there is no button event from device */
106 if (owner == 1)
107 return 0;
108
109 /* read UMP message offset */
110 ret = regmap_read(rt722->regmap,
111 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
112 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
113 if (ret < 0)
114 goto _end_btn_det_;
115
116 for (idx = 0; idx < sizeof(buf); idx++) {
117 ret = regmap_read(rt722->regmap,
118 RT722_BUF_ADDR_HID1 + offset + idx, &val);
119 if (ret < 0)
120 goto _end_btn_det_;
121 buf[idx] = val & 0xff;
122 }
123
124 if (buf[0] == 0x11)
125 btn_type = rt722_sdca_btn_type(&buf[1]);
126
127 _end_btn_det_:
128 /* Host is owner, so set back to device */
129 if (owner == 0)
130 /* set owner to device */
131 regmap_write(rt722->regmap,
132 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
133 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01);
134
135 return btn_type;
136 }
137
rt722_sdca_headset_detect(struct rt722_sdca_priv * rt722)138 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722)
139 {
140 unsigned int det_mode;
141 int ret;
142
143 /* get detected_mode */
144 ret = regmap_read(rt722->regmap,
145 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
146 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
147 if (ret < 0)
148 goto io_error;
149
150 switch (det_mode) {
151 case 0x00:
152 rt722->jack_type = 0;
153 break;
154 case 0x03:
155 rt722->jack_type = SND_JACK_HEADPHONE;
156 break;
157 case 0x05:
158 rt722->jack_type = SND_JACK_HEADSET;
159 break;
160 }
161
162 /* write selected_mode */
163 if (det_mode) {
164 ret = regmap_write(rt722->regmap,
165 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
166 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode);
167 if (ret < 0)
168 goto io_error;
169 }
170
171 dev_dbg(&rt722->slave->dev,
172 "%s, detected_mode=0x%x\n", __func__, det_mode);
173
174 return 0;
175
176 io_error:
177 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
178 return ret;
179 }
180
rt722_sdca_jack_detect_handler(struct work_struct * work)181 static void rt722_sdca_jack_detect_handler(struct work_struct *work)
182 {
183 struct rt722_sdca_priv *rt722 =
184 container_of(work, struct rt722_sdca_priv, jack_detect_work.work);
185 int btn_type = 0, ret;
186
187 if (!rt722->hs_jack)
188 return;
189
190 if (!rt722->component->card || !rt722->component->card->instantiated)
191 return;
192
193 /* SDW_SCP_SDCA_INT_SDCA_6 is used for jack detection */
194 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_6) {
195 ret = rt722_sdca_headset_detect(rt722);
196 if (ret < 0)
197 return;
198 }
199
200 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
201 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
202 btn_type = rt722_sdca_button_detect(rt722);
203
204 if (rt722->jack_type == 0)
205 btn_type = 0;
206
207 dev_dbg(&rt722->slave->dev,
208 "in %s, jack_type=%d\n", __func__, rt722->jack_type);
209 dev_dbg(&rt722->slave->dev,
210 "in %s, btn_type=0x%x\n", __func__, btn_type);
211 dev_dbg(&rt722->slave->dev,
212 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
213 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
214
215 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
216 SND_JACK_HEADSET |
217 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
218 SND_JACK_BTN_2 | SND_JACK_BTN_3);
219
220 if (btn_type) {
221 /* button released */
222 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
223 SND_JACK_HEADSET |
224 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
225 SND_JACK_BTN_2 | SND_JACK_BTN_3);
226
227 mod_delayed_work(system_power_efficient_wq,
228 &rt722->jack_btn_check_work, msecs_to_jiffies(200));
229 }
230 }
231
rt722_sdca_btn_check_handler(struct work_struct * work)232 static void rt722_sdca_btn_check_handler(struct work_struct *work)
233 {
234 struct rt722_sdca_priv *rt722 =
235 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work);
236 int btn_type = 0, ret, idx;
237 unsigned int det_mode, offset, val;
238 unsigned char buf[3];
239
240 ret = regmap_read(rt722->regmap,
241 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
242 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
243 if (ret < 0)
244 goto io_error;
245
246 /* pin attached */
247 if (det_mode) {
248 /* read UMP message offset */
249 ret = regmap_read(rt722->regmap,
250 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
251 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
252 if (ret < 0)
253 goto io_error;
254
255 for (idx = 0; idx < sizeof(buf); idx++) {
256 ret = regmap_read(rt722->regmap,
257 RT722_BUF_ADDR_HID1 + offset + idx, &val);
258 if (ret < 0)
259 goto io_error;
260 buf[idx] = val & 0xff;
261 }
262
263 if (buf[0] == 0x11)
264 btn_type = rt722_sdca_btn_type(&buf[1]);
265 } else
266 rt722->jack_type = 0;
267
268 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
269 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
270 SND_JACK_HEADSET |
271 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
272 SND_JACK_BTN_2 | SND_JACK_BTN_3);
273
274 if (btn_type) {
275 /* button released */
276 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
277 SND_JACK_HEADSET |
278 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
279 SND_JACK_BTN_2 | SND_JACK_BTN_3);
280
281 mod_delayed_work(system_power_efficient_wq,
282 &rt722->jack_btn_check_work, msecs_to_jiffies(200));
283 }
284
285 return;
286
287 io_error:
288 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
289 }
290
rt722_sdca_jack_init(struct rt722_sdca_priv * rt722)291 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722)
292 {
293 mutex_lock(&rt722->calibrate_mutex);
294 if (rt722->hs_jack) {
295 /* set SCP_SDCA_IntMask1[0]=1 */
296 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
297 SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6);
298 /* set SCP_SDCA_IntMask2[0]=1 */
299 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
300 SDW_SCP_SDCA_INTMASK_SDCA_8);
301 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__);
302 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
303 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E);
304 /* set XU(et03h) & XU(et0Dh) to Not bypassed */
305 regmap_write(rt722->regmap,
306 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03,
307 RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
308 regmap_write(rt722->regmap,
309 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D,
310 RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
311 /* trigger GE interrupt */
312 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
313 RT722_GE_RELATED_CTL2, 0x4000, 0x4000);
314 }
315 mutex_unlock(&rt722->calibrate_mutex);
316 }
317
rt722_sdca_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)318 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component,
319 struct snd_soc_jack *hs_jack, void *data)
320 {
321 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
322 int ret;
323
324 rt722->hs_jack = hs_jack;
325
326 ret = pm_runtime_resume_and_get(component->dev);
327 if (ret < 0) {
328 if (ret != -EACCES) {
329 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
330 return ret;
331 }
332 /* pm_runtime not enabled yet */
333 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
334 return 0;
335 }
336
337 rt722_sdca_jack_init(rt722);
338
339 pm_runtime_mark_last_busy(component->dev);
340 pm_runtime_put_autosuspend(component->dev);
341
342 return 0;
343 }
344
345 /* For SDCA control DAC/ADC Gain */
rt722_sdca_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)346 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348 {
349 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
350 struct soc_mixer_control *mc =
351 (struct soc_mixer_control *)kcontrol->private_value;
352 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
353 unsigned int read_l, read_r, gain_l_val, gain_r_val;
354 unsigned int adc_vol_flag = 0, changed = 0;
355 unsigned int lvalue, rvalue;
356 const unsigned int interval_offset = 0xc0;
357 const unsigned int tendB = 0xa00;
358
359 if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
360 strstr(ucontrol->id.name, "FU0F Capture Volume"))
361 adc_vol_flag = 1;
362
363 regmap_read(rt722->mbq_regmap, mc->reg, &lvalue);
364 regmap_read(rt722->mbq_regmap, mc->rreg, &rvalue);
365
366 /* L Channel */
367 gain_l_val = ucontrol->value.integer.value[0];
368 if (gain_l_val > mc->max)
369 gain_l_val = mc->max;
370
371 if (mc->shift == 8) /* boost gain */
372 gain_l_val = gain_l_val * tendB;
373 else {
374 /* ADC/DAC gain */
375 if (adc_vol_flag)
376 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset);
377 else
378 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
379 gain_l_val &= 0xffff;
380 }
381
382 /* R Channel */
383 gain_r_val = ucontrol->value.integer.value[1];
384 if (gain_r_val > mc->max)
385 gain_r_val = mc->max;
386
387 if (mc->shift == 8) /* boost gain */
388 gain_r_val = gain_r_val * tendB;
389 else {
390 /* ADC/DAC gain */
391 if (adc_vol_flag)
392 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset);
393 else
394 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
395 gain_r_val &= 0xffff;
396 }
397
398 if (lvalue != gain_l_val || rvalue != gain_r_val)
399 changed = 1;
400 else
401 return 0;
402
403 /* Lch*/
404 regmap_write(rt722->mbq_regmap, mc->reg, gain_l_val);
405
406 /* Rch */
407 regmap_write(rt722->mbq_regmap, mc->rreg, gain_r_val);
408
409 regmap_read(rt722->mbq_regmap, mc->reg, &read_l);
410 regmap_read(rt722->mbq_regmap, mc->rreg, &read_r);
411 if (read_r == gain_r_val && read_l == gain_l_val)
412 return changed;
413
414 return -EIO;
415 }
416
rt722_sdca_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)417 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol)
419 {
420 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
421 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
422 struct soc_mixer_control *mc =
423 (struct soc_mixer_control *)kcontrol->private_value;
424 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
425 unsigned int adc_vol_flag = 0;
426 const unsigned int interval_offset = 0xc0;
427 const unsigned int tendB = 0xa00;
428
429 if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
430 strstr(ucontrol->id.name, "FU0F Capture Volume"))
431 adc_vol_flag = 1;
432
433 regmap_read(rt722->mbq_regmap, mc->reg, &read_l);
434 regmap_read(rt722->mbq_regmap, mc->rreg, &read_r);
435
436 if (mc->shift == 8) /* boost gain */
437 ctl_l = read_l / tendB;
438 else {
439 if (adc_vol_flag)
440 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset);
441 else
442 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
443 }
444
445 if (read_l != read_r) {
446 if (mc->shift == 8) /* boost gain */
447 ctl_r = read_r / tendB;
448 else { /* ADC/DAC gain */
449 if (adc_vol_flag)
450 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset);
451 else
452 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
453 }
454 } else {
455 ctl_r = ctl_l;
456 }
457
458 ucontrol->value.integer.value[0] = ctl_l;
459 ucontrol->value.integer.value[1] = ctl_r;
460
461 return 0;
462 }
463
rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv * rt722)464 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722)
465 {
466 int err, i;
467 unsigned int ch_mute;
468
469 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) {
470 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i];
471 err = regmap_write(rt722->regmap,
472 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
473 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
474 if (err < 0)
475 return err;
476 }
477
478 return 0;
479 }
480
rt722_sdca_fu1e_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)481 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol)
483 {
484 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
485 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
486 struct rt722_sdca_dmic_kctrl_priv *p =
487 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
488 unsigned int i;
489
490 for (i = 0; i < p->count; i++)
491 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i];
492
493 return 0;
494 }
495
rt722_sdca_fu1e_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)496 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol,
497 struct snd_ctl_elem_value *ucontrol)
498 {
499 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
500 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
501 struct rt722_sdca_dmic_kctrl_priv *p =
502 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
503 int err, changed = 0, i;
504
505 for (i = 0; i < p->count; i++) {
506 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i])
507 changed = 1;
508 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i];
509 }
510
511 err = rt722_sdca_set_fu1e_capture_ctl(rt722);
512 if (err < 0)
513 return err;
514
515 return changed;
516 }
517
rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv * rt722)518 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722)
519 {
520 int err;
521 unsigned int ch_l, ch_r;
522
523 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00;
524 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00;
525
526 err = regmap_write(rt722->regmap,
527 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
528 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l);
529 if (err < 0)
530 return err;
531
532 err = regmap_write(rt722->regmap,
533 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
534 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r);
535 if (err < 0)
536 return err;
537
538 return 0;
539 }
540
rt722_sdca_fu0f_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)541 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
542 struct snd_ctl_elem_value *ucontrol)
543 {
544 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
545 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
546
547 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute;
548 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute;
549 return 0;
550 }
551
rt722_sdca_fu0f_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)552 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_value *ucontrol)
554 {
555 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
556 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
557 int err, changed = 0;
558
559 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] ||
560 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1])
561 changed = 1;
562
563 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
564 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
565 err = rt722_sdca_set_fu0f_capture_ctl(rt722);
566 if (err < 0)
567 return err;
568
569 return changed;
570 }
571
rt722_sdca_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)572 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol,
573 struct snd_ctl_elem_info *uinfo)
574 {
575 struct rt722_sdca_dmic_kctrl_priv *p =
576 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
577
578 if (p->max == 1)
579 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
580 else
581 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
582 uinfo->count = p->count;
583 uinfo->value.integer.min = 0;
584 uinfo->value.integer.max = p->max;
585 return 0;
586 }
587
rt722_sdca_dmic_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)588 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol,
589 struct snd_ctl_elem_value *ucontrol)
590 {
591 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
592 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
593 struct rt722_sdca_dmic_kctrl_priv *p =
594 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
595 unsigned int boost_step = 0x0a00;
596 unsigned int vol_max = 0x1e00;
597 unsigned int regvalue, ctl, i;
598 unsigned int adc_vol_flag = 0;
599 const unsigned int interval_offset = 0xc0;
600
601 if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
602 adc_vol_flag = 1;
603
604 /* check all channels */
605 for (i = 0; i < p->count; i++) {
606 regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value);
607
608 if (!adc_vol_flag) /* boost gain */
609 ctl = regvalue / boost_step;
610 else /* ADC gain */
611 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset);
612
613 ucontrol->value.integer.value[i] = ctl;
614 }
615
616 return 0;
617 }
618
rt722_sdca_dmic_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)619 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol,
620 struct snd_ctl_elem_value *ucontrol)
621 {
622 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
623 struct rt722_sdca_dmic_kctrl_priv *p =
624 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
625 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
626 unsigned int boost_step = 0x0a00;
627 unsigned int vol_max = 0x1e00;
628 unsigned int gain_val[4];
629 unsigned int i, adc_vol_flag = 0, changed = 0;
630 unsigned int regvalue[4];
631 const unsigned int interval_offset = 0xc0;
632 int err;
633
634 if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
635 adc_vol_flag = 1;
636
637 /* check all channels */
638 for (i = 0; i < p->count; i++) {
639 regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value[i]);
640
641 gain_val[i] = ucontrol->value.integer.value[i];
642 if (gain_val[i] > p->max)
643 gain_val[i] = p->max;
644
645 if (!adc_vol_flag) /* boost gain */
646 gain_val[i] = gain_val[i] * boost_step;
647 else { /* ADC gain */
648 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset);
649 gain_val[i] &= 0xffff;
650 }
651
652 if (regvalue[i] != gain_val[i])
653 changed = 1;
654 }
655
656 if (!changed)
657 return 0;
658
659 for (i = 0; i < p->count; i++) {
660 err = regmap_write(rt722->mbq_regmap, p->reg_base + i, gain_val[i]);
661 if (err < 0)
662 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n",
663 __func__, p->reg_base + i);
664 }
665
666 return changed;
667 }
668
669 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \
670 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \
671 {.reg_base = xreg_base, .count = xcount, .max = xmax, \
672 .invert = xinvert})
673
674 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
675 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
676 .info = rt722_sdca_fu_info, \
677 .get = rt722_sdca_fu1e_capture_get, \
678 .put = rt722_sdca_fu1e_capture_put, \
679 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
680
681 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
682 xhandler_put, xcount, xmax, tlv_array) \
683 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
684 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
685 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
686 .tlv.p = (tlv_array), \
687 .info = rt722_sdca_fu_info, \
688 .get = xhandler_get, .put = xhandler_put, \
689 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
690
691 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
692 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0);
693 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0);
694
695 static const struct snd_kcontrol_new rt722_sdca_controls[] = {
696 /* Headphone playback settings */
697 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
698 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
699 RT722_SDCA_CTL_FU_VOLUME, CH_L),
700 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
701 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
702 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
703 /* Headset mic capture settings */
704 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
705 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put),
706 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
707 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
708 RT722_SDCA_CTL_FU_VOLUME, CH_L),
709 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
710 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0,
711 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv),
712 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume",
713 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
714 RT722_SDCA_CTL_FU_CH_GAIN, CH_L),
715 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
716 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0,
717 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv),
718 /* AMP playback settings */
719 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume",
720 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
721 RT722_SDCA_CTL_FU_VOLUME, CH_L),
722 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
723 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
724 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
725 /* DMIC capture settings */
726 RT722_SDCA_FU_CTRL("FU1E Capture Switch",
727 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
728 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4),
729 RT722_SDCA_EXT_TLV("FU1E Capture Volume",
730 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
731 RT722_SDCA_CTL_FU_VOLUME, CH_01),
732 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
733 4, 0x3f, mic_vol_tlv),
734 RT722_SDCA_EXT_TLV("FU15 Boost Volume",
735 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15,
736 RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
737 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
738 4, 3, boost_vol_tlv),
739 };
740
rt722_sdca_adc_mux_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)741 static int rt722_sdca_adc_mux_get(struct snd_kcontrol *kcontrol,
742 struct snd_ctl_elem_value *ucontrol)
743 {
744 struct snd_soc_component *component =
745 snd_soc_dapm_kcontrol_component(kcontrol);
746 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
747 unsigned int val = 0, mask_sft;
748
749 if (strstr(ucontrol->id.name, "ADC 22 Mux"))
750 mask_sft = 12;
751 else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
752 mask_sft = 4;
753 else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
754 mask_sft = 0;
755 else
756 return -EINVAL;
757
758 rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL,
759 RT722_HDA_LEGACY_MUX_CTL0, &val);
760
761 ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7;
762
763 return 0;
764 }
765
rt722_sdca_adc_mux_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)766 static int rt722_sdca_adc_mux_put(struct snd_kcontrol *kcontrol,
767 struct snd_ctl_elem_value *ucontrol)
768 {
769 struct snd_soc_component *component =
770 snd_soc_dapm_kcontrol_component(kcontrol);
771 struct snd_soc_dapm_context *dapm =
772 snd_soc_dapm_kcontrol_dapm(kcontrol);
773 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
774 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
775 unsigned int *item = ucontrol->value.enumerated.item;
776 unsigned int val, val2 = 0, change, mask_sft;
777
778 if (item[0] >= e->items)
779 return -EINVAL;
780
781 if (strstr(ucontrol->id.name, "ADC 22 Mux"))
782 mask_sft = 12;
783 else if (strstr(ucontrol->id.name, "ADC 24 Mux"))
784 mask_sft = 4;
785 else if (strstr(ucontrol->id.name, "ADC 25 Mux"))
786 mask_sft = 0;
787 else
788 return -EINVAL;
789
790 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
791
792 rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL,
793 RT722_HDA_LEGACY_MUX_CTL0, &val2);
794 val2 = (0x7 << mask_sft) & val2;
795
796 if (val == val2)
797 change = 0;
798 else
799 change = 1;
800
801 if (change)
802 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
803 RT722_HDA_LEGACY_MUX_CTL0, 0x7 << mask_sft,
804 val << mask_sft);
805
806 snd_soc_dapm_mux_update_power(dapm, kcontrol,
807 item[0], e, NULL);
808
809 return change;
810 }
811
812 static const char * const adc22_mux_text[] = {
813 "MIC2",
814 "LINE1",
815 "LINE2",
816 };
817
818 static const char * const adc07_10_mux_text[] = {
819 "DMIC1",
820 "DMIC2",
821 };
822
823 static SOC_ENUM_SINGLE_DECL(
824 rt722_adc22_enum, SND_SOC_NOPM, 0, adc22_mux_text);
825
826 static SOC_ENUM_SINGLE_DECL(
827 rt722_adc24_enum, SND_SOC_NOPM, 0, adc07_10_mux_text);
828
829 static SOC_ENUM_SINGLE_DECL(
830 rt722_adc25_enum, SND_SOC_NOPM, 0, adc07_10_mux_text);
831
832 static const struct snd_kcontrol_new rt722_sdca_adc22_mux =
833 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt722_adc22_enum,
834 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
835
836 static const struct snd_kcontrol_new rt722_sdca_adc24_mux =
837 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt722_adc24_enum,
838 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
839
840 static const struct snd_kcontrol_new rt722_sdca_adc25_mux =
841 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt722_adc25_enum,
842 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put);
843
rt722_sdca_fu42_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)844 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w,
845 struct snd_kcontrol *kcontrol, int event)
846 {
847 struct snd_soc_component *component =
848 snd_soc_dapm_to_component(w->dapm);
849 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
850 unsigned char unmute = 0x0, mute = 0x1;
851
852 switch (event) {
853 case SND_SOC_DAPM_POST_PMU:
854 regmap_write(rt722->regmap,
855 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
856 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
857 regmap_write(rt722->regmap,
858 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
859 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
860 break;
861 case SND_SOC_DAPM_PRE_PMD:
862 regmap_write(rt722->regmap,
863 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
864 RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
865 regmap_write(rt722->regmap,
866 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
867 RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
868 break;
869 }
870 return 0;
871 }
872
rt722_sdca_fu21_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)873 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w,
874 struct snd_kcontrol *kcontrol, int event)
875 {
876 struct snd_soc_component *component =
877 snd_soc_dapm_to_component(w->dapm);
878 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
879 unsigned char unmute = 0x0, mute = 0x1;
880
881 switch (event) {
882 case SND_SOC_DAPM_POST_PMU:
883 regmap_write(rt722->regmap,
884 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
885 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
886 regmap_write(rt722->regmap,
887 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
888 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
889 break;
890 case SND_SOC_DAPM_PRE_PMD:
891 regmap_write(rt722->regmap,
892 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
893 RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
894 regmap_write(rt722->regmap,
895 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
896 RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
897 break;
898 }
899 return 0;
900 }
901
rt722_sdca_fu113_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)902 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w,
903 struct snd_kcontrol *kcontrol, int event)
904 {
905 struct snd_soc_component *component =
906 snd_soc_dapm_to_component(w->dapm);
907 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
908
909 switch (event) {
910 case SND_SOC_DAPM_POST_PMU:
911 rt722->fu1e_dapm_mute = false;
912 rt722_sdca_set_fu1e_capture_ctl(rt722);
913 break;
914 case SND_SOC_DAPM_PRE_PMD:
915 rt722->fu1e_dapm_mute = true;
916 rt722_sdca_set_fu1e_capture_ctl(rt722);
917 break;
918 }
919 return 0;
920 }
921
rt722_sdca_fu36_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)922 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w,
923 struct snd_kcontrol *kcontrol, int event)
924 {
925 struct snd_soc_component *component =
926 snd_soc_dapm_to_component(w->dapm);
927 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
928
929 switch (event) {
930 case SND_SOC_DAPM_POST_PMU:
931 rt722->fu0f_dapm_mute = false;
932 rt722_sdca_set_fu0f_capture_ctl(rt722);
933 break;
934 case SND_SOC_DAPM_PRE_PMD:
935 rt722->fu0f_dapm_mute = true;
936 rt722_sdca_set_fu0f_capture_ctl(rt722);
937 break;
938 }
939 return 0;
940 }
941
rt722_sdca_pde47_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)942 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w,
943 struct snd_kcontrol *kcontrol, int event)
944 {
945 struct snd_soc_component *component =
946 snd_soc_dapm_to_component(w->dapm);
947 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
948 unsigned char ps0 = 0x0, ps3 = 0x3;
949
950 switch (event) {
951 case SND_SOC_DAPM_POST_PMU:
952 regmap_write(rt722->regmap,
953 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
954 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
955 break;
956 case SND_SOC_DAPM_PRE_PMD:
957 regmap_write(rt722->regmap,
958 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
959 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
960 break;
961 }
962 return 0;
963 }
964
rt722_sdca_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)965 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w,
966 struct snd_kcontrol *kcontrol, int event)
967 {
968 struct snd_soc_component *component =
969 snd_soc_dapm_to_component(w->dapm);
970 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
971 unsigned char ps0 = 0x0, ps3 = 0x3;
972
973 switch (event) {
974 case SND_SOC_DAPM_POST_PMU:
975 regmap_write(rt722->regmap,
976 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
977 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
978 break;
979 case SND_SOC_DAPM_PRE_PMD:
980 regmap_write(rt722->regmap,
981 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
982 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
983 break;
984 }
985 return 0;
986 }
987
rt722_sdca_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)988 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w,
989 struct snd_kcontrol *kcontrol, int event)
990 {
991 struct snd_soc_component *component =
992 snd_soc_dapm_to_component(w->dapm);
993 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
994 unsigned char ps0 = 0x0, ps3 = 0x3;
995
996 switch (event) {
997 case SND_SOC_DAPM_POST_PMU:
998 regmap_write(rt722->regmap,
999 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
1000 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1001 break;
1002 case SND_SOC_DAPM_PRE_PMD:
1003 regmap_write(rt722->regmap,
1004 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
1005 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1006 break;
1007 }
1008 return 0;
1009 }
1010
rt722_sdca_pde12_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1011 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w,
1012 struct snd_kcontrol *kcontrol, int event)
1013 {
1014 struct snd_soc_component *component =
1015 snd_soc_dapm_to_component(w->dapm);
1016 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1017 unsigned char ps0 = 0x0, ps3 = 0x3;
1018
1019 switch (event) {
1020 case SND_SOC_DAPM_POST_PMU:
1021 regmap_write(rt722->regmap,
1022 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
1023 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1024 break;
1025 case SND_SOC_DAPM_PRE_PMD:
1026 regmap_write(rt722->regmap,
1027 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
1028 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1029 break;
1030 }
1031 return 0;
1032 }
1033
1034 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = {
1035 SND_SOC_DAPM_OUTPUT("HP"),
1036 SND_SOC_DAPM_OUTPUT("SPK"),
1037 SND_SOC_DAPM_INPUT("MIC2"),
1038 SND_SOC_DAPM_INPUT("LINE1"),
1039 SND_SOC_DAPM_INPUT("LINE2"),
1040 SND_SOC_DAPM_INPUT("DMIC1_2"),
1041 SND_SOC_DAPM_INPUT("DMIC3_4"),
1042
1043 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1044 rt722_sdca_pde23_event,
1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1046 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0,
1047 rt722_sdca_pde47_event,
1048 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1049 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
1050 rt722_sdca_pde11_event,
1051 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1052 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0,
1053 rt722_sdca_pde12_event,
1054 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1055
1056 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0,
1057 rt722_sdca_fu21_event,
1058 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1059 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0,
1060 rt722_sdca_fu42_event,
1061 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1062 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0,
1063 rt722_sdca_fu36_event,
1064 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1065 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0,
1066 rt722_sdca_fu113_event,
1067 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1068 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
1069 &rt722_sdca_adc22_mux),
1070 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
1071 &rt722_sdca_adc24_mux),
1072 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
1073 &rt722_sdca_adc25_mux),
1074
1075 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0),
1076 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0),
1077 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0),
1078 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0),
1079 };
1080
1081 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = {
1082 {"FU 42", NULL, "DP1RX"},
1083 {"FU 21", NULL, "DP3RX"},
1084
1085 {"ADC 22 Mux", "MIC2", "MIC2"},
1086 {"ADC 22 Mux", "LINE1", "LINE1"},
1087 {"ADC 22 Mux", "LINE2", "LINE2"},
1088 {"ADC 24 Mux", "DMIC1", "DMIC1_2"},
1089 {"ADC 24 Mux", "DMIC2", "DMIC3_4"},
1090 {"ADC 25 Mux", "DMIC1", "DMIC1_2"},
1091 {"ADC 25 Mux", "DMIC2", "DMIC3_4"},
1092 {"FU 36", NULL, "PDE 12"},
1093 {"FU 36", NULL, "ADC 22 Mux"},
1094 {"FU 113", NULL, "PDE 11"},
1095 {"FU 113", NULL, "ADC 24 Mux"},
1096 {"FU 113", NULL, "ADC 25 Mux"},
1097 {"DP2TX", NULL, "FU 36"},
1098 {"DP6TX", NULL, "FU 113"},
1099
1100 {"HP", NULL, "PDE 47"},
1101 {"HP", NULL, "FU 42"},
1102 {"SPK", NULL, "PDE 23"},
1103 {"SPK", NULL, "FU 21"},
1104 };
1105
rt722_sdca_parse_dt(struct rt722_sdca_priv * rt722,struct device * dev)1106 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev)
1107 {
1108 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src);
1109
1110 return 0;
1111 }
1112
rt722_sdca_probe(struct snd_soc_component * component)1113 static int rt722_sdca_probe(struct snd_soc_component *component)
1114 {
1115 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1116 int ret;
1117
1118 rt722_sdca_parse_dt(rt722, &rt722->slave->dev);
1119 rt722->component = component;
1120
1121 ret = pm_runtime_resume(component->dev);
1122 if (ret < 0 && ret != -EACCES)
1123 return ret;
1124
1125 return 0;
1126 }
1127
1128 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = {
1129 .probe = rt722_sdca_probe,
1130 .controls = rt722_sdca_controls,
1131 .num_controls = ARRAY_SIZE(rt722_sdca_controls),
1132 .dapm_widgets = rt722_sdca_dapm_widgets,
1133 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets),
1134 .dapm_routes = rt722_sdca_audio_map,
1135 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map),
1136 .set_jack = rt722_sdca_set_jack_detect,
1137 .endianness = 1,
1138 };
1139
rt722_sdca_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)1140 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
1141 int direction)
1142 {
1143 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
1144
1145 return 0;
1146 }
1147
rt722_sdca_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1148 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream,
1149 struct snd_soc_dai *dai)
1150 {
1151 snd_soc_dai_set_dma_data(dai, substream, NULL);
1152 }
1153
rt722_sdca_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1154 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
1155 struct snd_pcm_hw_params *params,
1156 struct snd_soc_dai *dai)
1157 {
1158 struct snd_soc_component *component = dai->component;
1159 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1160 struct sdw_stream_config stream_config;
1161 struct sdw_port_config port_config;
1162 enum sdw_data_direction direction;
1163 struct sdw_stream_runtime *sdw_stream;
1164 int retval, port, num_channels;
1165 unsigned int sampling_rate;
1166
1167 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
1168 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
1169
1170 if (!sdw_stream)
1171 return -EINVAL;
1172
1173 if (!rt722->slave)
1174 return -EINVAL;
1175
1176 /*
1177 * RT722_AIF1 with port = 1 for headphone playback
1178 * RT722_AIF1 with port = 2 for headset-mic capture
1179 * RT722_AIF2 with port = 3 for speaker playback
1180 * RT722_AIF3 with port = 6 for digital-mic capture
1181 */
1182 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1183 direction = SDW_DATA_DIR_RX;
1184 if (dai->id == RT722_AIF1)
1185 port = 1;
1186 else if (dai->id == RT722_AIF2)
1187 port = 3;
1188 else
1189 return -EINVAL;
1190 } else {
1191 direction = SDW_DATA_DIR_TX;
1192 if (dai->id == RT722_AIF1)
1193 port = 2;
1194 else if (dai->id == RT722_AIF3)
1195 port = 6;
1196 else
1197 return -EINVAL;
1198 }
1199 stream_config.frame_rate = params_rate(params);
1200 stream_config.ch_count = params_channels(params);
1201 stream_config.bps = snd_pcm_format_width(params_format(params));
1202 stream_config.direction = direction;
1203
1204 num_channels = params_channels(params);
1205 port_config.ch_mask = GENMASK(num_channels - 1, 0);
1206 port_config.num = port;
1207
1208 retval = sdw_stream_add_slave(rt722->slave, &stream_config,
1209 &port_config, 1, sdw_stream);
1210 if (retval) {
1211 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
1212 return retval;
1213 }
1214
1215 if (params_channels(params) > 16) {
1216 dev_err(component->dev, "%s: Unsupported channels %d\n",
1217 __func__, params_channels(params));
1218 return -EINVAL;
1219 }
1220
1221 /* sampling rate configuration */
1222 switch (params_rate(params)) {
1223 case 44100:
1224 sampling_rate = RT722_SDCA_RATE_44100HZ;
1225 break;
1226 case 48000:
1227 sampling_rate = RT722_SDCA_RATE_48000HZ;
1228 break;
1229 case 96000:
1230 sampling_rate = RT722_SDCA_RATE_96000HZ;
1231 break;
1232 case 192000:
1233 sampling_rate = RT722_SDCA_RATE_192000HZ;
1234 break;
1235 default:
1236 dev_err(component->dev, "%s: Rate %d is not supported\n",
1237 __func__, params_rate(params));
1238 return -EINVAL;
1239 }
1240
1241 /* set sampling frequency */
1242 if (dai->id == RT722_AIF1) {
1243 regmap_write(rt722->regmap,
1244 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01,
1245 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1246 regmap_write(rt722->regmap,
1247 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11,
1248 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1249 }
1250
1251 if (dai->id == RT722_AIF2)
1252 regmap_write(rt722->regmap,
1253 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31,
1254 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1255
1256 if (dai->id == RT722_AIF3)
1257 regmap_write(rt722->regmap,
1258 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F,
1259 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1260
1261 return 0;
1262 }
1263
rt722_sdca_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1264 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
1265 struct snd_soc_dai *dai)
1266 {
1267 struct snd_soc_component *component = dai->component;
1268 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1269 struct sdw_stream_runtime *sdw_stream =
1270 snd_soc_dai_get_dma_data(dai, substream);
1271
1272 if (!rt722->slave)
1273 return -EINVAL;
1274
1275 sdw_stream_remove_slave(rt722->slave, sdw_stream);
1276 return 0;
1277 }
1278
1279 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
1280 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
1281 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1282 SNDRV_PCM_FMTBIT_S24_LE)
1283
1284 static const struct snd_soc_dai_ops rt722_sdca_ops = {
1285 .hw_params = rt722_sdca_pcm_hw_params,
1286 .hw_free = rt722_sdca_pcm_hw_free,
1287 .set_stream = rt722_sdca_set_sdw_stream,
1288 .shutdown = rt722_sdca_shutdown,
1289 };
1290
1291 static struct snd_soc_dai_driver rt722_sdca_dai[] = {
1292 {
1293 .name = "rt722-sdca-aif1",
1294 .id = RT722_AIF1,
1295 .playback = {
1296 .stream_name = "DP1 Headphone Playback",
1297 .channels_min = 1,
1298 .channels_max = 2,
1299 .rates = RT722_STEREO_RATES,
1300 .formats = RT722_FORMATS,
1301 },
1302 .capture = {
1303 .stream_name = "DP2 Headset Capture",
1304 .channels_min = 1,
1305 .channels_max = 2,
1306 .rates = RT722_STEREO_RATES,
1307 .formats = RT722_FORMATS,
1308 },
1309 .ops = &rt722_sdca_ops,
1310 },
1311 {
1312 .name = "rt722-sdca-aif2",
1313 .id = RT722_AIF2,
1314 .playback = {
1315 .stream_name = "DP3 Speaker Playback",
1316 .channels_min = 1,
1317 .channels_max = 2,
1318 .rates = RT722_STEREO_RATES,
1319 .formats = RT722_FORMATS,
1320 },
1321 .ops = &rt722_sdca_ops,
1322 },
1323 {
1324 .name = "rt722-sdca-aif3",
1325 .id = RT722_AIF3,
1326 .capture = {
1327 .stream_name = "DP6 DMic Capture",
1328 .channels_min = 1,
1329 .channels_max = 4,
1330 .rates = RT722_STEREO_RATES,
1331 .formats = RT722_FORMATS,
1332 },
1333 .ops = &rt722_sdca_ops,
1334 }
1335 };
1336
rt722_sdca_init(struct device * dev,struct regmap * regmap,struct regmap * mbq_regmap,struct sdw_slave * slave)1337 int rt722_sdca_init(struct device *dev, struct regmap *regmap,
1338 struct regmap *mbq_regmap, struct sdw_slave *slave)
1339 {
1340 struct rt722_sdca_priv *rt722;
1341
1342 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL);
1343 if (!rt722)
1344 return -ENOMEM;
1345
1346 dev_set_drvdata(dev, rt722);
1347 rt722->slave = slave;
1348 rt722->regmap = regmap;
1349 rt722->mbq_regmap = mbq_regmap;
1350
1351 mutex_init(&rt722->calibrate_mutex);
1352 mutex_init(&rt722->disable_irq_lock);
1353
1354 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler);
1355 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler);
1356
1357 /*
1358 * Mark hw_init to false
1359 * HW init will be performed when device reports present
1360 */
1361 rt722->hw_init = false;
1362 rt722->first_hw_init = false;
1363 rt722->fu1e_dapm_mute = true;
1364 rt722->fu0f_dapm_mute = true;
1365 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true;
1366 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] =
1367 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true;
1368
1369 return devm_snd_soc_register_component(dev,
1370 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai));
1371 }
1372
rt722_sdca_dmic_preset(struct rt722_sdca_priv * rt722)1373 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722)
1374 {
1375 /* Set AD07 power entity floating control */
1376 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1377 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29);
1378 /* Set AD10 power entity floating control */
1379 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1380 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00);
1381 /* Set DMIC1/DMIC2 power entity floating control */
1382 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1383 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a);
1384 /* Set DMIC2 IT entity floating control */
1385 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1386 RT722_DMIC_ENT_FLOAT_CTL, 0x2626);
1387 /* Set AD10 FU entity floating control */
1388 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1389 RT722_ADC_ENT_FLOAT_CTL, 0x1e00);
1390 /* Set DMIC2 FU entity floating control */
1391 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1392 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515);
1393 /* Set AD10 FU channel floating control */
1394 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1395 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304);
1396 /* Set DMIC2 FU channel floating control */
1397 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1398 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304);
1399 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */
1400 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1401 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000);
1402 /* Enable vf707_r12_05/vf707_r13_05 */
1403 regmap_write(rt722->regmap,
1404 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26,
1405 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01);
1406 /* Fine tune PDE2A latency */
1407 regmap_write(rt722->regmap, 0x2f5c, 0x25);
1408 }
1409
rt722_sdca_amp_preset(struct rt722_sdca_priv * rt722)1410 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722)
1411 {
1412 /* Set DVQ=01 */
1413 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1414 0xc215);
1415 /* Reset dc_cal_top */
1416 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1417 0x702c);
1418 /* W1C Trigger Calibration */
1419 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1420 0xf02d);
1421 /* Set DAC02/ClassD power entity floating control */
1422 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL,
1423 0x2323);
1424 /* Set EAPD high */
1425 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL,
1426 0x0002);
1427 /* Enable vf707_r14 */
1428 regmap_write(rt722->regmap,
1429 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23,
1430 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04);
1431 }
1432
rt722_sdca_jack_preset(struct rt722_sdca_priv * rt722)1433 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722)
1434 {
1435 int loop_check, chk_cnt = 100, ret;
1436 unsigned int calib_status = 0;
1437
1438 /* Config analog bias */
1439 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3,
1440 0xa081);
1441 /* GE related settings */
1442 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2,
1443 0xa009);
1444 /* Button A, B, C, D bypass mode */
1445 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4,
1446 0xcf00);
1447 /* HID1 slot enable */
1448 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5,
1449 0x000f);
1450 /* Report ID for HID1 */
1451 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0,
1452 0x1100);
1453 /* OSC/OOC for slot 2, 3 */
1454 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7,
1455 0x0c12);
1456 /* Set JD de-bounce clock control */
1457 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1,
1458 0x7002);
1459 /* Set DVQ=01 */
1460 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1461 0xc215);
1462 /* FSM switch to calibration manual mode */
1463 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL,
1464 0x4100);
1465 /* W1C Trigger DC calibration (HP) */
1466 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3,
1467 0x008d);
1468 /* check HP calibration FSM status */
1469 for (loop_check = 0; loop_check < chk_cnt; loop_check++) {
1470 usleep_range(10000, 11000);
1471 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI,
1472 RT722_DAC_DC_CALI_CTL3, &calib_status);
1473 if (ret < 0)
1474 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret);
1475 if ((calib_status & 0x0040) == 0x0)
1476 break;
1477 }
1478
1479 if (loop_check == chk_cnt)
1480 dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__);
1481
1482 /* Set ADC09 power entity floating control */
1483 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL,
1484 0x2a12);
1485 /* Set MIC2 and LINE1 power entity floating control */
1486 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL,
1487 0x3429);
1488 /* Set ET41h and LINE2 power entity floating control */
1489 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL,
1490 0x4112);
1491 /* Set DAC03 and HP power entity floating control */
1492 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL,
1493 0x4040);
1494 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1,
1495 0x4141);
1496 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1,
1497 0x0101);
1498 /* Fine tune PDE40 latency */
1499 regmap_write(rt722->regmap, 0x2f58, 0x07);
1500 regmap_write(rt722->regmap, 0x2f03, 0x06);
1501 /* MIC VRefo */
1502 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG,
1503 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200);
1504 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG,
1505 RT722_VREFO_GAT, 0x4000, 0x4000);
1506 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */
1507 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4,
1508 0x0010);
1509 }
1510
rt722_sdca_io_init(struct device * dev,struct sdw_slave * slave)1511 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave)
1512 {
1513 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
1514
1515 rt722->disable_irq = false;
1516
1517 if (rt722->hw_init)
1518 return 0;
1519
1520 if (rt722->first_hw_init) {
1521 regcache_cache_only(rt722->regmap, false);
1522 regcache_cache_bypass(rt722->regmap, true);
1523 regcache_cache_only(rt722->mbq_regmap, false);
1524 regcache_cache_bypass(rt722->mbq_regmap, true);
1525 } else {
1526 /*
1527 * PM runtime is only enabled when a Slave reports as Attached
1528 */
1529
1530 /* set autosuspend parameters */
1531 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
1532 pm_runtime_use_autosuspend(&slave->dev);
1533
1534 /* update count of parent 'active' children */
1535 pm_runtime_set_active(&slave->dev);
1536
1537 /* make sure the device does not suspend immediately */
1538 pm_runtime_mark_last_busy(&slave->dev);
1539
1540 pm_runtime_enable(&slave->dev);
1541 }
1542
1543 pm_runtime_get_noresume(&slave->dev);
1544
1545 rt722_sdca_dmic_preset(rt722);
1546 rt722_sdca_amp_preset(rt722);
1547 rt722_sdca_jack_preset(rt722);
1548
1549 if (rt722->first_hw_init) {
1550 regcache_cache_bypass(rt722->regmap, false);
1551 regcache_mark_dirty(rt722->regmap);
1552 regcache_cache_bypass(rt722->mbq_regmap, false);
1553 regcache_mark_dirty(rt722->mbq_regmap);
1554 } else
1555 rt722->first_hw_init = true;
1556
1557 /* Mark Slave initialization complete */
1558 rt722->hw_init = true;
1559
1560 pm_runtime_mark_last_busy(&slave->dev);
1561 pm_runtime_put_autosuspend(&slave->dev);
1562
1563 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1564 return 0;
1565 }
1566
1567 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
1568 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1569 MODULE_LICENSE("GPL");
1570