1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
4
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/cleanup.h>
9 #include <linux/device.h>
10 #include <linux/wait.h>
11 #include <linux/bitops.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/kernel.h>
16 #include <linux/slimbus.h>
17 #include <sound/soc.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <sound/tlv.h>
24 #include <sound/info.h>
25 #include "wcd9335.h"
26 #include "wcd-clsh-v2.h"
27
28 #include <dt-bindings/sound/qcom,wcd9335.h>
29
30 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
31 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
32 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
33 /* Fractional Rates */
34 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
35 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE)
37
38 /* slave port water mark level
39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
40 */
41 #define SLAVE_PORT_WATER_MARK_6BYTES 0
42 #define SLAVE_PORT_WATER_MARK_9BYTES 1
43 #define SLAVE_PORT_WATER_MARK_12BYTES 2
44 #define SLAVE_PORT_WATER_MARK_15BYTES 3
45 #define SLAVE_PORT_WATER_MARK_SHIFT 1
46 #define SLAVE_PORT_ENABLE 1
47 #define SLAVE_PORT_DISABLE 0
48 #define WCD9335_SLIM_WATER_MARK_VAL \
49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
50 (SLAVE_PORT_ENABLE))
51
52 #define WCD9335_SLIM_NUM_PORT_REG 3
53 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
54
55 #define WCD9335_MCLK_CLK_12P288MHZ 12288000
56 #define WCD9335_MCLK_CLK_9P6MHZ 9600000
57
58 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
59 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
60 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
61 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
62
63 #define WCD9335_NUM_INTERPOLATORS 9
64 #define WCD9335_RX_START 16
65 #define WCD9335_SLIM_CH_START 128
66 #define WCD9335_MAX_MICBIAS 4
67 #define WCD9335_MAX_VALID_ADC_MUX 13
68 #define WCD9335_INVALID_ADC_MUX 9
69
70 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
71 #define CF_MIN_3DB_4HZ 0x0
72 #define CF_MIN_3DB_75HZ 0x1
73 #define CF_MIN_3DB_150HZ 0x2
74 #define WCD9335_DMIC_CLK_DIV_2 0x0
75 #define WCD9335_DMIC_CLK_DIV_3 0x1
76 #define WCD9335_DMIC_CLK_DIV_4 0x2
77 #define WCD9335_DMIC_CLK_DIV_6 0x3
78 #define WCD9335_DMIC_CLK_DIV_8 0x4
79 #define WCD9335_DMIC_CLK_DIV_16 0x5
80 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
81 #define WCD9335_AMIC_PWR_LEVEL_LP 0
82 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
83 #define WCD9335_AMIC_PWR_LEVEL_HP 2
84 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
85 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
86
87 #define WCD9335_DEC_PWR_LVL_MASK 0x06
88 #define WCD9335_DEC_PWR_LVL_LP 0x02
89 #define WCD9335_DEC_PWR_LVL_HP 0x04
90 #define WCD9335_DEC_PWR_LVL_DF 0x00
91
92 #define WCD9335_SLIM_RX_CH(p) \
93 {.port = p + WCD9335_RX_START, .shift = p,}
94
95 #define WCD9335_SLIM_TX_CH(p) \
96 {.port = p, .shift = p,}
97
98 /* vout step value */
99 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
100
101 #define WCD9335_INTERPOLATOR_PATH(id) \
102 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
103 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
104 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
105 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
106 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
107 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
108 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
109 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
110 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
111 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
112 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
113 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
114 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
115 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
116 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
117 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
118 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
119 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
120 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
121 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
122 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
123 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
124 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
125 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
126 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
127 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
128 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
129 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
130 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
131 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
132 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
133 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
136 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
138 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
139 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
140 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
141
142 #define WCD9335_ADC_MUX_PATH(id) \
143 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
144 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
145 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
146 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
147 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
148 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
149 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
150 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
151 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
152 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
153 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
154 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
155 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
156 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
157 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
158 {"AMIC MUX" #id, "ADC4", "ADC4"}, \
159 {"AMIC MUX" #id, "ADC5", "ADC5"}, \
160 {"AMIC MUX" #id, "ADC6", "ADC6"}
161
162 enum {
163 WCD9335_RX0 = 0,
164 WCD9335_RX1,
165 WCD9335_RX2,
166 WCD9335_RX3,
167 WCD9335_RX4,
168 WCD9335_RX5,
169 WCD9335_RX6,
170 WCD9335_RX7,
171 WCD9335_RX8,
172 WCD9335_RX9,
173 WCD9335_RX10,
174 WCD9335_RX11,
175 WCD9335_RX12,
176 WCD9335_RX_MAX,
177 };
178
179 enum {
180 WCD9335_TX0 = 0,
181 WCD9335_TX1,
182 WCD9335_TX2,
183 WCD9335_TX3,
184 WCD9335_TX4,
185 WCD9335_TX5,
186 WCD9335_TX6,
187 WCD9335_TX7,
188 WCD9335_TX8,
189 WCD9335_TX9,
190 WCD9335_TX10,
191 WCD9335_TX11,
192 WCD9335_TX12,
193 WCD9335_TX13,
194 WCD9335_TX14,
195 WCD9335_TX15,
196 WCD9335_TX_MAX,
197 };
198
199 enum {
200 SIDO_SOURCE_INTERNAL = 0,
201 SIDO_SOURCE_RCO_BG,
202 };
203
204 enum wcd9335_sido_voltage {
205 SIDO_VOLTAGE_SVS_MV = 950,
206 SIDO_VOLTAGE_NOMINAL_MV = 1100,
207 };
208
209 enum {
210 COMPANDER_1, /* HPH_L */
211 COMPANDER_2, /* HPH_R */
212 COMPANDER_3, /* LO1_DIFF */
213 COMPANDER_4, /* LO2_DIFF */
214 COMPANDER_5, /* LO3_SE */
215 COMPANDER_6, /* LO4_SE */
216 COMPANDER_7, /* SWR SPK CH1 */
217 COMPANDER_8, /* SWR SPK CH2 */
218 COMPANDER_MAX,
219 };
220
221 enum {
222 INTn_2_INP_SEL_ZERO = 0,
223 INTn_2_INP_SEL_RX0,
224 INTn_2_INP_SEL_RX1,
225 INTn_2_INP_SEL_RX2,
226 INTn_2_INP_SEL_RX3,
227 INTn_2_INP_SEL_RX4,
228 INTn_2_INP_SEL_RX5,
229 INTn_2_INP_SEL_RX6,
230 INTn_2_INP_SEL_RX7,
231 INTn_2_INP_SEL_PROXIMITY,
232 };
233
234 enum {
235 INTn_1_MIX_INP_SEL_ZERO = 0,
236 INTn_1_MIX_INP_SEL_DEC0,
237 INTn_1_MIX_INP_SEL_DEC1,
238 INTn_1_MIX_INP_SEL_IIR0,
239 INTn_1_MIX_INP_SEL_IIR1,
240 INTn_1_MIX_INP_SEL_RX0,
241 INTn_1_MIX_INP_SEL_RX1,
242 INTn_1_MIX_INP_SEL_RX2,
243 INTn_1_MIX_INP_SEL_RX3,
244 INTn_1_MIX_INP_SEL_RX4,
245 INTn_1_MIX_INP_SEL_RX5,
246 INTn_1_MIX_INP_SEL_RX6,
247 INTn_1_MIX_INP_SEL_RX7,
248
249 };
250
251 enum {
252 INTERP_EAR = 0,
253 INTERP_HPHL,
254 INTERP_HPHR,
255 INTERP_LO1,
256 INTERP_LO2,
257 INTERP_LO3,
258 INTERP_LO4,
259 INTERP_SPKR1,
260 INTERP_SPKR2,
261 };
262
263 enum wcd_clock_type {
264 WCD_CLK_OFF,
265 WCD_CLK_RCO,
266 WCD_CLK_MCLK,
267 };
268
269 enum {
270 MIC_BIAS_1 = 1,
271 MIC_BIAS_2,
272 MIC_BIAS_3,
273 MIC_BIAS_4
274 };
275
276 enum {
277 MICB_PULLUP_ENABLE,
278 MICB_PULLUP_DISABLE,
279 MICB_ENABLE,
280 MICB_DISABLE,
281 };
282
283 struct wcd9335_slim_ch {
284 u32 ch_num;
285 u16 port;
286 u16 shift;
287 struct list_head list;
288 };
289
290 struct wcd_slim_codec_dai_data {
291 struct list_head slim_ch_list;
292 struct slim_stream_config sconfig;
293 struct slim_stream_runtime *sruntime;
294 };
295
296 struct wcd9335_codec {
297 struct device *dev;
298 struct clk *mclk;
299 struct clk *native_clk;
300 u32 mclk_rate;
301
302 struct slim_device *slim;
303 struct slim_device *slim_ifc_dev;
304 struct regmap *regmap;
305 struct regmap *if_regmap;
306 struct regmap_irq_chip_data *irq_data;
307
308 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
309 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
310 u32 num_rx_port;
311 u32 num_tx_port;
312
313 int sido_input_src;
314 enum wcd9335_sido_voltage sido_voltage;
315
316 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
317 struct snd_soc_component *component;
318
319 int master_bias_users;
320 int clk_mclk_users;
321 int clk_rco_users;
322 int sido_ccl_cnt;
323 enum wcd_clock_type clk_type;
324
325 struct wcd_clsh_ctrl *clsh_ctrl;
326 u32 hph_mode;
327 int prim_int_users[WCD9335_NUM_INTERPOLATORS];
328
329 int comp_enabled[COMPANDER_MAX];
330
331 int intr1;
332 struct gpio_desc *reset_gpio;
333
334 unsigned int rx_port_value[WCD9335_RX_MAX];
335 unsigned int tx_port_value[WCD9335_TX_MAX];
336 int hph_l_gain;
337 int hph_r_gain;
338 u32 rx_bias_count;
339
340 /*TX*/
341 int micb_ref[WCD9335_MAX_MICBIAS];
342 int pullup_ref[WCD9335_MAX_MICBIAS];
343
344 int dmic_0_1_clk_cnt;
345 int dmic_2_3_clk_cnt;
346 int dmic_4_5_clk_cnt;
347 };
348
349 struct wcd9335_irq {
350 int irq;
351 irqreturn_t (*handler)(int irq, void *data);
352 char *name;
353 };
354
355 static const char * const wcd9335_supplies[] = {
356 "vdd-buck", "vdd-buck-sido", "vdd-tx", "vdd-rx", "vdd-io",
357 };
358
359 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
360 WCD9335_SLIM_TX_CH(0),
361 WCD9335_SLIM_TX_CH(1),
362 WCD9335_SLIM_TX_CH(2),
363 WCD9335_SLIM_TX_CH(3),
364 WCD9335_SLIM_TX_CH(4),
365 WCD9335_SLIM_TX_CH(5),
366 WCD9335_SLIM_TX_CH(6),
367 WCD9335_SLIM_TX_CH(7),
368 WCD9335_SLIM_TX_CH(8),
369 WCD9335_SLIM_TX_CH(9),
370 WCD9335_SLIM_TX_CH(10),
371 WCD9335_SLIM_TX_CH(11),
372 WCD9335_SLIM_TX_CH(12),
373 WCD9335_SLIM_TX_CH(13),
374 WCD9335_SLIM_TX_CH(14),
375 WCD9335_SLIM_TX_CH(15),
376 };
377
378 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
379 WCD9335_SLIM_RX_CH(0), /* 16 */
380 WCD9335_SLIM_RX_CH(1), /* 17 */
381 WCD9335_SLIM_RX_CH(2),
382 WCD9335_SLIM_RX_CH(3),
383 WCD9335_SLIM_RX_CH(4),
384 WCD9335_SLIM_RX_CH(5),
385 WCD9335_SLIM_RX_CH(6),
386 WCD9335_SLIM_RX_CH(7),
387 WCD9335_SLIM_RX_CH(8),
388 WCD9335_SLIM_RX_CH(9),
389 WCD9335_SLIM_RX_CH(10),
390 WCD9335_SLIM_RX_CH(11),
391 WCD9335_SLIM_RX_CH(12),
392 };
393
394 struct interp_sample_rate {
395 int rate;
396 int rate_val;
397 };
398
399 static const struct interp_sample_rate int_mix_rate_val[] = {
400 {48000, 0x4}, /* 48K */
401 {96000, 0x5}, /* 96K */
402 {192000, 0x6}, /* 192K */
403 };
404
405 static const struct interp_sample_rate int_prim_rate_val[] = {
406 {8000, 0x0}, /* 8K */
407 {16000, 0x1}, /* 16K */
408 {24000, -EINVAL},/* 24K */
409 {32000, 0x3}, /* 32K */
410 {48000, 0x4}, /* 48K */
411 {96000, 0x5}, /* 96K */
412 {192000, 0x6}, /* 192K */
413 {384000, 0x7}, /* 384K */
414 {44100, 0x8}, /* 44.1K */
415 };
416
417 struct wcd9335_reg_mask_val {
418 u16 reg;
419 u8 mask;
420 u8 val;
421 };
422
423 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
424 /* Rbuckfly/R_EAR(32) */
425 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
426 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
427 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
428 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
429 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
430 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
431 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
432 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
433 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
434 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
435 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
436 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
437 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
438 {WCD9335_EAR_CMBUFF, 0x08, 0x00},
439 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
440 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
441 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
442 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
443 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
444 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
445 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
446 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
447 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
448 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
449 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
450 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
451 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
452 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
453 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
454 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
455 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
456 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
457 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
458 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
459 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
460 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
461 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
462 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
463 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
464 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
465 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
466 {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
467 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
468 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
469 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
470 {WCD9335_HPH_L_TEST, 0x01, 0x01},
471 {WCD9335_HPH_R_TEST, 0x01, 0x01},
472 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
473 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
474 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
475 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
476 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
477 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
478 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
479 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
480 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
481 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
482 };
483
484 /* Cutoff frequency for high pass filter */
485 static const char * const cf_text[] = {
486 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
487 };
488
489 static const char * const rx_cf_text[] = {
490 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
491 "CF_NEG_3DB_0P48HZ"
492 };
493
494 static const char * const rx_int0_7_mix_mux_text[] = {
495 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
496 "RX6", "RX7", "PROXIMITY"
497 };
498
499 static const char * const rx_int_mix_mux_text[] = {
500 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
501 "RX6", "RX7"
502 };
503
504 static const char * const rx_prim_mix_text[] = {
505 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
506 "RX3", "RX4", "RX5", "RX6", "RX7"
507 };
508
509 static const char * const rx_int_dem_inp_mux_text[] = {
510 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
511 };
512
513 static const char * const rx_int0_interp_mux_text[] = {
514 "ZERO", "RX INT0 MIX2",
515 };
516
517 static const char * const rx_int1_interp_mux_text[] = {
518 "ZERO", "RX INT1 MIX2",
519 };
520
521 static const char * const rx_int2_interp_mux_text[] = {
522 "ZERO", "RX INT2 MIX2",
523 };
524
525 static const char * const rx_int3_interp_mux_text[] = {
526 "ZERO", "RX INT3 MIX2",
527 };
528
529 static const char * const rx_int4_interp_mux_text[] = {
530 "ZERO", "RX INT4 MIX2",
531 };
532
533 static const char * const rx_int5_interp_mux_text[] = {
534 "ZERO", "RX INT5 MIX2",
535 };
536
537 static const char * const rx_int6_interp_mux_text[] = {
538 "ZERO", "RX INT6 MIX2",
539 };
540
541 static const char * const rx_int7_interp_mux_text[] = {
542 "ZERO", "RX INT7 MIX2",
543 };
544
545 static const char * const rx_int8_interp_mux_text[] = {
546 "ZERO", "RX INT8 SEC MIX"
547 };
548
549 static const char * const rx_hph_mode_mux_text[] = {
550 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
551 "Class-H Hi-Fi Low Power"
552 };
553
554 static const char *const slim_rx_mux_text[] = {
555 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
556 };
557
558 static const char * const adc_mux_text[] = {
559 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
560 };
561
562 static const char * const dmic_mux_text[] = {
563 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
564 "SMIC0", "SMIC1", "SMIC2", "SMIC3"
565 };
566
567 static const char * const dmic_mux_alt_text[] = {
568 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
569 };
570
571 static const char * const amic_mux_text[] = {
572 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
573 };
574
575 static const char * const sb_tx0_mux_text[] = {
576 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
577 };
578
579 static const char * const sb_tx1_mux_text[] = {
580 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
581 };
582
583 static const char * const sb_tx2_mux_text[] = {
584 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
585 };
586
587 static const char * const sb_tx3_mux_text[] = {
588 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
589 };
590
591 static const char * const sb_tx4_mux_text[] = {
592 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
593 };
594
595 static const char * const sb_tx5_mux_text[] = {
596 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
597 };
598
599 static const char * const sb_tx6_mux_text[] = {
600 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
601 };
602
603 static const char * const sb_tx7_mux_text[] = {
604 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
605 };
606
607 static const char * const sb_tx8_mux_text[] = {
608 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
609 };
610
611 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
612 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
613 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
614 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
615
616 static const struct soc_enum cf_dec0_enum =
617 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
618
619 static const struct soc_enum cf_dec1_enum =
620 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
621
622 static const struct soc_enum cf_dec2_enum =
623 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
624
625 static const struct soc_enum cf_dec3_enum =
626 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
627
628 static const struct soc_enum cf_dec4_enum =
629 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
630
631 static const struct soc_enum cf_dec5_enum =
632 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
633
634 static const struct soc_enum cf_dec6_enum =
635 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
636
637 static const struct soc_enum cf_dec7_enum =
638 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
639
640 static const struct soc_enum cf_dec8_enum =
641 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
642
643 static const struct soc_enum cf_int0_1_enum =
644 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
645
646 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
647 rx_cf_text);
648
649 static const struct soc_enum cf_int1_1_enum =
650 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
651
652 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
653 rx_cf_text);
654
655 static const struct soc_enum cf_int2_1_enum =
656 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
657
658 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
659 rx_cf_text);
660
661 static const struct soc_enum cf_int3_1_enum =
662 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
663
664 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
665 rx_cf_text);
666
667 static const struct soc_enum cf_int4_1_enum =
668 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
669
670 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
671 rx_cf_text);
672
673 static const struct soc_enum cf_int5_1_enum =
674 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
675
676 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
677 rx_cf_text);
678
679 static const struct soc_enum cf_int6_1_enum =
680 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
681
682 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
683 rx_cf_text);
684
685 static const struct soc_enum cf_int7_1_enum =
686 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
687
688 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
689 rx_cf_text);
690
691 static const struct soc_enum cf_int8_1_enum =
692 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
693
694 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
695 rx_cf_text);
696
697 static const struct soc_enum rx_hph_mode_mux_enum =
698 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
699 rx_hph_mode_mux_text);
700
701 static const struct soc_enum slim_rx_mux_enum =
702 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
703
704 static const struct soc_enum rx_int0_2_mux_chain_enum =
705 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
706 rx_int0_7_mix_mux_text);
707
708 static const struct soc_enum rx_int1_2_mux_chain_enum =
709 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
710 rx_int_mix_mux_text);
711
712 static const struct soc_enum rx_int2_2_mux_chain_enum =
713 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
714 rx_int_mix_mux_text);
715
716 static const struct soc_enum rx_int3_2_mux_chain_enum =
717 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
718 rx_int_mix_mux_text);
719
720 static const struct soc_enum rx_int4_2_mux_chain_enum =
721 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
722 rx_int_mix_mux_text);
723
724 static const struct soc_enum rx_int5_2_mux_chain_enum =
725 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
726 rx_int_mix_mux_text);
727
728 static const struct soc_enum rx_int6_2_mux_chain_enum =
729 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
730 rx_int_mix_mux_text);
731
732 static const struct soc_enum rx_int7_2_mux_chain_enum =
733 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
734 rx_int0_7_mix_mux_text);
735
736 static const struct soc_enum rx_int8_2_mux_chain_enum =
737 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
738 rx_int_mix_mux_text);
739
740 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
741 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
742 rx_prim_mix_text);
743
744 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
745 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
746 rx_prim_mix_text);
747
748 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
749 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
750 rx_prim_mix_text);
751
752 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
753 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
754 rx_prim_mix_text);
755
756 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
757 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
758 rx_prim_mix_text);
759
760 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
761 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
762 rx_prim_mix_text);
763
764 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
765 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
766 rx_prim_mix_text);
767
768 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
769 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
770 rx_prim_mix_text);
771
772 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
773 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
774 rx_prim_mix_text);
775
776 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
777 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
778 rx_prim_mix_text);
779
780 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
781 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
782 rx_prim_mix_text);
783
784 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
785 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
786 rx_prim_mix_text);
787
788 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
789 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
790 rx_prim_mix_text);
791
792 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
793 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
794 rx_prim_mix_text);
795
796 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
797 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
798 rx_prim_mix_text);
799
800 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
801 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
802 rx_prim_mix_text);
803
804 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
805 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
806 rx_prim_mix_text);
807
808 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
809 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
810 rx_prim_mix_text);
811
812 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
813 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
814 rx_prim_mix_text);
815
816 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
817 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
818 rx_prim_mix_text);
819
820 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
821 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
822 rx_prim_mix_text);
823
824 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
825 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
826 rx_prim_mix_text);
827
828 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
829 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
830 rx_prim_mix_text);
831
832 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
833 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
834 rx_prim_mix_text);
835
836 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
837 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
838 rx_prim_mix_text);
839
840 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
841 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
842 rx_prim_mix_text);
843
844 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
845 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
846 rx_prim_mix_text);
847
848 static const struct soc_enum rx_int0_dem_inp_mux_enum =
849 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
850 ARRAY_SIZE(rx_int_dem_inp_mux_text),
851 rx_int_dem_inp_mux_text);
852
853 static const struct soc_enum rx_int1_dem_inp_mux_enum =
854 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
855 ARRAY_SIZE(rx_int_dem_inp_mux_text),
856 rx_int_dem_inp_mux_text);
857
858 static const struct soc_enum rx_int2_dem_inp_mux_enum =
859 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
860 ARRAY_SIZE(rx_int_dem_inp_mux_text),
861 rx_int_dem_inp_mux_text);
862
863 static const struct soc_enum rx_int0_interp_mux_enum =
864 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
865 rx_int0_interp_mux_text);
866
867 static const struct soc_enum rx_int1_interp_mux_enum =
868 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
869 rx_int1_interp_mux_text);
870
871 static const struct soc_enum rx_int2_interp_mux_enum =
872 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
873 rx_int2_interp_mux_text);
874
875 static const struct soc_enum rx_int3_interp_mux_enum =
876 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
877 rx_int3_interp_mux_text);
878
879 static const struct soc_enum rx_int4_interp_mux_enum =
880 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
881 rx_int4_interp_mux_text);
882
883 static const struct soc_enum rx_int5_interp_mux_enum =
884 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
885 rx_int5_interp_mux_text);
886
887 static const struct soc_enum rx_int6_interp_mux_enum =
888 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
889 rx_int6_interp_mux_text);
890
891 static const struct soc_enum rx_int7_interp_mux_enum =
892 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
893 rx_int7_interp_mux_text);
894
895 static const struct soc_enum rx_int8_interp_mux_enum =
896 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
897 rx_int8_interp_mux_text);
898
899 static const struct soc_enum tx_adc_mux0_chain_enum =
900 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
901 adc_mux_text);
902
903 static const struct soc_enum tx_adc_mux1_chain_enum =
904 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
905 adc_mux_text);
906
907 static const struct soc_enum tx_adc_mux2_chain_enum =
908 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
909 adc_mux_text);
910
911 static const struct soc_enum tx_adc_mux3_chain_enum =
912 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
913 adc_mux_text);
914
915 static const struct soc_enum tx_adc_mux4_chain_enum =
916 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
917 adc_mux_text);
918
919 static const struct soc_enum tx_adc_mux5_chain_enum =
920 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
921 adc_mux_text);
922
923 static const struct soc_enum tx_adc_mux6_chain_enum =
924 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
925 adc_mux_text);
926
927 static const struct soc_enum tx_adc_mux7_chain_enum =
928 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
929 adc_mux_text);
930
931 static const struct soc_enum tx_adc_mux8_chain_enum =
932 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
933 adc_mux_text);
934
935 static const struct soc_enum tx_dmic_mux0_enum =
936 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
937 dmic_mux_text);
938
939 static const struct soc_enum tx_dmic_mux1_enum =
940 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
941 dmic_mux_text);
942
943 static const struct soc_enum tx_dmic_mux2_enum =
944 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
945 dmic_mux_text);
946
947 static const struct soc_enum tx_dmic_mux3_enum =
948 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
949 dmic_mux_text);
950
951 static const struct soc_enum tx_dmic_mux4_enum =
952 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
953 dmic_mux_alt_text);
954
955 static const struct soc_enum tx_dmic_mux5_enum =
956 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
957 dmic_mux_alt_text);
958
959 static const struct soc_enum tx_dmic_mux6_enum =
960 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
961 dmic_mux_alt_text);
962
963 static const struct soc_enum tx_dmic_mux7_enum =
964 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
965 dmic_mux_alt_text);
966
967 static const struct soc_enum tx_dmic_mux8_enum =
968 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
969 dmic_mux_alt_text);
970
971 static const struct soc_enum tx_amic_mux0_enum =
972 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
973 amic_mux_text);
974
975 static const struct soc_enum tx_amic_mux1_enum =
976 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
977 amic_mux_text);
978
979 static const struct soc_enum tx_amic_mux2_enum =
980 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
981 amic_mux_text);
982
983 static const struct soc_enum tx_amic_mux3_enum =
984 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
985 amic_mux_text);
986
987 static const struct soc_enum tx_amic_mux4_enum =
988 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
989 amic_mux_text);
990
991 static const struct soc_enum tx_amic_mux5_enum =
992 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
993 amic_mux_text);
994
995 static const struct soc_enum tx_amic_mux6_enum =
996 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
997 amic_mux_text);
998
999 static const struct soc_enum tx_amic_mux7_enum =
1000 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1001 amic_mux_text);
1002
1003 static const struct soc_enum tx_amic_mux8_enum =
1004 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1005 amic_mux_text);
1006
1007 static const struct soc_enum sb_tx0_mux_enum =
1008 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1009 sb_tx0_mux_text);
1010
1011 static const struct soc_enum sb_tx1_mux_enum =
1012 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1013 sb_tx1_mux_text);
1014
1015 static const struct soc_enum sb_tx2_mux_enum =
1016 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1017 sb_tx2_mux_text);
1018
1019 static const struct soc_enum sb_tx3_mux_enum =
1020 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1021 sb_tx3_mux_text);
1022
1023 static const struct soc_enum sb_tx4_mux_enum =
1024 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1025 sb_tx4_mux_text);
1026
1027 static const struct soc_enum sb_tx5_mux_enum =
1028 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1029 sb_tx5_mux_text);
1030
1031 static const struct soc_enum sb_tx6_mux_enum =
1032 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1033 sb_tx6_mux_text);
1034
1035 static const struct soc_enum sb_tx7_mux_enum =
1036 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1037 sb_tx7_mux_text);
1038
1039 static const struct soc_enum sb_tx8_mux_enum =
1040 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1041 sb_tx8_mux_text);
1042
1043 static const struct snd_kcontrol_new rx_int0_2_mux =
1044 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1045
1046 static const struct snd_kcontrol_new rx_int1_2_mux =
1047 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1048
1049 static const struct snd_kcontrol_new rx_int2_2_mux =
1050 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1051
1052 static const struct snd_kcontrol_new rx_int3_2_mux =
1053 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1054
1055 static const struct snd_kcontrol_new rx_int4_2_mux =
1056 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1057
1058 static const struct snd_kcontrol_new rx_int5_2_mux =
1059 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1060
1061 static const struct snd_kcontrol_new rx_int6_2_mux =
1062 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1063
1064 static const struct snd_kcontrol_new rx_int7_2_mux =
1065 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1066
1067 static const struct snd_kcontrol_new rx_int8_2_mux =
1068 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1069
1070 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1071 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1072
1073 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1074 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1075
1076 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1077 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1078
1079 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1080 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1081
1082 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1083 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1084
1085 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1086 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1087
1088 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1089 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1090
1091 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1092 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1093
1094 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1095 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1096
1097 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1098 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1099
1100 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1101 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1102
1103 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1104 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1105
1106 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1107 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1108
1109 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1110 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1111
1112 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1113 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1114
1115 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1116 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1117
1118 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1119 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1120
1121 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1122 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1123
1124 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1125 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1126
1127 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1128 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1129
1130 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1131 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1132
1133 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1134 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1135
1136 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1137 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1138
1139 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1140 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1141
1142 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1143 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1144
1145 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1146 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1147
1148 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1149 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1150
1151 static const struct snd_kcontrol_new rx_int0_interp_mux =
1152 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1153
1154 static const struct snd_kcontrol_new rx_int1_interp_mux =
1155 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1156
1157 static const struct snd_kcontrol_new rx_int2_interp_mux =
1158 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1159
1160 static const struct snd_kcontrol_new rx_int3_interp_mux =
1161 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1162
1163 static const struct snd_kcontrol_new rx_int4_interp_mux =
1164 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1165
1166 static const struct snd_kcontrol_new rx_int5_interp_mux =
1167 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1168
1169 static const struct snd_kcontrol_new rx_int6_interp_mux =
1170 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1171
1172 static const struct snd_kcontrol_new rx_int7_interp_mux =
1173 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1174
1175 static const struct snd_kcontrol_new rx_int8_interp_mux =
1176 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1177
1178 static const struct snd_kcontrol_new tx_dmic_mux0 =
1179 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1180
1181 static const struct snd_kcontrol_new tx_dmic_mux1 =
1182 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1183
1184 static const struct snd_kcontrol_new tx_dmic_mux2 =
1185 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1186
1187 static const struct snd_kcontrol_new tx_dmic_mux3 =
1188 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1189
1190 static const struct snd_kcontrol_new tx_dmic_mux4 =
1191 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1192
1193 static const struct snd_kcontrol_new tx_dmic_mux5 =
1194 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1195
1196 static const struct snd_kcontrol_new tx_dmic_mux6 =
1197 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1198
1199 static const struct snd_kcontrol_new tx_dmic_mux7 =
1200 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1201
1202 static const struct snd_kcontrol_new tx_dmic_mux8 =
1203 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1204
1205 static const struct snd_kcontrol_new tx_amic_mux0 =
1206 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1207
1208 static const struct snd_kcontrol_new tx_amic_mux1 =
1209 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1210
1211 static const struct snd_kcontrol_new tx_amic_mux2 =
1212 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1213
1214 static const struct snd_kcontrol_new tx_amic_mux3 =
1215 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1216
1217 static const struct snd_kcontrol_new tx_amic_mux4 =
1218 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1219
1220 static const struct snd_kcontrol_new tx_amic_mux5 =
1221 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1222
1223 static const struct snd_kcontrol_new tx_amic_mux6 =
1224 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1225
1226 static const struct snd_kcontrol_new tx_amic_mux7 =
1227 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1228
1229 static const struct snd_kcontrol_new tx_amic_mux8 =
1230 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1231
1232 static const struct snd_kcontrol_new sb_tx0_mux =
1233 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1234
1235 static const struct snd_kcontrol_new sb_tx1_mux =
1236 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1237
1238 static const struct snd_kcontrol_new sb_tx2_mux =
1239 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1240
1241 static const struct snd_kcontrol_new sb_tx3_mux =
1242 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1243
1244 static const struct snd_kcontrol_new sb_tx4_mux =
1245 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1246
1247 static const struct snd_kcontrol_new sb_tx5_mux =
1248 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1249
1250 static const struct snd_kcontrol_new sb_tx6_mux =
1251 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1252
1253 static const struct snd_kcontrol_new sb_tx7_mux =
1254 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1255
1256 static const struct snd_kcontrol_new sb_tx8_mux =
1257 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1258
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1259 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1260 struct snd_ctl_elem_value *ucontrol)
1261 {
1262 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1263 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1264 u32 port_id = w->shift;
1265
1266 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1267
1268 return 0;
1269 }
1270
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1271 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1272 struct snd_ctl_elem_value *ucontrol)
1273 {
1274 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1275 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1276 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1277 struct snd_soc_dapm_update *update = NULL;
1278 u32 port_id = w->shift;
1279
1280 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1281 return 0;
1282
1283 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1284
1285 /* Remove channel from any list it's in before adding it to a new one */
1286 list_del_init(&wcd->rx_chs[port_id].list);
1287
1288 switch (wcd->rx_port_value[port_id]) {
1289 case 0:
1290 /* Channel already removed from lists. Nothing to do here */
1291 break;
1292 case 1:
1293 list_add_tail(&wcd->rx_chs[port_id].list,
1294 &wcd->dai[AIF1_PB].slim_ch_list);
1295 break;
1296 case 2:
1297 list_add_tail(&wcd->rx_chs[port_id].list,
1298 &wcd->dai[AIF2_PB].slim_ch_list);
1299 break;
1300 case 3:
1301 list_add_tail(&wcd->rx_chs[port_id].list,
1302 &wcd->dai[AIF3_PB].slim_ch_list);
1303 break;
1304 case 4:
1305 list_add_tail(&wcd->rx_chs[port_id].list,
1306 &wcd->dai[AIF4_PB].slim_ch_list);
1307 break;
1308 default:
1309 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1310 goto err;
1311 }
1312
1313 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1314 e, update);
1315
1316 return 0;
1317 err:
1318 return -EINVAL;
1319 }
1320
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1321 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1322 struct snd_ctl_elem_value *ucontrol)
1323 {
1324
1325 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1326 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1327 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1328 struct soc_mixer_control *mixer =
1329 (struct soc_mixer_control *)kc->private_value;
1330 int dai_id = widget->shift;
1331 int port_id = mixer->shift;
1332
1333 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
1334
1335 return 0;
1336 }
1337
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1338 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1339 struct snd_ctl_elem_value *ucontrol)
1340 {
1341
1342 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1343 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1344 struct snd_soc_dapm_update *update = NULL;
1345 struct soc_mixer_control *mixer =
1346 (struct soc_mixer_control *)kc->private_value;
1347 int enable = ucontrol->value.integer.value[0];
1348 int dai_id = widget->shift;
1349 int port_id = mixer->shift;
1350
1351 switch (dai_id) {
1352 case AIF1_CAP:
1353 case AIF2_CAP:
1354 case AIF3_CAP:
1355 /* only add to the list if value not set */
1356 if (enable && wcd->tx_port_value[port_id] != dai_id) {
1357 wcd->tx_port_value[port_id] = dai_id;
1358 list_add_tail(&wcd->tx_chs[port_id].list,
1359 &wcd->dai[dai_id].slim_ch_list);
1360 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
1361 wcd->tx_port_value[port_id] = -1;
1362 list_del_init(&wcd->tx_chs[port_id].list);
1363 }
1364 break;
1365 default:
1366 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1367 return -EINVAL;
1368 }
1369
1370 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1371
1372 return 0;
1373 }
1374
1375 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1376 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1377 slim_rx_mux_get, slim_rx_mux_put),
1378 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1379 slim_rx_mux_get, slim_rx_mux_put),
1380 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1381 slim_rx_mux_get, slim_rx_mux_put),
1382 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1383 slim_rx_mux_get, slim_rx_mux_put),
1384 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1385 slim_rx_mux_get, slim_rx_mux_put),
1386 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1387 slim_rx_mux_get, slim_rx_mux_put),
1388 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1389 slim_rx_mux_get, slim_rx_mux_put),
1390 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1391 slim_rx_mux_get, slim_rx_mux_put),
1392 };
1393
1394 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1395 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1396 slim_tx_mixer_get, slim_tx_mixer_put),
1397 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1398 slim_tx_mixer_get, slim_tx_mixer_put),
1399 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1400 slim_tx_mixer_get, slim_tx_mixer_put),
1401 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1402 slim_tx_mixer_get, slim_tx_mixer_put),
1403 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1404 slim_tx_mixer_get, slim_tx_mixer_put),
1405 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1406 slim_tx_mixer_get, slim_tx_mixer_put),
1407 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1408 slim_tx_mixer_get, slim_tx_mixer_put),
1409 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1410 slim_tx_mixer_get, slim_tx_mixer_put),
1411 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1412 slim_tx_mixer_get, slim_tx_mixer_put),
1413 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1414 slim_tx_mixer_get, slim_tx_mixer_put),
1415 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1416 slim_tx_mixer_get, slim_tx_mixer_put),
1417 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1418 slim_tx_mixer_get, slim_tx_mixer_put),
1419 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1420 slim_tx_mixer_get, slim_tx_mixer_put),
1421 };
1422
1423 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1424 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1425 slim_tx_mixer_get, slim_tx_mixer_put),
1426 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1427 slim_tx_mixer_get, slim_tx_mixer_put),
1428 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1429 slim_tx_mixer_get, slim_tx_mixer_put),
1430 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1431 slim_tx_mixer_get, slim_tx_mixer_put),
1432 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1433 slim_tx_mixer_get, slim_tx_mixer_put),
1434 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1435 slim_tx_mixer_get, slim_tx_mixer_put),
1436 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1437 slim_tx_mixer_get, slim_tx_mixer_put),
1438 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1439 slim_tx_mixer_get, slim_tx_mixer_put),
1440 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1441 slim_tx_mixer_get, slim_tx_mixer_put),
1442 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1443 slim_tx_mixer_get, slim_tx_mixer_put),
1444 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1445 slim_tx_mixer_get, slim_tx_mixer_put),
1446 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1447 slim_tx_mixer_get, slim_tx_mixer_put),
1448 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1449 slim_tx_mixer_get, slim_tx_mixer_put),
1450 };
1451
1452 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1453 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1454 slim_tx_mixer_get, slim_tx_mixer_put),
1455 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1456 slim_tx_mixer_get, slim_tx_mixer_put),
1457 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1458 slim_tx_mixer_get, slim_tx_mixer_put),
1459 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1460 slim_tx_mixer_get, slim_tx_mixer_put),
1461 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1462 slim_tx_mixer_get, slim_tx_mixer_put),
1463 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1464 slim_tx_mixer_get, slim_tx_mixer_put),
1465 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1466 slim_tx_mixer_get, slim_tx_mixer_put),
1467 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1468 slim_tx_mixer_get, slim_tx_mixer_put),
1469 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1470 slim_tx_mixer_get, slim_tx_mixer_put),
1471 };
1472
wcd9335_put_dec_enum(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1473 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1474 struct snd_ctl_elem_value *ucontrol)
1475 {
1476 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1477 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1478 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1479 unsigned int val, reg, sel;
1480
1481 val = ucontrol->value.enumerated.item[0];
1482
1483 switch (e->reg) {
1484 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1485 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1486 break;
1487 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1488 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1489 break;
1490 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1491 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1492 break;
1493 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1494 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1495 break;
1496 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1497 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1498 break;
1499 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1500 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1501 break;
1502 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1503 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1504 break;
1505 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1506 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1507 break;
1508 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1509 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1510 break;
1511 default:
1512 return -EINVAL;
1513 }
1514
1515 /* AMIC: 0, DMIC: 1 */
1516 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1517 snd_soc_component_update_bits(component, reg,
1518 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1519 sel);
1520
1521 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1522 }
1523
wcd9335_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1524 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1525 struct snd_ctl_elem_value *ucontrol)
1526 {
1527 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1528 struct snd_soc_component *component;
1529 int reg, val;
1530
1531 component = snd_soc_dapm_kcontrol_component(kc);
1532 val = ucontrol->value.enumerated.item[0];
1533
1534 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1535 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1536 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1537 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1538 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1539 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1540 else
1541 return -EINVAL;
1542
1543 /* Set Look Ahead Delay */
1544 snd_soc_component_update_bits(component, reg,
1545 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1546 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1547 /* Set DEM INP Select */
1548 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1549 }
1550
1551 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1552 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1553 snd_soc_dapm_get_enum_double,
1554 wcd9335_int_dem_inp_mux_put);
1555
1556 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1557 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1558 snd_soc_dapm_get_enum_double,
1559 wcd9335_int_dem_inp_mux_put);
1560
1561 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1562 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1563 snd_soc_dapm_get_enum_double,
1564 wcd9335_int_dem_inp_mux_put);
1565
1566 static const struct snd_kcontrol_new tx_adc_mux0 =
1567 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1568 snd_soc_dapm_get_enum_double,
1569 wcd9335_put_dec_enum);
1570
1571 static const struct snd_kcontrol_new tx_adc_mux1 =
1572 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1573 snd_soc_dapm_get_enum_double,
1574 wcd9335_put_dec_enum);
1575
1576 static const struct snd_kcontrol_new tx_adc_mux2 =
1577 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1578 snd_soc_dapm_get_enum_double,
1579 wcd9335_put_dec_enum);
1580
1581 static const struct snd_kcontrol_new tx_adc_mux3 =
1582 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1583 snd_soc_dapm_get_enum_double,
1584 wcd9335_put_dec_enum);
1585
1586 static const struct snd_kcontrol_new tx_adc_mux4 =
1587 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1588 snd_soc_dapm_get_enum_double,
1589 wcd9335_put_dec_enum);
1590
1591 static const struct snd_kcontrol_new tx_adc_mux5 =
1592 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1593 snd_soc_dapm_get_enum_double,
1594 wcd9335_put_dec_enum);
1595
1596 static const struct snd_kcontrol_new tx_adc_mux6 =
1597 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1598 snd_soc_dapm_get_enum_double,
1599 wcd9335_put_dec_enum);
1600
1601 static const struct snd_kcontrol_new tx_adc_mux7 =
1602 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1603 snd_soc_dapm_get_enum_double,
1604 wcd9335_put_dec_enum);
1605
1606 static const struct snd_kcontrol_new tx_adc_mux8 =
1607 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1608 snd_soc_dapm_get_enum_double,
1609 wcd9335_put_dec_enum);
1610
wcd9335_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1611 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1612 int rate_val,
1613 u32 rate)
1614 {
1615 struct snd_soc_component *component = dai->component;
1616 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1617 struct wcd9335_slim_ch *ch;
1618 int val, j;
1619
1620 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1621 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1622 val = snd_soc_component_read(component,
1623 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1624 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1625
1626 if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1627 snd_soc_component_update_bits(component,
1628 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1629 WCD9335_CDC_MIX_PCM_RATE_MASK,
1630 rate_val);
1631 }
1632 }
1633
1634 return 0;
1635 }
1636
wcd9335_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1637 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1638 u8 rate_val,
1639 u32 rate)
1640 {
1641 struct snd_soc_component *comp = dai->component;
1642 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1643 struct wcd9335_slim_ch *ch;
1644 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1645 int inp, j;
1646
1647 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1648 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1649 /*
1650 * Loop through all interpolator MUX inputs and find out
1651 * to which interpolator input, the slim rx port
1652 * is connected
1653 */
1654 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1655 cfg0 = snd_soc_component_read(comp,
1656 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1657 cfg1 = snd_soc_component_read(comp,
1658 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1659
1660 inp0_sel = cfg0 &
1661 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1662 inp1_sel = (cfg0 >> 4) &
1663 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1664 inp2_sel = (cfg1 >> 4) &
1665 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1666
1667 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1668 (inp2_sel == inp)) {
1669 /* rate is in Hz */
1670 if ((j == 0) && (rate == 44100))
1671 dev_info(wcd->dev,
1672 "Cannot set 44.1KHz on INT0\n");
1673 else
1674 snd_soc_component_update_bits(comp,
1675 WCD9335_CDC_RX_PATH_CTL(j),
1676 WCD9335_CDC_MIX_PCM_RATE_MASK,
1677 rate_val);
1678 }
1679 }
1680 }
1681
1682 return 0;
1683 }
1684
wcd9335_set_interpolator_rate(struct snd_soc_dai * dai,u32 rate)1685 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1686 {
1687 int i;
1688
1689 /* set mixing path rate */
1690 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1691 if (rate == int_mix_rate_val[i].rate) {
1692 wcd9335_set_mix_interpolator_rate(dai,
1693 int_mix_rate_val[i].rate_val, rate);
1694 break;
1695 }
1696 }
1697
1698 /* set primary path sample rate */
1699 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1700 if (rate == int_prim_rate_val[i].rate) {
1701 wcd9335_set_prim_interpolator_rate(dai,
1702 int_prim_rate_val[i].rate_val, rate);
1703 break;
1704 }
1705 }
1706
1707 return 0;
1708 }
1709
wcd9335_slim_set_hw_params(struct wcd9335_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1710 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1711 struct wcd_slim_codec_dai_data *dai_data,
1712 int direction)
1713 {
1714 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1715 struct slim_stream_config *cfg = &dai_data->sconfig;
1716 struct wcd9335_slim_ch *ch;
1717 u16 payload = 0;
1718 int ret, i;
1719
1720 cfg->ch_count = 0;
1721 cfg->direction = direction;
1722 cfg->port_mask = 0;
1723
1724 /* Configure slave interface device */
1725 list_for_each_entry(ch, slim_ch_list, list) {
1726 cfg->ch_count++;
1727 payload |= 1 << ch->shift;
1728 cfg->port_mask |= BIT(ch->port);
1729 }
1730
1731 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1732 if (!cfg->chs)
1733 return -ENOMEM;
1734
1735 i = 0;
1736 list_for_each_entry(ch, slim_ch_list, list) {
1737 cfg->chs[i++] = ch->ch_num;
1738 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1739 /* write to interface device */
1740 ret = regmap_write(wcd->if_regmap,
1741 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1742 payload);
1743
1744 if (ret < 0)
1745 goto err;
1746
1747 /* configure the slave port for water mark and enable*/
1748 ret = regmap_write(wcd->if_regmap,
1749 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1750 WCD9335_SLIM_WATER_MARK_VAL);
1751 if (ret < 0)
1752 goto err;
1753 } else {
1754 ret = regmap_write(wcd->if_regmap,
1755 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1756 payload & 0x00FF);
1757 if (ret < 0)
1758 goto err;
1759
1760 /* ports 8,9 */
1761 ret = regmap_write(wcd->if_regmap,
1762 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1763 (payload & 0xFF00)>>8);
1764 if (ret < 0)
1765 goto err;
1766
1767 /* configure the slave port for water mark and enable*/
1768 ret = regmap_write(wcd->if_regmap,
1769 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1770 WCD9335_SLIM_WATER_MARK_VAL);
1771
1772 if (ret < 0)
1773 goto err;
1774 }
1775 }
1776
1777 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1778
1779 return 0;
1780
1781 err:
1782 dev_err(wcd->dev, "Error Setting slim hw params\n");
1783 kfree(cfg->chs);
1784 cfg->chs = NULL;
1785
1786 return ret;
1787 }
1788
wcd9335_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1789 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1790 u8 rate_val, u32 rate)
1791 {
1792 struct snd_soc_component *comp = dai->component;
1793 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1794 u8 shift = 0, shift_val = 0, tx_mux_sel;
1795 struct wcd9335_slim_ch *ch;
1796 int tx_port, tx_port_reg;
1797 int decimator = -1;
1798
1799 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1800 tx_port = ch->port;
1801 if ((tx_port == 12) || (tx_port >= 14)) {
1802 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1803 tx_port, dai->id);
1804 return -EINVAL;
1805 }
1806 /* Find the SB TX MUX input - which decimator is connected */
1807 if (tx_port < 4) {
1808 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1809 shift = (tx_port << 1);
1810 shift_val = 0x03;
1811 } else if (tx_port < 8) {
1812 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1813 shift = ((tx_port - 4) << 1);
1814 shift_val = 0x03;
1815 } else if (tx_port < 11) {
1816 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1817 shift = ((tx_port - 8) << 1);
1818 shift_val = 0x03;
1819 } else if (tx_port == 11) {
1820 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1821 shift = 0;
1822 shift_val = 0x0F;
1823 } else /* (tx_port == 13) */ {
1824 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1825 shift = 4;
1826 shift_val = 0x03;
1827 }
1828
1829 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1830 (shift_val << shift);
1831
1832 tx_mux_sel = tx_mux_sel >> shift;
1833 if (tx_port <= 8) {
1834 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1835 decimator = tx_port;
1836 } else if (tx_port <= 10) {
1837 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1838 decimator = ((tx_port == 9) ? 7 : 6);
1839 } else if (tx_port == 11) {
1840 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1841 decimator = tx_mux_sel - 1;
1842 } else if (tx_port == 13) {
1843 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1844 decimator = 5;
1845 }
1846
1847 if (decimator >= 0) {
1848 snd_soc_component_update_bits(comp,
1849 WCD9335_CDC_TX_PATH_CTL(decimator),
1850 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1851 rate_val);
1852 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1853 /* Check if the TX Mux input is RX MIX TXn */
1854 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1855 tx_port, tx_port);
1856 } else {
1857 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1858 decimator);
1859 return -EINVAL;
1860 }
1861 }
1862
1863 return 0;
1864 }
1865
wcd9335_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1866 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1867 struct snd_pcm_hw_params *params,
1868 struct snd_soc_dai *dai)
1869 {
1870 struct wcd9335_codec *wcd;
1871 int ret, tx_fs_rate = 0;
1872
1873 wcd = snd_soc_component_get_drvdata(dai->component);
1874
1875 switch (substream->stream) {
1876 case SNDRV_PCM_STREAM_PLAYBACK:
1877 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1878 if (ret) {
1879 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1880 params_rate(params));
1881 return ret;
1882 }
1883 switch (params_width(params)) {
1884 case 16 ... 24:
1885 wcd->dai[dai->id].sconfig.bps = params_width(params);
1886 break;
1887 default:
1888 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1889 __func__, params_width(params));
1890 return -EINVAL;
1891 }
1892 break;
1893
1894 case SNDRV_PCM_STREAM_CAPTURE:
1895 switch (params_rate(params)) {
1896 case 8000:
1897 tx_fs_rate = 0;
1898 break;
1899 case 16000:
1900 tx_fs_rate = 1;
1901 break;
1902 case 32000:
1903 tx_fs_rate = 3;
1904 break;
1905 case 48000:
1906 tx_fs_rate = 4;
1907 break;
1908 case 96000:
1909 tx_fs_rate = 5;
1910 break;
1911 case 192000:
1912 tx_fs_rate = 6;
1913 break;
1914 case 384000:
1915 tx_fs_rate = 7;
1916 break;
1917 default:
1918 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1919 __func__, params_rate(params));
1920 return -EINVAL;
1921
1922 }
1923
1924 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1925 params_rate(params));
1926 if (ret < 0) {
1927 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1928 return ret;
1929 }
1930 switch (params_width(params)) {
1931 case 16 ... 32:
1932 wcd->dai[dai->id].sconfig.bps = params_width(params);
1933 break;
1934 default:
1935 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1936 __func__, params_width(params));
1937 return -EINVAL;
1938 }
1939 break;
1940 default:
1941 dev_err(wcd->dev, "Invalid stream type %d\n",
1942 substream->stream);
1943 return -EINVAL;
1944 }
1945
1946 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1947 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1948
1949 return 0;
1950 }
1951
wcd9335_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1952 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1953 struct snd_soc_dai *dai)
1954 {
1955 struct wcd_slim_codec_dai_data *dai_data;
1956 struct wcd9335_codec *wcd;
1957 struct slim_stream_config *cfg;
1958
1959 wcd = snd_soc_component_get_drvdata(dai->component);
1960
1961 dai_data = &wcd->dai[dai->id];
1962
1963 switch (cmd) {
1964 case SNDRV_PCM_TRIGGER_START:
1965 case SNDRV_PCM_TRIGGER_RESUME:
1966 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1967 cfg = &dai_data->sconfig;
1968 slim_stream_prepare(dai_data->sruntime, cfg);
1969 slim_stream_enable(dai_data->sruntime);
1970 break;
1971 case SNDRV_PCM_TRIGGER_STOP:
1972 case SNDRV_PCM_TRIGGER_SUSPEND:
1973 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1974 slim_stream_disable(dai_data->sruntime);
1975 slim_stream_unprepare(dai_data->sruntime);
1976 break;
1977 default:
1978 break;
1979 }
1980
1981 return 0;
1982 }
1983
wcd9335_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,const unsigned int * tx_slot,unsigned int rx_num,const unsigned int * rx_slot)1984 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1985 unsigned int tx_num,
1986 const unsigned int *tx_slot,
1987 unsigned int rx_num,
1988 const unsigned int *rx_slot)
1989 {
1990 struct wcd9335_codec *wcd;
1991 int i;
1992
1993 wcd = snd_soc_component_get_drvdata(dai->component);
1994
1995 if (!tx_slot || !rx_slot) {
1996 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1997 tx_slot, rx_slot);
1998 return -EINVAL;
1999 }
2000
2001 wcd->num_rx_port = rx_num;
2002 for (i = 0; i < rx_num; i++) {
2003 wcd->rx_chs[i].ch_num = rx_slot[i];
2004 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2005 }
2006
2007 wcd->num_tx_port = tx_num;
2008 for (i = 0; i < tx_num; i++) {
2009 wcd->tx_chs[i].ch_num = tx_slot[i];
2010 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2011 }
2012
2013 return 0;
2014 }
2015
wcd9335_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)2016 static int wcd9335_get_channel_map(const struct snd_soc_dai *dai,
2017 unsigned int *tx_num, unsigned int *tx_slot,
2018 unsigned int *rx_num, unsigned int *rx_slot)
2019 {
2020 struct wcd9335_slim_ch *ch;
2021 struct wcd9335_codec *wcd;
2022 int i = 0;
2023
2024 wcd = snd_soc_component_get_drvdata(dai->component);
2025
2026 switch (dai->id) {
2027 case AIF1_PB:
2028 case AIF2_PB:
2029 case AIF3_PB:
2030 case AIF4_PB:
2031 if (!rx_slot || !rx_num) {
2032 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2033 rx_slot, rx_num);
2034 return -EINVAL;
2035 }
2036
2037 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2038 rx_slot[i++] = ch->ch_num;
2039
2040 *rx_num = i;
2041 break;
2042 case AIF1_CAP:
2043 case AIF2_CAP:
2044 case AIF3_CAP:
2045 if (!tx_slot || !tx_num) {
2046 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2047 tx_slot, tx_num);
2048 return -EINVAL;
2049 }
2050 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2051 tx_slot[i++] = ch->ch_num;
2052
2053 *tx_num = i;
2054 break;
2055 default:
2056 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2057 break;
2058 }
2059
2060 return 0;
2061 }
2062
2063 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2064 .hw_params = wcd9335_hw_params,
2065 .trigger = wcd9335_trigger,
2066 .set_channel_map = wcd9335_set_channel_map,
2067 .get_channel_map = wcd9335_get_channel_map,
2068 };
2069
2070 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2071 [0] = {
2072 .name = "wcd9335_rx1",
2073 .id = AIF1_PB,
2074 .playback = {
2075 .stream_name = "AIF1 Playback",
2076 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2077 SNDRV_PCM_RATE_384000,
2078 .formats = WCD9335_FORMATS_S16_S24_LE,
2079 .rate_max = 384000,
2080 .rate_min = 8000,
2081 .channels_min = 1,
2082 .channels_max = 2,
2083 },
2084 .ops = &wcd9335_dai_ops,
2085 },
2086 [1] = {
2087 .name = "wcd9335_tx1",
2088 .id = AIF1_CAP,
2089 .capture = {
2090 .stream_name = "AIF1 Capture",
2091 .rates = WCD9335_RATES_MASK,
2092 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2093 .rate_min = 8000,
2094 .rate_max = 192000,
2095 .channels_min = 1,
2096 .channels_max = 4,
2097 },
2098 .ops = &wcd9335_dai_ops,
2099 },
2100 [2] = {
2101 .name = "wcd9335_rx2",
2102 .id = AIF2_PB,
2103 .playback = {
2104 .stream_name = "AIF2 Playback",
2105 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2106 SNDRV_PCM_RATE_384000,
2107 .formats = WCD9335_FORMATS_S16_S24_LE,
2108 .rate_min = 8000,
2109 .rate_max = 384000,
2110 .channels_min = 1,
2111 .channels_max = 2,
2112 },
2113 .ops = &wcd9335_dai_ops,
2114 },
2115 [3] = {
2116 .name = "wcd9335_tx2",
2117 .id = AIF2_CAP,
2118 .capture = {
2119 .stream_name = "AIF2 Capture",
2120 .rates = WCD9335_RATES_MASK,
2121 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2122 .rate_min = 8000,
2123 .rate_max = 192000,
2124 .channels_min = 1,
2125 .channels_max = 4,
2126 },
2127 .ops = &wcd9335_dai_ops,
2128 },
2129 [4] = {
2130 .name = "wcd9335_rx3",
2131 .id = AIF3_PB,
2132 .playback = {
2133 .stream_name = "AIF3 Playback",
2134 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2135 SNDRV_PCM_RATE_384000,
2136 .formats = WCD9335_FORMATS_S16_S24_LE,
2137 .rate_min = 8000,
2138 .rate_max = 384000,
2139 .channels_min = 1,
2140 .channels_max = 2,
2141 },
2142 .ops = &wcd9335_dai_ops,
2143 },
2144 [5] = {
2145 .name = "wcd9335_tx3",
2146 .id = AIF3_CAP,
2147 .capture = {
2148 .stream_name = "AIF3 Capture",
2149 .rates = WCD9335_RATES_MASK,
2150 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2151 .rate_min = 8000,
2152 .rate_max = 192000,
2153 .channels_min = 1,
2154 .channels_max = 4,
2155 },
2156 .ops = &wcd9335_dai_ops,
2157 },
2158 [6] = {
2159 .name = "wcd9335_rx4",
2160 .id = AIF4_PB,
2161 .playback = {
2162 .stream_name = "AIF4 Playback",
2163 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2164 SNDRV_PCM_RATE_384000,
2165 .formats = WCD9335_FORMATS_S16_S24_LE,
2166 .rate_min = 8000,
2167 .rate_max = 384000,
2168 .channels_min = 1,
2169 .channels_max = 2,
2170 },
2171 .ops = &wcd9335_dai_ops,
2172 },
2173 };
2174
wcd9335_get_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2175 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2176 struct snd_ctl_elem_value *ucontrol)
2177 {
2178
2179 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2180 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2181 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2182
2183 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2184 return 0;
2185 }
2186
wcd9335_set_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2187 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2188 struct snd_ctl_elem_value *ucontrol)
2189 {
2190 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2191 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2192 int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2193 int value = ucontrol->value.integer.value[0];
2194 int sel;
2195
2196 wcd->comp_enabled[comp] = value;
2197 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2198 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2199
2200 /* Any specific register configuration for compander */
2201 switch (comp) {
2202 case COMPANDER_1:
2203 /* Set Gain Source Select based on compander enable/disable */
2204 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2205 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2206 break;
2207 case COMPANDER_2:
2208 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2209 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2210 break;
2211 case COMPANDER_5:
2212 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2213 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2214 break;
2215 case COMPANDER_6:
2216 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2217 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2218 break;
2219 default:
2220 break;
2221 }
2222
2223 return 0;
2224 }
2225
wcd9335_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2226 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2227 struct snd_ctl_elem_value *ucontrol)
2228 {
2229 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2230 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2231
2232 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2233
2234 return 0;
2235 }
2236
wcd9335_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2237 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2238 struct snd_ctl_elem_value *ucontrol)
2239 {
2240 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2241 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2242 u32 mode_val;
2243
2244 mode_val = ucontrol->value.enumerated.item[0];
2245
2246 if (mode_val == 0) {
2247 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2248 mode_val = CLS_H_HIFI;
2249 }
2250 wcd->hph_mode = mode_val;
2251
2252 return 0;
2253 }
2254
2255 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2256 /* -84dB min - 40dB max */
2257 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2258 -84, 40, digital_gain),
2259 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2260 -84, 40, digital_gain),
2261 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2262 -84, 40, digital_gain),
2263 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2264 -84, 40, digital_gain),
2265 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2266 -84, 40, digital_gain),
2267 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2268 -84, 40, digital_gain),
2269 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2270 -84, 40, digital_gain),
2271 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2272 -84, 40, digital_gain),
2273 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2274 -84, 40, digital_gain),
2275 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2276 -84, 40, digital_gain),
2277 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2278 -84, 40, digital_gain),
2279 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2280 -84, 40, digital_gain),
2281 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2282 -84, 40, digital_gain),
2283 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2284 -84, 40, digital_gain),
2285 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2286 -84, 40, digital_gain),
2287 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2288 -84, 40, digital_gain),
2289 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2290 -84, 40, digital_gain),
2291 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2292 -84, 40, digital_gain),
2293 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2294 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2295 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2296 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2297 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2298 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2299 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2300 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2301 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2302 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2303 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2304 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2305 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2306 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2307 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2308 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2309 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2310 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2311 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2312 wcd9335_get_compander, wcd9335_set_compander),
2313 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2314 wcd9335_get_compander, wcd9335_set_compander),
2315 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2316 wcd9335_get_compander, wcd9335_set_compander),
2317 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2318 wcd9335_get_compander, wcd9335_set_compander),
2319 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2320 wcd9335_get_compander, wcd9335_set_compander),
2321 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2322 wcd9335_get_compander, wcd9335_set_compander),
2323 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2324 wcd9335_get_compander, wcd9335_set_compander),
2325 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2326 wcd9335_get_compander, wcd9335_set_compander),
2327 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2328 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2329
2330 /* Gain Controls */
2331 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2332 ear_pa_gain),
2333 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2334 line_gain),
2335 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2336 line_gain),
2337 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2338 3, 16, 1, line_gain),
2339 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2340 3, 16, 1, line_gain),
2341 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2342 line_gain),
2343 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2344 line_gain),
2345
2346 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2347 analog_gain),
2348 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2349 analog_gain),
2350 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2351 analog_gain),
2352 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2353 analog_gain),
2354 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2355 analog_gain),
2356 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2357 analog_gain),
2358
2359 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2360 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2361 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2362 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2363 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2364 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2365 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2366 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2367 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2368 };
2369
2370 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2371 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2372 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2373 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2374 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2375 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2376 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2377 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2378 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2379
2380 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2381 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2382 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2383 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2384 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2385 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2386 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2387 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2388
2389 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2390 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2391 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2392 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2393 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2394 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2395 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2396 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2397
2398 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2399 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2400 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2401 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2402 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2403 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2404 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2405 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2406
2407 {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2408 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2409 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2410 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2411 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2412 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2413 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2414 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2415
2416 WCD9335_INTERPOLATOR_PATH(0),
2417 WCD9335_INTERPOLATOR_PATH(1),
2418 WCD9335_INTERPOLATOR_PATH(2),
2419 WCD9335_INTERPOLATOR_PATH(3),
2420 WCD9335_INTERPOLATOR_PATH(4),
2421 WCD9335_INTERPOLATOR_PATH(5),
2422 WCD9335_INTERPOLATOR_PATH(6),
2423 WCD9335_INTERPOLATOR_PATH(7),
2424 WCD9335_INTERPOLATOR_PATH(8),
2425
2426 /* EAR PA */
2427 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2428 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2429 {"RX INT0 DAC", NULL, "RX_BIAS"},
2430 {"EAR PA", NULL, "RX INT0 DAC"},
2431 {"EAR", NULL, "EAR PA"},
2432
2433 /* HPHL */
2434 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2435 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2436 {"RX INT1 DAC", NULL, "RX_BIAS"},
2437 {"HPHL PA", NULL, "RX INT1 DAC"},
2438 {"HPHL", NULL, "HPHL PA"},
2439
2440 /* HPHR */
2441 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2442 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2443 {"RX INT2 DAC", NULL, "RX_BIAS"},
2444 {"HPHR PA", NULL, "RX INT2 DAC"},
2445 {"HPHR", NULL, "HPHR PA"},
2446
2447 /* LINEOUT1 */
2448 {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2449 {"RX INT3 DAC", NULL, "RX_BIAS"},
2450 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2451 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2452
2453 /* LINEOUT2 */
2454 {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2455 {"RX INT4 DAC", NULL, "RX_BIAS"},
2456 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2457 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2458
2459 /* LINEOUT3 */
2460 {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2461 {"RX INT5 DAC", NULL, "RX_BIAS"},
2462 {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2463 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2464
2465 /* LINEOUT4 */
2466 {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2467 {"RX INT6 DAC", NULL, "RX_BIAS"},
2468 {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2469 {"LINEOUT4", NULL, "LINEOUT4 PA"},
2470
2471 /* SLIMBUS Connections */
2472 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2473 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2474 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2475
2476 /* ADC Mux */
2477 WCD9335_ADC_MUX_PATH(0),
2478 WCD9335_ADC_MUX_PATH(1),
2479 WCD9335_ADC_MUX_PATH(2),
2480 WCD9335_ADC_MUX_PATH(3),
2481 WCD9335_ADC_MUX_PATH(4),
2482 WCD9335_ADC_MUX_PATH(5),
2483 WCD9335_ADC_MUX_PATH(6),
2484 WCD9335_ADC_MUX_PATH(7),
2485 WCD9335_ADC_MUX_PATH(8),
2486
2487 /* ADC Connections */
2488 {"ADC1", NULL, "AMIC1"},
2489 {"ADC2", NULL, "AMIC2"},
2490 {"ADC3", NULL, "AMIC3"},
2491 {"ADC4", NULL, "AMIC4"},
2492 {"ADC5", NULL, "AMIC5"},
2493 {"ADC6", NULL, "AMIC6"},
2494 };
2495
wcd9335_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2496 static int wcd9335_micbias_control(struct snd_soc_component *component,
2497 int micb_num, int req, bool is_dapm)
2498 {
2499 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2500 int micb_index = micb_num - 1;
2501 u16 micb_reg;
2502
2503 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2504 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2505 micb_index);
2506 return -EINVAL;
2507 }
2508
2509 switch (micb_num) {
2510 case MIC_BIAS_1:
2511 micb_reg = WCD9335_ANA_MICB1;
2512 break;
2513 case MIC_BIAS_2:
2514 micb_reg = WCD9335_ANA_MICB2;
2515 break;
2516 case MIC_BIAS_3:
2517 micb_reg = WCD9335_ANA_MICB3;
2518 break;
2519 case MIC_BIAS_4:
2520 micb_reg = WCD9335_ANA_MICB4;
2521 break;
2522 default:
2523 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2524 __func__, micb_num);
2525 return -EINVAL;
2526 }
2527
2528 switch (req) {
2529 case MICB_PULLUP_ENABLE:
2530 wcd->pullup_ref[micb_index]++;
2531 if ((wcd->pullup_ref[micb_index] == 1) &&
2532 (wcd->micb_ref[micb_index] == 0))
2533 snd_soc_component_update_bits(component, micb_reg,
2534 0xC0, 0x80);
2535 break;
2536 case MICB_PULLUP_DISABLE:
2537 wcd->pullup_ref[micb_index]--;
2538 if ((wcd->pullup_ref[micb_index] == 0) &&
2539 (wcd->micb_ref[micb_index] == 0))
2540 snd_soc_component_update_bits(component, micb_reg,
2541 0xC0, 0x00);
2542 break;
2543 case MICB_ENABLE:
2544 wcd->micb_ref[micb_index]++;
2545 if (wcd->micb_ref[micb_index] == 1)
2546 snd_soc_component_update_bits(component, micb_reg,
2547 0xC0, 0x40);
2548 break;
2549 case MICB_DISABLE:
2550 wcd->micb_ref[micb_index]--;
2551 if ((wcd->micb_ref[micb_index] == 0) &&
2552 (wcd->pullup_ref[micb_index] > 0))
2553 snd_soc_component_update_bits(component, micb_reg,
2554 0xC0, 0x80);
2555 else if ((wcd->micb_ref[micb_index] == 0) &&
2556 (wcd->pullup_ref[micb_index] == 0)) {
2557 snd_soc_component_update_bits(component, micb_reg,
2558 0xC0, 0x00);
2559 }
2560 break;
2561 }
2562
2563 return 0;
2564 }
2565
__wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)2566 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2567 int event)
2568 {
2569 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2570 int micb_num;
2571
2572 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2573 micb_num = MIC_BIAS_1;
2574 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2575 micb_num = MIC_BIAS_2;
2576 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2577 micb_num = MIC_BIAS_3;
2578 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2579 micb_num = MIC_BIAS_4;
2580 else
2581 return -EINVAL;
2582
2583 switch (event) {
2584 case SND_SOC_DAPM_PRE_PMU:
2585 /*
2586 * MIC BIAS can also be requested by MBHC,
2587 * so use ref count to handle micbias pullup
2588 * and enable requests
2589 */
2590 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2591 break;
2592 case SND_SOC_DAPM_POST_PMU:
2593 /* wait for cnp time */
2594 usleep_range(1000, 1100);
2595 break;
2596 case SND_SOC_DAPM_POST_PMD:
2597 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2598 break;
2599 }
2600
2601 return 0;
2602 }
2603
wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2604 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2605 struct snd_kcontrol *kc, int event)
2606 {
2607 return __wcd9335_codec_enable_micbias(w, event);
2608 }
2609
wcd9335_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)2610 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2611 u16 amic_reg, bool set)
2612 {
2613 u8 mask = 0x20;
2614 u8 val;
2615
2616 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2617 amic_reg == WCD9335_ANA_AMIC5)
2618 mask = 0x40;
2619
2620 val = set ? mask : 0x00;
2621
2622 switch (amic_reg) {
2623 case WCD9335_ANA_AMIC1:
2624 case WCD9335_ANA_AMIC2:
2625 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2626 val);
2627 break;
2628 case WCD9335_ANA_AMIC3:
2629 case WCD9335_ANA_AMIC4:
2630 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2631 val);
2632 break;
2633 case WCD9335_ANA_AMIC5:
2634 case WCD9335_ANA_AMIC6:
2635 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2636 val);
2637 break;
2638 default:
2639 dev_err(comp->dev, "%s: invalid amic: %d\n",
2640 __func__, amic_reg);
2641 break;
2642 }
2643 }
2644
wcd9335_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2645 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2646 struct snd_kcontrol *kc, int event)
2647 {
2648 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2649
2650 switch (event) {
2651 case SND_SOC_DAPM_PRE_PMU:
2652 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2653 break;
2654 default:
2655 break;
2656 }
2657
2658 return 0;
2659 }
2660
wcd9335_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)2661 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2662 int adc_mux_n)
2663 {
2664 int mux_sel, reg, mreg;
2665
2666 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2667 adc_mux_n == WCD9335_INVALID_ADC_MUX)
2668 return 0;
2669
2670 /* Check whether adc mux input is AMIC or DMIC */
2671 if (adc_mux_n < 4) {
2672 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2673 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2674 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2675 } else {
2676 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2677 mreg = reg;
2678 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2679 }
2680
2681 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2682 return 0;
2683
2684 return snd_soc_component_read(comp, mreg) & 0x07;
2685 }
2686
wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)2687 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2688 int amic)
2689 {
2690 u16 pwr_level_reg = 0;
2691
2692 switch (amic) {
2693 case 1:
2694 case 2:
2695 pwr_level_reg = WCD9335_ANA_AMIC1;
2696 break;
2697
2698 case 3:
2699 case 4:
2700 pwr_level_reg = WCD9335_ANA_AMIC3;
2701 break;
2702
2703 case 5:
2704 case 6:
2705 pwr_level_reg = WCD9335_ANA_AMIC5;
2706 break;
2707 default:
2708 dev_err(comp->dev, "invalid amic: %d\n", amic);
2709 break;
2710 }
2711
2712 return pwr_level_reg;
2713 }
2714
wcd9335_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2715 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2716 struct snd_kcontrol *kc, int event)
2717 {
2718 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2719 unsigned int decimator;
2720 char *dec_adc_mux_name = NULL;
2721 char *widget_name;
2722 int ret = 0, amic_n;
2723 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2724 u16 tx_gain_ctl_reg;
2725 char *dec;
2726 u8 hpf_coff_freq;
2727
2728 char *wname __free(kfree) = kmemdup_nul(w->name, 15, GFP_KERNEL);
2729 if (!wname)
2730 return -ENOMEM;
2731
2732 widget_name = wname;
2733 dec_adc_mux_name = strsep(&widget_name, " ");
2734 if (!dec_adc_mux_name) {
2735 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2736 __func__, w->name);
2737 return -EINVAL;
2738 }
2739 dec_adc_mux_name = widget_name;
2740
2741 dec = strpbrk(dec_adc_mux_name, "012345678");
2742 if (!dec) {
2743 dev_err(comp->dev, "%s: decimator index not found\n",
2744 __func__);
2745 return -EINVAL;
2746 }
2747
2748 ret = kstrtouint(dec, 10, &decimator);
2749 if (ret < 0) {
2750 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2751 __func__, wname);
2752 return -EINVAL;
2753 }
2754
2755 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2756 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2757 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2758 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2759
2760 switch (event) {
2761 case SND_SOC_DAPM_PRE_PMU:
2762 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2763 if (amic_n)
2764 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2765 amic_n);
2766
2767 if (pwr_level_reg) {
2768 switch ((snd_soc_component_read(comp, pwr_level_reg) &
2769 WCD9335_AMIC_PWR_LVL_MASK) >>
2770 WCD9335_AMIC_PWR_LVL_SHIFT) {
2771 case WCD9335_AMIC_PWR_LEVEL_LP:
2772 snd_soc_component_update_bits(comp, dec_cfg_reg,
2773 WCD9335_DEC_PWR_LVL_MASK,
2774 WCD9335_DEC_PWR_LVL_LP);
2775 break;
2776
2777 case WCD9335_AMIC_PWR_LEVEL_HP:
2778 snd_soc_component_update_bits(comp, dec_cfg_reg,
2779 WCD9335_DEC_PWR_LVL_MASK,
2780 WCD9335_DEC_PWR_LVL_HP);
2781 break;
2782 case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2783 default:
2784 snd_soc_component_update_bits(comp, dec_cfg_reg,
2785 WCD9335_DEC_PWR_LVL_MASK,
2786 WCD9335_DEC_PWR_LVL_DF);
2787 break;
2788 }
2789 }
2790 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2791 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2792
2793 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2794 snd_soc_component_update_bits(comp, dec_cfg_reg,
2795 TX_HPF_CUT_OFF_FREQ_MASK,
2796 CF_MIN_3DB_150HZ << 5);
2797 /* Enable TX PGA Mute */
2798 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2799 0x10, 0x10);
2800 /* Enable APC */
2801 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2802 break;
2803 case SND_SOC_DAPM_POST_PMU:
2804 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2805
2806 if (decimator == 0) {
2807 snd_soc_component_write(comp,
2808 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2809 snd_soc_component_write(comp,
2810 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2811 snd_soc_component_write(comp,
2812 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2813 snd_soc_component_write(comp,
2814 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2815 }
2816
2817 snd_soc_component_update_bits(comp, hpf_gate_reg,
2818 0x01, 0x01);
2819 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2820 0x10, 0x00);
2821 snd_soc_component_write(comp, tx_gain_ctl_reg,
2822 snd_soc_component_read(comp, tx_gain_ctl_reg));
2823 break;
2824 case SND_SOC_DAPM_PRE_PMD:
2825 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2826 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2827 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2828 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2829 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2830 snd_soc_component_update_bits(comp, dec_cfg_reg,
2831 TX_HPF_CUT_OFF_FREQ_MASK,
2832 hpf_coff_freq << 5);
2833 }
2834 break;
2835 case SND_SOC_DAPM_POST_PMD:
2836 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2837 break;
2838 }
2839
2840 return ret;
2841 }
2842
wcd9335_get_dmic_clk_val(struct snd_soc_component * component,u32 mclk_rate)2843 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2844 u32 mclk_rate)
2845 {
2846 u8 dmic_ctl_val;
2847
2848 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2849 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2850 else
2851 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2852
2853 return dmic_ctl_val;
2854 }
2855
wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2856 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2857 struct snd_kcontrol *kc, int event)
2858 {
2859 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2860 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2861 u8 dmic_clk_en = 0x01;
2862 u16 dmic_clk_reg;
2863 s32 *dmic_clk_cnt;
2864 u8 dmic_rate_val, dmic_rate_shift = 1;
2865 unsigned int dmic;
2866 int ret;
2867 char *wname;
2868
2869 wname = strpbrk(w->name, "012345");
2870 if (!wname) {
2871 dev_err(comp->dev, "%s: widget not found\n", __func__);
2872 return -EINVAL;
2873 }
2874
2875 ret = kstrtouint(wname, 10, &dmic);
2876 if (ret < 0) {
2877 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2878 __func__);
2879 return -EINVAL;
2880 }
2881
2882 switch (dmic) {
2883 case 0:
2884 case 1:
2885 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2886 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2887 break;
2888 case 2:
2889 case 3:
2890 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2891 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2892 break;
2893 case 4:
2894 case 5:
2895 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2896 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2897 break;
2898 default:
2899 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2900 __func__);
2901 return -EINVAL;
2902 }
2903
2904 switch (event) {
2905 case SND_SOC_DAPM_PRE_PMU:
2906 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2907 (*dmic_clk_cnt)++;
2908 if (*dmic_clk_cnt == 1) {
2909 snd_soc_component_update_bits(comp, dmic_clk_reg,
2910 0x07 << dmic_rate_shift,
2911 dmic_rate_val << dmic_rate_shift);
2912 snd_soc_component_update_bits(comp, dmic_clk_reg,
2913 dmic_clk_en, dmic_clk_en);
2914 }
2915
2916 break;
2917 case SND_SOC_DAPM_POST_PMD:
2918 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2919 (*dmic_clk_cnt)--;
2920 if (*dmic_clk_cnt == 0) {
2921 snd_soc_component_update_bits(comp, dmic_clk_reg,
2922 dmic_clk_en, 0);
2923 snd_soc_component_update_bits(comp, dmic_clk_reg,
2924 0x07 << dmic_rate_shift,
2925 dmic_rate_val << dmic_rate_shift);
2926 }
2927 break;
2928 }
2929
2930 return 0;
2931 }
2932
wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)2933 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2934 struct snd_soc_component *component)
2935 {
2936 int port_num = 0;
2937 unsigned short reg = 0;
2938 unsigned int val = 0;
2939 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2940 struct wcd9335_slim_ch *ch;
2941
2942 list_for_each_entry(ch, &dai->slim_ch_list, list) {
2943 if (ch->port >= WCD9335_RX_START) {
2944 port_num = ch->port - WCD9335_RX_START;
2945 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
2946 } else {
2947 port_num = ch->port;
2948 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
2949 }
2950
2951 regmap_read(wcd->if_regmap, reg, &val);
2952 if (!(val & BIT(port_num % 8)))
2953 regmap_write(wcd->if_regmap, reg,
2954 val | BIT(port_num % 8));
2955 }
2956 }
2957
wcd9335_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2958 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
2959 struct snd_kcontrol *kc,
2960 int event)
2961 {
2962 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2963 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2964 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
2965
2966 switch (event) {
2967 case SND_SOC_DAPM_POST_PMU:
2968 wcd9335_codec_enable_int_port(dai, comp);
2969 break;
2970 case SND_SOC_DAPM_POST_PMD:
2971 kfree(dai->sconfig.chs);
2972
2973 break;
2974 }
2975
2976 return 0;
2977 }
2978
wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2979 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
2980 struct snd_kcontrol *kc, int event)
2981 {
2982 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2983 u16 gain_reg;
2984 int val = 0;
2985
2986 switch (w->reg) {
2987 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
2988 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
2989 break;
2990 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
2991 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
2992 break;
2993 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
2994 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
2995 break;
2996 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
2997 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
2998 break;
2999 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3000 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3001 break;
3002 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3003 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3004 break;
3005 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3006 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3007 break;
3008 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3009 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3010 break;
3011 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3012 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3013 break;
3014 default:
3015 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3016 __func__, w->name);
3017 return 0;
3018 }
3019
3020 switch (event) {
3021 case SND_SOC_DAPM_POST_PMU:
3022 val = snd_soc_component_read(comp, gain_reg);
3023 snd_soc_component_write(comp, gain_reg, val);
3024 break;
3025 case SND_SOC_DAPM_POST_PMD:
3026 break;
3027 }
3028
3029 return 0;
3030 }
3031
wcd9335_interp_get_primary_reg(u16 reg,u16 * ind)3032 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3033 {
3034 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3035
3036 switch (reg) {
3037 case WCD9335_CDC_RX0_RX_PATH_CTL:
3038 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3039 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3040 *ind = 0;
3041 break;
3042 case WCD9335_CDC_RX1_RX_PATH_CTL:
3043 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3044 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3045 *ind = 1;
3046 break;
3047 case WCD9335_CDC_RX2_RX_PATH_CTL:
3048 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3049 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3050 *ind = 2;
3051 break;
3052 case WCD9335_CDC_RX3_RX_PATH_CTL:
3053 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3054 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3055 *ind = 3;
3056 break;
3057 case WCD9335_CDC_RX4_RX_PATH_CTL:
3058 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3059 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3060 *ind = 4;
3061 break;
3062 case WCD9335_CDC_RX5_RX_PATH_CTL:
3063 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3064 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3065 *ind = 5;
3066 break;
3067 case WCD9335_CDC_RX6_RX_PATH_CTL:
3068 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3069 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3070 *ind = 6;
3071 break;
3072 case WCD9335_CDC_RX7_RX_PATH_CTL:
3073 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3074 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3075 *ind = 7;
3076 break;
3077 case WCD9335_CDC_RX8_RX_PATH_CTL:
3078 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3079 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3080 *ind = 8;
3081 break;
3082 }
3083
3084 return prim_int_reg;
3085 }
3086
wcd9335_codec_hd2_control(struct snd_soc_component * component,u16 prim_int_reg,int event)3087 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3088 u16 prim_int_reg, int event)
3089 {
3090 u16 hd2_scale_reg;
3091 u16 hd2_enable_reg = 0;
3092
3093 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3094 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3095 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3096 }
3097 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3098 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3099 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3100 }
3101
3102 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3103 snd_soc_component_update_bits(component, hd2_scale_reg,
3104 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3105 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3106 snd_soc_component_update_bits(component, hd2_scale_reg,
3107 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3108 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3109 snd_soc_component_update_bits(component, hd2_enable_reg,
3110 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3111 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3112 }
3113
3114 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3115 snd_soc_component_update_bits(component, hd2_enable_reg,
3116 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3117 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3118 snd_soc_component_update_bits(component, hd2_scale_reg,
3119 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3120 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3121 snd_soc_component_update_bits(component, hd2_scale_reg,
3122 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3123 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3124 }
3125 }
3126
wcd9335_codec_enable_prim_interpolator(struct snd_soc_component * comp,u16 reg,int event)3127 static int wcd9335_codec_enable_prim_interpolator(
3128 struct snd_soc_component *comp,
3129 u16 reg, int event)
3130 {
3131 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3132 u16 ind = 0;
3133 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3134
3135 switch (event) {
3136 case SND_SOC_DAPM_PRE_PMU:
3137 wcd->prim_int_users[ind]++;
3138 if (wcd->prim_int_users[ind] == 1) {
3139 snd_soc_component_update_bits(comp, prim_int_reg,
3140 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3141 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3142 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3143 snd_soc_component_update_bits(comp, prim_int_reg,
3144 WCD9335_CDC_RX_CLK_EN_MASK,
3145 WCD9335_CDC_RX_CLK_ENABLE);
3146 }
3147
3148 if ((reg != prim_int_reg) &&
3149 ((snd_soc_component_read(comp, prim_int_reg)) &
3150 WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3151 snd_soc_component_update_bits(comp, reg,
3152 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3153 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3154 break;
3155 case SND_SOC_DAPM_POST_PMD:
3156 wcd->prim_int_users[ind]--;
3157 if (wcd->prim_int_users[ind] == 0) {
3158 snd_soc_component_update_bits(comp, prim_int_reg,
3159 WCD9335_CDC_RX_CLK_EN_MASK,
3160 WCD9335_CDC_RX_CLK_DISABLE);
3161 snd_soc_component_update_bits(comp, prim_int_reg,
3162 WCD9335_CDC_RX_RESET_MASK,
3163 WCD9335_CDC_RX_RESET_ENABLE);
3164 snd_soc_component_update_bits(comp, prim_int_reg,
3165 WCD9335_CDC_RX_RESET_MASK,
3166 WCD9335_CDC_RX_RESET_DISABLE);
3167 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3168 }
3169 break;
3170 }
3171
3172 return 0;
3173 }
3174
wcd9335_config_compander(struct snd_soc_component * component,int interp_n,int event)3175 static int wcd9335_config_compander(struct snd_soc_component *component,
3176 int interp_n, int event)
3177 {
3178 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3179 int comp;
3180 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3181
3182 /* EAR does not have compander */
3183 if (!interp_n)
3184 return 0;
3185
3186 comp = interp_n - 1;
3187 if (!wcd->comp_enabled[comp])
3188 return 0;
3189
3190 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3191 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3192
3193 if (SND_SOC_DAPM_EVENT_ON(event)) {
3194 /* Enable Compander Clock */
3195 snd_soc_component_update_bits(component, comp_ctl0_reg,
3196 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3197 WCD9335_CDC_COMPANDER_CLK_ENABLE);
3198 /* Reset comander */
3199 snd_soc_component_update_bits(component, comp_ctl0_reg,
3200 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3201 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3202 snd_soc_component_update_bits(component, comp_ctl0_reg,
3203 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3204 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3205 /* Enables DRE in this path */
3206 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3207 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3208 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3209 }
3210
3211 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3212 snd_soc_component_update_bits(component, comp_ctl0_reg,
3213 WCD9335_CDC_COMPANDER_HALT_MASK,
3214 WCD9335_CDC_COMPANDER_HALT);
3215 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3216 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3217 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3218
3219 snd_soc_component_update_bits(component, comp_ctl0_reg,
3220 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3221 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3222 snd_soc_component_update_bits(component, comp_ctl0_reg,
3223 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3224 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3225 snd_soc_component_update_bits(component, comp_ctl0_reg,
3226 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3227 WCD9335_CDC_COMPANDER_CLK_DISABLE);
3228 snd_soc_component_update_bits(component, comp_ctl0_reg,
3229 WCD9335_CDC_COMPANDER_HALT_MASK,
3230 WCD9335_CDC_COMPANDER_NOHALT);
3231 }
3232
3233 return 0;
3234 }
3235
wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3236 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3237 struct snd_kcontrol *kc, int event)
3238 {
3239 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3240 u16 gain_reg;
3241 u16 reg;
3242 int val;
3243
3244 if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT0 INTERP"))) {
3245 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3246 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3247 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT1 INTERP"))) {
3248 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3249 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3250 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT2 INTERP"))) {
3251 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3252 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3253 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT3 INTERP"))) {
3254 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3255 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3256 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT4 INTERP"))) {
3257 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3258 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3259 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT5 INTERP"))) {
3260 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3261 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3262 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT6 INTERP"))) {
3263 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3264 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3265 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT7 INTERP"))) {
3266 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3267 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3268 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT8 INTERP"))) {
3269 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3270 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3271 } else {
3272 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3273 __func__);
3274 return -EINVAL;
3275 }
3276
3277 switch (event) {
3278 case SND_SOC_DAPM_PRE_PMU:
3279 /* Reset if needed */
3280 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3281 break;
3282 case SND_SOC_DAPM_POST_PMU:
3283 wcd9335_config_compander(comp, w->shift, event);
3284 val = snd_soc_component_read(comp, gain_reg);
3285 snd_soc_component_write(comp, gain_reg, val);
3286 break;
3287 case SND_SOC_DAPM_POST_PMD:
3288 wcd9335_config_compander(comp, w->shift, event);
3289 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3290 break;
3291 }
3292
3293 return 0;
3294 }
3295
wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component * component,u8 gain)3296 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3297 u8 gain)
3298 {
3299 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3300 u8 hph_l_en, hph_r_en;
3301 u8 l_val, r_val;
3302 u8 hph_pa_status;
3303 bool is_hphl_pa, is_hphr_pa;
3304
3305 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3306 is_hphl_pa = hph_pa_status >> 7;
3307 is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3308
3309 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3310 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3311
3312 l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3313 r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3314
3315 /*
3316 * Set HPH_L & HPH_R gain source selection to REGISTER
3317 * for better click and pop only if corresponding PAs are
3318 * not enabled. Also cache the values of the HPHL/R
3319 * PA gains to be applied after PAs are enabled
3320 */
3321 if ((l_val != hph_l_en) && !is_hphl_pa) {
3322 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3323 wcd->hph_l_gain = hph_l_en & 0x1F;
3324 }
3325
3326 if ((r_val != hph_r_en) && !is_hphr_pa) {
3327 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3328 wcd->hph_r_gain = hph_r_en & 0x1F;
3329 }
3330 }
3331
wcd9335_codec_hph_lohifi_config(struct snd_soc_component * comp,int event)3332 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3333 int event)
3334 {
3335 if (SND_SOC_DAPM_EVENT_ON(event)) {
3336 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3337 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3338 0x06);
3339 snd_soc_component_update_bits(comp,
3340 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3341 0xF0, 0x40);
3342 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3343 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3344 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3345 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3346 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3347 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3348 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3349 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3350 0x0C);
3351 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3352 }
3353
3354 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3355 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3356 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3357 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3358 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3359 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3360 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3361 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3362 0x8A);
3363 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3364 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3365 0x0A);
3366 }
3367 }
3368
wcd9335_codec_hph_lp_config(struct snd_soc_component * comp,int event)3369 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3370 int event)
3371 {
3372 if (SND_SOC_DAPM_EVENT_ON(event)) {
3373 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3374 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3375 0x0C);
3376 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3377 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3378 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3379 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3380 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3381 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3382 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3383 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3384 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3385 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3386 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3387 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3388 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3389 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3390 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3391 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3392 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3393 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3394 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3395 snd_soc_component_update_bits(comp,
3396 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3397 snd_soc_component_update_bits(comp,
3398 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3399 }
3400
3401 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3402 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3403 0x88);
3404 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3405 0x33);
3406 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3407 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3408 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3409 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3410 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3411 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3412 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3413 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3414 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3415 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3416 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3417 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3418 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3419 WCD9335_HPH_CONST_SEL_L_MASK,
3420 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3421 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3422 WCD9335_HPH_CONST_SEL_L_MASK,
3423 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3424 }
3425 }
3426
wcd9335_codec_hph_hifi_config(struct snd_soc_component * comp,int event)3427 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3428 int event)
3429 {
3430 if (SND_SOC_DAPM_EVENT_ON(event)) {
3431 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3432 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3433 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3434 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3435 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3436 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3437 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3438 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3439 0x0C);
3440 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3441 }
3442
3443 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3444 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3445 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3446 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3447 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3448 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3449 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3450 }
3451 }
3452
wcd9335_codec_hph_mode_config(struct snd_soc_component * component,int event,int mode)3453 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3454 int event, int mode)
3455 {
3456 switch (mode) {
3457 case CLS_H_LP:
3458 wcd9335_codec_hph_lp_config(component, event);
3459 break;
3460 case CLS_H_LOHIFI:
3461 wcd9335_codec_hph_lohifi_config(component, event);
3462 break;
3463 case CLS_H_HIFI:
3464 wcd9335_codec_hph_hifi_config(component, event);
3465 break;
3466 }
3467 }
3468
wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3469 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3470 struct snd_kcontrol *kc,
3471 int event)
3472 {
3473 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3474 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3475 int hph_mode = wcd->hph_mode;
3476 u8 dem_inp;
3477
3478 switch (event) {
3479 case SND_SOC_DAPM_PRE_PMU:
3480 /* Read DEM INP Select */
3481 dem_inp = snd_soc_component_read(comp,
3482 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3483 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3484 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3485 dev_err(comp->dev, "Incorrect DEM Input\n");
3486 return -EINVAL;
3487 }
3488 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3489 WCD_CLSH_STATE_HPHL,
3490 ((hph_mode == CLS_H_LOHIFI) ?
3491 CLS_H_HIFI : hph_mode));
3492
3493 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3494
3495 break;
3496 case SND_SOC_DAPM_POST_PMU:
3497 usleep_range(1000, 1100);
3498 break;
3499 case SND_SOC_DAPM_PRE_PMD:
3500 break;
3501 case SND_SOC_DAPM_POST_PMD:
3502 /* 1000us required as per HW requirement */
3503 usleep_range(1000, 1100);
3504
3505 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3506 WCD_CLSH_STATE_HPHR))
3507 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3508
3509 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3510 WCD_CLSH_STATE_HPHL,
3511 ((hph_mode == CLS_H_LOHIFI) ?
3512 CLS_H_HIFI : hph_mode));
3513 break;
3514 }
3515
3516 return 0;
3517 }
3518
wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3519 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3520 struct snd_kcontrol *kc, int event)
3521 {
3522 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3523 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3524
3525 switch (event) {
3526 case SND_SOC_DAPM_PRE_PMU:
3527 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3528 WCD_CLSH_STATE_LO, CLS_AB);
3529 break;
3530 case SND_SOC_DAPM_POST_PMD:
3531 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3532 WCD_CLSH_STATE_LO, CLS_AB);
3533 break;
3534 }
3535
3536 return 0;
3537 }
3538
wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3539 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3540 struct snd_kcontrol *kc, int event)
3541 {
3542 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3543 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3544
3545 switch (event) {
3546 case SND_SOC_DAPM_PRE_PMU:
3547 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3548 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3549
3550 break;
3551 case SND_SOC_DAPM_POST_PMD:
3552 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3553 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3554 break;
3555 }
3556
3557 return 0;
3558 }
3559
wcd9335_codec_hph_post_pa_config(struct wcd9335_codec * wcd,int mode,int event)3560 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3561 int mode, int event)
3562 {
3563 u8 scale_val = 0;
3564
3565 switch (event) {
3566 case SND_SOC_DAPM_POST_PMU:
3567 switch (mode) {
3568 case CLS_H_HIFI:
3569 scale_val = 0x3;
3570 break;
3571 case CLS_H_LOHIFI:
3572 scale_val = 0x1;
3573 break;
3574 }
3575 break;
3576 case SND_SOC_DAPM_PRE_PMD:
3577 scale_val = 0x6;
3578 break;
3579 }
3580
3581 if (scale_val)
3582 snd_soc_component_update_bits(wcd->component,
3583 WCD9335_HPH_PA_CTL1,
3584 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3585 scale_val << 1);
3586 if (SND_SOC_DAPM_EVENT_ON(event)) {
3587 if (wcd->comp_enabled[COMPANDER_1] ||
3588 wcd->comp_enabled[COMPANDER_2]) {
3589 /* GAIN Source Selection */
3590 snd_soc_component_update_bits(wcd->component,
3591 WCD9335_HPH_L_EN,
3592 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3593 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3594 snd_soc_component_update_bits(wcd->component,
3595 WCD9335_HPH_R_EN,
3596 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3597 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3598 snd_soc_component_update_bits(wcd->component,
3599 WCD9335_HPH_AUTO_CHOP,
3600 WCD9335_HPH_AUTO_CHOP_MASK,
3601 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3602 }
3603 snd_soc_component_update_bits(wcd->component,
3604 WCD9335_HPH_L_EN,
3605 WCD9335_HPH_PA_GAIN_MASK,
3606 wcd->hph_l_gain);
3607 snd_soc_component_update_bits(wcd->component,
3608 WCD9335_HPH_R_EN,
3609 WCD9335_HPH_PA_GAIN_MASK,
3610 wcd->hph_r_gain);
3611 }
3612
3613 if (SND_SOC_DAPM_EVENT_OFF(event))
3614 snd_soc_component_update_bits(wcd->component,
3615 WCD9335_HPH_AUTO_CHOP,
3616 WCD9335_HPH_AUTO_CHOP_MASK,
3617 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3618 }
3619
wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3620 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3621 struct snd_kcontrol *kc,
3622 int event)
3623 {
3624 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3625 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3626 int hph_mode = wcd->hph_mode;
3627 u8 dem_inp;
3628
3629 switch (event) {
3630 case SND_SOC_DAPM_PRE_PMU:
3631
3632 /* Read DEM INP Select */
3633 dem_inp = snd_soc_component_read(comp,
3634 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3635 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3636 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3637 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3638 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3639 hph_mode);
3640 return -EINVAL;
3641 }
3642
3643 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3644 WCD_CLSH_EVENT_PRE_DAC,
3645 WCD_CLSH_STATE_HPHR,
3646 ((hph_mode == CLS_H_LOHIFI) ?
3647 CLS_H_HIFI : hph_mode));
3648
3649 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3650
3651 break;
3652 case SND_SOC_DAPM_POST_PMD:
3653 /* 1000us required as per HW requirement */
3654 usleep_range(1000, 1100);
3655
3656 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3657 WCD_CLSH_STATE_HPHL))
3658 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3659
3660 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3661 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3662 CLS_H_HIFI : hph_mode));
3663 break;
3664 }
3665
3666 return 0;
3667 }
3668
wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3669 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3670 struct snd_kcontrol *kc,
3671 int event)
3672 {
3673 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3674 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3675 int hph_mode = wcd->hph_mode;
3676
3677 switch (event) {
3678 case SND_SOC_DAPM_PRE_PMU:
3679 break;
3680 case SND_SOC_DAPM_POST_PMU:
3681 /*
3682 * 7ms sleep is required after PA is enabled as per
3683 * HW requirement
3684 */
3685 usleep_range(7000, 7100);
3686
3687 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3688 snd_soc_component_update_bits(comp,
3689 WCD9335_CDC_RX1_RX_PATH_CTL,
3690 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3691 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3692
3693 /* Remove mix path mute if it is enabled */
3694 if ((snd_soc_component_read(comp,
3695 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3696 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3697 snd_soc_component_update_bits(comp,
3698 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3699 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3700 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3701
3702 break;
3703 case SND_SOC_DAPM_PRE_PMD:
3704 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3705 break;
3706 case SND_SOC_DAPM_POST_PMD:
3707 /* 5ms sleep is required after PA is disabled as per
3708 * HW requirement
3709 */
3710 usleep_range(5000, 5500);
3711 break;
3712 }
3713
3714 return 0;
3715 }
3716
wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3717 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3718 struct snd_kcontrol *kc,
3719 int event)
3720 {
3721 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3722 int vol_reg = 0, mix_vol_reg = 0;
3723
3724 if (w->reg == WCD9335_ANA_LO_1_2) {
3725 if (w->shift == 7) {
3726 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3727 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3728 } else if (w->shift == 6) {
3729 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3730 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3731 }
3732 } else if (w->reg == WCD9335_ANA_LO_3_4) {
3733 if (w->shift == 7) {
3734 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3735 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3736 } else if (w->shift == 6) {
3737 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3738 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3739 }
3740 } else {
3741 dev_err(comp->dev, "Error enabling lineout PA\n");
3742 return -EINVAL;
3743 }
3744
3745 switch (event) {
3746 case SND_SOC_DAPM_POST_PMU:
3747 /* 5ms sleep is required after PA is enabled as per
3748 * HW requirement
3749 */
3750 usleep_range(5000, 5500);
3751 snd_soc_component_update_bits(comp, vol_reg,
3752 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3753 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3754
3755 /* Remove mix path mute if it is enabled */
3756 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3757 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3758 snd_soc_component_update_bits(comp, mix_vol_reg,
3759 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3760 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3761 break;
3762 case SND_SOC_DAPM_POST_PMD:
3763 /* 5ms sleep is required after PA is disabled as per
3764 * HW requirement
3765 */
3766 usleep_range(5000, 5500);
3767 break;
3768 }
3769
3770 return 0;
3771 }
3772
wcd9335_codec_init_flyback(struct snd_soc_component * component)3773 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3774 {
3775 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3776 WCD9335_HPH_CONST_SEL_L_MASK,
3777 WCD9335_HPH_CONST_SEL_L_BYPASS);
3778 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3779 WCD9335_HPH_CONST_SEL_L_MASK,
3780 WCD9335_HPH_CONST_SEL_L_BYPASS);
3781 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3782 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3783 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3784 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3785 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3786 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3787 }
3788
wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3789 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3790 struct snd_kcontrol *kc, int event)
3791 {
3792 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3793 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3794
3795 switch (event) {
3796 case SND_SOC_DAPM_PRE_PMU:
3797 wcd->rx_bias_count++;
3798 if (wcd->rx_bias_count == 1) {
3799 wcd9335_codec_init_flyback(comp);
3800 snd_soc_component_update_bits(comp,
3801 WCD9335_ANA_RX_SUPPLIES,
3802 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3803 WCD9335_ANA_RX_BIAS_ENABLE);
3804 }
3805 break;
3806 case SND_SOC_DAPM_POST_PMD:
3807 wcd->rx_bias_count--;
3808 if (!wcd->rx_bias_count)
3809 snd_soc_component_update_bits(comp,
3810 WCD9335_ANA_RX_SUPPLIES,
3811 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3812 WCD9335_ANA_RX_BIAS_DISABLE);
3813 break;
3814 }
3815
3816 return 0;
3817 }
3818
wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3819 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3820 struct snd_kcontrol *kc, int event)
3821 {
3822 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3823 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3824 int hph_mode = wcd->hph_mode;
3825
3826 switch (event) {
3827 case SND_SOC_DAPM_PRE_PMU:
3828 break;
3829 case SND_SOC_DAPM_POST_PMU:
3830 /*
3831 * 7ms sleep is required after PA is enabled as per
3832 * HW requirement
3833 */
3834 usleep_range(7000, 7100);
3835 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3836 snd_soc_component_update_bits(comp,
3837 WCD9335_CDC_RX2_RX_PATH_CTL,
3838 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3839 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3840 /* Remove mix path mute if it is enabled */
3841 if ((snd_soc_component_read(comp,
3842 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3843 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3844 snd_soc_component_update_bits(comp,
3845 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3846 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3847 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3848
3849 break;
3850
3851 case SND_SOC_DAPM_PRE_PMD:
3852 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3853 break;
3854 case SND_SOC_DAPM_POST_PMD:
3855 /* 5ms sleep is required after PA is disabled as per
3856 * HW requirement
3857 */
3858 usleep_range(5000, 5500);
3859 break;
3860 }
3861
3862 return 0;
3863 }
3864
wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3865 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3866 struct snd_kcontrol *kc, int event)
3867 {
3868 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3869
3870 switch (event) {
3871 case SND_SOC_DAPM_POST_PMU:
3872 /* 5ms sleep is required after PA is enabled as per
3873 * HW requirement
3874 */
3875 usleep_range(5000, 5500);
3876 snd_soc_component_update_bits(comp,
3877 WCD9335_CDC_RX0_RX_PATH_CTL,
3878 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3879 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3880 /* Remove mix path mute if it is enabled */
3881 if ((snd_soc_component_read(comp,
3882 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3883 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3884 snd_soc_component_update_bits(comp,
3885 WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3886 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3887 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3888 break;
3889 case SND_SOC_DAPM_POST_PMD:
3890 /* 5ms sleep is required after PA is disabled as per
3891 * HW requirement
3892 */
3893 usleep_range(5000, 5500);
3894
3895 break;
3896 }
3897
3898 return 0;
3899 }
3900
wcd9335_slimbus_irq(int irq,void * data)3901 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3902 {
3903 struct wcd9335_codec *wcd = data;
3904 unsigned long status = 0;
3905 int i, j, port_id;
3906 unsigned int val, int_val = 0;
3907 irqreturn_t ret = IRQ_NONE;
3908 bool tx;
3909 unsigned short reg = 0;
3910
3911 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3912 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3913 regmap_read(wcd->if_regmap, i, &val);
3914 status |= ((u32)val << (8 * j));
3915 }
3916
3917 for_each_set_bit(j, &status, 32) {
3918 tx = (j >= 16);
3919 port_id = (tx ? j - 16 : j);
3920 regmap_read(wcd->if_regmap,
3921 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3922 if (val) {
3923 if (!tx)
3924 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3925 (port_id / 8);
3926 else
3927 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3928 (port_id / 8);
3929 regmap_read(
3930 wcd->if_regmap, reg, &int_val);
3931 /*
3932 * Ignore interrupts for ports for which the
3933 * interrupts are not specifically enabled.
3934 */
3935 if (!(int_val & (1 << (port_id % 8))))
3936 continue;
3937 }
3938
3939 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
3940 dev_err_ratelimited(wcd->dev,
3941 "%s: overflow error on %s port %d, value %x\n",
3942 __func__, (tx ? "TX" : "RX"), port_id, val);
3943
3944 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
3945 dev_err_ratelimited(wcd->dev,
3946 "%s: underflow error on %s port %d, value %x\n",
3947 __func__, (tx ? "TX" : "RX"), port_id, val);
3948
3949 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
3950 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
3951 if (!tx)
3952 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3953 (port_id / 8);
3954 else
3955 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3956 (port_id / 8);
3957 regmap_read(
3958 wcd->if_regmap, reg, &int_val);
3959 if (int_val & (1 << (port_id % 8))) {
3960 int_val = int_val ^ (1 << (port_id % 8));
3961 regmap_write(wcd->if_regmap,
3962 reg, int_val);
3963 }
3964 }
3965
3966 regmap_write(wcd->if_regmap,
3967 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
3968 BIT(j % 8));
3969 ret = IRQ_HANDLED;
3970 }
3971
3972 return ret;
3973 }
3974
3975 static const struct wcd9335_irq wcd9335_irqs[] = {
3976 {
3977 .irq = WCD9335_IRQ_SLIMBUS,
3978 .handler = wcd9335_slimbus_irq,
3979 .name = "SLIM Slave",
3980 },
3981 };
3982
wcd9335_setup_irqs(struct wcd9335_codec * wcd)3983 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
3984 {
3985 int irq, ret, i;
3986
3987 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
3988 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
3989 if (irq < 0) {
3990 dev_err(wcd->dev, "Failed to get %s\n",
3991 wcd9335_irqs[i].name);
3992 return irq;
3993 }
3994
3995 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
3996 wcd9335_irqs[i].handler,
3997 IRQF_TRIGGER_RISING |
3998 IRQF_ONESHOT,
3999 wcd9335_irqs[i].name, wcd);
4000 if (ret) {
4001 dev_err(wcd->dev, "Failed to request %s\n",
4002 wcd9335_irqs[i].name);
4003 return ret;
4004 }
4005 }
4006
4007 /* enable interrupts on all slave ports */
4008 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4009 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4010 0xFF);
4011
4012 return ret;
4013 }
4014
wcd9335_teardown_irqs(struct wcd9335_codec * wcd)4015 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4016 {
4017 int i;
4018
4019 /* disable interrupts on all slave ports */
4020 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4021 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4022 0x00);
4023 }
4024
wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec * wcd,bool ccl_flag)4025 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4026 bool ccl_flag)
4027 {
4028 struct snd_soc_component *comp = wcd->component;
4029
4030 if (ccl_flag) {
4031 if (++wcd->sido_ccl_cnt == 1)
4032 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4033 WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4034 } else {
4035 if (wcd->sido_ccl_cnt == 0) {
4036 dev_err(wcd->dev, "sido_ccl already disabled\n");
4037 return;
4038 }
4039 if (--wcd->sido_ccl_cnt == 0)
4040 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4041 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4042 }
4043 }
4044
wcd9335_enable_master_bias(struct wcd9335_codec * wcd)4045 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4046 {
4047 wcd->master_bias_users++;
4048 if (wcd->master_bias_users == 1) {
4049 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4050 WCD9335_ANA_BIAS_EN_MASK,
4051 WCD9335_ANA_BIAS_ENABLE);
4052 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4053 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4054 WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4055 /*
4056 * 1ms delay is required after pre-charge is enabled
4057 * as per HW requirement
4058 */
4059 usleep_range(1000, 1100);
4060 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4061 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4062 WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4063 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4064 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4065 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4066 }
4067
4068 return 0;
4069 }
4070
wcd9335_enable_mclk(struct wcd9335_codec * wcd)4071 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4072 {
4073 /* Enable mclk requires master bias to be enabled first */
4074 if (wcd->master_bias_users <= 0)
4075 return -EINVAL;
4076
4077 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4078 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4079 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4080 wcd->clk_type);
4081 return -EINVAL;
4082 }
4083
4084 if (++wcd->clk_mclk_users == 1) {
4085 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4086 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4087 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4088 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4089 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4090 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4091 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4092 WCD9335_ANA_CLK_MCLK_EN_MASK,
4093 WCD9335_ANA_CLK_MCLK_ENABLE);
4094 regmap_update_bits(wcd->regmap,
4095 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4096 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4097 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4098 regmap_update_bits(wcd->regmap,
4099 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4100 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4101 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4102 /*
4103 * 10us sleep is required after clock is enabled
4104 * as per HW requirement
4105 */
4106 usleep_range(10, 15);
4107 }
4108
4109 wcd->clk_type = WCD_CLK_MCLK;
4110
4111 return 0;
4112 }
4113
wcd9335_disable_mclk(struct wcd9335_codec * wcd)4114 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4115 {
4116 if (wcd->clk_mclk_users <= 0)
4117 return -EINVAL;
4118
4119 if (--wcd->clk_mclk_users == 0) {
4120 if (wcd->clk_rco_users > 0) {
4121 /* MCLK to RCO switch */
4122 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4123 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4124 WCD9335_ANA_CLK_MCLK_SRC_RCO);
4125 wcd->clk_type = WCD_CLK_RCO;
4126 } else {
4127 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4128 WCD9335_ANA_CLK_MCLK_EN_MASK,
4129 WCD9335_ANA_CLK_MCLK_DISABLE);
4130 wcd->clk_type = WCD_CLK_OFF;
4131 }
4132
4133 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4134 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4135 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4136 }
4137
4138 return 0;
4139 }
4140
wcd9335_disable_master_bias(struct wcd9335_codec * wcd)4141 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4142 {
4143 if (wcd->master_bias_users <= 0)
4144 return -EINVAL;
4145
4146 wcd->master_bias_users--;
4147 if (wcd->master_bias_users == 0) {
4148 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4149 WCD9335_ANA_BIAS_EN_MASK,
4150 WCD9335_ANA_BIAS_DISABLE);
4151 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4152 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4153 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4154 }
4155 return 0;
4156 }
4157
wcd9335_cdc_req_mclk_enable(struct wcd9335_codec * wcd,bool enable)4158 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4159 bool enable)
4160 {
4161 int ret = 0;
4162
4163 if (enable) {
4164 wcd9335_cdc_sido_ccl_enable(wcd, true);
4165 ret = clk_prepare_enable(wcd->mclk);
4166 if (ret) {
4167 dev_err(wcd->dev, "%s: ext clk enable failed\n",
4168 __func__);
4169 goto err;
4170 }
4171 /* get BG */
4172 wcd9335_enable_master_bias(wcd);
4173 /* get MCLK */
4174 wcd9335_enable_mclk(wcd);
4175
4176 } else {
4177 /* put MCLK */
4178 wcd9335_disable_mclk(wcd);
4179 /* put BG */
4180 wcd9335_disable_master_bias(wcd);
4181 clk_disable_unprepare(wcd->mclk);
4182 wcd9335_cdc_sido_ccl_enable(wcd, false);
4183 }
4184 err:
4185 return ret;
4186 }
4187
wcd9335_codec_apply_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4188 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4189 enum wcd9335_sido_voltage req_mv)
4190 {
4191 struct snd_soc_component *comp = wcd->component;
4192 int vout_d_val;
4193
4194 if (req_mv == wcd->sido_voltage)
4195 return;
4196
4197 /* compute the vout_d step value */
4198 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4199 WCD9335_ANA_BUCK_VOUT_MASK;
4200 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4201 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4202 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4203 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4204
4205 /* 1 msec sleep required after SIDO Vout_D voltage change */
4206 usleep_range(1000, 1100);
4207 wcd->sido_voltage = req_mv;
4208 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4209 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4210 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4211 }
4212
wcd9335_codec_update_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4213 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4214 enum wcd9335_sido_voltage req_mv)
4215 {
4216 int ret = 0;
4217
4218 /* enable mclk before setting SIDO voltage */
4219 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4220 if (ret) {
4221 dev_err(wcd->dev, "Ext clk enable failed\n");
4222 goto err;
4223 }
4224
4225 wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4226 wcd9335_cdc_req_mclk_enable(wcd, false);
4227
4228 err:
4229 return ret;
4230 }
4231
_wcd9335_codec_enable_mclk(struct snd_soc_component * component,int enable)4232 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4233 int enable)
4234 {
4235 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4236 int ret;
4237
4238 if (enable) {
4239 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4240 if (ret)
4241 return ret;
4242
4243 wcd9335_codec_apply_sido_voltage(wcd,
4244 SIDO_VOLTAGE_NOMINAL_MV);
4245 } else {
4246 wcd9335_codec_update_sido_voltage(wcd,
4247 wcd->sido_voltage);
4248 wcd9335_cdc_req_mclk_enable(wcd, false);
4249 }
4250
4251 return 0;
4252 }
4253
wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4254 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4255 struct snd_kcontrol *kc, int event)
4256 {
4257 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4258
4259 switch (event) {
4260 case SND_SOC_DAPM_PRE_PMU:
4261 return _wcd9335_codec_enable_mclk(comp, true);
4262 case SND_SOC_DAPM_POST_PMD:
4263 return _wcd9335_codec_enable_mclk(comp, false);
4264 }
4265
4266 return 0;
4267 }
4268
4269 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4270 /* TODO SPK1 & SPK2 OUT*/
4271 SND_SOC_DAPM_OUTPUT("EAR"),
4272 SND_SOC_DAPM_OUTPUT("HPHL"),
4273 SND_SOC_DAPM_OUTPUT("HPHR"),
4274 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4275 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4276 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4277 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4278 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4279 AIF1_PB, 0, wcd9335_codec_enable_slim,
4280 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4281 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4282 AIF2_PB, 0, wcd9335_codec_enable_slim,
4283 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4284 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4285 AIF3_PB, 0, wcd9335_codec_enable_slim,
4286 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4287 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4288 AIF4_PB, 0, wcd9335_codec_enable_slim,
4289 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4290 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4291 &slim_rx_mux[WCD9335_RX0]),
4292 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4293 &slim_rx_mux[WCD9335_RX1]),
4294 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4295 &slim_rx_mux[WCD9335_RX2]),
4296 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4297 &slim_rx_mux[WCD9335_RX3]),
4298 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4299 &slim_rx_mux[WCD9335_RX4]),
4300 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4301 &slim_rx_mux[WCD9335_RX5]),
4302 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4303 &slim_rx_mux[WCD9335_RX6]),
4304 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4305 &slim_rx_mux[WCD9335_RX7]),
4306 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4307 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4308 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4309 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4310 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4311 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4312 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4313 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4314 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4315 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4316 SND_SOC_DAPM_POST_PMU),
4317 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4318 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4319 SND_SOC_DAPM_POST_PMU),
4320 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4321 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4322 SND_SOC_DAPM_POST_PMU),
4323 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4324 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4325 SND_SOC_DAPM_POST_PMU),
4326 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4327 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4328 SND_SOC_DAPM_POST_PMU),
4329 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4330 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4331 SND_SOC_DAPM_POST_PMU),
4332 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4333 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4334 SND_SOC_DAPM_POST_PMU),
4335 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4336 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4337 SND_SOC_DAPM_POST_PMU),
4338 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4339 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4340 SND_SOC_DAPM_POST_PMU),
4341 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4342 &rx_int0_1_mix_inp0_mux),
4343 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4344 &rx_int0_1_mix_inp1_mux),
4345 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4346 &rx_int0_1_mix_inp2_mux),
4347 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4348 &rx_int1_1_mix_inp0_mux),
4349 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4350 &rx_int1_1_mix_inp1_mux),
4351 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4352 &rx_int1_1_mix_inp2_mux),
4353 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4354 &rx_int2_1_mix_inp0_mux),
4355 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4356 &rx_int2_1_mix_inp1_mux),
4357 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4358 &rx_int2_1_mix_inp2_mux),
4359 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4360 &rx_int3_1_mix_inp0_mux),
4361 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4362 &rx_int3_1_mix_inp1_mux),
4363 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4364 &rx_int3_1_mix_inp2_mux),
4365 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4366 &rx_int4_1_mix_inp0_mux),
4367 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4368 &rx_int4_1_mix_inp1_mux),
4369 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4370 &rx_int4_1_mix_inp2_mux),
4371 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4372 &rx_int5_1_mix_inp0_mux),
4373 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4374 &rx_int5_1_mix_inp1_mux),
4375 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4376 &rx_int5_1_mix_inp2_mux),
4377 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4378 &rx_int6_1_mix_inp0_mux),
4379 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4380 &rx_int6_1_mix_inp1_mux),
4381 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4382 &rx_int6_1_mix_inp2_mux),
4383 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4384 &rx_int7_1_mix_inp0_mux),
4385 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4386 &rx_int7_1_mix_inp1_mux),
4387 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4388 &rx_int7_1_mix_inp2_mux),
4389 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4390 &rx_int8_1_mix_inp0_mux),
4391 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4392 &rx_int8_1_mix_inp1_mux),
4393 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4394 &rx_int8_1_mix_inp2_mux),
4395
4396 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4397 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4398 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4399 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4400 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4401 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4402 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4403 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4404 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4405 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4406 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4407 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4408 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4409 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4410 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4411 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4412 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4413 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4414
4415 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4416 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4417 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4418 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4419 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4420 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4421 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4422 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4423 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4424
4425 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4426 &rx_int0_dem_inp_mux),
4427 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4428 &rx_int1_dem_inp_mux),
4429 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4430 &rx_int2_dem_inp_mux),
4431
4432 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4433 INTERP_EAR, 0, &rx_int0_interp_mux,
4434 wcd9335_codec_enable_interpolator,
4435 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4436 SND_SOC_DAPM_POST_PMD),
4437 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4438 INTERP_HPHL, 0, &rx_int1_interp_mux,
4439 wcd9335_codec_enable_interpolator,
4440 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4441 SND_SOC_DAPM_POST_PMD),
4442 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4443 INTERP_HPHR, 0, &rx_int2_interp_mux,
4444 wcd9335_codec_enable_interpolator,
4445 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4446 SND_SOC_DAPM_POST_PMD),
4447 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4448 INTERP_LO1, 0, &rx_int3_interp_mux,
4449 wcd9335_codec_enable_interpolator,
4450 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4451 SND_SOC_DAPM_POST_PMD),
4452 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4453 INTERP_LO2, 0, &rx_int4_interp_mux,
4454 wcd9335_codec_enable_interpolator,
4455 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4456 SND_SOC_DAPM_POST_PMD),
4457 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4458 INTERP_LO3, 0, &rx_int5_interp_mux,
4459 wcd9335_codec_enable_interpolator,
4460 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4461 SND_SOC_DAPM_POST_PMD),
4462 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4463 INTERP_LO4, 0, &rx_int6_interp_mux,
4464 wcd9335_codec_enable_interpolator,
4465 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4466 SND_SOC_DAPM_POST_PMD),
4467 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4468 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4469 wcd9335_codec_enable_interpolator,
4470 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4471 SND_SOC_DAPM_POST_PMD),
4472 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4473 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4474 wcd9335_codec_enable_interpolator,
4475 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4476 SND_SOC_DAPM_POST_PMD),
4477
4478 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4479 0, 0, wcd9335_codec_ear_dac_event,
4480 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4481 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4482 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4483 5, 0, wcd9335_codec_hphl_dac_event,
4484 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4485 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4486 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4487 4, 0, wcd9335_codec_hphr_dac_event,
4488 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4489 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4490 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4491 0, 0, wcd9335_codec_lineout_dac_event,
4492 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4493 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4494 0, 0, wcd9335_codec_lineout_dac_event,
4495 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4496 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4497 0, 0, wcd9335_codec_lineout_dac_event,
4498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4499 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4500 0, 0, wcd9335_codec_lineout_dac_event,
4501 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4502 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4503 wcd9335_codec_enable_hphl_pa,
4504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4505 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4506 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4507 wcd9335_codec_enable_hphr_pa,
4508 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4509 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4510 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4511 wcd9335_codec_enable_ear_pa,
4512 SND_SOC_DAPM_POST_PMU |
4513 SND_SOC_DAPM_POST_PMD),
4514 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4515 wcd9335_codec_enable_lineout_pa,
4516 SND_SOC_DAPM_POST_PMU |
4517 SND_SOC_DAPM_POST_PMD),
4518 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4519 wcd9335_codec_enable_lineout_pa,
4520 SND_SOC_DAPM_POST_PMU |
4521 SND_SOC_DAPM_POST_PMD),
4522 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4523 wcd9335_codec_enable_lineout_pa,
4524 SND_SOC_DAPM_POST_PMU |
4525 SND_SOC_DAPM_POST_PMD),
4526 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4527 wcd9335_codec_enable_lineout_pa,
4528 SND_SOC_DAPM_POST_PMU |
4529 SND_SOC_DAPM_POST_PMD),
4530 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4531 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4532 SND_SOC_DAPM_POST_PMD),
4533 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4534 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4535 SND_SOC_DAPM_POST_PMD),
4536
4537 /* TX */
4538 SND_SOC_DAPM_INPUT("AMIC1"),
4539 SND_SOC_DAPM_INPUT("AMIC2"),
4540 SND_SOC_DAPM_INPUT("AMIC3"),
4541 SND_SOC_DAPM_INPUT("AMIC4"),
4542 SND_SOC_DAPM_INPUT("AMIC5"),
4543 SND_SOC_DAPM_INPUT("AMIC6"),
4544
4545 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4546 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4548
4549 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4550 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4551 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4552
4553 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4554 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4555 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4556
4557 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4558 wcd9335_codec_enable_micbias,
4559 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4560 SND_SOC_DAPM_POST_PMD),
4561 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4562 wcd9335_codec_enable_micbias,
4563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4564 SND_SOC_DAPM_POST_PMD),
4565 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4566 wcd9335_codec_enable_micbias,
4567 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4568 SND_SOC_DAPM_POST_PMD),
4569 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4570 wcd9335_codec_enable_micbias,
4571 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4572 SND_SOC_DAPM_POST_PMD),
4573
4574 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4575 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4576 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4577 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4578 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4579 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4580 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4581 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4582 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4583 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4584 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4585 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4586
4587 /* Digital Mic Inputs */
4588 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4589 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4590 SND_SOC_DAPM_POST_PMD),
4591
4592 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4593 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4594 SND_SOC_DAPM_POST_PMD),
4595
4596 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4597 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4598 SND_SOC_DAPM_POST_PMD),
4599
4600 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4601 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4602 SND_SOC_DAPM_POST_PMD),
4603
4604 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4605 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4606 SND_SOC_DAPM_POST_PMD),
4607
4608 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4609 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4610 SND_SOC_DAPM_POST_PMD),
4611
4612 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4613 &tx_dmic_mux0),
4614 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4615 &tx_dmic_mux1),
4616 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4617 &tx_dmic_mux2),
4618 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4619 &tx_dmic_mux3),
4620 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4621 &tx_dmic_mux4),
4622 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4623 &tx_dmic_mux5),
4624 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4625 &tx_dmic_mux6),
4626 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4627 &tx_dmic_mux7),
4628 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4629 &tx_dmic_mux8),
4630
4631 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4632 &tx_amic_mux0),
4633 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4634 &tx_amic_mux1),
4635 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4636 &tx_amic_mux2),
4637 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4638 &tx_amic_mux3),
4639 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4640 &tx_amic_mux4),
4641 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4642 &tx_amic_mux5),
4643 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4644 &tx_amic_mux6),
4645 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4646 &tx_amic_mux7),
4647 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4648 &tx_amic_mux8),
4649
4650 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4651 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4652
4653 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4654 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4655
4656 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4657 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4658
4659 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4660 &sb_tx0_mux),
4661 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4662 &sb_tx1_mux),
4663 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4664 &sb_tx2_mux),
4665 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4666 &sb_tx3_mux),
4667 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4668 &sb_tx4_mux),
4669 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4670 &sb_tx5_mux),
4671 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4672 &sb_tx6_mux),
4673 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4674 &sb_tx7_mux),
4675 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4676 &sb_tx8_mux),
4677
4678 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4679 &tx_adc_mux0, wcd9335_codec_enable_dec,
4680 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4681 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4682
4683 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4684 &tx_adc_mux1, wcd9335_codec_enable_dec,
4685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4686 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4687
4688 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4689 &tx_adc_mux2, wcd9335_codec_enable_dec,
4690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4691 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4692
4693 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4694 &tx_adc_mux3, wcd9335_codec_enable_dec,
4695 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4696 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4697
4698 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4699 &tx_adc_mux4, wcd9335_codec_enable_dec,
4700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4701 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4702
4703 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4704 &tx_adc_mux5, wcd9335_codec_enable_dec,
4705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4706 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4707
4708 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4709 &tx_adc_mux6, wcd9335_codec_enable_dec,
4710 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4711 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4712
4713 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4714 &tx_adc_mux7, wcd9335_codec_enable_dec,
4715 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4716 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4717
4718 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4719 &tx_adc_mux8, wcd9335_codec_enable_dec,
4720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4721 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4722 };
4723
wcd9335_enable_sido_buck(struct snd_soc_component * component)4724 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4725 {
4726 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4727
4728 snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4729 WCD9335_ANA_RCO_BG_EN_MASK,
4730 WCD9335_ANA_RCO_BG_ENABLE);
4731 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4732 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4733 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4734 /* 100us sleep needed after IREF settings */
4735 usleep_range(100, 110);
4736 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4737 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4738 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4739 /* 100us sleep needed after VREF settings */
4740 usleep_range(100, 110);
4741 wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4742 }
4743
wcd9335_enable_efuse_sensing(struct snd_soc_component * comp)4744 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4745 {
4746 _wcd9335_codec_enable_mclk(comp, true);
4747 snd_soc_component_update_bits(comp,
4748 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4749 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4750 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4751 /*
4752 * 5ms sleep required after enabling efuse control
4753 * before checking the status.
4754 */
4755 usleep_range(5000, 5500);
4756
4757 if (!(snd_soc_component_read(comp,
4758 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4759 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4760 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4761
4762 wcd9335_enable_sido_buck(comp);
4763 _wcd9335_codec_enable_mclk(comp, false);
4764
4765 return 0;
4766 }
4767
wcd9335_codec_init(struct snd_soc_component * component)4768 static void wcd9335_codec_init(struct snd_soc_component *component)
4769 {
4770 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4771 int i;
4772
4773 /* ungate MCLK and set clk rate */
4774 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4775 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4776
4777 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4778 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4779 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4780
4781 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4782 snd_soc_component_update_bits(component,
4783 wcd9335_codec_reg_init[i].reg,
4784 wcd9335_codec_reg_init[i].mask,
4785 wcd9335_codec_reg_init[i].val);
4786
4787 wcd9335_enable_efuse_sensing(component);
4788 }
4789
wcd9335_codec_probe(struct snd_soc_component * component)4790 static int wcd9335_codec_probe(struct snd_soc_component *component)
4791 {
4792 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4793 int ret;
4794 int i;
4795
4796 snd_soc_component_init_regmap(component, wcd->regmap);
4797 /* Class-H Init*/
4798 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4799 if (IS_ERR(wcd->clsh_ctrl))
4800 return PTR_ERR(wcd->clsh_ctrl);
4801
4802 /* Default HPH Mode to Class-H HiFi */
4803 wcd->hph_mode = CLS_H_HIFI;
4804 wcd->component = component;
4805
4806 wcd9335_codec_init(component);
4807
4808 for (i = 0; i < NUM_CODEC_DAIS; i++)
4809 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4810
4811 ret = wcd9335_setup_irqs(wcd);
4812 if (ret)
4813 goto free_clsh_ctrl;
4814
4815 return 0;
4816
4817 free_clsh_ctrl:
4818 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4819 return ret;
4820 }
4821
wcd9335_codec_remove(struct snd_soc_component * comp)4822 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4823 {
4824 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4825
4826 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4827 wcd9335_teardown_irqs(wcd);
4828 }
4829
wcd9335_codec_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)4830 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4831 int clk_id, int source,
4832 unsigned int freq, int dir)
4833 {
4834 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4835
4836 wcd->mclk_rate = freq;
4837
4838 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4839 snd_soc_component_update_bits(comp,
4840 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4841 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4842 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4843 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4844 snd_soc_component_update_bits(comp,
4845 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4846 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4847 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4848
4849 return clk_set_rate(wcd->mclk, freq);
4850 }
4851
4852 static const struct snd_soc_component_driver wcd9335_component_drv = {
4853 .probe = wcd9335_codec_probe,
4854 .remove = wcd9335_codec_remove,
4855 .set_sysclk = wcd9335_codec_set_sysclk,
4856 .controls = wcd9335_snd_controls,
4857 .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4858 .dapm_widgets = wcd9335_dapm_widgets,
4859 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4860 .dapm_routes = wcd9335_audio_map,
4861 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4862 .endianness = 1,
4863 };
4864
wcd9335_probe(struct wcd9335_codec * wcd)4865 static int wcd9335_probe(struct wcd9335_codec *wcd)
4866 {
4867 struct device *dev = wcd->dev;
4868
4869 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4870 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4871
4872 wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4873 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4874
4875 return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4876 wcd9335_slim_dais,
4877 ARRAY_SIZE(wcd9335_slim_dais));
4878 }
4879
4880 static const struct regmap_range_cfg wcd9335_ranges[] = {
4881 {
4882 .name = "WCD9335",
4883 .range_min = 0x0,
4884 .range_max = WCD9335_MAX_REGISTER,
4885 .selector_reg = WCD9335_SEL_REGISTER,
4886 .selector_mask = 0xff,
4887 .selector_shift = 0,
4888 .window_start = 0x800,
4889 .window_len = 0x100,
4890 },
4891 };
4892
wcd9335_is_volatile_register(struct device * dev,unsigned int reg)4893 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4894 {
4895 switch (reg) {
4896 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4897 case WCD9335_ANA_MBHC_RESULT_3:
4898 case WCD9335_ANA_MBHC_RESULT_2:
4899 case WCD9335_ANA_MBHC_RESULT_1:
4900 case WCD9335_ANA_MBHC_MECH:
4901 case WCD9335_ANA_MBHC_ELECT:
4902 case WCD9335_ANA_MBHC_ZDET:
4903 case WCD9335_ANA_MICB2:
4904 case WCD9335_ANA_RCO:
4905 case WCD9335_ANA_BIAS:
4906 return true;
4907 default:
4908 return false;
4909 }
4910 }
4911
4912 static const struct regmap_config wcd9335_regmap_config = {
4913 .reg_bits = 16,
4914 .val_bits = 8,
4915 .cache_type = REGCACHE_MAPLE,
4916 .max_register = WCD9335_MAX_REGISTER,
4917 .can_multi_write = true,
4918 .ranges = wcd9335_ranges,
4919 .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4920 .volatile_reg = wcd9335_is_volatile_register,
4921 };
4922
4923 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4924 {
4925 .name = "WCD9335-IFC-DEV",
4926 .range_min = 0x0,
4927 .range_max = WCD9335_MAX_REGISTER,
4928 .selector_reg = WCD9335_SEL_REGISTER,
4929 .selector_mask = 0xfff,
4930 .selector_shift = 0,
4931 .window_start = 0x800,
4932 .window_len = 0x400,
4933 },
4934 };
4935
4936 static const struct regmap_config wcd9335_ifc_regmap_config = {
4937 .reg_bits = 16,
4938 .val_bits = 8,
4939 .can_multi_write = true,
4940 .max_register = WCD9335_MAX_REGISTER,
4941 .ranges = wcd9335_ifc_ranges,
4942 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
4943 };
4944
4945 static const struct regmap_irq wcd9335_codec_irqs[] = {
4946 /* INTR_REG 0 */
4947 [WCD9335_IRQ_SLIMBUS] = {
4948 .reg_offset = 0,
4949 .mask = BIT(0),
4950 .type = {
4951 .type_reg_offset = 0,
4952 .types_supported = IRQ_TYPE_EDGE_BOTH,
4953 .type_reg_mask = BIT(0),
4954 },
4955 },
4956 };
4957
4958 static const unsigned int wcd9335_config_regs[] = {
4959 WCD9335_INTR_LEVEL0,
4960 };
4961
4962 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
4963 .name = "wcd9335_pin1_irq",
4964 .status_base = WCD9335_INTR_PIN1_STATUS0,
4965 .mask_base = WCD9335_INTR_PIN1_MASK0,
4966 .ack_base = WCD9335_INTR_PIN1_CLEAR0,
4967 .num_regs = 4,
4968 .irqs = wcd9335_codec_irqs,
4969 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
4970 .config_base = wcd9335_config_regs,
4971 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs),
4972 .num_config_regs = 4,
4973 .set_type_config = regmap_irq_set_type_config_simple,
4974 };
4975
wcd9335_parse_dt(struct wcd9335_codec * wcd)4976 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
4977 {
4978 struct device *dev = wcd->dev;
4979 int ret;
4980
4981 wcd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
4982 if (IS_ERR(wcd->reset_gpio))
4983 return dev_err_probe(dev, PTR_ERR(wcd->reset_gpio), "Reset GPIO missing from DT\n");
4984
4985 wcd->mclk = devm_clk_get(dev, "mclk");
4986 if (IS_ERR(wcd->mclk))
4987 return dev_err_probe(dev, PTR_ERR(wcd->mclk), "mclk not found\n");
4988
4989 wcd->native_clk = devm_clk_get(dev, "slimbus");
4990 if (IS_ERR(wcd->native_clk))
4991 return dev_err_probe(dev, PTR_ERR(wcd->native_clk), "slimbus clock not found\n");
4992
4993 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd9335_supplies),
4994 wcd9335_supplies);
4995 if (ret)
4996 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
4997
4998 return 0;
4999 }
5000
wcd9335_power_on_reset(struct wcd9335_codec * wcd)5001 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5002 {
5003 /*
5004 * For WCD9335, it takes about 600us for the Vout_A and
5005 * Vout_D to be ready after BUCK_SIDO is powered up.
5006 * SYS_RST_N shouldn't be pulled high during this time
5007 * Toggle the reset line to make sure the reset pulse is
5008 * correctly applied
5009 */
5010 usleep_range(600, 650);
5011
5012 gpiod_set_value(wcd->reset_gpio, 1);
5013 msleep(20);
5014 gpiod_set_value(wcd->reset_gpio, 0);
5015 msleep(20);
5016
5017 return 0;
5018 }
5019
wcd9335_bring_up(struct wcd9335_codec * wcd)5020 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5021 {
5022 struct regmap *rm = wcd->regmap;
5023 int val, byte0;
5024
5025 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5026 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5027
5028 if ((val < 0) || (byte0 < 0)) {
5029 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5030 return -EINVAL;
5031 }
5032
5033 if (byte0 == 0x1) {
5034 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5035 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5036 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5037 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5038 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5039 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5040 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5041 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5042 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5043 } else {
5044 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5045 return -EINVAL;
5046 }
5047
5048 return 0;
5049 }
5050
wcd9335_irq_init(struct wcd9335_codec * wcd)5051 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5052 {
5053 int ret;
5054
5055 /*
5056 * INTR1 consists of all possible interrupt sources Ear OCP,
5057 * HPH OCP, MBHC, MAD, VBAT, and SVA
5058 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5059 */
5060 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5061 if (wcd->intr1 < 0)
5062 return dev_err_probe(wcd->dev, wcd->intr1,
5063 "Unable to configure IRQ\n");
5064
5065 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5066 IRQF_TRIGGER_HIGH, 0,
5067 &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5068 if (ret)
5069 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n");
5070
5071 return 0;
5072 }
5073
wcd9335_slim_probe(struct slim_device * slim)5074 static int wcd9335_slim_probe(struct slim_device *slim)
5075 {
5076 struct device *dev = &slim->dev;
5077 struct wcd9335_codec *wcd;
5078 int ret;
5079
5080 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5081 if (!wcd)
5082 return -ENOMEM;
5083
5084 wcd->dev = dev;
5085 ret = wcd9335_parse_dt(wcd);
5086 if (ret)
5087 return ret;
5088
5089 ret = wcd9335_power_on_reset(wcd);
5090 if (ret)
5091 return ret;
5092
5093 dev_set_drvdata(dev, wcd);
5094
5095 return 0;
5096 }
5097
wcd9335_slim_status(struct slim_device * sdev,enum slim_device_status status)5098 static int wcd9335_slim_status(struct slim_device *sdev,
5099 enum slim_device_status status)
5100 {
5101 struct device *dev = &sdev->dev;
5102 struct device_node *ifc_dev_np;
5103 struct wcd9335_codec *wcd;
5104 int ret;
5105
5106 wcd = dev_get_drvdata(dev);
5107
5108 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5109 if (!ifc_dev_np) {
5110 dev_err(dev, "No Interface device found\n");
5111 return -EINVAL;
5112 }
5113
5114 wcd->slim = sdev;
5115 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5116 of_node_put(ifc_dev_np);
5117 if (!wcd->slim_ifc_dev) {
5118 dev_err(dev, "Unable to get SLIM Interface device\n");
5119 return -EINVAL;
5120 }
5121
5122 slim_get_logical_addr(wcd->slim_ifc_dev);
5123
5124 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5125 if (IS_ERR(wcd->regmap))
5126 return dev_err_probe(dev, PTR_ERR(wcd->regmap),
5127 "Failed to allocate slim register map\n");
5128
5129 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5130 &wcd9335_ifc_regmap_config);
5131 if (IS_ERR(wcd->if_regmap))
5132 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5133 "Failed to allocate ifc register map\n");
5134
5135 ret = wcd9335_bring_up(wcd);
5136 if (ret) {
5137 dev_err(dev, "Failed to bringup WCD9335\n");
5138 return ret;
5139 }
5140
5141 ret = wcd9335_irq_init(wcd);
5142 if (ret)
5143 return ret;
5144
5145 wcd9335_probe(wcd);
5146
5147 return 0;
5148 }
5149
5150 static const struct slim_device_id wcd9335_slim_id[] = {
5151 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5152 {}
5153 };
5154 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5155
5156 static struct slim_driver wcd9335_slim_driver = {
5157 .driver = {
5158 .name = "wcd9335-slim",
5159 },
5160 .probe = wcd9335_slim_probe,
5161 .device_status = wcd9335_slim_status,
5162 .id_table = wcd9335_slim_id,
5163 };
5164
5165 module_slim_driver(wcd9335_slim_driver);
5166 MODULE_DESCRIPTION("WCD9335 slim driver");
5167 MODULE_LICENSE("GPL v2");
5168 MODULE_ALIAS("slim:217:1a0:*");
5169