1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
3
4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <linux/spinlock.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20
21 #include "rockchip_i2s_tdm.h"
22
23 #define DRV_NAME "rockchip-i2s-tdm"
24
25 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */
26 #define MULTIPLEX_CH_MAX 10
27
28 #define TRCM_TXRX 0
29 #define TRCM_TX 1
30 #define TRCM_RX 2
31
32 struct txrx_config {
33 u32 addr;
34 u32 reg;
35 u32 txonly;
36 u32 rxonly;
37 };
38
39 struct rk_i2s_soc_data {
40 u32 softrst_offset;
41 u32 grf_reg_offset;
42 u32 grf_shift;
43 int config_count;
44 const struct txrx_config *configs;
45 int (*init)(struct device *dev, u32 addr);
46 };
47
48 struct rk_i2s_tdm_dev {
49 struct device *dev;
50 struct clk *hclk;
51 struct clk *mclk_tx;
52 struct clk *mclk_rx;
53 struct regmap *regmap;
54 struct regmap *grf;
55 struct snd_dmaengine_dai_dma_data capture_dma_data;
56 struct snd_dmaengine_dai_dma_data playback_dma_data;
57 struct reset_control *tx_reset;
58 struct reset_control *rx_reset;
59 const struct rk_i2s_soc_data *soc_data;
60 bool is_master_mode;
61 bool io_multiplex;
62 bool tdm_mode;
63 unsigned int frame_width;
64 unsigned int clk_trcm;
65 unsigned int i2s_sdis[CH_GRP_MAX];
66 unsigned int i2s_sdos[CH_GRP_MAX];
67 int refcount;
68 spinlock_t lock; /* xfer lock */
69 bool has_playback;
70 bool has_capture;
71 struct snd_soc_dai_driver *dai;
72 unsigned int mclk_rx_freq;
73 unsigned int mclk_tx_freq;
74 };
75
to_ch_num(unsigned int val)76 static int to_ch_num(unsigned int val)
77 {
78 switch (val) {
79 case I2S_CHN_4:
80 return 4;
81 case I2S_CHN_6:
82 return 6;
83 case I2S_CHN_8:
84 return 8;
85 default:
86 return 2;
87 }
88 }
89
i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev * i2s_tdm)90 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
91 {
92 clk_disable_unprepare(i2s_tdm->mclk_tx);
93 clk_disable_unprepare(i2s_tdm->mclk_rx);
94 }
95
96 /**
97 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
98 * failure.
99 * @i2s_tdm: rk_i2s_tdm_dev struct
100 *
101 * This function attempts to enable all mclk clocks, but cleans up after
102 * itself on failure. Guarantees to balance its calls.
103 *
104 * Returns success (0) or negative errno.
105 */
i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev * i2s_tdm)106 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
107 {
108 int ret = 0;
109
110 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
111 if (ret)
112 goto err_mclk_tx;
113 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
114 if (ret)
115 goto err_mclk_rx;
116
117 return 0;
118
119 err_mclk_rx:
120 clk_disable_unprepare(i2s_tdm->mclk_tx);
121 err_mclk_tx:
122 return ret;
123 }
124
i2s_tdm_runtime_suspend(struct device * dev)125 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
126 {
127 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
128
129 regcache_cache_only(i2s_tdm->regmap, true);
130 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
131
132 clk_disable_unprepare(i2s_tdm->hclk);
133
134 return 0;
135 }
136
i2s_tdm_runtime_resume(struct device * dev)137 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
138 {
139 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
140 int ret;
141
142 ret = clk_prepare_enable(i2s_tdm->hclk);
143 if (ret)
144 goto err_hclk;
145
146 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
147 if (ret)
148 goto err_mclk;
149
150 regcache_cache_only(i2s_tdm->regmap, false);
151 regcache_mark_dirty(i2s_tdm->regmap);
152
153 ret = regcache_sync(i2s_tdm->regmap);
154 if (ret)
155 goto err_regcache;
156
157 return 0;
158
159 err_regcache:
160 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
161 err_mclk:
162 clk_disable_unprepare(i2s_tdm->hclk);
163 err_hclk:
164 return ret;
165 }
166
to_info(struct snd_soc_dai * dai)167 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
168 {
169 return snd_soc_dai_get_drvdata(dai);
170 }
171
172 /*
173 * Makes sure that both tx and rx are reset at the same time to sync lrck
174 * when clk_trcm > 0.
175 */
rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev * i2s_tdm)176 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
177 {
178 /* This is technically race-y.
179 *
180 * In an ideal world, we could atomically assert both resets at the
181 * same time, through an atomic bulk reset API. This API however does
182 * not exist, so what the downstream vendor code used to do was
183 * implement half a reset controller here and require the CRU to be
184 * passed to the driver as a device tree node. Violating abstractions
185 * like that is bad, especially when it influences something like the
186 * bindings which are supposed to describe the hardware, not whatever
187 * workarounds the driver needs, so it was dropped.
188 *
189 * In practice, asserting the resets one by one appears to work just
190 * fine for playback. During duplex (playback + capture) operation,
191 * this might become an issue, but that should be solved by the
192 * implementation of the aforementioned API, not by shoving a reset
193 * controller into an audio driver.
194 */
195
196 reset_control_assert(i2s_tdm->tx_reset);
197 reset_control_assert(i2s_tdm->rx_reset);
198 udelay(10);
199 reset_control_deassert(i2s_tdm->tx_reset);
200 reset_control_deassert(i2s_tdm->rx_reset);
201 udelay(10);
202 }
203
rockchip_snd_reset(struct reset_control * rc)204 static void rockchip_snd_reset(struct reset_control *rc)
205 {
206 reset_control_assert(rc);
207 udelay(10);
208 reset_control_deassert(rc);
209 udelay(10);
210 }
211
rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev * i2s_tdm,unsigned int clr)212 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
213 unsigned int clr)
214 {
215 unsigned int xfer_mask = 0;
216 unsigned int xfer_val = 0;
217 unsigned int val;
218 int retry = 10;
219 bool tx = clr & I2S_CLR_TXC;
220 bool rx = clr & I2S_CLR_RXC;
221
222 if (!(rx || tx))
223 return;
224
225 if (tx) {
226 xfer_mask = I2S_XFER_TXS_START;
227 xfer_val = I2S_XFER_TXS_STOP;
228 }
229 if (rx) {
230 xfer_mask |= I2S_XFER_RXS_START;
231 xfer_val |= I2S_XFER_RXS_STOP;
232 }
233
234 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
235 udelay(150);
236 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
237
238 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
239 /* Wait on the clear operation to finish */
240 while (val) {
241 udelay(15);
242 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
243 retry--;
244 if (!retry) {
245 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
246 tx ? "tx" : "", rx ? "rx" : "");
247 if (rx && tx)
248 rockchip_snd_xfer_sync_reset(i2s_tdm);
249 else if (tx)
250 rockchip_snd_reset(i2s_tdm->tx_reset);
251 else if (rx)
252 rockchip_snd_reset(i2s_tdm->rx_reset);
253 break;
254 }
255 }
256 }
257
rockchip_enable_tde(struct regmap * regmap)258 static inline void rockchip_enable_tde(struct regmap *regmap)
259 {
260 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
261 I2S_DMACR_TDE_ENABLE);
262 }
263
rockchip_disable_tde(struct regmap * regmap)264 static inline void rockchip_disable_tde(struct regmap *regmap)
265 {
266 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
267 I2S_DMACR_TDE_DISABLE);
268 }
269
rockchip_enable_rde(struct regmap * regmap)270 static inline void rockchip_enable_rde(struct regmap *regmap)
271 {
272 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
273 I2S_DMACR_RDE_ENABLE);
274 }
275
rockchip_disable_rde(struct regmap * regmap)276 static inline void rockchip_disable_rde(struct regmap *regmap)
277 {
278 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
279 I2S_DMACR_RDE_DISABLE);
280 }
281
282 /* only used when clk_trcm > 0 */
rockchip_snd_txrxctrl(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,int on)283 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
284 struct snd_soc_dai *dai, int on)
285 {
286 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
287 unsigned long flags;
288
289 spin_lock_irqsave(&i2s_tdm->lock, flags);
290 if (on) {
291 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
292 rockchip_enable_tde(i2s_tdm->regmap);
293 else
294 rockchip_enable_rde(i2s_tdm->regmap);
295
296 if (++i2s_tdm->refcount == 1) {
297 rockchip_snd_xfer_sync_reset(i2s_tdm);
298 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
299 I2S_XFER_TXS_START |
300 I2S_XFER_RXS_START,
301 I2S_XFER_TXS_START |
302 I2S_XFER_RXS_START);
303 }
304 } else {
305 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
306 rockchip_disable_tde(i2s_tdm->regmap);
307 else
308 rockchip_disable_rde(i2s_tdm->regmap);
309
310 if (--i2s_tdm->refcount == 0) {
311 rockchip_snd_xfer_clear(i2s_tdm,
312 I2S_CLR_TXC | I2S_CLR_RXC);
313 }
314 }
315 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
316 }
317
rockchip_snd_txctrl(struct rk_i2s_tdm_dev * i2s_tdm,int on)318 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
319 {
320 if (on) {
321 rockchip_enable_tde(i2s_tdm->regmap);
322
323 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
324 I2S_XFER_TXS_START,
325 I2S_XFER_TXS_START);
326 } else {
327 rockchip_disable_tde(i2s_tdm->regmap);
328
329 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
330 }
331 }
332
rockchip_snd_rxctrl(struct rk_i2s_tdm_dev * i2s_tdm,int on)333 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
334 {
335 if (on) {
336 rockchip_enable_rde(i2s_tdm->regmap);
337
338 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
339 I2S_XFER_RXS_START,
340 I2S_XFER_RXS_START);
341 } else {
342 rockchip_disable_rde(i2s_tdm->regmap);
343
344 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
345 }
346 }
347
rockchip_i2s_tdm_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)348 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
349 unsigned int fmt)
350 {
351 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
352 unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
353 int ret;
354 bool is_tdm = i2s_tdm->tdm_mode;
355
356 ret = pm_runtime_resume_and_get(cpu_dai->dev);
357 if (ret < 0 && ret != -EACCES)
358 return ret;
359
360 mask = I2S_CKR_MSS_MASK;
361 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
362 case SND_SOC_DAIFMT_BP_FP:
363 val = I2S_CKR_MSS_MASTER;
364 i2s_tdm->is_master_mode = true;
365 break;
366 case SND_SOC_DAIFMT_BC_FC:
367 val = I2S_CKR_MSS_SLAVE;
368 i2s_tdm->is_master_mode = false;
369 break;
370 default:
371 ret = -EINVAL;
372 goto err_pm_put;
373 }
374
375 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
376
377 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
378 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
379 case SND_SOC_DAIFMT_NB_NF:
380 val = I2S_CKR_CKP_NORMAL |
381 I2S_CKR_TLP_NORMAL |
382 I2S_CKR_RLP_NORMAL;
383 break;
384 case SND_SOC_DAIFMT_NB_IF:
385 val = I2S_CKR_CKP_NORMAL |
386 I2S_CKR_TLP_INVERTED |
387 I2S_CKR_RLP_INVERTED;
388 break;
389 case SND_SOC_DAIFMT_IB_NF:
390 val = I2S_CKR_CKP_INVERTED |
391 I2S_CKR_TLP_NORMAL |
392 I2S_CKR_RLP_NORMAL;
393 break;
394 case SND_SOC_DAIFMT_IB_IF:
395 val = I2S_CKR_CKP_INVERTED |
396 I2S_CKR_TLP_INVERTED |
397 I2S_CKR_RLP_INVERTED;
398 break;
399 default:
400 ret = -EINVAL;
401 goto err_pm_put;
402 }
403
404 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
405
406 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
407 case SND_SOC_DAIFMT_RIGHT_J:
408 txcr_val = I2S_TXCR_IBM_RSJM;
409 rxcr_val = I2S_RXCR_IBM_RSJM;
410 break;
411 case SND_SOC_DAIFMT_LEFT_J:
412 txcr_val = I2S_TXCR_IBM_LSJM;
413 rxcr_val = I2S_RXCR_IBM_LSJM;
414 break;
415 case SND_SOC_DAIFMT_I2S:
416 txcr_val = I2S_TXCR_IBM_NORMAL;
417 rxcr_val = I2S_RXCR_IBM_NORMAL;
418 break;
419 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
420 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
421 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
422 break;
423 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
424 txcr_val = I2S_TXCR_TFS_PCM;
425 rxcr_val = I2S_RXCR_TFS_PCM;
426 break;
427 default:
428 ret = -EINVAL;
429 goto err_pm_put;
430 }
431
432 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
433 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
434
435 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
436 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
437
438 if (is_tdm) {
439 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
440 case SND_SOC_DAIFMT_RIGHT_J:
441 val = I2S_TXCR_TFS_TDM_I2S;
442 tdm_val = TDM_SHIFT_CTRL(2);
443 break;
444 case SND_SOC_DAIFMT_LEFT_J:
445 val = I2S_TXCR_TFS_TDM_I2S;
446 tdm_val = TDM_SHIFT_CTRL(1);
447 break;
448 case SND_SOC_DAIFMT_I2S:
449 val = I2S_TXCR_TFS_TDM_I2S;
450 tdm_val = TDM_SHIFT_CTRL(0);
451 break;
452 case SND_SOC_DAIFMT_DSP_A:
453 val = I2S_TXCR_TFS_TDM_PCM;
454 tdm_val = TDM_SHIFT_CTRL(2);
455 break;
456 case SND_SOC_DAIFMT_DSP_B:
457 val = I2S_TXCR_TFS_TDM_PCM;
458 tdm_val = TDM_SHIFT_CTRL(4);
459 break;
460 default:
461 ret = -EINVAL;
462 goto err_pm_put;
463 }
464
465 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
466 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
467
468 mask = I2S_TXCR_TFS_MASK;
469 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
470 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
471
472 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
473 TDM_SHIFT_CTRL_MSK;
474 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
475 mask, tdm_val);
476 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
477 mask, tdm_val);
478 }
479
480 err_pm_put:
481 pm_runtime_put(cpu_dai->dev);
482
483 return ret;
484 }
485
rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)486 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
487 struct rk_i2s_tdm_dev *i2s_tdm)
488 {
489 int stream;
490
491 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
492 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
493 rockchip_disable_tde(i2s_tdm->regmap);
494 else
495 rockchip_disable_rde(i2s_tdm->regmap);
496
497 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
498 }
499
rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)500 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
501 struct rk_i2s_tdm_dev *i2s_tdm)
502 {
503 int stream;
504
505 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
506 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
507 rockchip_enable_tde(i2s_tdm->regmap);
508 else
509 rockchip_enable_rde(i2s_tdm->regmap);
510
511 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
512 I2S_XFER_TXS_START |
513 I2S_XFER_RXS_START,
514 I2S_XFER_TXS_START |
515 I2S_XFER_RXS_START);
516 }
517
rockchip_i2s_ch_to_io(unsigned int ch,bool substream_capture)518 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
519 {
520 if (substream_capture) {
521 switch (ch) {
522 case I2S_CHN_4:
523 return I2S_IO_6CH_OUT_4CH_IN;
524 case I2S_CHN_6:
525 return I2S_IO_4CH_OUT_6CH_IN;
526 case I2S_CHN_8:
527 return I2S_IO_2CH_OUT_8CH_IN;
528 default:
529 return I2S_IO_8CH_OUT_2CH_IN;
530 }
531 } else {
532 switch (ch) {
533 case I2S_CHN_4:
534 return I2S_IO_4CH_OUT_6CH_IN;
535 case I2S_CHN_6:
536 return I2S_IO_6CH_OUT_4CH_IN;
537 case I2S_CHN_8:
538 return I2S_IO_8CH_OUT_2CH_IN;
539 default:
540 return I2S_IO_2CH_OUT_8CH_IN;
541 }
542 }
543 }
544
rockchip_i2s_io_multiplex(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)545 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
546 struct snd_soc_dai *dai)
547 {
548 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
549 int usable_chs = MULTIPLEX_CH_MAX;
550 unsigned int val = 0;
551
552 if (!i2s_tdm->io_multiplex)
553 return 0;
554
555 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
556 dev_err(i2s_tdm->dev,
557 "io multiplex not supported for this device\n");
558 return -EINVAL;
559 }
560
561 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
562 struct snd_pcm_str *playback_str =
563 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
564
565 if (playback_str->substream_opened) {
566 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
567 val &= I2S_TXCR_CSR_MASK;
568 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
569 }
570
571 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
572 val &= I2S_RXCR_CSR_MASK;
573
574 if (to_ch_num(val) > usable_chs) {
575 dev_err(i2s_tdm->dev,
576 "Capture channels (%d) > usable channels (%d)\n",
577 to_ch_num(val), usable_chs);
578 return -EINVAL;
579 }
580
581 rockchip_i2s_ch_to_io(val, true);
582 } else {
583 struct snd_pcm_str *capture_str =
584 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
585
586 if (capture_str->substream_opened) {
587 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
588 val &= I2S_RXCR_CSR_MASK;
589 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
590 }
591
592 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
593 val &= I2S_TXCR_CSR_MASK;
594
595 if (to_ch_num(val) > usable_chs) {
596 dev_err(i2s_tdm->dev,
597 "Playback channels (%d) > usable channels (%d)\n",
598 to_ch_num(val), usable_chs);
599 return -EINVAL;
600 }
601 }
602
603 val <<= i2s_tdm->soc_data->grf_shift;
604 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
605 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
606
607 return 0;
608 }
609
rockchip_i2s_trcm_mode(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,unsigned int div_bclk,unsigned int div_lrck,unsigned int fmt)610 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
611 struct snd_soc_dai *dai,
612 unsigned int div_bclk,
613 unsigned int div_lrck,
614 unsigned int fmt)
615 {
616 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
617 unsigned long flags;
618
619 if (!i2s_tdm->clk_trcm)
620 return 0;
621
622 spin_lock_irqsave(&i2s_tdm->lock, flags);
623 if (i2s_tdm->refcount)
624 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
625
626 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
627 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
628 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
629 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
630 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
631 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
632
633 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
634 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
635 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
636 fmt);
637 else
638 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
639 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
640 fmt);
641
642 if (i2s_tdm->refcount)
643 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
644 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
645
646 return 0;
647 }
648
rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai * cpu_dai,int stream,unsigned int freq,int dir)649 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
650 unsigned int freq, int dir)
651 {
652 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
653
654 if (i2s_tdm->clk_trcm) {
655 i2s_tdm->mclk_tx_freq = freq;
656 i2s_tdm->mclk_rx_freq = freq;
657 } else {
658 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
659 i2s_tdm->mclk_tx_freq = freq;
660 else
661 i2s_tdm->mclk_rx_freq = freq;
662 }
663
664 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
665 stream ? "rx" : "tx", freq);
666
667 return 0;
668 }
669
rockchip_i2s_tdm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)670 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
671 struct snd_pcm_hw_params *params,
672 struct snd_soc_dai *dai)
673 {
674 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
675 unsigned int val = 0;
676 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
677 int err;
678
679 if (i2s_tdm->is_master_mode) {
680 struct clk *mclk;
681
682 if (i2s_tdm->clk_trcm == TRCM_TX) {
683 mclk = i2s_tdm->mclk_tx;
684 mclk_rate = i2s_tdm->mclk_tx_freq;
685 } else if (i2s_tdm->clk_trcm == TRCM_RX) {
686 mclk = i2s_tdm->mclk_rx;
687 mclk_rate = i2s_tdm->mclk_rx_freq;
688 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
689 mclk = i2s_tdm->mclk_tx;
690 mclk_rate = i2s_tdm->mclk_tx_freq;
691 } else {
692 mclk = i2s_tdm->mclk_rx;
693 mclk_rate = i2s_tdm->mclk_rx_freq;
694 }
695
696 err = clk_set_rate(mclk, mclk_rate);
697 if (err)
698 return err;
699
700 mclk_rate = clk_get_rate(mclk);
701 bclk_rate = i2s_tdm->frame_width * params_rate(params);
702 if (!bclk_rate)
703 return -EINVAL;
704
705 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
706 div_lrck = bclk_rate / params_rate(params);
707 }
708
709 switch (params_format(params)) {
710 case SNDRV_PCM_FORMAT_S8:
711 val |= I2S_TXCR_VDW(8);
712 break;
713 case SNDRV_PCM_FORMAT_S16_LE:
714 val |= I2S_TXCR_VDW(16);
715 break;
716 case SNDRV_PCM_FORMAT_S20_3LE:
717 val |= I2S_TXCR_VDW(20);
718 break;
719 case SNDRV_PCM_FORMAT_S24_LE:
720 val |= I2S_TXCR_VDW(24);
721 break;
722 case SNDRV_PCM_FORMAT_S32_LE:
723 val |= I2S_TXCR_VDW(32);
724 break;
725 default:
726 return -EINVAL;
727 }
728
729 switch (params_channels(params)) {
730 case 8:
731 val |= I2S_CHN_8;
732 break;
733 case 6:
734 val |= I2S_CHN_6;
735 break;
736 case 4:
737 val |= I2S_CHN_4;
738 break;
739 case 2:
740 val |= I2S_CHN_2;
741 break;
742 default:
743 return -EINVAL;
744 }
745
746 if (i2s_tdm->clk_trcm) {
747 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
748 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
749 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
750 I2S_CLKDIV_TXM_MASK,
751 I2S_CLKDIV_TXM(div_bclk));
752 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
753 I2S_CKR_TSD_MASK,
754 I2S_CKR_TSD(div_lrck));
755 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
756 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
757 val);
758 } else {
759 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
760 I2S_CLKDIV_RXM_MASK,
761 I2S_CLKDIV_RXM(div_bclk));
762 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
763 I2S_CKR_RSD_MASK,
764 I2S_CKR_RSD(div_lrck));
765 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
766 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
767 val);
768 }
769
770 return rockchip_i2s_io_multiplex(substream, dai);
771 }
772
rockchip_i2s_tdm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)773 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
774 int cmd, struct snd_soc_dai *dai)
775 {
776 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
777
778 switch (cmd) {
779 case SNDRV_PCM_TRIGGER_START:
780 case SNDRV_PCM_TRIGGER_RESUME:
781 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
782 if (i2s_tdm->clk_trcm)
783 rockchip_snd_txrxctrl(substream, dai, 1);
784 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
785 rockchip_snd_rxctrl(i2s_tdm, 1);
786 else
787 rockchip_snd_txctrl(i2s_tdm, 1);
788 break;
789 case SNDRV_PCM_TRIGGER_SUSPEND:
790 case SNDRV_PCM_TRIGGER_STOP:
791 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
792 if (i2s_tdm->clk_trcm)
793 rockchip_snd_txrxctrl(substream, dai, 0);
794 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
795 rockchip_snd_rxctrl(i2s_tdm, 0);
796 else
797 rockchip_snd_txctrl(i2s_tdm, 0);
798 break;
799 default:
800 return -EINVAL;
801 }
802
803 return 0;
804 }
805
rockchip_i2s_tdm_dai_probe(struct snd_soc_dai * dai)806 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
807 {
808 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
809
810 if (i2s_tdm->has_capture)
811 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data);
812 if (i2s_tdm->has_playback)
813 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
814
815 return 0;
816 }
817
rockchip_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)818 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
819 unsigned int tx_mask, unsigned int rx_mask,
820 int slots, int slot_width)
821 {
822 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
823 unsigned int mask, val;
824
825 i2s_tdm->tdm_mode = true;
826 i2s_tdm->frame_width = slots * slot_width;
827 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
828 val = TDM_SLOT_BIT_WIDTH(slot_width) |
829 TDM_FRAME_WIDTH(slots * slot_width);
830 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
831 mask, val);
832 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
833 mask, val);
834
835 return 0;
836 }
837
rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)838 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
839 unsigned int ratio)
840 {
841 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
842
843 if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
844 return -EINVAL;
845
846 i2s_tdm->frame_width = ratio;
847
848 return 0;
849 }
850
851 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
852 .probe = rockchip_i2s_tdm_dai_probe,
853 .hw_params = rockchip_i2s_tdm_hw_params,
854 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
855 .set_fmt = rockchip_i2s_tdm_set_fmt,
856 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
857 .set_tdm_slot = rockchip_dai_tdm_slot,
858 .trigger = rockchip_i2s_tdm_trigger,
859 };
860
861 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
862 .name = DRV_NAME,
863 .legacy_dai_naming = 1,
864 };
865
rockchip_i2s_tdm_wr_reg(struct device * dev,unsigned int reg)866 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
867 {
868 switch (reg) {
869 case I2S_TXCR:
870 case I2S_RXCR:
871 case I2S_CKR:
872 case I2S_DMACR:
873 case I2S_INTCR:
874 case I2S_XFER:
875 case I2S_CLR:
876 case I2S_TXDR:
877 case I2S_TDM_TXCR:
878 case I2S_TDM_RXCR:
879 case I2S_CLKDIV:
880 return true;
881 default:
882 return false;
883 }
884 }
885
rockchip_i2s_tdm_rd_reg(struct device * dev,unsigned int reg)886 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
887 {
888 switch (reg) {
889 case I2S_TXCR:
890 case I2S_RXCR:
891 case I2S_CKR:
892 case I2S_DMACR:
893 case I2S_INTCR:
894 case I2S_XFER:
895 case I2S_CLR:
896 case I2S_TXDR:
897 case I2S_RXDR:
898 case I2S_TXFIFOLR:
899 case I2S_INTSR:
900 case I2S_RXFIFOLR:
901 case I2S_TDM_TXCR:
902 case I2S_TDM_RXCR:
903 case I2S_CLKDIV:
904 return true;
905 default:
906 return false;
907 }
908 }
909
rockchip_i2s_tdm_volatile_reg(struct device * dev,unsigned int reg)910 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
911 {
912 switch (reg) {
913 case I2S_TXFIFOLR:
914 case I2S_INTSR:
915 case I2S_CLR:
916 case I2S_TXDR:
917 case I2S_RXDR:
918 case I2S_RXFIFOLR:
919 return true;
920 default:
921 return false;
922 }
923 }
924
rockchip_i2s_tdm_precious_reg(struct device * dev,unsigned int reg)925 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
926 {
927 if (reg == I2S_RXDR)
928 return true;
929 return false;
930 }
931
932 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
933 {0x00, 0x7200000f},
934 {0x04, 0x01c8000f},
935 {0x08, 0x00001f1f},
936 {0x10, 0x001f0000},
937 {0x14, 0x01f00000},
938 {0x30, 0x00003eff},
939 {0x34, 0x00003eff},
940 {0x38, 0x00000707},
941 };
942
943 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
944 .reg_bits = 32,
945 .reg_stride = 4,
946 .val_bits = 32,
947 .max_register = I2S_CLKDIV,
948 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
949 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
950 .writeable_reg = rockchip_i2s_tdm_wr_reg,
951 .readable_reg = rockchip_i2s_tdm_rd_reg,
952 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
953 .precious_reg = rockchip_i2s_tdm_precious_reg,
954 .cache_type = REGCACHE_FLAT,
955 };
956
common_soc_init(struct device * dev,u32 addr)957 static int common_soc_init(struct device *dev, u32 addr)
958 {
959 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
960 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
961 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
962 int i;
963
964 if (trcm == TRCM_TXRX)
965 return 0;
966
967 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
968 dev_err(i2s_tdm->dev,
969 "no grf present but non-txrx TRCM specified\n");
970 return -EINVAL;
971 }
972
973 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
974 if (addr != configs[i].addr)
975 continue;
976 reg = configs[i].reg;
977 if (trcm == TRCM_TX)
978 val = configs[i].txonly;
979 else
980 val = configs[i].rxonly;
981
982 if (reg)
983 regmap_write(i2s_tdm->grf, reg, val);
984 }
985
986 return 0;
987 }
988
989 static const struct txrx_config px30_txrx_config[] = {
990 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
991 };
992
993 static const struct txrx_config rk1808_txrx_config[] = {
994 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
995 };
996
997 static const struct txrx_config rk3308_txrx_config[] = {
998 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
999 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1000 };
1001
1002 static const struct txrx_config rk3568_txrx_config[] = {
1003 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1004 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1005 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1006 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1007 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1008 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1009 };
1010
1011 static const struct txrx_config rv1126_txrx_config[] = {
1012 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1013 };
1014
1015 static const struct rk_i2s_soc_data px30_i2s_soc_data = {
1016 .softrst_offset = 0x0300,
1017 .configs = px30_txrx_config,
1018 .config_count = ARRAY_SIZE(px30_txrx_config),
1019 .init = common_soc_init,
1020 };
1021
1022 static const struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1023 .softrst_offset = 0x0300,
1024 .configs = rk1808_txrx_config,
1025 .config_count = ARRAY_SIZE(rk1808_txrx_config),
1026 .init = common_soc_init,
1027 };
1028
1029 static const struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1030 .softrst_offset = 0x0400,
1031 .grf_reg_offset = 0x0308,
1032 .grf_shift = 5,
1033 .configs = rk3308_txrx_config,
1034 .config_count = ARRAY_SIZE(rk3308_txrx_config),
1035 .init = common_soc_init,
1036 };
1037
1038 static const struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1039 .softrst_offset = 0x0400,
1040 .configs = rk3568_txrx_config,
1041 .config_count = ARRAY_SIZE(rk3568_txrx_config),
1042 .init = common_soc_init,
1043 };
1044
1045 static const struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1046 .softrst_offset = 0x0300,
1047 .configs = rv1126_txrx_config,
1048 .config_count = ARRAY_SIZE(rv1126_txrx_config),
1049 .init = common_soc_init,
1050 };
1051
1052 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1053 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1054 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1055 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1056 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1057 { .compatible = "rockchip,rk3588-i2s-tdm" },
1058 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1059 {},
1060 };
1061
1062 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1063 .ops = &rockchip_i2s_tdm_dai_ops,
1064 };
1065
rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev * i2s_tdm)1066 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1067 {
1068 struct snd_soc_dai_driver *dai;
1069 struct property *dma_names;
1070 const char *dma_name;
1071 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1072 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1073 SNDRV_PCM_FMTBIT_S32_LE);
1074 struct device_node *node = i2s_tdm->dev->of_node;
1075
1076 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1077 if (!strcmp(dma_name, "tx"))
1078 i2s_tdm->has_playback = true;
1079 if (!strcmp(dma_name, "rx"))
1080 i2s_tdm->has_capture = true;
1081 }
1082
1083 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1084 sizeof(*dai), GFP_KERNEL);
1085 if (!dai)
1086 return -ENOMEM;
1087
1088 if (i2s_tdm->has_playback) {
1089 dai->playback.stream_name = "Playback";
1090 dai->playback.channels_min = 2;
1091 dai->playback.channels_max = 8;
1092 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1093 dai->playback.formats = formats;
1094 }
1095
1096 if (i2s_tdm->has_capture) {
1097 dai->capture.stream_name = "Capture";
1098 dai->capture.channels_min = 2;
1099 dai->capture.channels_max = 8;
1100 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1101 dai->capture.formats = formats;
1102 }
1103
1104 if (i2s_tdm->clk_trcm != TRCM_TXRX)
1105 dai->symmetric_rate = 1;
1106
1107 i2s_tdm->dai = dai;
1108
1109 return 0;
1110 }
1111
rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)1112 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1113 int num,
1114 bool is_rx_path)
1115 {
1116 unsigned int *i2s_data;
1117 int i, j;
1118
1119 if (is_rx_path)
1120 i2s_data = i2s_tdm->i2s_sdis;
1121 else
1122 i2s_data = i2s_tdm->i2s_sdos;
1123
1124 for (i = 0; i < num; i++) {
1125 if (i2s_data[i] > CH_GRP_MAX - 1) {
1126 dev_err(i2s_tdm->dev,
1127 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1128 is_rx_path ? "RX" : "TX",
1129 i, i2s_data[i], CH_GRP_MAX);
1130 return -EINVAL;
1131 }
1132
1133 for (j = 0; j < num; j++) {
1134 if (i == j)
1135 continue;
1136
1137 if (i2s_data[i] == i2s_data[j]) {
1138 dev_err(i2s_tdm->dev,
1139 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1140 is_rx_path ? "RX" : "TX",
1141 i, i2s_data[i],
1142 j, i2s_data[j]);
1143 return -EINVAL;
1144 }
1145 }
1146 }
1147
1148 return 0;
1149 }
1150
rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)1151 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1152 int num)
1153 {
1154 int idx;
1155
1156 for (idx = 0; idx < num; idx++) {
1157 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1158 I2S_TXCR_PATH_MASK(idx),
1159 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1160 }
1161 }
1162
rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)1163 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1164 int num)
1165 {
1166 int idx;
1167
1168 for (idx = 0; idx < num; idx++) {
1169 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1170 I2S_RXCR_PATH_MASK(idx),
1171 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1172 }
1173 }
1174
rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)1175 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1176 int num, bool is_rx_path)
1177 {
1178 if (is_rx_path)
1179 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1180 else
1181 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1182 }
1183
rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np,bool is_rx_path)1184 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1185 struct device_node *np,
1186 bool is_rx_path)
1187 {
1188 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1189 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1190 char *i2s_path_prop;
1191 unsigned int *i2s_data;
1192 int num, ret = 0;
1193
1194 if (is_rx_path) {
1195 i2s_path_prop = i2s_rx_path_prop;
1196 i2s_data = i2s_tdm->i2s_sdis;
1197 } else {
1198 i2s_path_prop = i2s_tx_path_prop;
1199 i2s_data = i2s_tdm->i2s_sdos;
1200 }
1201
1202 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1203 if (num < 0) {
1204 if (num != -ENOENT) {
1205 dev_err(i2s_tdm->dev,
1206 "Failed to read '%s' num: %d\n",
1207 i2s_path_prop, num);
1208 ret = num;
1209 }
1210 return ret;
1211 } else if (num != CH_GRP_MAX) {
1212 dev_err(i2s_tdm->dev,
1213 "The num: %d should be: %d\n", num, CH_GRP_MAX);
1214 return -EINVAL;
1215 }
1216
1217 ret = of_property_read_u32_array(np, i2s_path_prop,
1218 i2s_data, num);
1219 if (ret < 0) {
1220 dev_err(i2s_tdm->dev,
1221 "Failed to read '%s': %d\n",
1222 i2s_path_prop, ret);
1223 return ret;
1224 }
1225
1226 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1227 if (ret < 0) {
1228 dev_err(i2s_tdm->dev,
1229 "Failed to check i2s data bus: %d\n", ret);
1230 return ret;
1231 }
1232
1233 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1234
1235 return 0;
1236 }
1237
rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)1238 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1239 struct device_node *np)
1240 {
1241 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1242 }
1243
rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)1244 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1245 struct device_node *np)
1246 {
1247 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1248 }
1249
rockchip_i2s_tdm_probe(struct platform_device * pdev)1250 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1251 {
1252 struct device_node *node = pdev->dev.of_node;
1253 struct rk_i2s_tdm_dev *i2s_tdm;
1254 struct resource *res;
1255 void __iomem *regs;
1256 int ret;
1257
1258 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1259 if (!i2s_tdm)
1260 return -ENOMEM;
1261
1262 i2s_tdm->dev = &pdev->dev;
1263
1264 spin_lock_init(&i2s_tdm->lock);
1265 i2s_tdm->soc_data = device_get_match_data(&pdev->dev);
1266 i2s_tdm->frame_width = 64;
1267
1268 i2s_tdm->clk_trcm = TRCM_TXRX;
1269 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1270 i2s_tdm->clk_trcm = TRCM_TX;
1271 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1272 if (i2s_tdm->clk_trcm) {
1273 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1274 return -EINVAL;
1275 }
1276 i2s_tdm->clk_trcm = TRCM_RX;
1277 }
1278
1279 ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1280 if (ret)
1281 return ret;
1282
1283 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1284 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1285 "tx-m");
1286 if (IS_ERR(i2s_tdm->tx_reset)) {
1287 ret = PTR_ERR(i2s_tdm->tx_reset);
1288 return dev_err_probe(i2s_tdm->dev, ret,
1289 "Error in tx-m reset control\n");
1290 }
1291
1292 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1293 "rx-m");
1294 if (IS_ERR(i2s_tdm->rx_reset)) {
1295 ret = PTR_ERR(i2s_tdm->rx_reset);
1296 return dev_err_probe(i2s_tdm->dev, ret,
1297 "Error in rx-m reset control\n");
1298 }
1299
1300 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1301 if (IS_ERR(i2s_tdm->hclk)) {
1302 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1303 "Failed to get clock hclk\n");
1304 }
1305
1306 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1307 if (IS_ERR(i2s_tdm->mclk_tx)) {
1308 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1309 "Failed to get clock mclk_tx\n");
1310 }
1311
1312 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1313 if (IS_ERR(i2s_tdm->mclk_rx)) {
1314 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1315 "Failed to get clock mclk_rx\n");
1316 }
1317
1318 i2s_tdm->io_multiplex =
1319 of_property_read_bool(node, "rockchip,io-multiplex");
1320
1321 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1322 if (IS_ERR(regs)) {
1323 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1324 "Failed to get resource IORESOURCE_MEM\n");
1325 }
1326
1327 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1328 &rockchip_i2s_tdm_regmap_config);
1329 if (IS_ERR(i2s_tdm->regmap)) {
1330 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1331 "Failed to initialise regmap\n");
1332 }
1333
1334 if (i2s_tdm->has_playback) {
1335 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1336 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1337 i2s_tdm->playback_dma_data.maxburst = 8;
1338 }
1339
1340 if (i2s_tdm->has_capture) {
1341 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1342 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1343 i2s_tdm->capture_dma_data.maxburst = 8;
1344 }
1345
1346 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1347 if (ret < 0) {
1348 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1349 return ret;
1350 }
1351
1352 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1353 if (ret < 0) {
1354 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1355 return ret;
1356 }
1357
1358 dev_set_drvdata(&pdev->dev, i2s_tdm);
1359
1360 ret = clk_prepare_enable(i2s_tdm->hclk);
1361 if (ret) {
1362 return dev_err_probe(i2s_tdm->dev, ret,
1363 "Failed to enable clock hclk\n");
1364 }
1365
1366 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1367 if (ret) {
1368 ret = dev_err_probe(i2s_tdm->dev, ret,
1369 "Failed to enable one or more mclks\n");
1370 goto err_disable_hclk;
1371 }
1372
1373 pm_runtime_enable(&pdev->dev);
1374
1375 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1376 I2S_DMACR_TDL(16));
1377 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1378 I2S_DMACR_RDL(16));
1379 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1380 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1381
1382 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1383 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1384
1385 ret = devm_snd_soc_register_component(&pdev->dev,
1386 &rockchip_i2s_tdm_component,
1387 i2s_tdm->dai, 1);
1388
1389 if (ret) {
1390 dev_err(&pdev->dev, "Could not register DAI\n");
1391 goto err_suspend;
1392 }
1393
1394 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1395 if (ret) {
1396 dev_err(&pdev->dev, "Could not register PCM\n");
1397 goto err_suspend;
1398 }
1399
1400 return 0;
1401
1402 err_suspend:
1403 if (!pm_runtime_status_suspended(&pdev->dev))
1404 i2s_tdm_runtime_suspend(&pdev->dev);
1405 pm_runtime_disable(&pdev->dev);
1406
1407 err_disable_hclk:
1408 clk_disable_unprepare(i2s_tdm->hclk);
1409
1410 return ret;
1411 }
1412
rockchip_i2s_tdm_remove(struct platform_device * pdev)1413 static void rockchip_i2s_tdm_remove(struct platform_device *pdev)
1414 {
1415 if (!pm_runtime_status_suspended(&pdev->dev))
1416 i2s_tdm_runtime_suspend(&pdev->dev);
1417
1418 pm_runtime_disable(&pdev->dev);
1419 }
1420
rockchip_i2s_tdm_suspend(struct device * dev)1421 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1422 {
1423 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1424
1425 regcache_mark_dirty(i2s_tdm->regmap);
1426
1427 return 0;
1428 }
1429
rockchip_i2s_tdm_resume(struct device * dev)1430 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1431 {
1432 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1433 int ret;
1434
1435 ret = pm_runtime_resume_and_get(dev);
1436 if (ret < 0)
1437 return ret;
1438 ret = regcache_sync(i2s_tdm->regmap);
1439 pm_runtime_put(dev);
1440
1441 return ret;
1442 }
1443
1444 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1445 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1446 NULL)
1447 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1448 rockchip_i2s_tdm_resume)
1449 };
1450
1451 static struct platform_driver rockchip_i2s_tdm_driver = {
1452 .probe = rockchip_i2s_tdm_probe,
1453 .remove = rockchip_i2s_tdm_remove,
1454 .driver = {
1455 .name = DRV_NAME,
1456 .of_match_table = rockchip_i2s_tdm_match,
1457 .pm = &rockchip_i2s_tdm_pm_ops,
1458 },
1459 };
1460 module_platform_driver(rockchip_i2s_tdm_driver);
1461
1462 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1463 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1464 MODULE_LICENSE("GPL v2");
1465 MODULE_ALIAS("platform:" DRV_NAME);
1466 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
1467