1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
4 //
5 // Copyright (C) 2021 Renesas Electronics Corp.
6 // Copyright (C) 2019 Chris Brandt.
7 //
8
9 #include <linux/clk.h>
10 #include <linux/dmaengine.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <sound/soc.h>
16
17 /* REGISTER OFFSET */
18 #define SSICR 0x000
19 #define SSISR 0x004
20 #define SSIFCR 0x010
21 #define SSIFSR 0x014
22 #define SSIFTDR 0x018
23 #define SSIFRDR 0x01c
24 #define SSIOFR 0x020
25 #define SSISCR 0x024
26
27 /* SSI REGISTER BITS */
28 #define SSICR_DWL(x) (((x) & 0x7) << 19)
29 #define SSICR_SWL(x) (((x) & 0x7) << 16)
30
31 #define SSICR_CKS BIT(30)
32 #define SSICR_TUIEN BIT(29)
33 #define SSICR_TOIEN BIT(28)
34 #define SSICR_RUIEN BIT(27)
35 #define SSICR_ROIEN BIT(26)
36 #define SSICR_MST BIT(14)
37 #define SSICR_BCKP BIT(13)
38 #define SSICR_LRCKP BIT(12)
39 #define SSICR_CKDV(x) (((x) & 0xf) << 4)
40 #define SSICR_TEN BIT(1)
41 #define SSICR_REN BIT(0)
42
43 #define SSISR_TUIRQ BIT(29)
44 #define SSISR_TOIRQ BIT(28)
45 #define SSISR_RUIRQ BIT(27)
46 #define SSISR_ROIRQ BIT(26)
47 #define SSISR_IIRQ BIT(25)
48
49 #define SSIFCR_AUCKE BIT(31)
50 #define SSIFCR_SSIRST BIT(16)
51 #define SSIFCR_TIE BIT(3)
52 #define SSIFCR_RIE BIT(2)
53 #define SSIFCR_TFRST BIT(1)
54 #define SSIFCR_RFRST BIT(0)
55 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST)
56
57 #define SSIFSR_TDC_MASK 0x3f
58 #define SSIFSR_TDC_SHIFT 24
59 #define SSIFSR_RDC_MASK 0x3f
60 #define SSIFSR_RDC_SHIFT 8
61
62 #define SSIFSR_TDE BIT(16)
63 #define SSIFSR_RDF BIT(0)
64
65 #define SSIOFR_LRCONT BIT(8)
66
67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8)
68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0)
69
70 /* Pre allocated buffers sizes */
71 #define PREALLOC_BUFFER (SZ_32K)
72 #define PREALLOC_BUFFER_MAX (SZ_32K)
73
74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */
75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE
76 #define SSI_CHAN_MIN 2
77 #define SSI_CHAN_MAX 2
78 #define SSI_FIFO_DEPTH 32
79
80 struct rz_ssi_priv;
81
82 struct rz_ssi_stream {
83 struct rz_ssi_priv *priv;
84 struct snd_pcm_substream *substream;
85 int fifo_sample_size; /* sample capacity of SSI FIFO */
86 int dma_buffer_pos; /* The address for the next DMA descriptor */
87 int period_counter; /* for keeping track of periods transferred */
88 int sample_width;
89 int buffer_pos; /* current frame position in the buffer */
90 int running; /* 0=stopped, 1=running */
91
92 int uerr_num;
93 int oerr_num;
94
95 struct dma_chan *dma_ch;
96
97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
98 };
99
100 struct rz_ssi_priv {
101 void __iomem *base;
102 struct platform_device *pdev;
103 struct reset_control *rstc;
104 struct device *dev;
105 struct clk *sfr_clk;
106 struct clk *clk;
107
108 phys_addr_t phys;
109 int irq_int;
110 int irq_tx;
111 int irq_rx;
112 int irq_rt;
113
114 spinlock_t lock;
115
116 /*
117 * The SSI supports full-duplex transmission and reception.
118 * However, if an error occurs, channel reset (both transmission
119 * and reception reset) is required.
120 * So it is better to use as half-duplex (playing and recording
121 * should be done on separate channels).
122 */
123 struct rz_ssi_stream playback;
124 struct rz_ssi_stream capture;
125
126 /* clock */
127 unsigned long audio_mck;
128 unsigned long audio_clk_1;
129 unsigned long audio_clk_2;
130
131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
133 bool dma_rt;
134
135 /* Full duplex communication support */
136 struct {
137 unsigned int rate;
138 unsigned int channels;
139 unsigned int sample_width;
140 unsigned int sample_bits;
141 } hw_params_cache;
142 };
143
144 static void rz_ssi_dma_complete(void *data);
145
rz_ssi_reg_writel(struct rz_ssi_priv * priv,uint reg,u32 data)146 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
147 {
148 writel(data, (priv->base + reg));
149 }
150
rz_ssi_reg_readl(struct rz_ssi_priv * priv,uint reg)151 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
152 {
153 return readl(priv->base + reg);
154 }
155
rz_ssi_reg_mask_setl(struct rz_ssi_priv * priv,uint reg,u32 bclr,u32 bset)156 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
157 u32 bclr, u32 bset)
158 {
159 u32 val;
160
161 val = readl(priv->base + reg);
162 val = (val & ~bclr) | bset;
163 writel(val, (priv->base + reg));
164 }
165
166 static inline struct snd_soc_dai *
rz_ssi_get_dai(struct snd_pcm_substream * substream)167 rz_ssi_get_dai(struct snd_pcm_substream *substream)
168 {
169 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
170
171 return snd_soc_rtd_to_cpu(rtd, 0);
172 }
173
rz_ssi_stream_is_play(struct rz_ssi_priv * ssi,struct snd_pcm_substream * substream)174 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi,
175 struct snd_pcm_substream *substream)
176 {
177 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
178 }
179
180 static inline struct rz_ssi_stream *
rz_ssi_stream_get(struct rz_ssi_priv * ssi,struct snd_pcm_substream * substream)181 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
182 {
183 struct rz_ssi_stream *stream = &ssi->playback;
184
185 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
186 stream = &ssi->capture;
187
188 return stream;
189 }
190
rz_ssi_is_dma_enabled(struct rz_ssi_priv * ssi)191 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
192 {
193 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
194 }
195
rz_ssi_set_substream(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)196 static void rz_ssi_set_substream(struct rz_ssi_stream *strm,
197 struct snd_pcm_substream *substream)
198 {
199 struct rz_ssi_priv *ssi = strm->priv;
200 unsigned long flags;
201
202 spin_lock_irqsave(&ssi->lock, flags);
203 strm->substream = substream;
204 spin_unlock_irqrestore(&ssi->lock, flags);
205 }
206
rz_ssi_stream_is_valid(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)207 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
208 struct rz_ssi_stream *strm)
209 {
210 unsigned long flags;
211 bool ret;
212
213 spin_lock_irqsave(&ssi->lock, flags);
214 ret = strm->substream && strm->substream->runtime;
215 spin_unlock_irqrestore(&ssi->lock, flags);
216
217 return ret;
218 }
219
rz_ssi_is_stream_running(struct rz_ssi_stream * strm)220 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm)
221 {
222 return strm->substream && strm->running;
223 }
224
rz_ssi_stream_init(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)225 static void rz_ssi_stream_init(struct rz_ssi_stream *strm,
226 struct snd_pcm_substream *substream)
227 {
228 struct snd_pcm_runtime *runtime = substream->runtime;
229
230 rz_ssi_set_substream(strm, substream);
231 strm->sample_width = samples_to_bytes(runtime, 1);
232 strm->dma_buffer_pos = 0;
233 strm->period_counter = 0;
234 strm->buffer_pos = 0;
235
236 strm->oerr_num = 0;
237 strm->uerr_num = 0;
238 strm->running = 0;
239
240 /* fifo init */
241 strm->fifo_sample_size = SSI_FIFO_DEPTH;
242 }
243
rz_ssi_stream_quit(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)244 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
245 struct rz_ssi_stream *strm)
246 {
247 struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream);
248
249 rz_ssi_set_substream(strm, NULL);
250
251 if (strm->oerr_num > 0)
252 dev_info(dai->dev, "overrun = %d\n", strm->oerr_num);
253
254 if (strm->uerr_num > 0)
255 dev_info(dai->dev, "underrun = %d\n", strm->uerr_num);
256 }
257
rz_ssi_clk_setup(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels)258 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
259 unsigned int channels)
260 {
261 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 };
262 unsigned int channel_bits = 32; /* System Word Length */
263 unsigned long bclk_rate = rate * channels * channel_bits;
264 unsigned int div;
265 unsigned int i;
266 u32 ssicr = 0;
267 u32 clk_ckdv;
268
269 /* Clear AUCKE so we can set MST */
270 rz_ssi_reg_writel(ssi, SSIFCR, 0);
271
272 /* Continue to output LRCK pin even when idle */
273 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
274 if (ssi->audio_clk_1 && ssi->audio_clk_2) {
275 if (ssi->audio_clk_1 % bclk_rate)
276 ssi->audio_mck = ssi->audio_clk_2;
277 else
278 ssi->audio_mck = ssi->audio_clk_1;
279 }
280
281 /* Clock setting */
282 ssicr |= SSICR_MST;
283 if (ssi->audio_mck == ssi->audio_clk_1)
284 ssicr |= SSICR_CKS;
285 if (ssi->bckp_rise)
286 ssicr |= SSICR_BCKP;
287 if (ssi->lrckp_fsync_fall)
288 ssicr |= SSICR_LRCKP;
289
290 /* Determine the clock divider */
291 clk_ckdv = 0;
292 div = ssi->audio_mck / bclk_rate;
293 /* try to find an match */
294 for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
295 if (ckdv[i] == div) {
296 clk_ckdv = i;
297 break;
298 }
299 }
300
301 if (i == ARRAY_SIZE(ckdv)) {
302 dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
303 return -EINVAL;
304 }
305
306 /*
307 * DWL: Data Word Length = 16 bits
308 * SWL: System Word Length = 32 bits
309 */
310 ssicr |= SSICR_CKDV(clk_ckdv);
311 ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
312 rz_ssi_reg_writel(ssi, SSICR, ssicr);
313 rz_ssi_reg_writel(ssi, SSIFCR,
314 (SSIFCR_AUCKE | SSIFCR_TFRST | SSIFCR_RFRST));
315
316 return 0;
317 }
318
rz_ssi_set_idle(struct rz_ssi_priv * ssi)319 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi)
320 {
321 int timeout;
322
323 /* Disable irqs */
324 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
325 SSICR_RUIEN | SSICR_ROIEN, 0);
326 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
327
328 /* Clear all error flags */
329 rz_ssi_reg_mask_setl(ssi, SSISR,
330 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
331 SSISR_RUIRQ), 0);
332
333 /* Wait for idle */
334 timeout = 100;
335 while (--timeout) {
336 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ)
337 break;
338 udelay(1);
339 }
340
341 if (!timeout)
342 dev_info(ssi->dev, "timeout waiting for SSI idle\n");
343
344 /* Hold FIFOs in reset */
345 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0,
346 SSIFCR_TFRST | SSIFCR_RFRST);
347 }
348
rz_ssi_start(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)349 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
350 {
351 bool is_play = rz_ssi_stream_is_play(ssi, strm->substream);
352 bool is_full_duplex;
353 u32 ssicr, ssifcr;
354
355 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) ||
356 rz_ssi_is_stream_running(&ssi->capture);
357 ssicr = rz_ssi_reg_readl(ssi, SSICR);
358 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR);
359 if (!is_full_duplex) {
360 ssifcr &= ~0xF;
361 } else {
362 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
363 rz_ssi_set_idle(ssi);
364 ssifcr &= ~SSIFCR_FIFO_RST;
365 }
366
367 /* FIFO interrupt thresholds */
368 if (rz_ssi_is_dma_enabled(ssi))
369 rz_ssi_reg_writel(ssi, SSISCR, 0);
370 else
371 rz_ssi_reg_writel(ssi, SSISCR,
372 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
373 SSISCR_RDFS(0));
374
375 /* enable IRQ */
376 if (is_play) {
377 ssicr |= SSICR_TUIEN | SSICR_TOIEN;
378 ssifcr |= SSIFCR_TIE;
379 if (!is_full_duplex)
380 ssifcr |= SSIFCR_RFRST;
381 } else {
382 ssicr |= SSICR_RUIEN | SSICR_ROIEN;
383 ssifcr |= SSIFCR_RIE;
384 if (!is_full_duplex)
385 ssifcr |= SSIFCR_TFRST;
386 }
387
388 rz_ssi_reg_writel(ssi, SSICR, ssicr);
389 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
390
391 /* Clear all error flags */
392 rz_ssi_reg_mask_setl(ssi, SSISR,
393 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
394 SSISR_RUIRQ), 0);
395
396 strm->running = 1;
397 if (is_full_duplex)
398 ssicr |= SSICR_TEN | SSICR_REN;
399 else
400 ssicr |= is_play ? SSICR_TEN : SSICR_REN;
401
402 rz_ssi_reg_writel(ssi, SSICR, ssicr);
403
404 return 0;
405 }
406
rz_ssi_stop(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)407 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
408 {
409 strm->running = 0;
410
411 if (rz_ssi_is_stream_running(&ssi->playback) ||
412 rz_ssi_is_stream_running(&ssi->capture))
413 return 0;
414
415 /* Disable TX/RX */
416 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
417
418 /* Cancel all remaining DMA transactions */
419 if (rz_ssi_is_dma_enabled(ssi)) {
420 if (ssi->playback.dma_ch)
421 dmaengine_terminate_async(ssi->playback.dma_ch);
422 if (ssi->capture.dma_ch)
423 dmaengine_terminate_async(ssi->capture.dma_ch);
424 }
425
426 rz_ssi_set_idle(ssi);
427
428 return 0;
429 }
430
rz_ssi_pointer_update(struct rz_ssi_stream * strm,int frames)431 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
432 {
433 struct snd_pcm_substream *substream = strm->substream;
434 struct snd_pcm_runtime *runtime;
435 int current_period;
436
437 if (!strm->running || !substream || !substream->runtime)
438 return;
439
440 runtime = substream->runtime;
441 strm->buffer_pos += frames;
442 WARN_ON(strm->buffer_pos > runtime->buffer_size);
443
444 /* ring buffer */
445 if (strm->buffer_pos == runtime->buffer_size)
446 strm->buffer_pos = 0;
447
448 current_period = strm->buffer_pos / runtime->period_size;
449 if (strm->period_counter != current_period) {
450 snd_pcm_period_elapsed(strm->substream);
451 strm->period_counter = current_period;
452 }
453 }
454
rz_ssi_pio_recv(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)455 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
456 {
457 struct snd_pcm_substream *substream = strm->substream;
458 struct snd_pcm_runtime *runtime;
459 u16 *buf;
460 int fifo_samples;
461 int frames_left;
462 int samples;
463 int i;
464
465 if (!rz_ssi_stream_is_valid(ssi, strm))
466 return -EINVAL;
467
468 runtime = substream->runtime;
469
470 do {
471 /* frames left in this period */
472 frames_left = runtime->period_size -
473 (strm->buffer_pos % runtime->period_size);
474 if (!frames_left)
475 frames_left = runtime->period_size;
476
477 /* Samples in RX FIFO */
478 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
479 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
480
481 /* Only read full frames at a time */
482 samples = 0;
483 while (frames_left && (fifo_samples >= runtime->channels)) {
484 samples += runtime->channels;
485 fifo_samples -= runtime->channels;
486 frames_left--;
487 }
488
489 /* not enough samples yet */
490 if (!samples)
491 break;
492
493 /* calculate new buffer index */
494 buf = (u16 *)runtime->dma_area;
495 buf += strm->buffer_pos * runtime->channels;
496
497 /* Note, only supports 16-bit samples */
498 for (i = 0; i < samples; i++)
499 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
500
501 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
502 rz_ssi_pointer_update(strm, samples / runtime->channels);
503 } while (!frames_left && fifo_samples >= runtime->channels);
504
505 return 0;
506 }
507
rz_ssi_pio_send(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)508 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
509 {
510 struct snd_pcm_substream *substream = strm->substream;
511 struct snd_pcm_runtime *runtime = substream->runtime;
512 int sample_space;
513 int samples = 0;
514 int frames_left;
515 int i;
516 u32 ssifsr;
517 u16 *buf;
518
519 if (!rz_ssi_stream_is_valid(ssi, strm))
520 return -EINVAL;
521
522 /* frames left in this period */
523 frames_left = runtime->period_size - (strm->buffer_pos %
524 runtime->period_size);
525 if (frames_left == 0)
526 frames_left = runtime->period_size;
527
528 sample_space = strm->fifo_sample_size;
529 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
530 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
531 if (sample_space < 0)
532 return -EINVAL;
533
534 /* Only add full frames at a time */
535 while (frames_left && (sample_space >= runtime->channels)) {
536 samples += runtime->channels;
537 sample_space -= runtime->channels;
538 frames_left--;
539 }
540
541 /* no space to send anything right now */
542 if (samples == 0)
543 return 0;
544
545 /* calculate new buffer index */
546 buf = (u16 *)(runtime->dma_area);
547 buf += strm->buffer_pos * runtime->channels;
548
549 /* Note, only supports 16-bit samples */
550 for (i = 0; i < samples; i++)
551 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
552
553 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
554 rz_ssi_pointer_update(strm, samples / runtime->channels);
555
556 return 0;
557 }
558
rz_ssi_interrupt(int irq,void * data)559 static irqreturn_t rz_ssi_interrupt(int irq, void *data)
560 {
561 struct rz_ssi_stream *strm_playback = NULL;
562 struct rz_ssi_stream *strm_capture = NULL;
563 struct rz_ssi_priv *ssi = data;
564 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
565
566 if (ssi->playback.substream)
567 strm_playback = &ssi->playback;
568 if (ssi->capture.substream)
569 strm_capture = &ssi->capture;
570
571 if (!strm_playback && !strm_capture)
572 return IRQ_HANDLED; /* Left over TX/RX interrupt */
573
574 if (irq == ssi->irq_int) { /* error or idle */
575 bool is_stopped = false;
576 int i, count;
577
578 if (rz_ssi_is_dma_enabled(ssi))
579 count = 4;
580 else
581 count = 1;
582
583 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ))
584 is_stopped = true;
585
586 if (ssi->capture.substream && is_stopped) {
587 if (ssisr & SSISR_RUIRQ)
588 strm_capture->uerr_num++;
589 if (ssisr & SSISR_ROIRQ)
590 strm_capture->oerr_num++;
591
592 rz_ssi_stop(ssi, strm_capture);
593 }
594
595 if (ssi->playback.substream && is_stopped) {
596 if (ssisr & SSISR_TUIRQ)
597 strm_playback->uerr_num++;
598 if (ssisr & SSISR_TOIRQ)
599 strm_playback->oerr_num++;
600
601 rz_ssi_stop(ssi, strm_playback);
602 }
603
604 /* Clear all flags */
605 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ |
606 SSISR_ROIRQ | SSISR_RUIRQ, 0);
607
608 /* Add/remove more data */
609 if (ssi->capture.substream && is_stopped) {
610 for (i = 0; i < count; i++)
611 strm_capture->transfer(ssi, strm_capture);
612 }
613
614 if (ssi->playback.substream && is_stopped) {
615 for (i = 0; i < count; i++)
616 strm_playback->transfer(ssi, strm_playback);
617 }
618
619 /* Resume */
620 if (ssi->playback.substream && is_stopped)
621 rz_ssi_start(ssi, &ssi->playback);
622 if (ssi->capture.substream && is_stopped)
623 rz_ssi_start(ssi, &ssi->capture);
624 }
625
626 if (!rz_ssi_is_stream_running(&ssi->playback) &&
627 !rz_ssi_is_stream_running(&ssi->capture))
628 return IRQ_HANDLED;
629
630 /* tx data empty */
631 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback))
632 strm_playback->transfer(ssi, &ssi->playback);
633
634 /* rx data full */
635 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) {
636 strm_capture->transfer(ssi, &ssi->capture);
637 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
638 }
639
640 if (irq == ssi->irq_rt) {
641 if (ssi->playback.substream) {
642 strm_playback->transfer(ssi, &ssi->playback);
643 } else {
644 strm_capture->transfer(ssi, &ssi->capture);
645 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
646 }
647 }
648
649 return IRQ_HANDLED;
650 }
651
rz_ssi_dma_slave_config(struct rz_ssi_priv * ssi,struct dma_chan * dma_ch,bool is_play)652 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
653 struct dma_chan *dma_ch, bool is_play)
654 {
655 struct dma_slave_config cfg;
656
657 memset(&cfg, 0, sizeof(cfg));
658
659 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
660 cfg.dst_addr = ssi->phys + SSIFTDR;
661 cfg.src_addr = ssi->phys + SSIFRDR;
662 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
663 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
664
665 return dmaengine_slave_config(dma_ch, &cfg);
666 }
667
rz_ssi_dma_transfer(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)668 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
669 struct rz_ssi_stream *strm)
670 {
671 struct snd_pcm_substream *substream = strm->substream;
672 struct dma_async_tx_descriptor *desc;
673 struct snd_pcm_runtime *runtime;
674 enum dma_transfer_direction dir;
675 u32 dma_paddr, dma_size;
676 int amount;
677
678 if (!rz_ssi_stream_is_valid(ssi, strm))
679 return -EINVAL;
680
681 runtime = substream->runtime;
682 if (runtime->state == SNDRV_PCM_STATE_DRAINING)
683 /*
684 * Stream is ending, so do not queue up any more DMA
685 * transfers otherwise we play partial sound clips
686 * because we can't shut off the DMA quick enough.
687 */
688 return 0;
689
690 dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
691
692 /* Always transfer 1 period */
693 amount = runtime->period_size;
694
695 /* DMA physical address and size */
696 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
697 strm->dma_buffer_pos);
698 dma_size = frames_to_bytes(runtime, amount);
699 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
700 dir,
701 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
702 if (!desc) {
703 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
704 return -ENOMEM;
705 }
706
707 desc->callback = rz_ssi_dma_complete;
708 desc->callback_param = strm;
709
710 if (dmaengine_submit(desc) < 0) {
711 dev_err(ssi->dev, "dmaengine_submit() fail\n");
712 return -EIO;
713 }
714
715 /* Update DMA pointer */
716 strm->dma_buffer_pos += amount;
717 if (strm->dma_buffer_pos >= runtime->buffer_size)
718 strm->dma_buffer_pos = 0;
719
720 /* Start DMA */
721 dma_async_issue_pending(strm->dma_ch);
722
723 return 0;
724 }
725
rz_ssi_dma_complete(void * data)726 static void rz_ssi_dma_complete(void *data)
727 {
728 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
729
730 if (!strm->running || !strm->substream || !strm->substream->runtime)
731 return;
732
733 /* Note that next DMA transaction has probably already started */
734 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
735
736 /* Queue up another DMA transaction */
737 rz_ssi_dma_transfer(strm->priv, strm);
738 }
739
rz_ssi_release_dma_channels(struct rz_ssi_priv * ssi)740 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
741 {
742 if (ssi->playback.dma_ch) {
743 dma_release_channel(ssi->playback.dma_ch);
744 ssi->playback.dma_ch = NULL;
745 if (ssi->dma_rt)
746 ssi->dma_rt = false;
747 }
748
749 if (ssi->capture.dma_ch) {
750 dma_release_channel(ssi->capture.dma_ch);
751 ssi->capture.dma_ch = NULL;
752 }
753 }
754
rz_ssi_dma_request(struct rz_ssi_priv * ssi,struct device * dev)755 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
756 {
757 ssi->playback.dma_ch = dma_request_chan(dev, "tx");
758 if (IS_ERR(ssi->playback.dma_ch))
759 ssi->playback.dma_ch = NULL;
760
761 ssi->capture.dma_ch = dma_request_chan(dev, "rx");
762 if (IS_ERR(ssi->capture.dma_ch))
763 ssi->capture.dma_ch = NULL;
764
765 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
766 ssi->playback.dma_ch = dma_request_chan(dev, "rt");
767 if (IS_ERR(ssi->playback.dma_ch)) {
768 ssi->playback.dma_ch = NULL;
769 goto no_dma;
770 }
771
772 ssi->dma_rt = true;
773 }
774
775 if (!rz_ssi_is_dma_enabled(ssi))
776 goto no_dma;
777
778 if (ssi->playback.dma_ch &&
779 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
780 goto no_dma;
781
782 if (ssi->capture.dma_ch &&
783 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0))
784 goto no_dma;
785
786 return 0;
787
788 no_dma:
789 rz_ssi_release_dma_channels(ssi);
790
791 return -ENODEV;
792 }
793
rz_ssi_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)794 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
795 struct snd_soc_dai *dai)
796 {
797 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
798 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
799 int ret = 0, i, num_transfer = 1;
800
801 switch (cmd) {
802 case SNDRV_PCM_TRIGGER_START:
803 /* Soft Reset */
804 if (!rz_ssi_is_stream_running(&ssi->playback) &&
805 !rz_ssi_is_stream_running(&ssi->capture)) {
806 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
807 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
808 udelay(5);
809 }
810
811 rz_ssi_stream_init(strm, substream);
812
813 if (ssi->dma_rt) {
814 bool is_playback;
815
816 is_playback = rz_ssi_stream_is_play(ssi, substream);
817 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
818 is_playback);
819 /* Fallback to pio */
820 if (ret < 0) {
821 ssi->playback.transfer = rz_ssi_pio_send;
822 ssi->capture.transfer = rz_ssi_pio_recv;
823 rz_ssi_release_dma_channels(ssi);
824 }
825 }
826
827 /* For DMA, queue up multiple DMA descriptors */
828 if (rz_ssi_is_dma_enabled(ssi))
829 num_transfer = 4;
830
831 for (i = 0; i < num_transfer; i++) {
832 ret = strm->transfer(ssi, strm);
833 if (ret)
834 goto done;
835 }
836
837 ret = rz_ssi_start(ssi, strm);
838 break;
839 case SNDRV_PCM_TRIGGER_STOP:
840 rz_ssi_stop(ssi, strm);
841 rz_ssi_stream_quit(ssi, strm);
842 break;
843 }
844
845 done:
846 return ret;
847 }
848
rz_ssi_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)849 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
850 {
851 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
852
853 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
854 case SND_SOC_DAIFMT_BP_FP:
855 break;
856 default:
857 dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
858 return -EINVAL;
859 }
860
861 /*
862 * set clock polarity
863 *
864 * "normal" BCLK = Signal is available at rising edge of BCLK
865 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
866 */
867 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
868 case SND_SOC_DAIFMT_NB_NF:
869 ssi->bckp_rise = false;
870 ssi->lrckp_fsync_fall = false;
871 break;
872 case SND_SOC_DAIFMT_NB_IF:
873 ssi->bckp_rise = false;
874 ssi->lrckp_fsync_fall = true;
875 break;
876 case SND_SOC_DAIFMT_IB_NF:
877 ssi->bckp_rise = true;
878 ssi->lrckp_fsync_fall = false;
879 break;
880 case SND_SOC_DAIFMT_IB_IF:
881 ssi->bckp_rise = true;
882 ssi->lrckp_fsync_fall = true;
883 break;
884 default:
885 return -EINVAL;
886 }
887
888 /* only i2s support */
889 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
890 case SND_SOC_DAIFMT_I2S:
891 break;
892 default:
893 dev_err(ssi->dev, "Only I2S mode is supported.\n");
894 return -EINVAL;
895 }
896
897 return 0;
898 }
899
rz_ssi_is_valid_hw_params(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels,unsigned int sample_width,unsigned int sample_bits)900 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate,
901 unsigned int channels,
902 unsigned int sample_width,
903 unsigned int sample_bits)
904 {
905 if (ssi->hw_params_cache.rate != rate ||
906 ssi->hw_params_cache.channels != channels ||
907 ssi->hw_params_cache.sample_width != sample_width ||
908 ssi->hw_params_cache.sample_bits != sample_bits)
909 return false;
910
911 return true;
912 }
913
rz_ssi_cache_hw_params(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels,unsigned int sample_width,unsigned int sample_bits)914 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate,
915 unsigned int channels,
916 unsigned int sample_width,
917 unsigned int sample_bits)
918 {
919 ssi->hw_params_cache.rate = rate;
920 ssi->hw_params_cache.channels = channels;
921 ssi->hw_params_cache.sample_width = sample_width;
922 ssi->hw_params_cache.sample_bits = sample_bits;
923 }
924
rz_ssi_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)925 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
926 struct snd_pcm_hw_params *params,
927 struct snd_soc_dai *dai)
928 {
929 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
930 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
931 unsigned int sample_bits = hw_param_interval(params,
932 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
933 unsigned int channels = params_channels(params);
934 unsigned int rate = params_rate(params);
935
936 if (sample_bits != 16) {
937 dev_err(ssi->dev, "Unsupported sample width: %d\n",
938 sample_bits);
939 return -EINVAL;
940 }
941
942 if (channels != 2) {
943 dev_err(ssi->dev, "Number of channels not matched: %d\n",
944 channels);
945 return -EINVAL;
946 }
947
948 if (rz_ssi_is_stream_running(&ssi->playback) ||
949 rz_ssi_is_stream_running(&ssi->capture)) {
950 if (rz_ssi_is_valid_hw_params(ssi, rate, channels,
951 strm->sample_width, sample_bits))
952 return 0;
953
954 dev_err(ssi->dev, "Full duplex needs same HW params\n");
955 return -EINVAL;
956 }
957
958 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width,
959 sample_bits);
960
961 return rz_ssi_clk_setup(ssi, rate, channels);
962 }
963
964 static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
965 .trigger = rz_ssi_dai_trigger,
966 .set_fmt = rz_ssi_dai_set_fmt,
967 .hw_params = rz_ssi_dai_hw_params,
968 };
969
970 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
971 .info = SNDRV_PCM_INFO_INTERLEAVED |
972 SNDRV_PCM_INFO_MMAP |
973 SNDRV_PCM_INFO_MMAP_VALID,
974 .buffer_bytes_max = PREALLOC_BUFFER,
975 .period_bytes_min = 32,
976 .period_bytes_max = 8192,
977 .channels_min = SSI_CHAN_MIN,
978 .channels_max = SSI_CHAN_MAX,
979 .periods_min = 1,
980 .periods_max = 32,
981 .fifo_size = 32 * 2,
982 };
983
rz_ssi_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)984 static int rz_ssi_pcm_open(struct snd_soc_component *component,
985 struct snd_pcm_substream *substream)
986 {
987 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
988
989 return snd_pcm_hw_constraint_integer(substream->runtime,
990 SNDRV_PCM_HW_PARAM_PERIODS);
991 }
992
rz_ssi_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)993 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
994 struct snd_pcm_substream *substream)
995 {
996 struct snd_soc_dai *dai = rz_ssi_get_dai(substream);
997 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
998 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
999
1000 return strm->buffer_pos;
1001 }
1002
rz_ssi_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)1003 static int rz_ssi_pcm_new(struct snd_soc_component *component,
1004 struct snd_soc_pcm_runtime *rtd)
1005 {
1006 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
1007 rtd->card->snd_card->dev,
1008 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1009 return 0;
1010 }
1011
1012 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
1013 {
1014 .name = "rz-ssi-dai",
1015 .playback = {
1016 .rates = SSI_RATES,
1017 .formats = SSI_FMTS,
1018 .channels_min = SSI_CHAN_MIN,
1019 .channels_max = SSI_CHAN_MAX,
1020 },
1021 .capture = {
1022 .rates = SSI_RATES,
1023 .formats = SSI_FMTS,
1024 .channels_min = SSI_CHAN_MIN,
1025 .channels_max = SSI_CHAN_MAX,
1026 },
1027 .ops = &rz_ssi_dai_ops,
1028 },
1029 };
1030
1031 static const struct snd_soc_component_driver rz_ssi_soc_component = {
1032 .name = "rz-ssi",
1033 .open = rz_ssi_pcm_open,
1034 .pointer = rz_ssi_pcm_pointer,
1035 .pcm_construct = rz_ssi_pcm_new,
1036 .legacy_dai_naming = 1,
1037 };
1038
rz_ssi_probe(struct platform_device * pdev)1039 static int rz_ssi_probe(struct platform_device *pdev)
1040 {
1041 struct rz_ssi_priv *ssi;
1042 struct clk *audio_clk;
1043 struct resource *res;
1044 int ret;
1045
1046 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
1047 if (!ssi)
1048 return -ENOMEM;
1049
1050 ssi->pdev = pdev;
1051 ssi->dev = &pdev->dev;
1052 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1053 if (IS_ERR(ssi->base))
1054 return PTR_ERR(ssi->base);
1055
1056 ssi->phys = res->start;
1057 ssi->clk = devm_clk_get(&pdev->dev, "ssi");
1058 if (IS_ERR(ssi->clk))
1059 return PTR_ERR(ssi->clk);
1060
1061 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr");
1062 if (IS_ERR(ssi->sfr_clk))
1063 return PTR_ERR(ssi->sfr_clk);
1064
1065 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1");
1066 if (IS_ERR(audio_clk))
1067 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
1068 "no audio clk1");
1069
1070 ssi->audio_clk_1 = clk_get_rate(audio_clk);
1071 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2");
1072 if (IS_ERR(audio_clk))
1073 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
1074 "no audio clk2");
1075
1076 ssi->audio_clk_2 = clk_get_rate(audio_clk);
1077 if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
1078 return dev_err_probe(&pdev->dev, -EINVAL,
1079 "no audio clk1 or audio clk2");
1080
1081 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
1082
1083 /* Detect DMA support */
1084 ret = rz_ssi_dma_request(ssi, &pdev->dev);
1085 if (ret < 0) {
1086 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1087 ssi->playback.transfer = rz_ssi_pio_send;
1088 ssi->capture.transfer = rz_ssi_pio_recv;
1089 } else {
1090 dev_info(&pdev->dev, "DMA enabled");
1091 ssi->playback.transfer = rz_ssi_dma_transfer;
1092 ssi->capture.transfer = rz_ssi_dma_transfer;
1093 }
1094
1095 ssi->playback.priv = ssi;
1096 ssi->capture.priv = ssi;
1097
1098 spin_lock_init(&ssi->lock);
1099 dev_set_drvdata(&pdev->dev, ssi);
1100
1101 /* Error Interrupt */
1102 ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
1103 if (ssi->irq_int < 0) {
1104 rz_ssi_release_dma_channels(ssi);
1105 return ssi->irq_int;
1106 }
1107
1108 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
1109 0, dev_name(&pdev->dev), ssi);
1110 if (ret < 0) {
1111 rz_ssi_release_dma_channels(ssi);
1112 return dev_err_probe(&pdev->dev, ret,
1113 "irq request error (int_req)\n");
1114 }
1115
1116 if (!rz_ssi_is_dma_enabled(ssi)) {
1117 /* Tx and Rx interrupts (pio only) */
1118 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
1119 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
1120 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
1121 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
1122 if (ssi->irq_rt < 0)
1123 return ssi->irq_rt;
1124
1125 ret = devm_request_irq(&pdev->dev, ssi->irq_rt,
1126 &rz_ssi_interrupt, 0,
1127 dev_name(&pdev->dev), ssi);
1128 if (ret < 0)
1129 return dev_err_probe(&pdev->dev, ret,
1130 "irq request error (dma_rt)\n");
1131 } else {
1132 if (ssi->irq_tx < 0)
1133 return ssi->irq_tx;
1134
1135 if (ssi->irq_rx < 0)
1136 return ssi->irq_rx;
1137
1138 ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
1139 &rz_ssi_interrupt, 0,
1140 dev_name(&pdev->dev), ssi);
1141 if (ret < 0)
1142 return dev_err_probe(&pdev->dev, ret,
1143 "irq request error (dma_tx)\n");
1144
1145 ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
1146 &rz_ssi_interrupt, 0,
1147 dev_name(&pdev->dev), ssi);
1148 if (ret < 0)
1149 return dev_err_probe(&pdev->dev, ret,
1150 "irq request error (dma_rx)\n");
1151 }
1152 }
1153
1154 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1155 if (IS_ERR(ssi->rstc)) {
1156 ret = PTR_ERR(ssi->rstc);
1157 goto err_reset;
1158 }
1159
1160 reset_control_deassert(ssi->rstc);
1161 pm_runtime_enable(&pdev->dev);
1162 ret = pm_runtime_resume_and_get(&pdev->dev);
1163 if (ret < 0) {
1164 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n");
1165 goto err_pm;
1166 }
1167
1168 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component,
1169 rz_ssi_soc_dai,
1170 ARRAY_SIZE(rz_ssi_soc_dai));
1171 if (ret < 0) {
1172 dev_err(&pdev->dev, "failed to register snd component\n");
1173 goto err_snd_soc;
1174 }
1175
1176 return 0;
1177
1178 err_snd_soc:
1179 pm_runtime_put(ssi->dev);
1180 err_pm:
1181 pm_runtime_disable(ssi->dev);
1182 reset_control_assert(ssi->rstc);
1183 err_reset:
1184 rz_ssi_release_dma_channels(ssi);
1185
1186 return ret;
1187 }
1188
rz_ssi_remove(struct platform_device * pdev)1189 static void rz_ssi_remove(struct platform_device *pdev)
1190 {
1191 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
1192
1193 rz_ssi_release_dma_channels(ssi);
1194
1195 pm_runtime_put(ssi->dev);
1196 pm_runtime_disable(ssi->dev);
1197 reset_control_assert(ssi->rstc);
1198 }
1199
1200 static const struct of_device_id rz_ssi_of_match[] = {
1201 { .compatible = "renesas,rz-ssi", },
1202 {/* Sentinel */},
1203 };
1204 MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
1205
1206 static struct platform_driver rz_ssi_driver = {
1207 .driver = {
1208 .name = "rz-ssi-pcm-audio",
1209 .of_match_table = rz_ssi_of_match,
1210 },
1211 .probe = rz_ssi_probe,
1212 .remove = rz_ssi_remove,
1213 };
1214
1215 module_platform_driver(rz_ssi_driver);
1216
1217 MODULE_LICENSE("GPL v2");
1218 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
1219 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1220