1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2014 Emilio López <emilio@elopez.com.ar>
4 * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
5 * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
6 * Copyright 2015 Adam Sampson <ats@offog.org>
7 * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
8 *
9 * Based on the Allwinner SDK driver, released under the GPL.
10 */
11
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <linux/gpio/consumer.h>
22
23 #include <sound/core.h>
24 #include <sound/jack.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/tlv.h>
29 #include <sound/initval.h>
30 #include <sound/dmaengine_pcm.h>
31
32 /* Codec DAC digital controls and FIFO registers */
33 #define SUN4I_CODEC_DAC_DPC (0x00)
34 #define SUN4I_CODEC_DAC_DPC_EN_DA (31)
35 #define SUN4I_CODEC_DAC_DPC_DVOL (12)
36 #define SUN4I_CODEC_DAC_FIFOC (0x04)
37 #define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29)
38 #define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28)
39 #define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26)
40 #define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24)
41 #define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21)
42 #define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8)
43 #define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6)
44 #define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5)
45 #define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4)
46 #define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0)
47 #define SUN4I_CODEC_DAC_FIFOS (0x08)
48 #define SUN4I_CODEC_DAC_TXDATA (0x0c)
49
50 /* Codec DAC side analog signal controls */
51 #define SUN4I_CODEC_DAC_ACTL (0x10)
52 #define SUN4I_CODEC_DAC_ACTL_DACAENR (31)
53 #define SUN4I_CODEC_DAC_ACTL_DACAENL (30)
54 #define SUN4I_CODEC_DAC_ACTL_MIXEN (29)
55 #define SUN4I_CODEC_DAC_ACTL_LNG (26)
56 #define SUN4I_CODEC_DAC_ACTL_FMG (23)
57 #define SUN4I_CODEC_DAC_ACTL_MICG (20)
58 #define SUN4I_CODEC_DAC_ACTL_LLNS (19)
59 #define SUN4I_CODEC_DAC_ACTL_RLNS (18)
60 #define SUN4I_CODEC_DAC_ACTL_LFMS (17)
61 #define SUN4I_CODEC_DAC_ACTL_RFMS (16)
62 #define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15)
63 #define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14)
64 #define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13)
65 #define SUN4I_CODEC_DAC_ACTL_MIC1LS (12)
66 #define SUN4I_CODEC_DAC_ACTL_MIC1RS (11)
67 #define SUN4I_CODEC_DAC_ACTL_MIC2LS (10)
68 #define SUN4I_CODEC_DAC_ACTL_MIC2RS (9)
69 #define SUN4I_CODEC_DAC_ACTL_DACPAS (8)
70 #define SUN4I_CODEC_DAC_ACTL_MIXPAS (7)
71 #define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6)
72 #define SUN4I_CODEC_DAC_ACTL_PA_VOL (0)
73 #define SUN4I_CODEC_DAC_TUNE (0x14)
74 #define SUN4I_CODEC_DAC_DEBUG (0x18)
75
76 /* Codec ADC digital controls and FIFO registers */
77 #define SUN4I_CODEC_ADC_FIFOC (0x1c)
78 #define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29)
79 #define SUN4I_CODEC_ADC_FIFOC_EN_AD (28)
80 #define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24)
81 #define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8)
82 #define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7)
83 #define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6)
84 #define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4)
85 #define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0)
86 #define SUN4I_CODEC_ADC_FIFOS (0x20)
87 #define SUN4I_CODEC_ADC_RXDATA (0x24)
88
89 /* Codec ADC side analog signal controls */
90 #define SUN4I_CODEC_ADC_ACTL (0x28)
91 #define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31)
92 #define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30)
93 #define SUN4I_CODEC_ADC_ACTL_PREG1EN (29)
94 #define SUN4I_CODEC_ADC_ACTL_PREG2EN (28)
95 #define SUN4I_CODEC_ADC_ACTL_VMICEN (27)
96 #define SUN4I_CODEC_ADC_ACTL_PREG1 (25)
97 #define SUN4I_CODEC_ADC_ACTL_PREG2 (23)
98 #define SUN4I_CODEC_ADC_ACTL_VADCG (20)
99 #define SUN4I_CODEC_ADC_ACTL_ADCIS (17)
100 #define SUN4I_CODEC_ADC_ACTL_LNPREG (13)
101 #define SUN4I_CODEC_ADC_ACTL_PA_EN (4)
102 #define SUN4I_CODEC_ADC_ACTL_DDE (3)
103 #define SUN4I_CODEC_ADC_DEBUG (0x2c)
104
105 /* FIFO counters */
106 #define SUN4I_CODEC_DAC_TXCNT (0x30)
107 #define SUN4I_CODEC_ADC_RXCNT (0x34)
108
109 /* Calibration register (sun7i only) */
110 #define SUN7I_CODEC_AC_DAC_CAL (0x38)
111
112 /* Microphone controls (sun7i only) */
113 #define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c)
114
115 #define SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG1 (29)
116 #define SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2 (26)
117
118 /*
119 * sun6i specific registers
120 *
121 * sun6i shares the same digital control and FIFO registers as sun4i,
122 * but only the DAC digital controls are at the same offset. The others
123 * have been moved around to accommodate extra analog controls.
124 */
125
126 /* Codec DAC digital controls and FIFO registers */
127 #define SUN6I_CODEC_ADC_FIFOC (0x10)
128 #define SUN6I_CODEC_ADC_FIFOC_EN_AD (28)
129 #define SUN6I_CODEC_ADC_FIFOS (0x14)
130 #define SUN6I_CODEC_ADC_RXDATA (0x18)
131
132 /* Output mixer and gain controls */
133 #define SUN6I_CODEC_OM_DACA_CTRL (0x20)
134 #define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31)
135 #define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30)
136 #define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29)
137 #define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28)
138 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23)
139 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22)
140 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21)
141 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20)
142 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19)
143 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18)
144 #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17)
145 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16)
146 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15)
147 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14)
148 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13)
149 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12)
150 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11)
151 #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10)
152 #define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9)
153 #define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8)
154 #define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7)
155 #define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6)
156 #define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0)
157 #define SUN6I_CODEC_OM_PA_CTRL (0x24)
158 #define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31)
159 #define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29)
160 #define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28)
161 #define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15)
162 #define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12)
163 #define SUN6I_CODEC_OM_PA_CTRL_LINEING (9)
164 #define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6)
165 #define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3)
166 #define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0)
167
168 /* Microphone, line out and phone out controls */
169 #define SUN6I_CODEC_MIC_CTRL (0x28)
170 #define SUN6I_CODEC_MIC_CTRL_HBIASEN (31)
171 #define SUN6I_CODEC_MIC_CTRL_MBIASEN (30)
172 #define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28)
173 #define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25)
174 #define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24)
175 #define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21)
176 #define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20)
177 #define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19)
178 #define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18)
179 #define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17)
180 #define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16)
181 #define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11)
182 #define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8)
183
184 /* ADC mixer controls */
185 #define SUN6I_CODEC_ADC_ACTL (0x2c)
186 #define SUN6I_CODEC_ADC_ACTL_ADCREN (31)
187 #define SUN6I_CODEC_ADC_ACTL_ADCLEN (30)
188 #define SUN6I_CODEC_ADC_ACTL_ADCRG (27)
189 #define SUN6I_CODEC_ADC_ACTL_ADCLG (24)
190 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13)
191 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12)
192 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11)
193 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10)
194 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9)
195 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8)
196 #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7)
197 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6)
198 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5)
199 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4)
200 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3)
201 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2)
202 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1)
203 #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0)
204
205 /* Analog performance tuning controls */
206 #define SUN6I_CODEC_ADDA_TUNE (0x30)
207
208 /* Calibration controls */
209 #define SUN6I_CODEC_CALIBRATION (0x34)
210
211 /* FIFO counters */
212 #define SUN6I_CODEC_DAC_TXCNT (0x40)
213 #define SUN6I_CODEC_ADC_RXCNT (0x44)
214
215 /* headset jack detection and button support registers */
216 #define SUN6I_CODEC_HMIC_CTL (0x50)
217 #define SUN6I_CODEC_HMIC_DATA (0x54)
218
219 /* TODO sun6i DAP (Digital Audio Processing) bits */
220
221 /* FIFO counters moved on A23 */
222 #define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
223 #define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
224
225 /* TX FIFO moved on H3 */
226 #define SUN8I_H3_CODEC_DAC_TXDATA (0x20)
227 #define SUN8I_H3_CODEC_DAC_DBG (0x48)
228 #define SUN8I_H3_CODEC_ADC_DBG (0x4c)
229
230 /* TODO H3 DAP (Digital Audio Processing) bits */
231
232 struct sun4i_codec {
233 struct device *dev;
234 struct regmap *regmap;
235 struct clk *clk_apb;
236 struct clk *clk_module;
237 struct reset_control *rst;
238 struct gpio_desc *gpio_pa;
239 struct gpio_desc *gpio_hp;
240
241 /* ADC_FIFOC register is at different offset on different SoCs */
242 struct regmap_field *reg_adc_fifoc;
243
244 struct snd_dmaengine_dai_dma_data capture_dma_data;
245 struct snd_dmaengine_dai_dma_data playback_dma_data;
246 };
247
sun4i_codec_start_playback(struct sun4i_codec * scodec)248 static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
249 {
250 /* Flush TX FIFO */
251 regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
252 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
253
254 /* Enable DAC DRQ */
255 regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
256 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
257 }
258
sun4i_codec_stop_playback(struct sun4i_codec * scodec)259 static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
260 {
261 /* Disable DAC DRQ */
262 regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
263 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
264 }
265
sun4i_codec_start_capture(struct sun4i_codec * scodec)266 static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
267 {
268 /* Enable ADC DRQ */
269 regmap_field_set_bits(scodec->reg_adc_fifoc,
270 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
271 }
272
sun4i_codec_stop_capture(struct sun4i_codec * scodec)273 static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
274 {
275 /* Disable ADC DRQ */
276 regmap_field_clear_bits(scodec->reg_adc_fifoc,
277 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
278 }
279
sun4i_codec_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)280 static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
281 struct snd_soc_dai *dai)
282 {
283 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
284 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
285
286 switch (cmd) {
287 case SNDRV_PCM_TRIGGER_START:
288 case SNDRV_PCM_TRIGGER_RESUME:
289 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
290 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
291 sun4i_codec_start_playback(scodec);
292 else
293 sun4i_codec_start_capture(scodec);
294 break;
295
296 case SNDRV_PCM_TRIGGER_STOP:
297 case SNDRV_PCM_TRIGGER_SUSPEND:
298 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
299 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
300 sun4i_codec_stop_playback(scodec);
301 else
302 sun4i_codec_stop_capture(scodec);
303 break;
304
305 default:
306 return -EINVAL;
307 }
308
309 return 0;
310 }
311
sun4i_codec_prepare_capture(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)312 static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
313 struct snd_soc_dai *dai)
314 {
315 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
316 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
317
318
319 /* Flush RX FIFO */
320 regmap_field_set_bits(scodec->reg_adc_fifoc,
321 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH));
322
323
324 /* Set RX FIFO trigger level */
325 regmap_field_update_bits(scodec->reg_adc_fifoc,
326 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
327 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
328
329 /*
330 * FIXME: Undocumented in the datasheet, but
331 * Allwinner's code mentions that it is
332 * related to microphone gain
333 */
334 if (of_device_is_compatible(scodec->dev->of_node,
335 "allwinner,sun4i-a10-codec") ||
336 of_device_is_compatible(scodec->dev->of_node,
337 "allwinner,sun7i-a20-codec")) {
338 regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
339 0x3 << 25,
340 0x1 << 25);
341 }
342
343 if (of_device_is_compatible(scodec->dev->of_node,
344 "allwinner,sun7i-a20-codec"))
345 /* FIXME: Undocumented bits */
346 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE,
347 0x3 << 8,
348 0x1 << 8);
349
350 return 0;
351 }
352
sun4i_codec_prepare_playback(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)353 static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
354 struct snd_soc_dai *dai)
355 {
356 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
357 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
358 u32 val;
359
360 /* Flush the TX FIFO */
361 regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
362 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
363
364 /* Set TX FIFO Empty Trigger Level */
365 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
366 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
367 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
368
369 if (substream->runtime->rate > 32000)
370 /* Use 64 bits FIR filter */
371 val = 0;
372 else
373 /* Use 32 bits FIR filter */
374 val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
375
376 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
377 BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
378 val);
379
380 /* Send zeros when we have an underrun */
381 regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
382 BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
383
384 return 0;
385 };
386
sun4i_codec_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)387 static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
388 struct snd_soc_dai *dai)
389 {
390 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
391 return sun4i_codec_prepare_playback(substream, dai);
392
393 return sun4i_codec_prepare_capture(substream, dai);
394 }
395
sun4i_codec_get_mod_freq(struct snd_pcm_hw_params * params)396 static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
397 {
398 unsigned int rate = params_rate(params);
399
400 switch (rate) {
401 case 176400:
402 case 88200:
403 case 44100:
404 case 33075:
405 case 22050:
406 case 14700:
407 case 11025:
408 case 7350:
409 return 22579200;
410
411 case 192000:
412 case 96000:
413 case 48000:
414 case 32000:
415 case 24000:
416 case 16000:
417 case 12000:
418 case 8000:
419 return 24576000;
420
421 default:
422 return 0;
423 }
424 }
425
sun4i_codec_get_hw_rate(struct snd_pcm_hw_params * params)426 static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
427 {
428 unsigned int rate = params_rate(params);
429
430 switch (rate) {
431 case 192000:
432 case 176400:
433 return 6;
434
435 case 96000:
436 case 88200:
437 return 7;
438
439 case 48000:
440 case 44100:
441 return 0;
442
443 case 32000:
444 case 33075:
445 return 1;
446
447 case 24000:
448 case 22050:
449 return 2;
450
451 case 16000:
452 case 14700:
453 return 3;
454
455 case 12000:
456 case 11025:
457 return 4;
458
459 case 8000:
460 case 7350:
461 return 5;
462
463 default:
464 return -EINVAL;
465 }
466 }
467
sun4i_codec_hw_params_capture(struct sun4i_codec * scodec,struct snd_pcm_hw_params * params,unsigned int hwrate)468 static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
469 struct snd_pcm_hw_params *params,
470 unsigned int hwrate)
471 {
472 /* Set ADC sample rate */
473 regmap_field_update_bits(scodec->reg_adc_fifoc,
474 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
475 hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
476
477 /* Set the number of channels we want to use */
478 if (params_channels(params) == 1)
479 regmap_field_set_bits(scodec->reg_adc_fifoc,
480 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
481 else
482 regmap_field_clear_bits(scodec->reg_adc_fifoc,
483 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
484
485 /* Set the number of sample bits to either 16 or 24 bits */
486 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
487 regmap_field_set_bits(scodec->reg_adc_fifoc,
488 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
489
490 regmap_field_clear_bits(scodec->reg_adc_fifoc,
491 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
492
493 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
494 } else {
495 regmap_field_clear_bits(scodec->reg_adc_fifoc,
496 BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
497
498 /* Fill most significant bits with valid data MSB */
499 regmap_field_set_bits(scodec->reg_adc_fifoc,
500 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
501
502 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
503 }
504
505 return 0;
506 }
507
sun4i_codec_hw_params_playback(struct sun4i_codec * scodec,struct snd_pcm_hw_params * params,unsigned int hwrate)508 static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
509 struct snd_pcm_hw_params *params,
510 unsigned int hwrate)
511 {
512 u32 val;
513
514 /* Set DAC sample rate */
515 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
516 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
517 hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
518
519 /* Set the number of channels we want to use */
520 if (params_channels(params) == 1)
521 val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
522 else
523 val = 0;
524
525 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
526 BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
527 val);
528
529 /* Set the number of sample bits to either 16 or 24 bits */
530 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
531 regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
532 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
533
534 /* Set TX FIFO mode to padding the LSBs with 0 */
535 regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
536 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
537
538 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
539 } else {
540 regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
541 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
542
543 /* Set TX FIFO mode to repeat the MSB */
544 regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
545 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
546
547 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
548 }
549
550 return 0;
551 }
552
sun4i_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)553 static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
554 struct snd_pcm_hw_params *params,
555 struct snd_soc_dai *dai)
556 {
557 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
558 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
559 unsigned long clk_freq;
560 int ret, hwrate;
561
562 clk_freq = sun4i_codec_get_mod_freq(params);
563 if (!clk_freq)
564 return -EINVAL;
565
566 ret = clk_set_rate(scodec->clk_module, clk_freq);
567 if (ret)
568 return ret;
569
570 hwrate = sun4i_codec_get_hw_rate(params);
571 if (hwrate < 0)
572 return hwrate;
573
574 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
575 return sun4i_codec_hw_params_playback(scodec, params,
576 hwrate);
577
578 return sun4i_codec_hw_params_capture(scodec, params,
579 hwrate);
580 }
581
sun4i_codec_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)582 static int sun4i_codec_startup(struct snd_pcm_substream *substream,
583 struct snd_soc_dai *dai)
584 {
585 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
586 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
587
588 /*
589 * Stop issuing DRQ when we have room for less than 16 samples
590 * in our TX FIFO
591 */
592 regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
593 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
594
595 return clk_prepare_enable(scodec->clk_module);
596 }
597
sun4i_codec_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)598 static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
599 struct snd_soc_dai *dai)
600 {
601 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
602 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
603
604 clk_disable_unprepare(scodec->clk_module);
605 }
606
607 static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
608 .startup = sun4i_codec_startup,
609 .shutdown = sun4i_codec_shutdown,
610 .trigger = sun4i_codec_trigger,
611 .hw_params = sun4i_codec_hw_params,
612 .prepare = sun4i_codec_prepare,
613 };
614
615 #define SUN4I_CODEC_RATES ( \
616 SNDRV_PCM_RATE_8000_48000 | \
617 SNDRV_PCM_RATE_12000 | \
618 SNDRV_PCM_RATE_24000 | \
619 SNDRV_PCM_RATE_96000 | \
620 SNDRV_PCM_RATE_192000)
621
622 static struct snd_soc_dai_driver sun4i_codec_dai = {
623 .name = "Codec",
624 .ops = &sun4i_codec_dai_ops,
625 .playback = {
626 .stream_name = "Codec Playback",
627 .channels_min = 1,
628 .channels_max = 2,
629 .rate_min = 8000,
630 .rate_max = 192000,
631 .rates = SUN4I_CODEC_RATES,
632 .formats = SNDRV_PCM_FMTBIT_S16_LE |
633 SNDRV_PCM_FMTBIT_S32_LE,
634 .sig_bits = 24,
635 },
636 .capture = {
637 .stream_name = "Codec Capture",
638 .channels_min = 1,
639 .channels_max = 2,
640 .rate_min = 8000,
641 .rate_max = 48000,
642 .rates = SUN4I_CODEC_RATES,
643 .formats = SNDRV_PCM_FMTBIT_S16_LE |
644 SNDRV_PCM_FMTBIT_S32_LE,
645 .sig_bits = 24,
646 },
647 };
648
649 /*** sun4i Codec ***/
650 static const struct snd_kcontrol_new sun4i_codec_pa_mute =
651 SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
652 SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
653
654 static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
655 static DECLARE_TLV_DB_SCALE(sun4i_codec_linein_loopback_gain_scale, -150, 150,
656 0);
657 static DECLARE_TLV_DB_SCALE(sun4i_codec_linein_preamp_gain_scale, -1200, 300,
658 0);
659 static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150,
660 0);
661 static DECLARE_TLV_DB_SCALE(sun4i_codec_micin_loopback_gain_scale, -450, 150,
662 0);
663 static DECLARE_TLV_DB_RANGE(sun4i_codec_micin_preamp_gain_scale,
664 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
665 1, 7, TLV_DB_SCALE_ITEM(3500, 300, 0));
666 static DECLARE_TLV_DB_RANGE(sun7i_codec_micin_preamp_gain_scale,
667 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
668 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0));
669
670 static const struct snd_kcontrol_new sun4i_codec_controls[] = {
671 SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
672 SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
673 sun4i_codec_pa_volume_scale),
674 SOC_SINGLE_TLV("Line Playback Volume", SUN4I_CODEC_DAC_ACTL,
675 SUN4I_CODEC_DAC_ACTL_LNG, 1, 0,
676 sun4i_codec_linein_loopback_gain_scale),
677 SOC_SINGLE_TLV("Line Boost Volume", SUN4I_CODEC_ADC_ACTL,
678 SUN4I_CODEC_ADC_ACTL_LNPREG, 7, 0,
679 sun4i_codec_linein_preamp_gain_scale),
680 SOC_SINGLE_TLV("FM Playback Volume", SUN4I_CODEC_DAC_ACTL,
681 SUN4I_CODEC_DAC_ACTL_FMG, 3, 0,
682 sun4i_codec_fmin_loopback_gain_scale),
683 SOC_SINGLE_TLV("Mic Playback Volume", SUN4I_CODEC_DAC_ACTL,
684 SUN4I_CODEC_DAC_ACTL_MICG, 7, 0,
685 sun4i_codec_micin_loopback_gain_scale),
686 SOC_SINGLE_TLV("Mic1 Boost Volume", SUN4I_CODEC_ADC_ACTL,
687 SUN4I_CODEC_ADC_ACTL_PREG1, 3, 0,
688 sun4i_codec_micin_preamp_gain_scale),
689 SOC_SINGLE_TLV("Mic2 Boost Volume", SUN4I_CODEC_ADC_ACTL,
690 SUN4I_CODEC_ADC_ACTL_PREG2, 3, 0,
691 sun4i_codec_micin_preamp_gain_scale),
692 };
693
694 static const struct snd_kcontrol_new sun7i_codec_controls[] = {
695 SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
696 SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
697 sun4i_codec_pa_volume_scale),
698 SOC_SINGLE_TLV("Line Playback Volume", SUN4I_CODEC_DAC_ACTL,
699 SUN4I_CODEC_DAC_ACTL_LNG, 1, 0,
700 sun4i_codec_linein_loopback_gain_scale),
701 SOC_SINGLE_TLV("Line Boost Volume", SUN4I_CODEC_ADC_ACTL,
702 SUN4I_CODEC_ADC_ACTL_LNPREG, 7, 0,
703 sun4i_codec_linein_preamp_gain_scale),
704 SOC_SINGLE_TLV("FM Playback Volume", SUN4I_CODEC_DAC_ACTL,
705 SUN4I_CODEC_DAC_ACTL_FMG, 3, 0,
706 sun4i_codec_fmin_loopback_gain_scale),
707 SOC_SINGLE_TLV("Mic Playback Volume", SUN4I_CODEC_DAC_ACTL,
708 SUN4I_CODEC_DAC_ACTL_MICG, 7, 0,
709 sun4i_codec_micin_loopback_gain_scale),
710 SOC_SINGLE_TLV("Mic1 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
711 SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG1, 7, 0,
712 sun7i_codec_micin_preamp_gain_scale),
713 SOC_SINGLE_TLV("Mic2 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
714 SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2, 7, 0,
715 sun7i_codec_micin_preamp_gain_scale),
716 };
717
718 static const struct snd_kcontrol_new sun4i_codec_mixer_controls[] = {
719 SOC_DAPM_SINGLE("Left Mixer Left DAC Playback Switch",
720 SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_LDACLMIXS,
721 1, 0),
722 SOC_DAPM_SINGLE("Right Mixer Right DAC Playback Switch",
723 SUN4I_CODEC_DAC_ACTL, SUN4I_CODEC_DAC_ACTL_RDACRMIXS,
724 1, 0),
725 SOC_DAPM_SINGLE("Right Mixer Left DAC Playback Switch",
726 SUN4I_CODEC_DAC_ACTL,
727 SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
728 SOC_DAPM_DOUBLE("Line Playback Switch", SUN4I_CODEC_DAC_ACTL,
729 SUN4I_CODEC_DAC_ACTL_LLNS,
730 SUN4I_CODEC_DAC_ACTL_RLNS, 1, 0),
731 SOC_DAPM_DOUBLE("FM Playback Switch", SUN4I_CODEC_DAC_ACTL,
732 SUN4I_CODEC_DAC_ACTL_LFMS,
733 SUN4I_CODEC_DAC_ACTL_RFMS, 1, 0),
734 SOC_DAPM_DOUBLE("Mic1 Playback Switch", SUN4I_CODEC_DAC_ACTL,
735 SUN4I_CODEC_DAC_ACTL_MIC1LS,
736 SUN4I_CODEC_DAC_ACTL_MIC1RS, 1, 0),
737 SOC_DAPM_DOUBLE("Mic2 Playback Switch", SUN4I_CODEC_DAC_ACTL,
738 SUN4I_CODEC_DAC_ACTL_MIC2LS,
739 SUN4I_CODEC_DAC_ACTL_MIC2RS, 1, 0),
740 };
741
742 static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
743 SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
744 SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
745 SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
746 SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
747 };
748
749 static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
750 /* Digital parts of the ADCs */
751 SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC,
752 SUN4I_CODEC_ADC_FIFOC_EN_AD, 0,
753 NULL, 0),
754
755 /* Digital parts of the DACs */
756 SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
757 SUN4I_CODEC_DAC_DPC_EN_DA, 0,
758 NULL, 0),
759
760 /* Analog parts of the ADCs */
761 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
762 SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0),
763 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
764 SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0),
765
766 /* Analog parts of the DACs */
767 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
768 SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
769 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
770 SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
771
772 /* Mixers */
773 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
774 sun4i_codec_mixer_controls,
775 ARRAY_SIZE(sun4i_codec_mixer_controls)),
776 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
777 sun4i_codec_mixer_controls,
778 ARRAY_SIZE(sun4i_codec_mixer_controls)),
779
780 /* Global Mixer Enable */
781 SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
782 SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
783
784 /* VMIC */
785 SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL,
786 SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0),
787
788 /* Mic Pre-Amplifiers */
789 SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
790 SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0),
791 SND_SOC_DAPM_PGA("MIC2 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
792 SUN4I_CODEC_ADC_ACTL_PREG2EN, 0, NULL, 0),
793
794 /* Power Amplifier */
795 SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
796 SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
797 sun4i_codec_pa_mixer_controls,
798 ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
799 SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0,
800 &sun4i_codec_pa_mute),
801
802 SND_SOC_DAPM_INPUT("Line Right"),
803 SND_SOC_DAPM_INPUT("Line Left"),
804 SND_SOC_DAPM_INPUT("FM Right"),
805 SND_SOC_DAPM_INPUT("FM Left"),
806 SND_SOC_DAPM_INPUT("Mic1"),
807 SND_SOC_DAPM_INPUT("Mic2"),
808
809 SND_SOC_DAPM_OUTPUT("HP Right"),
810 SND_SOC_DAPM_OUTPUT("HP Left"),
811 };
812
813 static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
814 /* Left ADC / DAC Routes */
815 { "Left ADC", NULL, "ADC" },
816 { "Left DAC", NULL, "DAC" },
817
818 /* Right ADC / DAC Routes */
819 { "Right ADC", NULL, "ADC" },
820 { "Right DAC", NULL, "DAC" },
821
822 /* Right Mixer Routes */
823 { "Right Mixer", NULL, "Mixer Enable" },
824 { "Right Mixer", "Right Mixer Left DAC Playback Switch", "Left DAC" },
825 { "Right Mixer", "Right Mixer Right DAC Playback Switch", "Right DAC" },
826 { "Right Mixer", "Line Playback Switch", "Line Right" },
827 { "Right Mixer", "FM Playback Switch", "FM Right" },
828 { "Right Mixer", "Mic1 Playback Switch", "MIC1 Pre-Amplifier" },
829 { "Right Mixer", "Mic2 Playback Switch", "MIC2 Pre-Amplifier" },
830
831 /* Left Mixer Routes */
832 { "Left Mixer", NULL, "Mixer Enable" },
833 { "Left Mixer", "Left Mixer Left DAC Playback Switch", "Left DAC" },
834 { "Left Mixer", "Line Playback Switch", "Line Left" },
835 { "Left Mixer", "FM Playback Switch", "FM Left" },
836 { "Left Mixer", "Mic1 Playback Switch", "MIC1 Pre-Amplifier" },
837 { "Left Mixer", "Mic2 Playback Switch", "MIC2 Pre-Amplifier" },
838
839 /* Power Amplifier Routes */
840 { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" },
841 { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" },
842 { "Power Amplifier", "DAC Playback Switch", "Left DAC" },
843 { "Power Amplifier", "DAC Playback Switch", "Right DAC" },
844
845 /* Headphone Output Routes */
846 { "Power Amplifier Mute", "Switch", "Power Amplifier" },
847 { "HP Right", NULL, "Power Amplifier Mute" },
848 { "HP Left", NULL, "Power Amplifier Mute" },
849
850 /* Mic1 Routes */
851 { "Left ADC", NULL, "MIC1 Pre-Amplifier" },
852 { "Right ADC", NULL, "MIC1 Pre-Amplifier" },
853 { "MIC1 Pre-Amplifier", NULL, "Mic1"},
854 { "Mic1", NULL, "VMIC" },
855
856 /* Mic2 Routes */
857 { "Left ADC", NULL, "MIC2 Pre-Amplifier" },
858 { "Right ADC", NULL, "MIC2 Pre-Amplifier" },
859 { "MIC2 Pre-Amplifier", NULL, "Mic2"},
860 { "Mic2", NULL, "VMIC" },
861 };
862
863 static const struct snd_soc_component_driver sun4i_codec_codec = {
864 .controls = sun4i_codec_controls,
865 .num_controls = ARRAY_SIZE(sun4i_codec_controls),
866 .dapm_widgets = sun4i_codec_codec_dapm_widgets,
867 .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
868 .dapm_routes = sun4i_codec_codec_dapm_routes,
869 .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
870 .idle_bias_on = 1,
871 .use_pmdown_time = 1,
872 .endianness = 1,
873 };
874
875 static const struct snd_soc_component_driver sun7i_codec_codec = {
876 .controls = sun7i_codec_controls,
877 .num_controls = ARRAY_SIZE(sun7i_codec_controls),
878 .dapm_widgets = sun4i_codec_codec_dapm_widgets,
879 .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
880 .dapm_routes = sun4i_codec_codec_dapm_routes,
881 .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
882 .idle_bias_on = 1,
883 .use_pmdown_time = 1,
884 .endianness = 1,
885 };
886
887 /*** sun6i Codec ***/
888
889 /* mixer controls */
890 static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
891 SOC_DAPM_DOUBLE("DAC Playback Switch",
892 SUN6I_CODEC_OM_DACA_CTRL,
893 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL,
894 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0),
895 SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
896 SUN6I_CODEC_OM_DACA_CTRL,
897 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR,
898 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0),
899 SOC_DAPM_DOUBLE("Line In Playback Switch",
900 SUN6I_CODEC_OM_DACA_CTRL,
901 SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL,
902 SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0),
903 SOC_DAPM_DOUBLE("Mic1 Playback Switch",
904 SUN6I_CODEC_OM_DACA_CTRL,
905 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1,
906 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0),
907 SOC_DAPM_DOUBLE("Mic2 Playback Switch",
908 SUN6I_CODEC_OM_DACA_CTRL,
909 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2,
910 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0),
911 };
912
913 /* ADC mixer controls */
914 static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = {
915 SOC_DAPM_DOUBLE("Mixer Capture Switch",
916 SUN6I_CODEC_ADC_ACTL,
917 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL,
918 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0),
919 SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
920 SUN6I_CODEC_ADC_ACTL,
921 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR,
922 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0),
923 SOC_DAPM_DOUBLE("Line In Capture Switch",
924 SUN6I_CODEC_ADC_ACTL,
925 SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL,
926 SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0),
927 SOC_DAPM_DOUBLE("Mic1 Capture Switch",
928 SUN6I_CODEC_ADC_ACTL,
929 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1,
930 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0),
931 SOC_DAPM_DOUBLE("Mic2 Capture Switch",
932 SUN6I_CODEC_ADC_ACTL,
933 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2,
934 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0),
935 };
936
937 /* headphone controls */
938 static const char * const sun6i_codec_hp_src_enum_text[] = {
939 "DAC", "Mixer",
940 };
941
942 static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
943 SUN6I_CODEC_OM_DACA_CTRL,
944 SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
945 SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
946 sun6i_codec_hp_src_enum_text);
947
948 static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
949 SOC_DAPM_ENUM("Headphone Source Playback Route",
950 sun6i_codec_hp_src_enum),
951 };
952
953 /* microphone controls */
954 static const char * const sun6i_codec_mic2_src_enum_text[] = {
955 "Mic2", "Mic3",
956 };
957
958 static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum,
959 SUN6I_CODEC_MIC_CTRL,
960 SUN6I_CODEC_MIC_CTRL_MIC2SLT,
961 sun6i_codec_mic2_src_enum_text);
962
963 static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = {
964 SOC_DAPM_ENUM("Mic2 Amplifier Source Route",
965 sun6i_codec_mic2_src_enum),
966 };
967
968 /* line out controls */
969 static const char * const sun6i_codec_lineout_src_enum_text[] = {
970 "Stereo", "Mono Differential",
971 };
972
973 static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum,
974 SUN6I_CODEC_MIC_CTRL,
975 SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC,
976 SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC,
977 sun6i_codec_lineout_src_enum_text);
978
979 static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = {
980 SOC_DAPM_ENUM("Line Out Source Playback Route",
981 sun6i_codec_lineout_src_enum),
982 };
983
984 /* volume / mute controls */
985 static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0);
986 static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1);
987 static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale,
988 -450, 150, 0);
989 static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale,
990 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
991 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
992 );
993 static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale,
994 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
995 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
996 );
997
998 static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
999 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
1000 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
1001 sun6i_codec_dvol_scale),
1002 SOC_SINGLE_TLV("Headphone Playback Volume",
1003 SUN6I_CODEC_OM_DACA_CTRL,
1004 SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0,
1005 sun6i_codec_hp_vol_scale),
1006 SOC_SINGLE_TLV("Line Out Playback Volume",
1007 SUN6I_CODEC_MIC_CTRL,
1008 SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0,
1009 sun6i_codec_lineout_vol_scale),
1010 SOC_DOUBLE("Headphone Playback Switch",
1011 SUN6I_CODEC_OM_DACA_CTRL,
1012 SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE,
1013 SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0),
1014 SOC_DOUBLE("Line Out Playback Switch",
1015 SUN6I_CODEC_MIC_CTRL,
1016 SUN6I_CODEC_MIC_CTRL_LINEOUTLEN,
1017 SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0),
1018 /* Mixer pre-gains */
1019 SOC_SINGLE_TLV("Line In Playback Volume",
1020 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING,
1021 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
1022 SOC_SINGLE_TLV("Mic1 Playback Volume",
1023 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G,
1024 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
1025 SOC_SINGLE_TLV("Mic2 Playback Volume",
1026 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G,
1027 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
1028
1029 /* Microphone Amp boost gains */
1030 SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL,
1031 SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0,
1032 sun6i_codec_mic_gain_scale),
1033 SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL,
1034 SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0,
1035 sun6i_codec_mic_gain_scale),
1036 SOC_DOUBLE_TLV("ADC Capture Volume",
1037 SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG,
1038 SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0,
1039 sun6i_codec_out_mixer_pregain_scale),
1040 };
1041
1042 static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
1043 /* Microphone inputs */
1044 SND_SOC_DAPM_INPUT("MIC1"),
1045 SND_SOC_DAPM_INPUT("MIC2"),
1046 SND_SOC_DAPM_INPUT("MIC3"),
1047
1048 /* Microphone Bias */
1049 SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL,
1050 SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0),
1051 SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL,
1052 SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0),
1053
1054 /* Mic input path */
1055 SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route",
1056 SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src),
1057 SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL,
1058 SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0),
1059 SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL,
1060 SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0),
1061
1062 /* Line In */
1063 SND_SOC_DAPM_INPUT("LINEIN"),
1064
1065 /* Digital parts of the ADCs */
1066 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
1067 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0,
1068 NULL, 0),
1069
1070 /* Analog parts of the ADCs */
1071 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
1072 SUN6I_CODEC_ADC_ACTL_ADCLEN, 0),
1073 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
1074 SUN6I_CODEC_ADC_ACTL_ADCREN, 0),
1075
1076 /* ADC Mixers */
1077 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1078 sun6i_codec_adc_mixer_controls),
1079 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1080 sun6i_codec_adc_mixer_controls),
1081
1082 /* Digital parts of the DACs */
1083 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
1084 SUN4I_CODEC_DAC_DPC_EN_DA, 0,
1085 NULL, 0),
1086
1087 /* Analog parts of the DACs */
1088 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback",
1089 SUN6I_CODEC_OM_DACA_CTRL,
1090 SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0),
1091 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback",
1092 SUN6I_CODEC_OM_DACA_CTRL,
1093 SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0),
1094
1095 /* Mixers */
1096 SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL,
1097 SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0,
1098 sun6i_codec_mixer_controls),
1099 SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL,
1100 SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0,
1101 sun6i_codec_mixer_controls),
1102
1103 /* Headphone output path */
1104 SND_SOC_DAPM_MUX("Headphone Source Playback Route",
1105 SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
1106 SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL,
1107 SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0),
1108 SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL,
1109 SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0),
1110 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL,
1111 SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0),
1112 SND_SOC_DAPM_OUTPUT("HP"),
1113
1114 /* Line Out path */
1115 SND_SOC_DAPM_MUX("Line Out Source Playback Route",
1116 SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src),
1117 SND_SOC_DAPM_OUTPUT("LINEOUT"),
1118 };
1119
1120 static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
1121 /* DAC Routes */
1122 { "Left DAC", NULL, "DAC Enable" },
1123 { "Right DAC", NULL, "DAC Enable" },
1124
1125 /* Microphone Routes */
1126 { "Mic1 Amplifier", NULL, "MIC1"},
1127 { "Mic2 Amplifier Source Route", "Mic2", "MIC2" },
1128 { "Mic2 Amplifier Source Route", "Mic3", "MIC3" },
1129 { "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"},
1130
1131 /* Left Mixer Routes */
1132 { "Left Mixer", "DAC Playback Switch", "Left DAC" },
1133 { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
1134 { "Left Mixer", "Line In Playback Switch", "LINEIN" },
1135 { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
1136 { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
1137
1138 /* Right Mixer Routes */
1139 { "Right Mixer", "DAC Playback Switch", "Right DAC" },
1140 { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
1141 { "Right Mixer", "Line In Playback Switch", "LINEIN" },
1142 { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
1143 { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
1144
1145 /* Left ADC Mixer Routes */
1146 { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
1147 { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
1148 { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
1149 { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
1150 { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
1151
1152 /* Right ADC Mixer Routes */
1153 { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
1154 { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
1155 { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
1156 { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
1157 { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
1158
1159 /* Headphone Routes */
1160 { "Headphone Source Playback Route", "DAC", "Left DAC" },
1161 { "Headphone Source Playback Route", "DAC", "Right DAC" },
1162 { "Headphone Source Playback Route", "Mixer", "Left Mixer" },
1163 { "Headphone Source Playback Route", "Mixer", "Right Mixer" },
1164 { "Headphone Amp", NULL, "Headphone Source Playback Route" },
1165 { "HP", NULL, "Headphone Amp" },
1166 { "HPCOM", NULL, "HPCOM Protection" },
1167
1168 /* Line Out Routes */
1169 { "Line Out Source Playback Route", "Stereo", "Left Mixer" },
1170 { "Line Out Source Playback Route", "Stereo", "Right Mixer" },
1171 { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
1172 { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
1173 { "LINEOUT", NULL, "Line Out Source Playback Route" },
1174
1175 /* ADC Routes */
1176 { "Left ADC", NULL, "ADC Enable" },
1177 { "Right ADC", NULL, "ADC Enable" },
1178 { "Left ADC", NULL, "Left ADC Mixer" },
1179 { "Right ADC", NULL, "Right ADC Mixer" },
1180 };
1181
1182 static const struct snd_soc_component_driver sun6i_codec_codec = {
1183 .controls = sun6i_codec_codec_widgets,
1184 .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets),
1185 .dapm_widgets = sun6i_codec_codec_dapm_widgets,
1186 .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets),
1187 .dapm_routes = sun6i_codec_codec_dapm_routes,
1188 .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes),
1189 .idle_bias_on = 1,
1190 .use_pmdown_time = 1,
1191 .endianness = 1,
1192 };
1193
1194 /* sun8i A23 codec */
1195 static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = {
1196 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
1197 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
1198 sun6i_codec_dvol_scale),
1199 };
1200
1201 static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = {
1202 /* Digital parts of the ADCs */
1203 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
1204 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
1205 /* Digital parts of the DACs */
1206 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
1207 SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
1208
1209 };
1210
1211 static const struct snd_soc_component_driver sun8i_a23_codec_codec = {
1212 .controls = sun8i_a23_codec_codec_controls,
1213 .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls),
1214 .dapm_widgets = sun8i_a23_codec_codec_widgets,
1215 .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets),
1216 .idle_bias_on = 1,
1217 .use_pmdown_time = 1,
1218 .endianness = 1,
1219 };
1220
1221 static const struct snd_soc_component_driver sun4i_codec_component = {
1222 .name = "sun4i-codec",
1223 .legacy_dai_naming = 1,
1224 #ifdef CONFIG_DEBUG_FS
1225 .debugfs_prefix = "cpu",
1226 #endif
1227 };
1228
1229 #define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
1230 SNDRV_PCM_FMTBIT_S32_LE)
1231
sun4i_codec_dai_probe(struct snd_soc_dai * dai)1232 static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
1233 {
1234 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1235 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
1236
1237 snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
1238 &scodec->capture_dma_data);
1239
1240 return 0;
1241 }
1242
1243 static const struct snd_soc_dai_ops dummy_dai_ops = {
1244 .probe = sun4i_codec_dai_probe,
1245 };
1246
1247 static struct snd_soc_dai_driver dummy_cpu_dai = {
1248 .name = "sun4i-codec-cpu-dai",
1249 .playback = {
1250 .stream_name = "Playback",
1251 .channels_min = 1,
1252 .channels_max = 2,
1253 .rates = SUN4I_CODEC_RATES,
1254 .formats = SUN4I_CODEC_FORMATS,
1255 .sig_bits = 24,
1256 },
1257 .capture = {
1258 .stream_name = "Capture",
1259 .channels_min = 1,
1260 .channels_max = 2,
1261 .rates = SUN4I_CODEC_RATES,
1262 .formats = SUN4I_CODEC_FORMATS,
1263 .sig_bits = 24,
1264 },
1265 .ops = &dummy_dai_ops,
1266 };
1267
1268 static struct snd_soc_jack sun4i_headphone_jack;
1269
1270 static struct snd_soc_jack_pin sun4i_headphone_jack_pins[] = {
1271 { .pin = "Headphone", .mask = SND_JACK_HEADPHONE },
1272 };
1273
1274 static struct snd_soc_jack_gpio sun4i_headphone_jack_gpio = {
1275 .name = "hp-det",
1276 .report = SND_JACK_HEADPHONE,
1277 .debounce_time = 150,
1278 };
1279
sun4i_codec_machine_init(struct snd_soc_pcm_runtime * rtd)1280 static int sun4i_codec_machine_init(struct snd_soc_pcm_runtime *rtd)
1281 {
1282 struct snd_soc_card *card = rtd->card;
1283 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
1284 int ret;
1285
1286 if (scodec->gpio_hp) {
1287 ret = snd_soc_card_jack_new_pins(card, "Headphone Jack",
1288 SND_JACK_HEADPHONE,
1289 &sun4i_headphone_jack,
1290 sun4i_headphone_jack_pins,
1291 ARRAY_SIZE(sun4i_headphone_jack_pins));
1292 if (ret) {
1293 dev_err(rtd->dev,
1294 "Headphone jack creation failed: %d\n", ret);
1295 return ret;
1296 }
1297
1298 sun4i_headphone_jack_gpio.desc = scodec->gpio_hp;
1299 ret = snd_soc_jack_add_gpios(&sun4i_headphone_jack, 1,
1300 &sun4i_headphone_jack_gpio);
1301
1302 if (ret) {
1303 dev_err(rtd->dev, "Headphone GPIO not added: %d\n", ret);
1304 return ret;
1305 }
1306 }
1307
1308 return 0;
1309 }
1310
sun4i_codec_create_link(struct device * dev,int * num_links)1311 static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
1312 int *num_links)
1313 {
1314 struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
1315 GFP_KERNEL);
1316 struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev,
1317 3 * sizeof(*dlc), GFP_KERNEL);
1318 if (!link || !dlc)
1319 return NULL;
1320
1321 link->cpus = &dlc[0];
1322 link->codecs = &dlc[1];
1323 link->platforms = &dlc[2];
1324
1325 link->num_cpus = 1;
1326 link->num_codecs = 1;
1327 link->num_platforms = 1;
1328
1329 link->name = "cdc";
1330 link->stream_name = "CDC PCM";
1331 link->codecs->dai_name = "Codec";
1332 link->cpus->dai_name = dev_name(dev);
1333 link->codecs->name = dev_name(dev);
1334 link->platforms->name = dev_name(dev);
1335 link->dai_fmt = SND_SOC_DAIFMT_I2S;
1336 link->init = sun4i_codec_machine_init;
1337
1338 *num_links = 1;
1339
1340 return link;
1341 };
1342
sun4i_codec_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1343 static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w,
1344 struct snd_kcontrol *k, int event)
1345 {
1346 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
1347
1348 gpiod_set_value_cansleep(scodec->gpio_pa,
1349 !!SND_SOC_DAPM_EVENT_ON(event));
1350
1351 if (SND_SOC_DAPM_EVENT_ON(event)) {
1352 /*
1353 * Need a delay to wait for DAC to push the data. 700ms seems
1354 * to be the best compromise not to feel this delay while
1355 * playing a sound.
1356 */
1357 msleep(700);
1358 }
1359
1360 return 0;
1361 }
1362
1363 static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = {
1364 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
1365 };
1366
1367 static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = {
1368 { "Speaker", NULL, "HP Right" },
1369 { "Speaker", NULL, "HP Left" },
1370 };
1371
sun4i_codec_create_card(struct device * dev)1372 static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
1373 {
1374 struct snd_soc_card *card;
1375
1376 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1377 if (!card)
1378 return ERR_PTR(-ENOMEM);
1379
1380 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1381 if (!card->dai_link)
1382 return ERR_PTR(-ENOMEM);
1383
1384 card->dev = dev;
1385 card->owner = THIS_MODULE;
1386 card->name = "sun4i-codec";
1387 card->dapm_widgets = sun4i_codec_card_dapm_widgets;
1388 card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets);
1389 card->dapm_routes = sun4i_codec_card_dapm_routes;
1390 card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes);
1391
1392 return card;
1393 };
1394
1395 static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
1396 SND_SOC_DAPM_HP("Headphone", NULL),
1397 SND_SOC_DAPM_LINE("Line In", NULL),
1398 SND_SOC_DAPM_LINE("Line Out", NULL),
1399 SND_SOC_DAPM_MIC("Headset Mic", NULL),
1400 SND_SOC_DAPM_MIC("Mic", NULL),
1401 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
1402 };
1403
sun6i_codec_create_card(struct device * dev)1404 static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
1405 {
1406 struct snd_soc_card *card;
1407 int ret;
1408
1409 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1410 if (!card)
1411 return ERR_PTR(-ENOMEM);
1412
1413 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1414 if (!card->dai_link)
1415 return ERR_PTR(-ENOMEM);
1416
1417 card->dev = dev;
1418 card->owner = THIS_MODULE;
1419 card->name = "A31 Audio Codec";
1420 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1421 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1422 card->fully_routed = true;
1423
1424 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1425 if (ret)
1426 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
1427
1428 return card;
1429 };
1430
1431 /* Connect digital side enables to analog side widgets */
1432 static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
1433 /* ADC Routes */
1434 { "Left ADC", NULL, "ADC Enable" },
1435 { "Right ADC", NULL, "ADC Enable" },
1436 { "Codec Capture", NULL, "Left ADC" },
1437 { "Codec Capture", NULL, "Right ADC" },
1438
1439 /* DAC Routes */
1440 { "Left DAC", NULL, "DAC Enable" },
1441 { "Right DAC", NULL, "DAC Enable" },
1442 { "Left DAC", NULL, "Codec Playback" },
1443 { "Right DAC", NULL, "Codec Playback" },
1444 };
1445
1446 static struct snd_soc_aux_dev aux_dev = {
1447 .dlc = COMP_EMPTY(),
1448 };
1449
sun8i_a23_codec_create_card(struct device * dev)1450 static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
1451 {
1452 struct snd_soc_card *card;
1453 int ret;
1454
1455 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1456 if (!card)
1457 return ERR_PTR(-ENOMEM);
1458
1459 aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
1460 "allwinner,codec-analog-controls",
1461 0);
1462 if (!aux_dev.dlc.of_node) {
1463 dev_err(dev, "Can't find analog controls for codec.\n");
1464 return ERR_PTR(-EINVAL);
1465 }
1466
1467 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1468 if (!card->dai_link)
1469 return ERR_PTR(-ENOMEM);
1470
1471 card->dev = dev;
1472 card->owner = THIS_MODULE;
1473 card->name = "A23 Audio Codec";
1474 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1475 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1476 card->dapm_routes = sun8i_codec_card_routes;
1477 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
1478 card->aux_dev = &aux_dev;
1479 card->num_aux_devs = 1;
1480 card->fully_routed = true;
1481
1482 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1483 if (ret)
1484 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
1485
1486 return card;
1487 };
1488
sun8i_h3_codec_create_card(struct device * dev)1489 static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev)
1490 {
1491 struct snd_soc_card *card;
1492 int ret;
1493
1494 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1495 if (!card)
1496 return ERR_PTR(-ENOMEM);
1497
1498 aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
1499 "allwinner,codec-analog-controls",
1500 0);
1501 if (!aux_dev.dlc.of_node) {
1502 dev_err(dev, "Can't find analog controls for codec.\n");
1503 return ERR_PTR(-EINVAL);
1504 }
1505
1506 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1507 if (!card->dai_link)
1508 return ERR_PTR(-ENOMEM);
1509
1510 card->dev = dev;
1511 card->owner = THIS_MODULE;
1512 card->name = "H3 Audio Codec";
1513 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1514 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1515 card->dapm_routes = sun8i_codec_card_routes;
1516 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
1517 card->aux_dev = &aux_dev;
1518 card->num_aux_devs = 1;
1519 card->fully_routed = true;
1520
1521 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1522 if (ret)
1523 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
1524
1525 return card;
1526 };
1527
sun8i_v3s_codec_create_card(struct device * dev)1528 static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev)
1529 {
1530 struct snd_soc_card *card;
1531 int ret;
1532
1533 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1534 if (!card)
1535 return ERR_PTR(-ENOMEM);
1536
1537 aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
1538 "allwinner,codec-analog-controls",
1539 0);
1540 if (!aux_dev.dlc.of_node) {
1541 dev_err(dev, "Can't find analog controls for codec.\n");
1542 return ERR_PTR(-EINVAL);
1543 }
1544
1545 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1546 if (!card->dai_link)
1547 return ERR_PTR(-ENOMEM);
1548
1549 card->dev = dev;
1550 card->owner = THIS_MODULE;
1551 card->name = "V3s Audio Codec";
1552 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1553 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1554 card->dapm_routes = sun8i_codec_card_routes;
1555 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
1556 card->aux_dev = &aux_dev;
1557 card->num_aux_devs = 1;
1558 card->fully_routed = true;
1559
1560 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1561 if (ret)
1562 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
1563
1564 return card;
1565 };
1566
1567 static const struct regmap_config sun4i_codec_regmap_config = {
1568 .reg_bits = 32,
1569 .reg_stride = 4,
1570 .val_bits = 32,
1571 .max_register = SUN4I_CODEC_ADC_RXCNT,
1572 };
1573
1574 static const struct regmap_config sun6i_codec_regmap_config = {
1575 .reg_bits = 32,
1576 .reg_stride = 4,
1577 .val_bits = 32,
1578 .max_register = SUN6I_CODEC_HMIC_DATA,
1579 };
1580
1581 static const struct regmap_config sun7i_codec_regmap_config = {
1582 .reg_bits = 32,
1583 .reg_stride = 4,
1584 .val_bits = 32,
1585 .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
1586 };
1587
1588 static const struct regmap_config sun8i_a23_codec_regmap_config = {
1589 .reg_bits = 32,
1590 .reg_stride = 4,
1591 .val_bits = 32,
1592 .max_register = SUN8I_A23_CODEC_ADC_RXCNT,
1593 };
1594
1595 static const struct regmap_config sun8i_h3_codec_regmap_config = {
1596 .reg_bits = 32,
1597 .reg_stride = 4,
1598 .val_bits = 32,
1599 .max_register = SUN8I_H3_CODEC_ADC_DBG,
1600 };
1601
1602 static const struct regmap_config sun8i_v3s_codec_regmap_config = {
1603 .reg_bits = 32,
1604 .reg_stride = 4,
1605 .val_bits = 32,
1606 .max_register = SUN8I_H3_CODEC_ADC_DBG,
1607 };
1608
1609 struct sun4i_codec_quirks {
1610 const struct regmap_config *regmap_config;
1611 const struct snd_soc_component_driver *codec;
1612 struct snd_soc_card * (*create_card)(struct device *dev);
1613 struct reg_field reg_adc_fifoc; /* used for regmap_field */
1614 unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
1615 unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
1616 bool has_reset;
1617 };
1618
1619 static const struct sun4i_codec_quirks sun4i_codec_quirks = {
1620 .regmap_config = &sun4i_codec_regmap_config,
1621 .codec = &sun4i_codec_codec,
1622 .create_card = sun4i_codec_create_card,
1623 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
1624 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1625 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
1626 };
1627
1628 static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
1629 .regmap_config = &sun6i_codec_regmap_config,
1630 .codec = &sun6i_codec_codec,
1631 .create_card = sun6i_codec_create_card,
1632 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1633 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1634 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1635 .has_reset = true,
1636 };
1637
1638 static const struct sun4i_codec_quirks sun7i_codec_quirks = {
1639 .regmap_config = &sun7i_codec_regmap_config,
1640 .codec = &sun7i_codec_codec,
1641 .create_card = sun4i_codec_create_card,
1642 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
1643 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1644 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
1645 };
1646
1647 static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
1648 .regmap_config = &sun8i_a23_codec_regmap_config,
1649 .codec = &sun8i_a23_codec_codec,
1650 .create_card = sun8i_a23_codec_create_card,
1651 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1652 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1653 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1654 .has_reset = true,
1655 };
1656
1657 static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
1658 .regmap_config = &sun8i_h3_codec_regmap_config,
1659 /*
1660 * TODO Share the codec structure with A23 for now.
1661 * This should be split out when adding digital audio
1662 * processing support for the H3.
1663 */
1664 .codec = &sun8i_a23_codec_codec,
1665 .create_card = sun8i_h3_codec_create_card,
1666 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1667 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
1668 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1669 .has_reset = true,
1670 };
1671
1672 static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = {
1673 .regmap_config = &sun8i_v3s_codec_regmap_config,
1674 /*
1675 * TODO The codec structure should be split out, like
1676 * H3, when adding digital audio processing support.
1677 */
1678 .codec = &sun8i_a23_codec_codec,
1679 .create_card = sun8i_v3s_codec_create_card,
1680 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1681 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
1682 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1683 .has_reset = true,
1684 };
1685
1686 static const struct of_device_id sun4i_codec_of_match[] = {
1687 {
1688 .compatible = "allwinner,sun4i-a10-codec",
1689 .data = &sun4i_codec_quirks,
1690 },
1691 {
1692 .compatible = "allwinner,sun6i-a31-codec",
1693 .data = &sun6i_a31_codec_quirks,
1694 },
1695 {
1696 .compatible = "allwinner,sun7i-a20-codec",
1697 .data = &sun7i_codec_quirks,
1698 },
1699 {
1700 .compatible = "allwinner,sun8i-a23-codec",
1701 .data = &sun8i_a23_codec_quirks,
1702 },
1703 {
1704 .compatible = "allwinner,sun8i-h3-codec",
1705 .data = &sun8i_h3_codec_quirks,
1706 },
1707 {
1708 .compatible = "allwinner,sun8i-v3s-codec",
1709 .data = &sun8i_v3s_codec_quirks,
1710 },
1711 {}
1712 };
1713 MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
1714
sun4i_codec_probe(struct platform_device * pdev)1715 static int sun4i_codec_probe(struct platform_device *pdev)
1716 {
1717 struct snd_soc_card *card;
1718 struct sun4i_codec *scodec;
1719 const struct sun4i_codec_quirks *quirks;
1720 struct resource *res;
1721 void __iomem *base;
1722 int ret;
1723
1724 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
1725 if (!scodec)
1726 return -ENOMEM;
1727
1728 scodec->dev = &pdev->dev;
1729
1730 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1731 if (IS_ERR(base))
1732 return PTR_ERR(base);
1733
1734 quirks = of_device_get_match_data(&pdev->dev);
1735 if (quirks == NULL) {
1736 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1737 return -ENODEV;
1738 }
1739
1740 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1741 quirks->regmap_config);
1742 if (IS_ERR(scodec->regmap)) {
1743 dev_err(&pdev->dev, "Failed to create our regmap\n");
1744 return PTR_ERR(scodec->regmap);
1745 }
1746
1747 /* Get the clocks from the DT */
1748 scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
1749 if (IS_ERR(scodec->clk_apb)) {
1750 dev_err(&pdev->dev, "Failed to get the APB clock\n");
1751 return PTR_ERR(scodec->clk_apb);
1752 }
1753
1754 scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
1755 if (IS_ERR(scodec->clk_module)) {
1756 dev_err(&pdev->dev, "Failed to get the module clock\n");
1757 return PTR_ERR(scodec->clk_module);
1758 }
1759
1760 if (quirks->has_reset) {
1761 scodec->rst = devm_reset_control_get_exclusive(&pdev->dev,
1762 NULL);
1763 if (IS_ERR(scodec->rst)) {
1764 dev_err(&pdev->dev, "Failed to get reset control\n");
1765 return PTR_ERR(scodec->rst);
1766 }
1767 }
1768
1769 scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
1770 GPIOD_OUT_LOW);
1771 if (IS_ERR(scodec->gpio_pa)) {
1772 ret = PTR_ERR(scodec->gpio_pa);
1773 dev_err_probe(&pdev->dev, ret, "Failed to get pa gpio\n");
1774 return ret;
1775 }
1776
1777 scodec->gpio_hp = devm_gpiod_get_optional(&pdev->dev, "hp-det", GPIOD_IN);
1778 if (IS_ERR(scodec->gpio_hp)) {
1779 ret = PTR_ERR(scodec->gpio_hp);
1780 dev_err_probe(&pdev->dev, ret, "Failed to get hp-det gpio\n");
1781 return ret;
1782 }
1783
1784 /* reg_field setup */
1785 scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev,
1786 scodec->regmap,
1787 quirks->reg_adc_fifoc);
1788 if (IS_ERR(scodec->reg_adc_fifoc)) {
1789 ret = PTR_ERR(scodec->reg_adc_fifoc);
1790 dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
1791 ret);
1792 return ret;
1793 }
1794
1795 /* Enable the bus clock */
1796 if (clk_prepare_enable(scodec->clk_apb)) {
1797 dev_err(&pdev->dev, "Failed to enable the APB clock\n");
1798 return -EINVAL;
1799 }
1800
1801 /* Deassert the reset control */
1802 if (scodec->rst) {
1803 ret = reset_control_deassert(scodec->rst);
1804 if (ret) {
1805 dev_err(&pdev->dev,
1806 "Failed to deassert the reset control\n");
1807 goto err_clk_disable;
1808 }
1809 }
1810
1811 /* DMA configuration for TX FIFO */
1812 scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
1813 scodec->playback_dma_data.maxburst = 8;
1814 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1815
1816 /* DMA configuration for RX FIFO */
1817 scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata;
1818 scodec->capture_dma_data.maxburst = 8;
1819 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1820
1821 ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec,
1822 &sun4i_codec_dai, 1);
1823 if (ret) {
1824 dev_err(&pdev->dev, "Failed to register our codec\n");
1825 goto err_assert_reset;
1826 }
1827
1828 ret = devm_snd_soc_register_component(&pdev->dev,
1829 &sun4i_codec_component,
1830 &dummy_cpu_dai, 1);
1831 if (ret) {
1832 dev_err(&pdev->dev, "Failed to register our DAI\n");
1833 goto err_assert_reset;
1834 }
1835
1836 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1837 if (ret) {
1838 dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
1839 goto err_assert_reset;
1840 }
1841
1842 card = quirks->create_card(&pdev->dev);
1843 if (IS_ERR(card)) {
1844 ret = PTR_ERR(card);
1845 dev_err(&pdev->dev, "Failed to create our card\n");
1846 goto err_assert_reset;
1847 }
1848
1849 snd_soc_card_set_drvdata(card, scodec);
1850
1851 ret = snd_soc_register_card(card);
1852 if (ret) {
1853 dev_err_probe(&pdev->dev, ret, "Failed to register our card\n");
1854 goto err_assert_reset;
1855 }
1856
1857 return 0;
1858
1859 err_assert_reset:
1860 if (scodec->rst)
1861 reset_control_assert(scodec->rst);
1862 err_clk_disable:
1863 clk_disable_unprepare(scodec->clk_apb);
1864 return ret;
1865 }
1866
sun4i_codec_remove(struct platform_device * pdev)1867 static void sun4i_codec_remove(struct platform_device *pdev)
1868 {
1869 struct snd_soc_card *card = platform_get_drvdata(pdev);
1870 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
1871
1872 snd_soc_unregister_card(card);
1873 if (scodec->rst)
1874 reset_control_assert(scodec->rst);
1875 clk_disable_unprepare(scodec->clk_apb);
1876 }
1877
1878 static struct platform_driver sun4i_codec_driver = {
1879 .driver = {
1880 .name = "sun4i-codec",
1881 .of_match_table = sun4i_codec_of_match,
1882 },
1883 .probe = sun4i_codec_probe,
1884 .remove = sun4i_codec_remove,
1885 };
1886 module_platform_driver(sun4i_codec_driver);
1887
1888 MODULE_DESCRIPTION("Allwinner A10 codec driver");
1889 MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
1890 MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
1891 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1892 MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
1893 MODULE_LICENSE("GPL");
1894